drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  73         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  74 };
  75
  76 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  77 {
  78         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  79         .codec_array = nv_video_codecs_encode_array,
  80 };
  81
  82 /* Navi1x */
  83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  84 {
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  91         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  92 };
  93
  94 static const struct amdgpu_video_codecs nv_video_codecs_decode =
  95 {
  96         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  97         .codec_array = nv_video_codecs_decode_array,
  98 };
  99
 100 /* Sienna Cichlid */
 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 102 {
 103         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 104         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 105         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 111 };
 112
 113 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 114 {
 115         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 116         .codec_array = sc_video_codecs_decode_array,
 117 };
 118
 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 121 {
 122         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 124 };
 125
 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
 127 {
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 130         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 131         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 132         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 133         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 134         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 135         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 136 };
 137
 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 139 {
 140         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 141         .codec_array = sriov_sc_video_codecs_encode_array,
 142 };
 143
 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
 145 {
 146         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
 147         .codec_array = sriov_sc_video_codecs_decode_array,
 148 };
 149
 150 /* Beige Goby*/
 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 152         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 153         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 154         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 155 };
 156
 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 158         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 159         .codec_array = bg_video_codecs_decode_array,
 160 };
 161
 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 163         .codec_count = 0,
 164         .codec_array = NULL,
 165 };
 166
 167 /* Yellow Carp*/
 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 169         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 170         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 171         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 172         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 173 };
 174
 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 176         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 177         .codec_array = yc_video_codecs_decode_array,
 178 };
 179
 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 181                                  const struct amdgpu_video_codecs **codecs)
 182 {
 183         switch (adev->asic_type) {
 184         case CHIP_SIENNA_CICHLID:
 185                 if (amdgpu_sriov_vf(adev)) {
 186                         if (encode)
 187                                 *codecs = &sriov_sc_video_codecs_encode;
 188                         else
 189                                 *codecs = &sriov_sc_video_codecs_decode;
 190                 } else {
 191                         if (encode)
 192                                 *codecs = &nv_video_codecs_encode;
 193                         else
 194                                 *codecs = &sc_video_codecs_decode;
 195                 }
 196                 return 0;
 197         case CHIP_NAVY_FLOUNDER:
 198         case CHIP_DIMGREY_CAVEFISH:
 199         case CHIP_VANGOGH:
 200                 if (encode)
 201                         *codecs = &nv_video_codecs_encode;
 202                 else
 203                         *codecs = &sc_video_codecs_decode;
 204                 return 0;
 205         case CHIP_YELLOW_CARP:
 206                 if (encode)
 207                         *codecs = &nv_video_codecs_encode;
 208                 else
 209                         *codecs = &yc_video_codecs_decode;
 210                 return 0;
 211         case CHIP_BEIGE_GOBY:
 212                 if (encode)
 213                         *codecs = &bg_video_codecs_encode;
 214                 else
 215                         *codecs = &bg_video_codecs_decode;
 216                 return 0;
 217         case CHIP_NAVI10:
 218         case CHIP_NAVI14:
 219         case CHIP_NAVI12:
 220                 if (encode)
 221                         *codecs = &nv_video_codecs_encode;
 222                 else
 223                         *codecs = &nv_video_codecs_decode;
 224                 return 0;
 225         default:
 226                 return -EINVAL;
 227         }
 228 }
 229
 230 /*
 231  * Indirect registers accessor
 232  */
 233 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 234 {
 235         unsigned long address, data;
 236         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 237         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 238
 239         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 240 }
 241
 242 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 243 {
 244         unsigned long address, data;
 245
 246         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 247         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 248
 249         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 250 }
 251
 252 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 253 {
 254         unsigned long address, data;
 255         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 256         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 257
 258         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 259 }
 260
 261 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 262 {
 263         unsigned long flags, address, data;
 264         u32 r;
 265         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 266         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 267
 268         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 269         WREG32(address, reg * 4);
 270         (void)RREG32(address);
 271         r = RREG32(data);
 272         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 273         return r;
 274 }
 275
 276 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 277 {
 278         unsigned long address, data;
 279
 280         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 281         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 282
 283         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 284 }
 285
 286 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 287 {
 288         unsigned long flags, address, data;
 289
 290         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 291         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 292
 293         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 294         WREG32(address, reg * 4);
 295         (void)RREG32(address);
 296         WREG32(data, v);
 297         (void)RREG32(data);
 298         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 299 }
 300
 301 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 302 {
 303         unsigned long flags, address, data;
 304         u32 r;
 305
 306         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 307         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 308
 309         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 310         WREG32(address, (reg));
 311         r = RREG32(data);
 312         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 313         return r;
 314 }
 315
 316 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 317 {
 318         unsigned long flags, address, data;
 319
 320         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 321         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 322
 323         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 324         WREG32(address, (reg));
 325         WREG32(data, (v));
 326         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 327 }
 328
 329 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 330 {
 331         return adev->nbio.funcs->get_memsize(adev);
 332 }
 333
 334 static u32 nv_get_xclk(struct amdgpu_device *adev)
 335 {
 336         return adev->clock.spll.reference_freq;
 337 }
 338
 339
 340 void nv_grbm_select(struct amdgpu_device *adev,
 341                      u32 me, u32 pipe, u32 queue, u32 vmid)
 342 {
 343         u32 grbm_gfx_cntl = 0;
 344         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 345         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 346         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 347         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 348
 349         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 350 }
 351
 352 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 353 {
 354         /* todo */
 355 }
 356
 357 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 358 {
 359         /* todo */
 360         return false;
 361 }
 362
 363 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 364                                   u8 *bios, u32 length_bytes)
 365 {
 366         u32 *dw_ptr;
 367         u32 i, length_dw;
 368         u32 rom_index_offset, rom_data_offset;
 369
 370         if (bios == NULL)
 371                 return false;
 372         if (length_bytes == 0)
 373                 return false;
 374         /* APU vbios image is part of sbios image */
 375         if (adev->flags & AMD_IS_APU)
 376                 return false;
 377
 378         dw_ptr = (u32 *)bios;
 379         length_dw = ALIGN(length_bytes, 4) / 4;
 380
 381         rom_index_offset =
 382                 adev->smuio.funcs->get_rom_index_offset(adev);
 383         rom_data_offset =
 384                 adev->smuio.funcs->get_rom_data_offset(adev);
 385
 386         /* set rom index to 0 */
 387         WREG32(rom_index_offset, 0);
 388         /* read out the rom data */
 389         for (i = 0; i < length_dw; i++)
 390                 dw_ptr[i] = RREG32(rom_data_offset);
 391
 392         return true;
 393 }
 394
 395 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 396         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 397         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 398         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 399         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 400         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 401         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 402         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 403         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 404         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 405         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 406         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 407         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 408         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 409         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 410         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 411         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 412         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 413         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 414         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 415 };
 416
 417 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 418                                          u32 sh_num, u32 reg_offset)
 419 {
 420         uint32_t val;
 421
 422         mutex_lock(&adev->grbm_idx_mutex);
 423         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 424                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 425
 426         val = RREG32(reg_offset);
 427
 428         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 429                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 430         mutex_unlock(&adev->grbm_idx_mutex);
 431         return val;
 432 }
 433
 434 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 435                                       bool indexed, u32 se_num,
 436                                       u32 sh_num, u32 reg_offset)
 437 {
 438         if (indexed) {
 439                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 440         } else {
 441                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 442                         return adev->gfx.config.gb_addr_config;
 443                 return RREG32(reg_offset);
 444         }
 445 }
 446
 447 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 448                             u32 sh_num, u32 reg_offset, u32 *value)
 449 {
 450         uint32_t i;
 451         struct soc15_allowed_register_entry  *en;
 452
 453         *value = 0;
 454         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 455                 en = &nv_allowed_read_registers[i];
 456                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 457                     reg_offset !=
 458                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 459                         continue;
 460
 461                 *value = nv_get_register_value(adev,
 462                                                nv_allowed_read_registers[i].grbm_indexed,
 463                                                se_num, sh_num, reg_offset);
 464                 return 0;
 465         }
 466         return -EINVAL;
 467 }
 468
 469 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 470 {
 471         u32 i;
 472         int ret = 0;
 473
 474         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 475
 476         /* disable BM */
 477         pci_clear_master(adev->pdev);
 478
 479         amdgpu_device_cache_pci_state(adev->pdev);
 480
 481         ret = amdgpu_dpm_mode2_reset(adev);
 482         if (ret)
 483                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 484
 485         amdgpu_device_load_pci_state(adev->pdev);
 486
 487         /* wait for asic to come out of reset */
 488         for (i = 0; i < adev->usec_timeout; i++) {
 489                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 490
 491                 if (memsize != 0xffffffff)
 492                         break;
 493                 udelay(1);
 494         }
 495
 496         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 497
 498         return ret;
 499 }
 500
 501 static enum amd_reset_method
 502 nv_asic_reset_method(struct amdgpu_device *adev)
 503 {
 504         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 505             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 506             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 507             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 508                 return amdgpu_reset_method;
 509
 510         if (amdgpu_reset_method != -1)
 511                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 512                                   amdgpu_reset_method);
 513
 514         switch (adev->asic_type) {
 515         case CHIP_VANGOGH:
 516         case CHIP_YELLOW_CARP:
 517                 return AMD_RESET_METHOD_MODE2;
 518         case CHIP_SIENNA_CICHLID:
 519         case CHIP_NAVY_FLOUNDER:
 520         case CHIP_DIMGREY_CAVEFISH:
 521         case CHIP_BEIGE_GOBY:
 522                 return AMD_RESET_METHOD_MODE1;
 523         default:
 524                 if (amdgpu_dpm_is_baco_supported(adev))
 525                         return AMD_RESET_METHOD_BACO;
 526                 else
 527                         return AMD_RESET_METHOD_MODE1;
 528         }
 529 }
 530
 531 static int nv_asic_reset(struct amdgpu_device *adev)
 532 {
 533         int ret = 0;
 534
 535         switch (nv_asic_reset_method(adev)) {
 536         case AMD_RESET_METHOD_PCI:
 537                 dev_info(adev->dev, "PCI reset\n");
 538                 ret = amdgpu_device_pci_reset(adev);
 539                 break;
 540         case AMD_RESET_METHOD_BACO:
 541                 dev_info(adev->dev, "BACO reset\n");
 542                 ret = amdgpu_dpm_baco_reset(adev);
 543                 break;
 544         case AMD_RESET_METHOD_MODE2:
 545                 dev_info(adev->dev, "MODE2 reset\n");
 546                 ret = nv_asic_mode2_reset(adev);
 547                 break;
 548         default:
 549                 dev_info(adev->dev, "MODE1 reset\n");
 550                 ret = amdgpu_device_mode1_reset(adev);
 551                 break;
 552         }
 553
 554         return ret;
 555 }
 556
 557 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 558 {
 559         /* todo */
 560         return 0;
 561 }
 562
 563 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 564 {
 565         /* todo */
 566         return 0;
 567 }
 568
 569 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 570 {
 571         if (pci_is_root_bus(adev->pdev->bus))
 572                 return;
 573
 574         if (amdgpu_pcie_gen2 == 0)
 575                 return;
 576
 577         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 578                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 579                 return;
 580
 581         /* todo */
 582 }
 583
 584 static void nv_program_aspm(struct amdgpu_device *adev)
 585 {
 586         if (!amdgpu_aspm)
 587                 return;
 588
 589         if (!(adev->flags & AMD_IS_APU) &&
 590             (adev->nbio.funcs->program_aspm))
 591                 adev->nbio.funcs->program_aspm(adev);
 592
 593 }
 594
 595 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 596                                         bool enable)
 597 {
 598         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 599         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 600 }
 601
 602 static const struct amdgpu_ip_block_version nv_common_ip_block =
 603 {
 604         .type = AMD_IP_BLOCK_TYPE_COMMON,
 605         .major = 1,
 606         .minor = 0,
 607         .rev = 0,
 608         .funcs = &nv_common_ip_funcs,
 609 };
 610
 611 static bool nv_is_headless_sku(struct pci_dev *pdev)
 612 {
 613         if ((pdev->device == 0x731E &&
 614             (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
 615             (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||
 616             (pdev->device == 0x7360 && pdev->revision == 0xC7))
 617                 return true;
 618         return false;
 619 }
 620
 621 static int nv_reg_base_init(struct amdgpu_device *adev)
 622 {
 623         int r;
 624
 625         if (amdgpu_discovery) {
 626                 r = amdgpu_discovery_reg_base_init(adev);
 627                 if (r) {
 628                         DRM_WARN("failed to init reg base from ip discovery table, "
 629                                         "fallback to legacy init method\n");
 630                         goto legacy_init;
 631                 }
 632
 633                 amdgpu_discovery_harvest_ip(adev);
 634                 if (nv_is_headless_sku(adev->pdev)) {
 635                         adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 636                         adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 637                 }
 638
 639                 return 0;
 640         }
 641
 642 legacy_init:
 643         switch (adev->asic_type) {
 644         case CHIP_NAVI10:
 645                 navi10_reg_base_init(adev);
 646                 break;
 647         case CHIP_NAVI14:
 648                 navi14_reg_base_init(adev);
 649                 break;
 650         case CHIP_NAVI12:
 651                 navi12_reg_base_init(adev);
 652                 break;
 653         case CHIP_SIENNA_CICHLID:
 654         case CHIP_NAVY_FLOUNDER:
 655                 sienna_cichlid_reg_base_init(adev);
 656                 break;
 657         case CHIP_VANGOGH:
 658                 vangogh_reg_base_init(adev);
 659                 break;
 660         case CHIP_DIMGREY_CAVEFISH:
 661                 dimgrey_cavefish_reg_base_init(adev);
 662                 break;
 663         case CHIP_BEIGE_GOBY:
 664                 beige_goby_reg_base_init(adev);
 665                 break;
 666         case CHIP_YELLOW_CARP:
 667                 yellow_carp_reg_base_init(adev);
 668                 break;
 669         case CHIP_CYAN_SKILLFISH:
 670                 cyan_skillfish_reg_base_init(adev);
 671                 break;
 672         default:
 673                 return -EINVAL;
 674         }
 675
 676         return 0;
 677 }
 678
 679 void nv_set_virt_ops(struct amdgpu_device *adev)
 680 {
 681         adev->virt.ops = &xgpu_nv_virt_ops;
 682 }
 683
 684 int nv_set_ip_blocks(struct amdgpu_device *adev)
 685 {
 686         int r;
 687
 688         if (adev->asic_type == CHIP_CYAN_SKILLFISH) {
 689                 adev->nbio.funcs = &nbio_v2_3_funcs;
 690                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 691         } else if (adev->flags & AMD_IS_APU) {
 692                 adev->nbio.funcs = &nbio_v7_2_funcs;
 693                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
 694         } else {
 695                 adev->nbio.funcs = &nbio_v2_3_funcs;
 696                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 697         }
 698         adev->hdp.funcs = &hdp_v5_0_funcs;
 699
 700         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 701                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
 702         else
 703                 adev->smuio.funcs = &smuio_v11_0_funcs;
 704
 705         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 706                 adev->gmc.xgmi.supported = true;
 707
 708         /* Set IP register base before any HW register access */
 709         r = nv_reg_base_init(adev);
 710         if (r)
 711                 return r;
 712
 713         switch (adev->asic_type) {
 714         case CHIP_NAVI10:
 715         case CHIP_NAVI14:
 716                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 717                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 718                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 719                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 720                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 721                     !amdgpu_sriov_vf(adev))
 722                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 723                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 724                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 725 #if defined(CONFIG_DRM_AMD_DC)
 726                 else if (amdgpu_device_has_dc_support(adev))
 727                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 728 #endif
 729                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 730                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 731                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 732                     !amdgpu_sriov_vf(adev))
 733                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 734                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 735                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 736                 if (adev->enable_mes)
 737                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 738                 break;
 739         case CHIP_NAVI12:
 740                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 741                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 742                 if (!amdgpu_sriov_vf(adev)) {
 743                         amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 744                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 745                 } else {
 746                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 747                         amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 748                 }
 749                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 750                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 751                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 752                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 753 #if defined(CONFIG_DRM_AMD_DC)
 754                 else if (amdgpu_device_has_dc_support(adev))
 755                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 756 #endif
 757                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 758                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 759                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 760                     !amdgpu_sriov_vf(adev))
 761                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 762                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 763                 if (!amdgpu_sriov_vf(adev))
 764                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 765                 break;
 766         case CHIP_SIENNA_CICHLID:
 767                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 768                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 769                 if (!amdgpu_sriov_vf(adev)) {
 770                         amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 771                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 772                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 773                 } else {
 774                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 775                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 776                         amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 777                 }
 778                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 779                     is_support_sw_smu(adev))
 780                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 781                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 782                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 783 #if defined(CONFIG_DRM_AMD_DC)
 784                 else if (amdgpu_device_has_dc_support(adev))
 785                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 786 #endif
 787                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 788                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 789                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 790                 if (!amdgpu_sriov_vf(adev))
 791                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 792                 if (adev->enable_mes)
 793                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 794                 break;
 795         case CHIP_NAVY_FLOUNDER:
 796                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 797                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 798                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 799                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 800                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 801                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 802                     is_support_sw_smu(adev))
 803                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 804                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 805                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 806 #if defined(CONFIG_DRM_AMD_DC)
 807                 else if (amdgpu_device_has_dc_support(adev))
 808                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 809 #endif
 810                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 811                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 812                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 813                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 814                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 815                     is_support_sw_smu(adev))
 816                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 817                 break;
 818         case CHIP_VANGOGH:
 819                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 820                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 821                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 822                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 823                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 824                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 825                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 826                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 827 #if defined(CONFIG_DRM_AMD_DC)
 828                 else if (amdgpu_device_has_dc_support(adev))
 829                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 830 #endif
 831                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 832                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 833                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 834                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 835                 break;
 836         case CHIP_DIMGREY_CAVEFISH:
 837                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 838                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 839                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 840                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 841                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 842                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 843                     is_support_sw_smu(adev))
 844                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 845                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 846                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 847 #if defined(CONFIG_DRM_AMD_DC)
 848                 else if (amdgpu_device_has_dc_support(adev))
 849                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 850 #endif
 851                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 852                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 853                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 854                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 855                 break;
 856         case CHIP_BEIGE_GOBY:
 857                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 858                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 859                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 860                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 861                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 862                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 863                     is_support_sw_smu(adev))
 864                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 865                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 866                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 867                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 868                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 869 #if defined(CONFIG_DRM_AMD_DC)
 870                 else if (amdgpu_device_has_dc_support(adev))
 871                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 872 #endif
 873                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 874                     is_support_sw_smu(adev))
 875                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 876                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 877                 break;
 878         case CHIP_YELLOW_CARP:
 879                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 880                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 881                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 882                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 883                         amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
 884                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
 885                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 886                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 887                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 888                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 889                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 890                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 891 #if defined(CONFIG_DRM_AMD_DC)
 892                 else if (amdgpu_device_has_dc_support(adev))
 893                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 894 #endif
 895                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 896                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 897                 break;
 898         case CHIP_CYAN_SKILLFISH:
 899                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 900                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 901                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 902                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 903                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 904                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
 905                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 906                 }
 907                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 908                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 909                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 910                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 911                 break;
 912         default:
 913                 return -EINVAL;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 920 {
 921         return adev->nbio.funcs->get_rev_id(adev);
 922 }
 923
 924 static bool nv_need_full_reset(struct amdgpu_device *adev)
 925 {
 926         return true;
 927 }
 928
 929 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 930 {
 931         u32 sol_reg;
 932
 933         if (adev->flags & AMD_IS_APU)
 934                 return false;
 935
 936         /* Check sOS sign of life register to confirm sys driver and sOS
 937          * are already been loaded.
 938          */
 939         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 940         if (sol_reg)
 941                 return true;
 942
 943         return false;
 944 }
 945
 946 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 947 {
 948
 949         /* TODO
 950          * dummy implement for pcie_replay_count sysfs interface
 951          * */
 952
 953         return 0;
 954 }
 955
 956 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 957 {
 958         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 959         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 960         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 961         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 962         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 963         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 964         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 965         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 966         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 967         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 968         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 969         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 970         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 971         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 972         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 973         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 974         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 975         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 976         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 977         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 978         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 979         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 980         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 981         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 982         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 983
 984         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 985         adev->doorbell_index.sdma_doorbell_range = 20;
 986 }
 987
 988 static void nv_pre_asic_init(struct amdgpu_device *adev)
 989 {
 990 }
 991
 992 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 993                                        bool enter)
 994 {
 995         if (enter)
 996                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 997         else
 998                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 999
1000         if (adev->gfx.funcs->update_perfmon_mgcg)
1001                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
1002
1003         if (!(adev->flags & AMD_IS_APU) &&
1004             (adev->nbio.funcs->enable_aspm))
1005                 adev->nbio.funcs->enable_aspm(adev, !enter);
1006
1007         return 0;
1008 }
1009
1010 static const struct amdgpu_asic_funcs nv_asic_funcs =
1011 {
1012         .read_disabled_bios = &nv_read_disabled_bios,
1013         .read_bios_from_rom = &nv_read_bios_from_rom,
1014         .read_register = &nv_read_register,
1015         .reset = &nv_asic_reset,
1016         .reset_method = &nv_asic_reset_method,
1017         .set_vga_state = &nv_vga_set_state,
1018         .get_xclk = &nv_get_xclk,
1019         .set_uvd_clocks = &nv_set_uvd_clocks,
1020         .set_vce_clocks = &nv_set_vce_clocks,
1021         .get_config_memsize = &nv_get_config_memsize,
1022         .init_doorbell_index = &nv_init_doorbell_index,
1023         .need_full_reset = &nv_need_full_reset,
1024         .need_reset_on_init = &nv_need_reset_on_init,
1025         .get_pcie_replay_count = &nv_get_pcie_replay_count,
1026         .supports_baco = &amdgpu_dpm_is_baco_supported,
1027         .pre_asic_init = &nv_pre_asic_init,
1028         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
1029         .query_video_codecs = &nv_query_video_codecs,
1030 };
1031
1032 static int nv_common_early_init(void *handle)
1033 {
1034 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036
1037         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1038         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1039         adev->smc_rreg = NULL;
1040         adev->smc_wreg = NULL;
1041         adev->pcie_rreg = &nv_pcie_rreg;
1042         adev->pcie_wreg = &nv_pcie_wreg;
1043         adev->pcie_rreg64 = &nv_pcie_rreg64;
1044         adev->pcie_wreg64 = &nv_pcie_wreg64;
1045         adev->pciep_rreg = &nv_pcie_port_rreg;
1046         adev->pciep_wreg = &nv_pcie_port_wreg;
1047
1048         /* TODO: will add them during VCN v2 implementation */
1049         adev->uvd_ctx_rreg = NULL;
1050         adev->uvd_ctx_wreg = NULL;
1051
1052         adev->didt_rreg = &nv_didt_rreg;
1053         adev->didt_wreg = &nv_didt_wreg;
1054
1055         adev->asic_funcs = &nv_asic_funcs;
1056
1057         adev->rev_id = nv_get_rev_id(adev);
1058         adev->external_rev_id = 0xff;
1059         switch (adev->asic_type) {
1060         case CHIP_NAVI10:
1061                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1062                         AMD_CG_SUPPORT_GFX_CGCG |
1063                         AMD_CG_SUPPORT_IH_CG |
1064                         AMD_CG_SUPPORT_HDP_MGCG |
1065                         AMD_CG_SUPPORT_HDP_LS |
1066                         AMD_CG_SUPPORT_SDMA_MGCG |
1067                         AMD_CG_SUPPORT_SDMA_LS |
1068                         AMD_CG_SUPPORT_MC_MGCG |
1069                         AMD_CG_SUPPORT_MC_LS |
1070                         AMD_CG_SUPPORT_ATHUB_MGCG |
1071                         AMD_CG_SUPPORT_ATHUB_LS |
1072                         AMD_CG_SUPPORT_VCN_MGCG |
1073                         AMD_CG_SUPPORT_JPEG_MGCG |
1074                         AMD_CG_SUPPORT_BIF_MGCG |
1075                         AMD_CG_SUPPORT_BIF_LS;
1076                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1077                         AMD_PG_SUPPORT_VCN_DPG |
1078                         AMD_PG_SUPPORT_JPEG |
1079                         AMD_PG_SUPPORT_ATHUB;
1080                 adev->external_rev_id = adev->rev_id + 0x1;
1081                 break;
1082         case CHIP_NAVI14:
1083                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1084                         AMD_CG_SUPPORT_GFX_CGCG |
1085                         AMD_CG_SUPPORT_IH_CG |
1086                         AMD_CG_SUPPORT_HDP_MGCG |
1087                         AMD_CG_SUPPORT_HDP_LS |
1088                         AMD_CG_SUPPORT_SDMA_MGCG |
1089                         AMD_CG_SUPPORT_SDMA_LS |
1090                         AMD_CG_SUPPORT_MC_MGCG |
1091                         AMD_CG_SUPPORT_MC_LS |
1092                         AMD_CG_SUPPORT_ATHUB_MGCG |
1093                         AMD_CG_SUPPORT_ATHUB_LS |
1094                         AMD_CG_SUPPORT_VCN_MGCG |
1095                         AMD_CG_SUPPORT_JPEG_MGCG |
1096                         AMD_CG_SUPPORT_BIF_MGCG |
1097                         AMD_CG_SUPPORT_BIF_LS;
1098                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1099                         AMD_PG_SUPPORT_JPEG |
1100                         AMD_PG_SUPPORT_VCN_DPG;
1101                 adev->external_rev_id = adev->rev_id + 20;
1102                 break;
1103         case CHIP_NAVI12:
1104                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1105                         AMD_CG_SUPPORT_GFX_MGLS |
1106                         AMD_CG_SUPPORT_GFX_CGCG |
1107                         AMD_CG_SUPPORT_GFX_CP_LS |
1108                         AMD_CG_SUPPORT_GFX_RLC_LS |
1109                         AMD_CG_SUPPORT_IH_CG |
1110                         AMD_CG_SUPPORT_HDP_MGCG |
1111                         AMD_CG_SUPPORT_HDP_LS |
1112                         AMD_CG_SUPPORT_SDMA_MGCG |
1113                         AMD_CG_SUPPORT_SDMA_LS |
1114                         AMD_CG_SUPPORT_MC_MGCG |
1115                         AMD_CG_SUPPORT_MC_LS |
1116                         AMD_CG_SUPPORT_ATHUB_MGCG |
1117                         AMD_CG_SUPPORT_ATHUB_LS |
1118                         AMD_CG_SUPPORT_VCN_MGCG |
1119                         AMD_CG_SUPPORT_JPEG_MGCG;
1120                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1121                         AMD_PG_SUPPORT_VCN_DPG |
1122                         AMD_PG_SUPPORT_JPEG |
1123                         AMD_PG_SUPPORT_ATHUB;
1124                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1125                  * as a consequence, the rev_id and external_rev_id are wrong.
1126                  * workaround it by hardcoding rev_id to 0 (default value).
1127                  */
1128                 if (amdgpu_sriov_vf(adev))
1129                         adev->rev_id = 0;
1130                 adev->external_rev_id = adev->rev_id + 0xa;
1131                 break;
1132         case CHIP_SIENNA_CICHLID:
1133                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1134                         AMD_CG_SUPPORT_GFX_CGCG |
1135                         AMD_CG_SUPPORT_GFX_CGLS |
1136                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1137                         AMD_CG_SUPPORT_MC_MGCG |
1138                         AMD_CG_SUPPORT_VCN_MGCG |
1139                         AMD_CG_SUPPORT_JPEG_MGCG |
1140                         AMD_CG_SUPPORT_HDP_MGCG |
1141                         AMD_CG_SUPPORT_HDP_LS |
1142                         AMD_CG_SUPPORT_IH_CG |
1143                         AMD_CG_SUPPORT_MC_LS;
1144                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1145                         AMD_PG_SUPPORT_VCN_DPG |
1146                         AMD_PG_SUPPORT_JPEG |
1147                         AMD_PG_SUPPORT_ATHUB |
1148                         AMD_PG_SUPPORT_MMHUB;
1149                 if (amdgpu_sriov_vf(adev)) {
1150                         /* hypervisor control CG and PG enablement */
1151                         adev->cg_flags = 0;
1152                         adev->pg_flags = 0;
1153                 }
1154                 adev->external_rev_id = adev->rev_id + 0x28;
1155                 break;
1156         case CHIP_NAVY_FLOUNDER:
1157                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1158                         AMD_CG_SUPPORT_GFX_CGCG |
1159                         AMD_CG_SUPPORT_GFX_CGLS |
1160                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1161                         AMD_CG_SUPPORT_VCN_MGCG |
1162                         AMD_CG_SUPPORT_JPEG_MGCG |
1163                         AMD_CG_SUPPORT_MC_MGCG |
1164                         AMD_CG_SUPPORT_MC_LS |
1165                         AMD_CG_SUPPORT_HDP_MGCG |
1166                         AMD_CG_SUPPORT_HDP_LS |
1167                         AMD_CG_SUPPORT_IH_CG;
1168                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1169                         AMD_PG_SUPPORT_VCN_DPG |
1170                         AMD_PG_SUPPORT_JPEG |
1171                         AMD_PG_SUPPORT_ATHUB |
1172                         AMD_PG_SUPPORT_MMHUB;
1173                 adev->external_rev_id = adev->rev_id + 0x32;
1174                 break;
1175
1176         case CHIP_VANGOGH:
1177                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1178                         AMD_CG_SUPPORT_GFX_MGLS |
1179                         AMD_CG_SUPPORT_GFX_CP_LS |
1180                         AMD_CG_SUPPORT_GFX_RLC_LS |
1181                         AMD_CG_SUPPORT_GFX_CGCG |
1182                         AMD_CG_SUPPORT_GFX_CGLS |
1183                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1184                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1185                         AMD_CG_SUPPORT_MC_MGCG |
1186                         AMD_CG_SUPPORT_MC_LS |
1187                         AMD_CG_SUPPORT_GFX_FGCG |
1188                         AMD_CG_SUPPORT_VCN_MGCG |
1189                         AMD_CG_SUPPORT_SDMA_MGCG |
1190                         AMD_CG_SUPPORT_SDMA_LS |
1191                         AMD_CG_SUPPORT_JPEG_MGCG;
1192                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1193                         AMD_PG_SUPPORT_VCN |
1194                         AMD_PG_SUPPORT_VCN_DPG |
1195                         AMD_PG_SUPPORT_JPEG;
1196                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1197                         adev->external_rev_id = adev->rev_id + 0x01;
1198                 break;
1199         case CHIP_DIMGREY_CAVEFISH:
1200                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1201                         AMD_CG_SUPPORT_GFX_CGCG |
1202                         AMD_CG_SUPPORT_GFX_CGLS |
1203                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1204                         AMD_CG_SUPPORT_VCN_MGCG |
1205                         AMD_CG_SUPPORT_JPEG_MGCG |
1206                         AMD_CG_SUPPORT_MC_MGCG |
1207                         AMD_CG_SUPPORT_MC_LS |
1208                         AMD_CG_SUPPORT_HDP_MGCG |
1209                         AMD_CG_SUPPORT_HDP_LS |
1210                         AMD_CG_SUPPORT_IH_CG;
1211                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1212                         AMD_PG_SUPPORT_VCN_DPG |
1213                         AMD_PG_SUPPORT_JPEG |
1214                         AMD_PG_SUPPORT_ATHUB |
1215                         AMD_PG_SUPPORT_MMHUB;
1216                 adev->external_rev_id = adev->rev_id + 0x3c;
1217                 break;
1218         case CHIP_BEIGE_GOBY:
1219                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1220                         AMD_CG_SUPPORT_GFX_CGCG |
1221                         AMD_CG_SUPPORT_GFX_CGLS |
1222                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1223                         AMD_CG_SUPPORT_MC_MGCG |
1224                         AMD_CG_SUPPORT_MC_LS |
1225                         AMD_CG_SUPPORT_HDP_MGCG |
1226                         AMD_CG_SUPPORT_HDP_LS |
1227                         AMD_CG_SUPPORT_IH_CG |
1228                         AMD_CG_SUPPORT_VCN_MGCG;
1229                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1230                         AMD_PG_SUPPORT_VCN_DPG |
1231                         AMD_PG_SUPPORT_ATHUB |
1232                         AMD_PG_SUPPORT_MMHUB;
1233                 adev->external_rev_id = adev->rev_id + 0x46;
1234                 break;
1235         case CHIP_YELLOW_CARP:
1236                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1237                         AMD_CG_SUPPORT_GFX_MGLS |
1238                         AMD_CG_SUPPORT_GFX_CGCG |
1239                         AMD_CG_SUPPORT_GFX_CGLS |
1240                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1241                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1242                         AMD_CG_SUPPORT_GFX_RLC_LS |
1243                         AMD_CG_SUPPORT_GFX_CP_LS |
1244                         AMD_CG_SUPPORT_GFX_FGCG |
1245                         AMD_CG_SUPPORT_MC_MGCG |
1246                         AMD_CG_SUPPORT_MC_LS |
1247                         AMD_CG_SUPPORT_SDMA_LS |
1248                         AMD_CG_SUPPORT_HDP_MGCG |
1249                         AMD_CG_SUPPORT_HDP_LS |
1250                         AMD_CG_SUPPORT_ATHUB_MGCG |
1251                         AMD_CG_SUPPORT_ATHUB_LS |
1252                         AMD_CG_SUPPORT_IH_CG |
1253                         AMD_CG_SUPPORT_VCN_MGCG |
1254                         AMD_CG_SUPPORT_JPEG_MGCG;
1255                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1256                         AMD_PG_SUPPORT_VCN |
1257                         AMD_PG_SUPPORT_VCN_DPG |
1258                         AMD_PG_SUPPORT_JPEG;
1259                 if (adev->pdev->device == 0x1681)
1260                         adev->external_rev_id = adev->rev_id + 0x19;
1261                 else
1262                         adev->external_rev_id = adev->rev_id + 0x01;
1263                 break;
1264         case CHIP_CYAN_SKILLFISH:
1265                 adev->cg_flags = 0;
1266                 adev->pg_flags = 0;
1267                 adev->external_rev_id = adev->rev_id + 0x82;
1268                 break;
1269         default:
1270                 /* FIXME: not supported yet */
1271                 return -EINVAL;
1272         }
1273
1274         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1275                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1276                                     AMD_PG_SUPPORT_VCN_DPG |
1277                                     AMD_PG_SUPPORT_JPEG);
1278
1279         if (amdgpu_sriov_vf(adev)) {
1280                 amdgpu_virt_init_setting(adev);
1281                 xgpu_nv_mailbox_set_irq_funcs(adev);
1282         }
1283
1284         return 0;
1285 }
1286
1287 static int nv_common_late_init(void *handle)
1288 {
1289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290
1291         if (amdgpu_sriov_vf(adev)) {
1292                 xgpu_nv_mailbox_get_irq(adev);
1293                 amdgpu_virt_update_sriov_video_codec(adev,
1294                                 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1295                                 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int nv_common_sw_init(void *handle)
1302 {
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304
1305         if (amdgpu_sriov_vf(adev))
1306                 xgpu_nv_mailbox_add_irq_id(adev);
1307
1308         return 0;
1309 }
1310
1311 static int nv_common_sw_fini(void *handle)
1312 {
1313         return 0;
1314 }
1315
1316 static int nv_common_hw_init(void *handle)
1317 {
1318         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1319
1320         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1321                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1322
1323         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1324                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1325
1326         /* enable pcie gen2/3 link */
1327         nv_pcie_gen3_enable(adev);
1328         /* enable aspm */
1329         nv_program_aspm(adev);
1330         /* setup nbio registers */
1331         adev->nbio.funcs->init_registers(adev);
1332         /* remap HDP registers to a hole in mmio space,
1333          * for the purpose of expose those registers
1334          * to process space
1335          */
1336         if (adev->nbio.funcs->remap_hdp_registers)
1337                 adev->nbio.funcs->remap_hdp_registers(adev);
1338         /* enable the doorbell aperture */
1339         nv_enable_doorbell_aperture(adev, true);
1340
1341         return 0;
1342 }
1343
1344 static int nv_common_hw_fini(void *handle)
1345 {
1346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347
1348         /* disable the doorbell aperture */
1349         nv_enable_doorbell_aperture(adev, false);
1350
1351         return 0;
1352 }
1353
1354 static int nv_common_suspend(void *handle)
1355 {
1356         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357
1358         return nv_common_hw_fini(adev);
1359 }
1360
1361 static int nv_common_resume(void *handle)
1362 {
1363         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364
1365         return nv_common_hw_init(adev);
1366 }
1367
1368 static bool nv_common_is_idle(void *handle)
1369 {
1370         return true;
1371 }
1372
1373 static int nv_common_wait_for_idle(void *handle)
1374 {
1375         return 0;
1376 }
1377
1378 static int nv_common_soft_reset(void *handle)
1379 {
1380         return 0;
1381 }
1382
1383 static int nv_common_set_clockgating_state(void *handle,
1384                                            enum amd_clockgating_state state)
1385 {
1386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1387
1388         if (amdgpu_sriov_vf(adev))
1389                 return 0;
1390
1391         switch (adev->asic_type) {
1392         case CHIP_NAVI10:
1393         case CHIP_NAVI14:
1394         case CHIP_NAVI12:
1395         case CHIP_SIENNA_CICHLID:
1396         case CHIP_NAVY_FLOUNDER:
1397         case CHIP_DIMGREY_CAVEFISH:
1398         case CHIP_BEIGE_GOBY:
1399                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1400                                 state == AMD_CG_STATE_GATE);
1401                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1402                                 state == AMD_CG_STATE_GATE);
1403                 adev->hdp.funcs->update_clock_gating(adev,
1404                                 state == AMD_CG_STATE_GATE);
1405                 adev->smuio.funcs->update_rom_clock_gating(adev,
1406                                 state == AMD_CG_STATE_GATE);
1407                 break;
1408         default:
1409                 break;
1410         }
1411         return 0;
1412 }
1413
1414 static int nv_common_set_powergating_state(void *handle,
1415                                            enum amd_powergating_state state)
1416 {
1417         /* TODO */
1418         return 0;
1419 }
1420
1421 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1422 {
1423         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1424
1425         if (amdgpu_sriov_vf(adev))
1426                 *flags = 0;
1427
1428         adev->nbio.funcs->get_clockgating_state(adev, flags);
1429
1430         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1431
1432         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1433
1434         return;
1435 }
1436
1437 static const struct amd_ip_funcs nv_common_ip_funcs = {
1438         .name = "nv_common",
1439         .early_init = nv_common_early_init,
1440         .late_init = nv_common_late_init,
1441         .sw_init = nv_common_sw_init,
1442         .sw_fini = nv_common_sw_fini,
1443         .hw_init = nv_common_hw_init,
1444         .hw_fini = nv_common_hw_fini,
1445         .suspend = nv_common_suspend,
1446         .resume = nv_common_resume,
1447         .is_idle = nv_common_is_idle,
1448         .wait_for_idle = nv_common_wait_for_idle,
1449         .soft_reset = nv_common_soft_reset,
1450         .set_clockgating_state = nv_common_set_clockgating_state,
1451         .set_powergating_state = nv_common_set_powergating_state,
1452         .get_clockgating_state = nv_common_get_clockgating_state,
1453 };