2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "nbio/nbio_2_3_offset.h"
26 #include "nbio/nbio_2_3_sh_mask.h"
27 #include "gc/gc_10_1_0_offset.h"
28 #include "gc/gc_10_1_0_sh_mask.h"
30 #include "navi10_ih.h"
31 #include "soc15_common.h"
34 static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
36 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
39 static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
41 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
45 * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
46 * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 1
49 * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
50 * correct value since it doesn't return the RCV_DW0 under the case that
51 * RCV_MSG_VALID is set by host.
53 static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)
55 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
59 static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,
64 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
68 xgpu_nv_mailbox_send_ack(adev);
73 static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)
75 return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
78 static int xgpu_nv_poll_ack(struct amdgpu_device *adev)
80 int timeout = NV_MAILBOX_POLL_ACK_TIMEDOUT;
84 reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
90 } while (timeout > 1);
92 pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", NV_MAILBOX_POLL_ACK_TIMEDOUT);
97 static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)
100 uint64_t timeout, now;
102 now = (uint64_t)ktime_to_ms(ktime_get());
103 timeout = now + NV_MAILBOX_POLL_MSG_TIMEDOUT;
106 r = xgpu_nv_mailbox_rcv_msg(adev, event);
111 now = (uint64_t)ktime_to_ms(ktime_get());
112 } while (timeout > now);
118 static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
119 enum idh_request req, u32 data1, u32 data2, u32 data3)
125 * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
126 * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
127 * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_nv_poll_ack()
128 * will return immediatly
131 xgpu_nv_mailbox_set_valid(adev, false);
132 trn = xgpu_nv_peek_ack(adev);
134 pr_err("trn=%x ACK should not assert! wait again !\n", trn);
139 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);
140 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);
141 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);
142 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3);
143 xgpu_nv_mailbox_set_valid(adev, true);
145 /* start to poll ack */
146 r = xgpu_nv_poll_ack(adev);
148 pr_err("Doesn't get ack from pf, continue\n");
150 xgpu_nv_mailbox_set_valid(adev, false);
153 static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
154 enum idh_request req)
157 enum idh_event event = -1;
160 xgpu_nv_mailbox_trans_msg(adev, req, 0, 0, 0);
163 case IDH_REQ_GPU_INIT_ACCESS:
164 case IDH_REQ_GPU_FINI_ACCESS:
165 case IDH_REQ_GPU_RESET_ACCESS:
166 event = IDH_READY_TO_ACCESS_GPU;
168 case IDH_REQ_GPU_INIT_DATA:
169 event = IDH_REQ_GPU_INIT_DATA_READY;
176 r = xgpu_nv_poll_msg(adev, event);
181 if (req != IDH_REQ_GPU_INIT_DATA) {
182 pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
185 else /* host doesn't support REQ_GPU_INIT_DATA handshake */
186 adev->virt.req_init_data_ver = 0;
188 if (req == IDH_REQ_GPU_INIT_DATA)
190 adev->virt.req_init_data_ver =
191 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);
193 /* assume V1 in case host doesn't set version number */
194 if (adev->virt.req_init_data_ver < 1)
195 adev->virt.req_init_data_ver = 1;
199 /* Retrieve checksum from mailbox2 */
200 if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
201 adev->virt.fw_reserve.checksum_key =
202 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);
209 static int xgpu_nv_request_reset(struct amdgpu_device *adev)
213 while (i < NV_MAILBOX_POLL_MSG_REP_MAX) {
214 ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
223 static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,
226 enum idh_request req;
228 req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
229 return xgpu_nv_send_access_requests(adev, req);
232 static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,
235 enum idh_request req;
238 req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
239 r = xgpu_nv_send_access_requests(adev, req);
244 static int xgpu_nv_request_init_data(struct amdgpu_device *adev)
246 return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);
249 static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,
250 struct amdgpu_irq_src *source,
251 struct amdgpu_iv_entry *entry)
253 DRM_DEBUG("get ack intr and do nothing.\n");
257 static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,
258 struct amdgpu_irq_src *source,
260 enum amdgpu_interrupt_state state)
262 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
264 if (state == AMDGPU_IRQ_STATE_ENABLE)
269 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
274 static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
276 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
277 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
278 int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;
280 /* block amdgpu_gpu_recover till msg FLR COMPLETE received,
281 * otherwise the mailbox msg will be ruined/reseted by
284 if (!down_write_trylock(&adev->reset_sem))
287 amdgpu_virt_fini_data_exchange(adev);
288 atomic_set(&adev->in_gpu_reset, 1);
290 xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);
293 if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
298 } while (timeout > 1);
301 atomic_set(&adev->in_gpu_reset, 0);
302 up_write(&adev->reset_sem);
304 /* Trigger recovery for world switch failure if no TDR */
305 if (amdgpu_device_should_recover_gpu(adev)
306 && (!amdgpu_device_has_job_running(adev) ||
307 adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT ||
308 adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||
309 adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||
310 adev->video_timeout == MAX_SCHEDULE_TIMEOUT))
311 amdgpu_device_gpu_recover(adev, NULL);
314 static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
315 struct amdgpu_irq_src *src,
317 enum amdgpu_interrupt_state state)
319 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
321 if (state == AMDGPU_IRQ_STATE_ENABLE)
326 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
331 static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,
332 struct amdgpu_irq_src *source,
333 struct amdgpu_iv_entry *entry)
335 enum idh_event event = xgpu_nv_mailbox_peek_msg(adev);
338 case IDH_FLR_NOTIFICATION:
339 if (amdgpu_sriov_runtime(adev))
340 schedule_work(&adev->virt.flr_work);
342 /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
343 * it byfar since that polling thread will handle it,
344 * other msg like flr complete is not handled here.
346 case IDH_CLR_MSG_BUF:
347 case IDH_FLR_NOTIFICATION_CMPL:
348 case IDH_READY_TO_ACCESS_GPU:
356 static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_ack_irq_funcs = {
357 .set = xgpu_nv_set_mailbox_ack_irq,
358 .process = xgpu_nv_mailbox_ack_irq,
361 static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_rcv_irq_funcs = {
362 .set = xgpu_nv_set_mailbox_rcv_irq,
363 .process = xgpu_nv_mailbox_rcv_irq,
366 void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev)
368 adev->virt.ack_irq.num_types = 1;
369 adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;
370 adev->virt.rcv_irq.num_types = 1;
371 adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;
374 int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev)
378 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
382 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
384 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
391 int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)
395 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
398 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
400 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
404 INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work);
409 void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)
411 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
412 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
415 const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
416 .req_full_gpu = xgpu_nv_request_full_gpu_access,
417 .rel_full_gpu = xgpu_nv_release_full_gpu_access,
418 .req_init_data = xgpu_nv_request_init_data,
419 .reset_gpu = xgpu_nv_request_reset,
421 .trans_msg = xgpu_nv_mailbox_trans_msg,