drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <drm/drm_drv.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_pm.h"
  34 #include "amdgpu_vcn.h"
  35 #include "soc15d.h"
  36
  37 /* Firmware Names */
  38 #define FIRMWARE_RAVEN          "amdgpu/raven_vcn.bin"
  39 #define FIRMWARE_PICASSO        "amdgpu/picasso_vcn.bin"
  40 #define FIRMWARE_RAVEN2         "amdgpu/raven2_vcn.bin"
  41 #define FIRMWARE_ARCTURUS       "amdgpu/arcturus_vcn.bin"
  42 #define FIRMWARE_RENOIR         "amdgpu/renoir_vcn.bin"
  43 #define FIRMWARE_GREEN_SARDINE  "amdgpu/green_sardine_vcn.bin"
  44 #define FIRMWARE_NAVI10         "amdgpu/navi10_vcn.bin"
  45 #define FIRMWARE_NAVI14         "amdgpu/navi14_vcn.bin"
  46 #define FIRMWARE_NAVI12         "amdgpu/navi12_vcn.bin"
  47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
  48 #define FIRMWARE_NAVY_FLOUNDER  "amdgpu/navy_flounder_vcn.bin"
  49 #define FIRMWARE_VANGOGH        "amdgpu/vangogh_vcn.bin"
  50 #define FIRMWARE_DIMGREY_CAVEFISH       "amdgpu/dimgrey_cavefish_vcn.bin"
  51 #define FIRMWARE_ALDEBARAN      "amdgpu/aldebaran_vcn.bin"
  52 #define FIRMWARE_BEIGE_GOBY     "amdgpu/beige_goby_vcn.bin"
  53 #define FIRMWARE_YELLOW_CARP    "amdgpu/yellow_carp_vcn.bin"
  54
  55 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  56 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  57 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
  59 MODULE_FIRMWARE(FIRMWARE_RENOIR);
  60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
  61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
  62 MODULE_FIRMWARE(FIRMWARE_NAVI10);
  63 MODULE_FIRMWARE(FIRMWARE_NAVI14);
  64 MODULE_FIRMWARE(FIRMWARE_NAVI12);
  65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
  66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
  67 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
  68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
  69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
  70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
  71
  72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  73
  74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  75 {
  76         unsigned long bo_size;
  77         const char *fw_name;
  78         const struct common_firmware_header *hdr;
  79         unsigned char fw_check;
  80         int i, r;
  81
  82         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  83         mutex_init(&adev->vcn.vcn_pg_lock);
  84         mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
  85         atomic_set(&adev->vcn.total_submission_cnt, 0);
  86         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
  87                 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
  88
  89         switch (adev->asic_type) {
  90         case CHIP_RAVEN:
  91                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
  92                         fw_name = FIRMWARE_RAVEN2;
  93                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
  94                         fw_name = FIRMWARE_PICASSO;
  95                 else
  96                         fw_name = FIRMWARE_RAVEN;
  97                 break;
  98         case CHIP_ARCTURUS:
  99                 fw_name = FIRMWARE_ARCTURUS;
 100                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 101                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 102                         adev->vcn.indirect_sram = true;
 103                 break;
 104         case CHIP_RENOIR:
 105                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
 106                         fw_name = FIRMWARE_RENOIR;
 107                 else
 108                         fw_name = FIRMWARE_GREEN_SARDINE;
 109
 110                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 111                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 112                         adev->vcn.indirect_sram = true;
 113                 break;
 114         case CHIP_ALDEBARAN:
 115                 fw_name = FIRMWARE_ALDEBARAN;
 116                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 117                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 118                         adev->vcn.indirect_sram = true;
 119                 break;
 120         case CHIP_NAVI10:
 121                 fw_name = FIRMWARE_NAVI10;
 122                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 123                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 124                         adev->vcn.indirect_sram = true;
 125                 break;
 126         case CHIP_NAVI14:
 127                 fw_name = FIRMWARE_NAVI14;
 128                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 129                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 130                         adev->vcn.indirect_sram = true;
 131                 break;
 132         case CHIP_NAVI12:
 133                 fw_name = FIRMWARE_NAVI12;
 134                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 135                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 136                         adev->vcn.indirect_sram = true;
 137                 break;
 138         case CHIP_SIENNA_CICHLID:
 139                 fw_name = FIRMWARE_SIENNA_CICHLID;
 140                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 141                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 142                         adev->vcn.indirect_sram = true;
 143                 break;
 144         case CHIP_NAVY_FLOUNDER:
 145                 fw_name = FIRMWARE_NAVY_FLOUNDER;
 146                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 147                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 148                         adev->vcn.indirect_sram = true;
 149                 break;
 150         case CHIP_VANGOGH:
 151                 fw_name = FIRMWARE_VANGOGH;
 152                 break;
 153         case CHIP_DIMGREY_CAVEFISH:
 154                 fw_name = FIRMWARE_DIMGREY_CAVEFISH;
 155                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 156                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 157                         adev->vcn.indirect_sram = true;
 158                 break;
 159         case CHIP_BEIGE_GOBY:
 160                 fw_name = FIRMWARE_BEIGE_GOBY;
 161                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 162                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 163                         adev->vcn.indirect_sram = true;
 164                 break;
 165         case CHIP_YELLOW_CARP:
 166                 fw_name = FIRMWARE_YELLOW_CARP;
 167                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 168                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 169                         adev->vcn.indirect_sram = true;
 170                 break;
 171         default:
 172                 return -EINVAL;
 173         }
 174
 175         r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
 176         if (r) {
 177                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
 178                         fw_name);
 179                 return r;
 180         }
 181
 182         r = amdgpu_ucode_validate(adev->vcn.fw);
 183         if (r) {
 184                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
 185                         fw_name);
 186                 release_firmware(adev->vcn.fw);
 187                 adev->vcn.fw = NULL;
 188                 return r;
 189         }
 190
 191         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 192         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 193
 194         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 195          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 196          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 197          * is zero in old naming convention, this field is always zero so far.
 198          * These four bits are used to tell which naming convention is present.
 199          */
 200         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 201         if (fw_check) {
 202                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 203
 204                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 205                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 206                 enc_major = fw_check;
 207                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 208                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 209                 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
 210                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 211         } else {
 212                 unsigned int version_major, version_minor, family_id;
 213
 214                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 215                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 216                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 217                 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
 218                         version_major, version_minor, family_id);
 219         }
 220
 221         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 222         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 223                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 224         bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 225
 226         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 227                 if (adev->vcn.harvest_config & (1 << i))
 228                         continue;
 229
 230                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 231                                                 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
 232                                                 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
 233                 if (r) {
 234                         dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 235                         return r;
 236                 }
 237
 238                 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr +
 239                                 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 240                 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr +
 241                                 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 242
 243                 if (adev->vcn.indirect_sram) {
 244                         r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 245                                         AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
 246                                         &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
 247                         if (r) {
 248                                 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 249                                 return r;
 250                         }
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 258 {
 259         int i, j;
 260
 261         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 262                 if (adev->vcn.harvest_config & (1 << j))
 263                         continue;
 264
 265                 if (adev->vcn.indirect_sram) {
 266                         amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
 267                                                   &adev->vcn.inst[j].dpg_sram_gpu_addr,
 268                                                   (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
 269                 }
 270                 kvfree(adev->vcn.inst[j].saved_bo);
 271
 272                 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
 273                                           &adev->vcn.inst[j].gpu_addr,
 274                                           (void **)&adev->vcn.inst[j].cpu_addr);
 275
 276                 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 277
 278                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 279                         amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 280         }
 281
 282         release_firmware(adev->vcn.fw);
 283         mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
 284         mutex_destroy(&adev->vcn.vcn_pg_lock);
 285
 286         return 0;
 287 }
 288
 289 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 290 {
 291         bool ret = false;
 292
 293         int major;
 294         int minor;
 295         int revision;
 296
 297         /* if cannot find IP data, then this VCN does not exist */
 298         if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0)
 299                 return true;
 300
 301         if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
 302                 ret = true;
 303         } else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) {
 304                 ret = true;
 305         } else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
 306                 ret = true;
 307         }
 308
 309         return ret;
 310 }
 311
 312 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 313 {
 314         unsigned size;
 315         void *ptr;
 316         int i, idx;
 317
 318         cancel_delayed_work_sync(&adev->vcn.idle_work);
 319
 320         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 321                 if (adev->vcn.harvest_config & (1 << i))
 322                         continue;
 323                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 324                         return 0;
 325
 326                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 327                 ptr = adev->vcn.inst[i].cpu_addr;
 328
 329                 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
 330                 if (!adev->vcn.inst[i].saved_bo)
 331                         return -ENOMEM;
 332
 333                 if (drm_dev_enter(&adev->ddev, &idx)) {
 334                         memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
 335                         drm_dev_exit(idx);
 336                 }
 337         }
 338         return 0;
 339 }
 340
 341 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 342 {
 343         unsigned size;
 344         void *ptr;
 345         int i, idx;
 346
 347         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 348                 if (adev->vcn.harvest_config & (1 << i))
 349                         continue;
 350                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 351                         return -EINVAL;
 352
 353                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 354                 ptr = adev->vcn.inst[i].cpu_addr;
 355
 356                 if (adev->vcn.inst[i].saved_bo != NULL) {
 357                         if (drm_dev_enter(&adev->ddev, &idx)) {
 358                                 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
 359                                 drm_dev_exit(idx);
 360                         }
 361                         kvfree(adev->vcn.inst[i].saved_bo);
 362                         adev->vcn.inst[i].saved_bo = NULL;
 363                 } else {
 364                         const struct common_firmware_header *hdr;
 365                         unsigned offset;
 366
 367                         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 368                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 369                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 370                                 if (drm_dev_enter(&adev->ddev, &idx)) {
 371                                         memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
 372                                                     le32_to_cpu(hdr->ucode_size_bytes));
 373                                         drm_dev_exit(idx);
 374                                 }
 375                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 376                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 377                         }
 378                         memset_io(ptr, 0, size);
 379                 }
 380         }
 381         return 0;
 382 }
 383
 384 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 385 {
 386         struct amdgpu_device *adev =
 387                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 388         unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 389         unsigned int i, j;
 390         int r = 0;
 391
 392         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 393                 if (adev->vcn.harvest_config & (1 << j))
 394                         continue;
 395
 396                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 397                         fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
 398                 }
 399
 400                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 401                         struct dpg_pause_state new_state;
 402
 403                         if (fence[j] ||
 404                                 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
 405                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 406                         else
 407                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 408
 409                         adev->vcn.pause_dpg_mode(adev, j, &new_state);
 410                 }
 411
 412                 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
 413                 fences += fence[j];
 414         }
 415
 416         if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
 417                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 418                        AMD_PG_STATE_GATE);
 419                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 420                                 false);
 421                 if (r)
 422                         dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
 423         } else {
 424                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 425         }
 426 }
 427
 428 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         int r = 0;
 432
 433         atomic_inc(&adev->vcn.total_submission_cnt);
 434
 435         if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
 436                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 437                                 true);
 438                 if (r)
 439                         dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
 440         }
 441
 442         mutex_lock(&adev->vcn.vcn_pg_lock);
 443         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 444                AMD_PG_STATE_UNGATE);
 445
 446         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 447                 struct dpg_pause_state new_state;
 448
 449                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
 450                         atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 451                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 452                 } else {
 453                         unsigned int fences = 0;
 454                         unsigned int i;
 455
 456                         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 457                                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
 458
 459                         if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
 460                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 461                         else
 462                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 463                 }
 464
 465                 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
 466         }
 467         mutex_unlock(&adev->vcn.vcn_pg_lock);
 468 }
 469
 470 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 471 {
 472         if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 473                 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 474                 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 475
 476         atomic_dec(&ring->adev->vcn.total_submission_cnt);
 477
 478         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 479 }
 480
 481 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 482 {
 483         struct amdgpu_device *adev = ring->adev;
 484         uint32_t tmp = 0;
 485         unsigned i;
 486         int r;
 487
 488         /* VCN in SRIOV does not support direct register read/write */
 489         if (amdgpu_sriov_vf(adev))
 490                 return 0;
 491
 492         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
 493         r = amdgpu_ring_alloc(ring, 3);
 494         if (r)
 495                 return r;
 496         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 497         amdgpu_ring_write(ring, 0xDEADBEEF);
 498         amdgpu_ring_commit(ring);
 499         for (i = 0; i < adev->usec_timeout; i++) {
 500                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
 501                 if (tmp == 0xDEADBEEF)
 502                         break;
 503                 udelay(1);
 504         }
 505
 506         if (i >= adev->usec_timeout)
 507                 r = -ETIMEDOUT;
 508
 509         return r;
 510 }
 511
 512 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
 513 {
 514         struct amdgpu_device *adev = ring->adev;
 515         uint32_t rptr;
 516         unsigned int i;
 517         int r;
 518
 519         if (amdgpu_sriov_vf(adev))
 520                 return 0;
 521
 522         r = amdgpu_ring_alloc(ring, 16);
 523         if (r)
 524                 return r;
 525
 526         rptr = amdgpu_ring_get_rptr(ring);
 527
 528         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
 529         amdgpu_ring_commit(ring);
 530
 531         for (i = 0; i < adev->usec_timeout; i++) {
 532                 if (amdgpu_ring_get_rptr(ring) != rptr)
 533                         break;
 534                 udelay(1);
 535         }
 536
 537         if (i >= adev->usec_timeout)
 538                 r = -ETIMEDOUT;
 539
 540         return r;
 541 }
 542
 543 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 544                                    struct amdgpu_bo *bo,
 545                                    struct dma_fence **fence)
 546 {
 547         struct amdgpu_device *adev = ring->adev;
 548         struct dma_fence *f = NULL;
 549         struct amdgpu_job *job;
 550         struct amdgpu_ib *ib;
 551         uint64_t addr;
 552         void *msg = NULL;
 553         int i, r;
 554
 555         r = amdgpu_job_alloc_with_ib(adev, 64,
 556                                         AMDGPU_IB_POOL_DIRECT, &job);
 557         if (r)
 558                 goto err;
 559
 560         ib = &job->ibs[0];
 561         addr = amdgpu_bo_gpu_offset(bo);
 562         msg = amdgpu_bo_kptr(bo);
 563         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 564         ib->ptr[1] = addr;
 565         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 566         ib->ptr[3] = addr >> 32;
 567         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 568         ib->ptr[5] = 0;
 569         for (i = 6; i < 16; i += 2) {
 570                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 571                 ib->ptr[i+1] = 0;
 572         }
 573         ib->length_dw = 16;
 574
 575         r = amdgpu_job_submit_direct(job, ring, &f);
 576         if (r)
 577                 goto err_free;
 578
 579         amdgpu_bo_fence(bo, f, false);
 580         amdgpu_bo_unreserve(bo);
 581         amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
 582
 583         if (fence)
 584                 *fence = dma_fence_get(f);
 585         dma_fence_put(f);
 586
 587         return 0;
 588
 589 err_free:
 590         amdgpu_job_free(job);
 591
 592 err:
 593         amdgpu_bo_unreserve(bo);
 594         amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
 595         return r;
 596 }
 597
 598 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 599                                          struct amdgpu_bo **bo)
 600 {
 601         struct amdgpu_device *adev = ring->adev;
 602         uint32_t *msg;
 603         int r, i;
 604
 605         *bo = NULL;
 606         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 607                                       AMDGPU_GEM_DOMAIN_VRAM,
 608                                       bo, NULL, (void **)&msg);
 609         if (r)
 610                 return r;
 611
 612         msg[0] = cpu_to_le32(0x00000028);
 613         msg[1] = cpu_to_le32(0x00000038);
 614         msg[2] = cpu_to_le32(0x00000001);
 615         msg[3] = cpu_to_le32(0x00000000);
 616         msg[4] = cpu_to_le32(handle);
 617         msg[5] = cpu_to_le32(0x00000000);
 618         msg[6] = cpu_to_le32(0x00000001);
 619         msg[7] = cpu_to_le32(0x00000028);
 620         msg[8] = cpu_to_le32(0x00000010);
 621         msg[9] = cpu_to_le32(0x00000000);
 622         msg[10] = cpu_to_le32(0x00000007);
 623         msg[11] = cpu_to_le32(0x00000000);
 624         msg[12] = cpu_to_le32(0x00000780);
 625         msg[13] = cpu_to_le32(0x00000440);
 626         for (i = 14; i < 1024; ++i)
 627                 msg[i] = cpu_to_le32(0x0);
 628
 629         return 0;
 630 }
 631
 632 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 633                                           struct amdgpu_bo **bo)
 634 {
 635         struct amdgpu_device *adev = ring->adev;
 636         uint32_t *msg;
 637         int r, i;
 638
 639         *bo = NULL;
 640         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 641                                       AMDGPU_GEM_DOMAIN_VRAM,
 642                                       bo, NULL, (void **)&msg);
 643         if (r)
 644                 return r;
 645
 646         msg[0] = cpu_to_le32(0x00000028);
 647         msg[1] = cpu_to_le32(0x00000018);
 648         msg[2] = cpu_to_le32(0x00000000);
 649         msg[3] = cpu_to_le32(0x00000002);
 650         msg[4] = cpu_to_le32(handle);
 651         msg[5] = cpu_to_le32(0x00000000);
 652         for (i = 6; i < 1024; ++i)
 653                 msg[i] = cpu_to_le32(0x0);
 654
 655         return 0;
 656 }
 657
 658 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 659 {
 660         struct dma_fence *fence = NULL;
 661         struct amdgpu_bo *bo;
 662         long r;
 663
 664         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
 665         if (r)
 666                 goto error;
 667
 668         r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
 669         if (r)
 670                 goto error;
 671         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
 672         if (r)
 673                 goto error;
 674
 675         r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
 676         if (r)
 677                 goto error;
 678
 679         r = dma_fence_wait_timeout(fence, false, timeout);
 680         if (r == 0)
 681                 r = -ETIMEDOUT;
 682         else if (r > 0)
 683                 r = 0;
 684
 685         dma_fence_put(fence);
 686 error:
 687         return r;
 688 }
 689
 690 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 691                                    struct amdgpu_bo *bo,
 692                                    struct dma_fence **fence)
 693 {
 694         struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
 695         const unsigned int ib_size_dw = 64;
 696         struct amdgpu_device *adev = ring->adev;
 697         struct dma_fence *f = NULL;
 698         struct amdgpu_job *job;
 699         struct amdgpu_ib *ib;
 700         uint64_t addr;
 701         int i, r;
 702
 703         r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
 704                                 AMDGPU_IB_POOL_DIRECT, &job);
 705         if (r)
 706                 goto err;
 707
 708         ib = &job->ibs[0];
 709         addr = amdgpu_bo_gpu_offset(bo);
 710         ib->length_dw = 0;
 711
 712         ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 713         ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 714         decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
 715         ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
 716         memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
 717
 718         decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
 719         decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
 720         decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
 721
 722         for (i = ib->length_dw; i < ib_size_dw; ++i)
 723                 ib->ptr[i] = 0x0;
 724
 725         r = amdgpu_job_submit_direct(job, ring, &f);
 726         if (r)
 727                 goto err_free;
 728
 729         amdgpu_bo_fence(bo, f, false);
 730         amdgpu_bo_unreserve(bo);
 731         amdgpu_bo_unref(&bo);
 732
 733         if (fence)
 734                 *fence = dma_fence_get(f);
 735         dma_fence_put(f);
 736
 737         return 0;
 738
 739 err_free:
 740         amdgpu_job_free(job);
 741
 742 err:
 743         amdgpu_bo_unreserve(bo);
 744         amdgpu_bo_unref(&bo);
 745         return r;
 746 }
 747
 748 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 749 {
 750         struct dma_fence *fence = NULL;
 751         struct amdgpu_bo *bo;
 752         long r;
 753
 754         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
 755         if (r)
 756                 goto error;
 757
 758         r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
 759         if (r)
 760                 goto error;
 761         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
 762         if (r)
 763                 goto error;
 764
 765         r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
 766         if (r)
 767                 goto error;
 768
 769         r = dma_fence_wait_timeout(fence, false, timeout);
 770         if (r == 0)
 771                 r = -ETIMEDOUT;
 772         else if (r > 0)
 773                 r = 0;
 774
 775         dma_fence_put(fence);
 776 error:
 777         return r;
 778 }
 779
 780 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 781 {
 782         struct amdgpu_device *adev = ring->adev;
 783         uint32_t rptr;
 784         unsigned i;
 785         int r;
 786
 787         if (amdgpu_sriov_vf(adev))
 788                 return 0;
 789
 790         r = amdgpu_ring_alloc(ring, 16);
 791         if (r)
 792                 return r;
 793
 794         rptr = amdgpu_ring_get_rptr(ring);
 795
 796         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 797         amdgpu_ring_commit(ring);
 798
 799         for (i = 0; i < adev->usec_timeout; i++) {
 800                 if (amdgpu_ring_get_rptr(ring) != rptr)
 801                         break;
 802                 udelay(1);
 803         }
 804
 805         if (i >= adev->usec_timeout)
 806                 r = -ETIMEDOUT;
 807
 808         return r;
 809 }
 810
 811 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 812                                          struct amdgpu_bo *bo,
 813                                          struct dma_fence **fence)
 814 {
 815         const unsigned ib_size_dw = 16;
 816         struct amdgpu_job *job;
 817         struct amdgpu_ib *ib;
 818         struct dma_fence *f = NULL;
 819         uint64_t addr;
 820         int i, r;
 821
 822         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 823                                         AMDGPU_IB_POOL_DIRECT, &job);
 824         if (r)
 825                 return r;
 826
 827         ib = &job->ibs[0];
 828         addr = amdgpu_bo_gpu_offset(bo);
 829
 830         ib->length_dw = 0;
 831         ib->ptr[ib->length_dw++] = 0x00000018;
 832         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 833         ib->ptr[ib->length_dw++] = handle;
 834         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 835         ib->ptr[ib->length_dw++] = addr;
 836         ib->ptr[ib->length_dw++] = 0x0000000b;
 837
 838         ib->ptr[ib->length_dw++] = 0x00000014;
 839         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 840         ib->ptr[ib->length_dw++] = 0x0000001c;
 841         ib->ptr[ib->length_dw++] = 0x00000000;
 842         ib->ptr[ib->length_dw++] = 0x00000000;
 843
 844         ib->ptr[ib->length_dw++] = 0x00000008;
 845         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 846
 847         for (i = ib->length_dw; i < ib_size_dw; ++i)
 848                 ib->ptr[i] = 0x0;
 849
 850         r = amdgpu_job_submit_direct(job, ring, &f);
 851         if (r)
 852                 goto err;
 853
 854         if (fence)
 855                 *fence = dma_fence_get(f);
 856         dma_fence_put(f);
 857
 858         return 0;
 859
 860 err:
 861         amdgpu_job_free(job);
 862         return r;
 863 }
 864
 865 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 866                                           struct amdgpu_bo *bo,
 867                                           struct dma_fence **fence)
 868 {
 869         const unsigned ib_size_dw = 16;
 870         struct amdgpu_job *job;
 871         struct amdgpu_ib *ib;
 872         struct dma_fence *f = NULL;
 873         uint64_t addr;
 874         int i, r;
 875
 876         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 877                                         AMDGPU_IB_POOL_DIRECT, &job);
 878         if (r)
 879                 return r;
 880
 881         ib = &job->ibs[0];
 882         addr = amdgpu_bo_gpu_offset(bo);
 883
 884         ib->length_dw = 0;
 885         ib->ptr[ib->length_dw++] = 0x00000018;
 886         ib->ptr[ib->length_dw++] = 0x00000001;
 887         ib->ptr[ib->length_dw++] = handle;
 888         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 889         ib->ptr[ib->length_dw++] = addr;
 890         ib->ptr[ib->length_dw++] = 0x0000000b;
 891
 892         ib->ptr[ib->length_dw++] = 0x00000014;
 893         ib->ptr[ib->length_dw++] = 0x00000002;
 894         ib->ptr[ib->length_dw++] = 0x0000001c;
 895         ib->ptr[ib->length_dw++] = 0x00000000;
 896         ib->ptr[ib->length_dw++] = 0x00000000;
 897
 898         ib->ptr[ib->length_dw++] = 0x00000008;
 899         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 900
 901         for (i = ib->length_dw; i < ib_size_dw; ++i)
 902                 ib->ptr[i] = 0x0;
 903
 904         r = amdgpu_job_submit_direct(job, ring, &f);
 905         if (r)
 906                 goto err;
 907
 908         if (fence)
 909                 *fence = dma_fence_get(f);
 910         dma_fence_put(f);
 911
 912         return 0;
 913
 914 err:
 915         amdgpu_job_free(job);
 916         return r;
 917 }
 918
 919 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 920 {
 921         struct dma_fence *fence = NULL;
 922         struct amdgpu_bo *bo = NULL;
 923         long r;
 924
 925         r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
 926                                       AMDGPU_GEM_DOMAIN_VRAM,
 927                                       &bo, NULL, NULL);
 928         if (r)
 929                 return r;
 930
 931         r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
 932         if (r)
 933                 goto error;
 934
 935         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
 936         if (r)
 937                 goto error;
 938
 939         r = dma_fence_wait_timeout(fence, false, timeout);
 940         if (r == 0)
 941                 r = -ETIMEDOUT;
 942         else if (r > 0)
 943                 r = 0;
 944
 945 error:
 946         dma_fence_put(fence);
 947         amdgpu_bo_unreserve(bo);
 948         amdgpu_bo_free_kernel(&bo, NULL, NULL);
 949
 950         return r;
 951 }