2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
30 #include <linux/pm_runtime.h>
33 #include "amdgpu_ras.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_xgmi.h"
36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
39 static const char *RAS_FS_NAME = "ras";
41 const char *ras_error_string[] = {
45 "multi_uncorrectable",
49 const char *ras_block_string[] = {
66 #define ras_err_str(i) (ras_error_string[ffs(i)])
67 #define ras_block_str(i) (ras_block_string[i])
69 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
71 /* inject address is 52 bits */
72 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
74 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
75 #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
77 enum amdgpu_ras_retire_page_reservation {
78 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
79 AMDGPU_RAS_RETIRE_PAGE_PENDING,
80 AMDGPU_RAS_RETIRE_PAGE_FAULT,
83 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
85 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
87 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
90 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
92 if (adev && amdgpu_ras_get_context(adev))
93 amdgpu_ras_get_context(adev)->error_query_ready = ready;
96 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
98 if (adev && amdgpu_ras_get_context(adev))
99 return amdgpu_ras_get_context(adev)->error_query_ready;
104 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
106 struct ras_err_data err_data = {0, 0, 0, NULL};
107 struct eeprom_table_record err_rec;
109 if ((address >= adev->gmc.mc_vram_size) ||
110 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
112 "RAS WARN: input address 0x%llx is invalid.\n",
117 if (amdgpu_ras_check_bad_page(adev, address)) {
119 "RAS WARN: 0x%llx has already been marked as bad page!\n",
124 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
126 err_rec.address = address;
127 err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
128 err_rec.ts = (uint64_t)ktime_get_real_seconds();
129 err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
131 err_data.err_addr = &err_rec;
132 err_data.err_addr_cnt = 1;
134 if (amdgpu_bad_page_threshold != 0) {
135 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
136 err_data.err_addr_cnt);
137 amdgpu_ras_save_bad_pages(adev);
140 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
141 dev_warn(adev->dev, "Clear EEPROM:\n");
142 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
147 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
148 size_t size, loff_t *pos)
150 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
151 struct ras_query_if info = {
157 if (amdgpu_ras_query_error_status(obj->adev, &info))
160 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
162 "ce", info.ce_count);
167 s = min_t(u64, s, size);
170 if (copy_to_user(buf, &val[*pos], s))
178 static const struct file_operations amdgpu_ras_debugfs_ops = {
179 .owner = THIS_MODULE,
180 .read = amdgpu_ras_debugfs_read,
182 .llseek = default_llseek
185 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
189 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
191 if (strcmp(name, ras_block_str(i)) == 0)
197 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
198 const char __user *buf, size_t size,
199 loff_t *pos, struct ras_debug_if *data)
201 ssize_t s = min_t(u64, 64, size);
214 memset(str, 0, sizeof(str));
215 memset(data, 0, sizeof(*data));
217 if (copy_from_user(str, buf, s))
220 if (sscanf(str, "disable %32s", block_name) == 1)
222 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
224 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
226 else if (strstr(str, "retire_page") != NULL)
228 else if (str[0] && str[1] && str[2] && str[3])
229 /* ascii string, but commands are not matched. */
234 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
235 sscanf(str, "%*s %llu", &address) != 1)
239 data->inject.address = address;
244 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
247 data->head.block = block_id;
248 /* only ue and ce errors are supported */
249 if (!memcmp("ue", err, 2))
250 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
251 else if (!memcmp("ce", err, 2))
252 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
259 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
260 &sub_block, &address, &value) != 3 &&
261 sscanf(str, "%*s %*s %*s %u %llu %llu",
262 &sub_block, &address, &value) != 3)
264 data->head.sub_block_index = sub_block;
265 data->inject.address = address;
266 data->inject.value = value;
269 if (size < sizeof(*data))
272 if (copy_from_user(data, buf, sizeof(*data)))
280 * DOC: AMDGPU RAS debugfs control interface
282 * The control interface accepts struct ras_debug_if which has two members.
284 * First member: ras_debug_if::head or ras_debug_if::inject.
286 * head is used to indicate which IP block will be under control.
288 * head has four members, they are block, type, sub_block_index, name.
289 * block: which IP will be under control.
290 * type: what kind of error will be enabled/disabled/injected.
291 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
292 * name: the name of IP.
294 * inject has two more members than head, they are address, value.
295 * As their names indicate, inject operation will write the
296 * value to the address.
298 * The second member: struct ras_debug_if::op.
299 * It has three kinds of operations.
301 * - 0: disable RAS on the block. Take ::head as its data.
302 * - 1: enable RAS on the block. Take ::head as its data.
303 * - 2: inject errors on the block. Take ::inject as its data.
305 * How to use the interface?
309 * Copy the struct ras_debug_if in your code and initialize it.
310 * Write the struct to the control interface.
314 * .. code-block:: bash
316 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
317 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
318 * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
320 * Where N, is the card which you want to affect.
322 * "disable" requires only the block.
323 * "enable" requires the block and error type.
324 * "inject" requires the block, error type, address, and value.
326 * The block is one of: umc, sdma, gfx, etc.
327 * see ras_block_string[] for details
329 * The error type is one of: ue, ce, where,
330 * ue is multi-uncorrectable
331 * ce is single-correctable
333 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
334 * The address and value are hexadecimal numbers, leading 0x is optional.
338 * .. code-block:: bash
340 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
341 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
342 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
344 * How to check the result of the operation?
346 * To check disable/enable, see "ras" features at,
347 * /sys/class/drm/card[0/1/2...]/device/ras/features
349 * To check inject, see the corresponding error count at,
350 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
353 * Operations are only allowed on blocks which are supported.
354 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
355 * to see which blocks support RAS on a particular asic.
358 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
359 const char __user *buf,
360 size_t size, loff_t *pos)
362 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
363 struct ras_debug_if data;
366 if (!amdgpu_ras_get_error_query_ready(adev)) {
367 dev_warn(adev->dev, "RAS WARN: error injection "
368 "currently inaccessible\n");
372 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
377 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
384 if (!amdgpu_ras_is_supported(adev, data.head.block))
389 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
392 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
395 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
396 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
397 dev_warn(adev->dev, "RAS WARN: input address "
398 "0x%llx is invalid.",
399 data.inject.address);
404 /* umc ce/ue error injection for a bad page is not allowed */
405 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
406 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
407 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
408 "already been marked as bad!\n",
409 data.inject.address);
413 /* data.inject.address is offset instead of absolute gpu address */
414 ret = amdgpu_ras_error_inject(adev, &data.inject);
428 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
430 * Some boards contain an EEPROM which is used to persistently store a list of
431 * bad pages which experiences ECC errors in vram. This interface provides
432 * a way to reset the EEPROM, e.g., after testing error injection.
436 * .. code-block:: bash
438 * echo 1 > ../ras/ras_eeprom_reset
440 * will reset EEPROM table to 0 entries.
443 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
444 const char __user *buf,
445 size_t size, loff_t *pos)
447 struct amdgpu_device *adev =
448 (struct amdgpu_device *)file_inode(f)->i_private;
451 ret = amdgpu_ras_eeprom_reset_table(
452 &(amdgpu_ras_get_context(adev)->eeprom_control));
455 /* Something was written to EEPROM.
457 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
464 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
465 .owner = THIS_MODULE,
467 .write = amdgpu_ras_debugfs_ctrl_write,
468 .llseek = default_llseek
471 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
472 .owner = THIS_MODULE,
474 .write = amdgpu_ras_debugfs_eeprom_write,
475 .llseek = default_llseek
479 * DOC: AMDGPU RAS sysfs Error Count Interface
481 * It allows the user to read the error count for each IP block on the gpu through
482 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
484 * It outputs the multiple lines which report the uncorrected (ue) and corrected
487 * The format of one line is below,
493 * .. code-block:: bash
499 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
500 struct device_attribute *attr, char *buf)
502 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
503 struct ras_query_if info = {
507 if (!amdgpu_ras_get_error_query_ready(obj->adev))
508 return sysfs_emit(buf, "Query currently inaccessible\n");
510 if (amdgpu_ras_query_error_status(obj->adev, &info))
514 if (obj->adev->asic_type == CHIP_ALDEBARAN) {
515 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
516 DRM_WARN("Failed to reset error counter and error status");
519 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
520 "ce", info.ce_count);
525 #define get_obj(obj) do { (obj)->use++; } while (0)
526 #define alive_obj(obj) ((obj)->use)
528 static inline void put_obj(struct ras_manager *obj)
530 if (obj && (--obj->use == 0))
531 list_del(&obj->node);
532 if (obj && (obj->use < 0))
533 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
536 /* make one obj and return it. */
537 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
538 struct ras_common_if *head)
540 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
541 struct ras_manager *obj;
543 if (!adev->ras_enabled || !con)
546 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
549 obj = &con->objs[head->block];
550 /* already exist. return obj? */
556 list_add(&obj->node, &con->head);
562 /* return an obj equal to head, or the first when head is NULL */
563 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
564 struct ras_common_if *head)
566 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
567 struct ras_manager *obj;
570 if (!adev->ras_enabled || !con)
574 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
577 obj = &con->objs[head->block];
579 if (alive_obj(obj)) {
580 WARN_ON(head->block != obj->head.block);
584 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
586 if (alive_obj(obj)) {
587 WARN_ON(i != obj->head.block);
597 /* feature ctl begin */
598 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
599 struct ras_common_if *head)
601 return adev->ras_hw_enabled & BIT(head->block);
604 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
605 struct ras_common_if *head)
607 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
609 return con->features & BIT(head->block);
613 * if obj is not created, then create one.
614 * set feature enable flag.
616 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
617 struct ras_common_if *head, int enable)
619 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
620 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
622 /* If hardware does not support ras, then do not create obj.
623 * But if hardware support ras, we can create the obj.
624 * Ras framework checks con->hw_supported to see if it need do
625 * corresponding initialization.
626 * IP checks con->support to see if it need disable ras.
628 if (!amdgpu_ras_is_feature_allowed(adev, head))
630 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
635 obj = amdgpu_ras_create_obj(adev, head);
639 /* In case we create obj somewhere else */
642 con->features |= BIT(head->block);
644 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
645 con->features &= ~BIT(head->block);
653 /* wrapper of psp_ras_enable_features */
654 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
655 struct ras_common_if *head, bool enable)
657 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
658 union ta_ras_cmd_input *info;
664 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
669 info->disable_features = (struct ta_ras_disable_features_input) {
670 .block_id = amdgpu_ras_block_to_ta(head->block),
671 .error_type = amdgpu_ras_error_to_ta(head->type),
674 info->enable_features = (struct ta_ras_enable_features_input) {
675 .block_id = amdgpu_ras_block_to_ta(head->block),
676 .error_type = amdgpu_ras_error_to_ta(head->type),
680 /* Do not enable if it is not allowed. */
681 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
682 /* Are we alerady in that state we are going to set? */
683 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
688 if (!amdgpu_ras_intr_triggered()) {
689 ret = psp_ras_enable_features(&adev->psp, info, enable);
691 dev_err(adev->dev, "ras %s %s failed %d\n",
692 enable ? "enable":"disable",
693 ras_block_str(head->block),
700 __amdgpu_ras_feature_enable(adev, head, enable);
707 /* Only used in device probe stage and called only once. */
708 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
709 struct ras_common_if *head, bool enable)
711 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
717 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
719 /* There is no harm to issue a ras TA cmd regardless of
720 * the currecnt ras state.
721 * If current state == target state, it will do nothing
722 * But sometimes it requests driver to reset and repost
723 * with error code -EAGAIN.
725 ret = amdgpu_ras_feature_enable(adev, head, 1);
726 /* With old ras TA, we might fail to enable ras.
727 * Log it and just setup the object.
728 * TODO need remove this WA in the future.
730 if (ret == -EINVAL) {
731 ret = __amdgpu_ras_feature_enable(adev, head, 1);
734 "RAS INFO: %s setup object\n",
735 ras_block_str(head->block));
738 /* setup the object then issue a ras TA disable cmd.*/
739 ret = __amdgpu_ras_feature_enable(adev, head, 1);
743 /* gfx block ras dsiable cmd must send to ras-ta */
744 if (head->block == AMDGPU_RAS_BLOCK__GFX)
745 con->features |= BIT(head->block);
747 ret = amdgpu_ras_feature_enable(adev, head, 0);
749 /* clean gfx block ras features flag */
750 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
751 con->features &= ~BIT(head->block);
754 ret = amdgpu_ras_feature_enable(adev, head, enable);
759 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
762 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
763 struct ras_manager *obj, *tmp;
765 list_for_each_entry_safe(obj, tmp, &con->head, node) {
767 * aka just release the obj and corresponding flags
770 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
773 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
778 return con->features;
781 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
784 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
785 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
787 const enum amdgpu_ras_error_type default_ras_type =
788 AMDGPU_RAS_ERROR__NONE;
790 for (i = 0; i < ras_block_count; i++) {
791 struct ras_common_if head = {
793 .type = default_ras_type,
794 .sub_block_index = 0,
796 strcpy(head.name, ras_block_str(i));
799 * bypass psp. vbios enable ras for us.
800 * so just create the obj
802 if (__amdgpu_ras_feature_enable(adev, &head, 1))
805 if (amdgpu_ras_feature_enable(adev, &head, 1))
810 return con->features;
812 /* feature ctl end */
814 /* query/inject/cure begin */
815 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
816 struct ras_query_if *info)
818 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
819 struct ras_err_data err_data = {0, 0, 0, NULL};
825 switch (info->head.block) {
826 case AMDGPU_RAS_BLOCK__UMC:
827 if (adev->umc.ras_funcs &&
828 adev->umc.ras_funcs->query_ras_error_count)
829 adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
830 /* umc query_ras_error_address is also responsible for clearing
833 if (adev->umc.ras_funcs &&
834 adev->umc.ras_funcs->query_ras_error_address)
835 adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
837 case AMDGPU_RAS_BLOCK__SDMA:
838 if (adev->sdma.funcs->query_ras_error_count) {
839 for (i = 0; i < adev->sdma.num_instances; i++)
840 adev->sdma.funcs->query_ras_error_count(adev, i,
844 case AMDGPU_RAS_BLOCK__GFX:
845 if (adev->gfx.ras_funcs &&
846 adev->gfx.ras_funcs->query_ras_error_count)
847 adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
849 if (adev->gfx.ras_funcs &&
850 adev->gfx.ras_funcs->query_ras_error_status)
851 adev->gfx.ras_funcs->query_ras_error_status(adev);
853 case AMDGPU_RAS_BLOCK__MMHUB:
854 if (adev->mmhub.ras_funcs &&
855 adev->mmhub.ras_funcs->query_ras_error_count)
856 adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
858 if (adev->mmhub.ras_funcs &&
859 adev->mmhub.ras_funcs->query_ras_error_status)
860 adev->mmhub.ras_funcs->query_ras_error_status(adev);
862 case AMDGPU_RAS_BLOCK__PCIE_BIF:
863 if (adev->nbio.ras_funcs &&
864 adev->nbio.ras_funcs->query_ras_error_count)
865 adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
867 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
868 if (adev->gmc.xgmi.ras_funcs &&
869 adev->gmc.xgmi.ras_funcs->query_ras_error_count)
870 adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
872 case AMDGPU_RAS_BLOCK__HDP:
873 if (adev->hdp.ras_funcs &&
874 adev->hdp.ras_funcs->query_ras_error_count)
875 adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
881 obj->err_data.ue_count += err_data.ue_count;
882 obj->err_data.ce_count += err_data.ce_count;
884 info->ue_count = obj->err_data.ue_count;
885 info->ce_count = obj->err_data.ce_count;
887 if (err_data.ce_count) {
888 if (adev->smuio.funcs &&
889 adev->smuio.funcs->get_socket_id &&
890 adev->smuio.funcs->get_die_id) {
891 dev_info(adev->dev, "socket: %d, die: %d "
892 "%ld correctable hardware errors "
893 "detected in %s block, no user "
894 "action is needed.\n",
895 adev->smuio.funcs->get_socket_id(adev),
896 adev->smuio.funcs->get_die_id(adev),
897 obj->err_data.ce_count,
898 ras_block_str(info->head.block));
900 dev_info(adev->dev, "%ld correctable hardware errors "
901 "detected in %s block, no user "
902 "action is needed.\n",
903 obj->err_data.ce_count,
904 ras_block_str(info->head.block));
907 if (err_data.ue_count) {
908 if (adev->smuio.funcs &&
909 adev->smuio.funcs->get_socket_id &&
910 adev->smuio.funcs->get_die_id) {
911 dev_info(adev->dev, "socket: %d, die: %d "
912 "%ld uncorrectable hardware errors "
913 "detected in %s block\n",
914 adev->smuio.funcs->get_socket_id(adev),
915 adev->smuio.funcs->get_die_id(adev),
916 obj->err_data.ue_count,
917 ras_block_str(info->head.block));
919 dev_info(adev->dev, "%ld uncorrectable hardware errors "
920 "detected in %s block\n",
921 obj->err_data.ue_count,
922 ras_block_str(info->head.block));
929 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
930 enum amdgpu_ras_block block)
932 if (!amdgpu_ras_is_supported(adev, block))
936 case AMDGPU_RAS_BLOCK__GFX:
937 if (adev->gfx.ras_funcs &&
938 adev->gfx.ras_funcs->reset_ras_error_count)
939 adev->gfx.ras_funcs->reset_ras_error_count(adev);
941 if (adev->gfx.ras_funcs &&
942 adev->gfx.ras_funcs->reset_ras_error_status)
943 adev->gfx.ras_funcs->reset_ras_error_status(adev);
945 case AMDGPU_RAS_BLOCK__MMHUB:
946 if (adev->mmhub.ras_funcs &&
947 adev->mmhub.ras_funcs->reset_ras_error_count)
948 adev->mmhub.ras_funcs->reset_ras_error_count(adev);
950 if (adev->mmhub.ras_funcs &&
951 adev->mmhub.ras_funcs->reset_ras_error_status)
952 adev->mmhub.ras_funcs->reset_ras_error_status(adev);
954 case AMDGPU_RAS_BLOCK__SDMA:
955 if (adev->sdma.funcs->reset_ras_error_count)
956 adev->sdma.funcs->reset_ras_error_count(adev);
958 case AMDGPU_RAS_BLOCK__HDP:
959 if (adev->hdp.ras_funcs &&
960 adev->hdp.ras_funcs->reset_ras_error_count)
961 adev->hdp.ras_funcs->reset_ras_error_count(adev);
970 /* Trigger XGMI/WAFL error */
971 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
972 struct ta_ras_trigger_error_input *block_info)
976 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
977 dev_warn(adev->dev, "Failed to disallow df cstate");
979 if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
980 dev_warn(adev->dev, "Failed to disallow XGMI power down");
982 ret = psp_ras_trigger_error(&adev->psp, block_info);
984 if (amdgpu_ras_intr_triggered())
987 if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
988 dev_warn(adev->dev, "Failed to allow XGMI power down");
990 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
991 dev_warn(adev->dev, "Failed to allow df cstate");
996 /* wrapper of psp_ras_trigger_error */
997 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
998 struct ras_inject_if *info)
1000 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1001 struct ta_ras_trigger_error_input block_info = {
1002 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1003 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1004 .sub_block_index = info->head.sub_block_index,
1005 .address = info->address,
1006 .value = info->value,
1013 /* Calculate XGMI relative offset */
1014 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1015 block_info.address =
1016 amdgpu_xgmi_get_relative_phy_addr(adev,
1017 block_info.address);
1020 switch (info->head.block) {
1021 case AMDGPU_RAS_BLOCK__GFX:
1022 if (adev->gfx.ras_funcs &&
1023 adev->gfx.ras_funcs->ras_error_inject)
1024 ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1028 case AMDGPU_RAS_BLOCK__UMC:
1029 case AMDGPU_RAS_BLOCK__SDMA:
1030 case AMDGPU_RAS_BLOCK__MMHUB:
1031 case AMDGPU_RAS_BLOCK__PCIE_BIF:
1032 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1034 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1035 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1038 dev_info(adev->dev, "%s error injection is not supported yet\n",
1039 ras_block_str(info->head.block));
1044 dev_err(adev->dev, "ras inject %s failed %d\n",
1045 ras_block_str(info->head.block), ret);
1051 * amdgpu_ras_query_error_count -- Get error counts of all IPs
1052 * adev: pointer to AMD GPU device
1053 * ce_count: pointer to an integer to be set to the count of correctible errors.
1054 * ue_count: pointer to an integer to be set to the count of uncorrectible
1057 * If set, @ce_count or @ue_count, count and return the corresponding
1058 * error counts in those integer pointers. Return 0 if the device
1059 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1061 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1062 unsigned long *ce_count,
1063 unsigned long *ue_count)
1065 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1066 struct ras_manager *obj;
1067 unsigned long ce, ue;
1069 if (!adev->ras_enabled || !con)
1072 /* Don't count since no reporting.
1074 if (!ce_count && !ue_count)
1079 list_for_each_entry(obj, &con->head, node) {
1080 struct ras_query_if info = {
1085 res = amdgpu_ras_query_error_status(adev, &info);
1089 ce += info.ce_count;
1090 ue += info.ue_count;
1101 /* query/inject/cure end */
1106 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1107 struct ras_badpage **bps, unsigned int *count);
1109 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1112 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1114 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1116 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1123 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1125 * It allows user to read the bad pages of vram on the gpu through
1126 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1128 * It outputs multiple lines, and each line stands for one gpu page.
1130 * The format of one line is below,
1131 * gpu pfn : gpu page size : flags
1133 * gpu pfn and gpu page size are printed in hex format.
1134 * flags can be one of below character,
1136 * R: reserved, this gpu page is reserved and not able to use.
1138 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1139 * in next window of page_reserve.
1141 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1145 * .. code-block:: bash
1147 * 0x00000001 : 0x00001000 : R
1148 * 0x00000002 : 0x00001000 : P
1152 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1153 struct kobject *kobj, struct bin_attribute *attr,
1154 char *buf, loff_t ppos, size_t count)
1156 struct amdgpu_ras *con =
1157 container_of(attr, struct amdgpu_ras, badpages_attr);
1158 struct amdgpu_device *adev = con->adev;
1159 const unsigned int element_size =
1160 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1161 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1162 unsigned int end = div64_ul(ppos + count - 1, element_size);
1164 struct ras_badpage *bps = NULL;
1165 unsigned int bps_count = 0;
1167 memset(buf, 0, count);
1169 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1172 for (; start < end && start < bps_count; start++)
1173 s += scnprintf(&buf[s], element_size + 1,
1174 "0x%08x : 0x%08x : %1s\n",
1177 amdgpu_ras_badpage_flags_str(bps[start].flags));
1184 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1185 struct device_attribute *attr, char *buf)
1187 struct amdgpu_ras *con =
1188 container_of(attr, struct amdgpu_ras, features_attr);
1190 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1193 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1195 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1197 sysfs_remove_file_from_group(&adev->dev->kobj,
1198 &con->badpages_attr.attr,
1202 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1204 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1205 struct attribute *attrs[] = {
1206 &con->features_attr.attr,
1209 struct attribute_group group = {
1210 .name = RAS_FS_NAME,
1214 sysfs_remove_group(&adev->dev->kobj, &group);
1219 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1220 struct ras_fs_if *head)
1222 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1224 if (!obj || obj->attr_inuse)
1229 memcpy(obj->fs_data.sysfs_name,
1231 sizeof(obj->fs_data.sysfs_name));
1233 obj->sysfs_attr = (struct device_attribute){
1235 .name = obj->fs_data.sysfs_name,
1238 .show = amdgpu_ras_sysfs_read,
1240 sysfs_attr_init(&obj->sysfs_attr.attr);
1242 if (sysfs_add_file_to_group(&adev->dev->kobj,
1243 &obj->sysfs_attr.attr,
1249 obj->attr_inuse = 1;
1254 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1255 struct ras_common_if *head)
1257 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1259 if (!obj || !obj->attr_inuse)
1262 sysfs_remove_file_from_group(&adev->dev->kobj,
1263 &obj->sysfs_attr.attr,
1265 obj->attr_inuse = 0;
1271 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1273 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1274 struct ras_manager *obj, *tmp;
1276 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1277 amdgpu_ras_sysfs_remove(adev, &obj->head);
1280 if (amdgpu_bad_page_threshold != 0)
1281 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1283 amdgpu_ras_sysfs_remove_feature_node(adev);
1290 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1292 * Normally when there is an uncorrectable error, the driver will reset
1293 * the GPU to recover. However, in the event of an unrecoverable error,
1294 * the driver provides an interface to reboot the system automatically
1297 * The following file in debugfs provides that interface:
1298 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1302 * .. code-block:: bash
1304 * echo true > .../ras/auto_reboot
1308 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1310 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1311 struct drm_minor *minor = adev_to_drm(adev)->primary;
1314 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1315 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1316 &amdgpu_ras_debugfs_ctrl_ops);
1317 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1318 &amdgpu_ras_debugfs_eeprom_ops);
1319 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1320 &con->bad_page_cnt_threshold);
1321 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1322 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1323 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1324 &amdgpu_ras_debugfs_eeprom_size_ops);
1325 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1327 &amdgpu_ras_debugfs_eeprom_table_ops);
1328 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1331 * After one uncorrectable error happens, usually GPU recovery will
1332 * be scheduled. But due to the known problem in GPU recovery failing
1333 * to bring GPU back, below interface provides one direct way to
1334 * user to reboot system automatically in such case within
1335 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1336 * will never be called.
1338 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1341 * User could set this not to clean up hardware's error count register
1342 * of RAS IPs during ras recovery.
1344 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1345 &con->disable_ras_err_cnt_harvest);
1349 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1350 struct ras_fs_if *head,
1353 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1360 memcpy(obj->fs_data.debugfs_name,
1362 sizeof(obj->fs_data.debugfs_name));
1364 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1365 obj, &amdgpu_ras_debugfs_ops);
1368 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1370 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1372 struct ras_manager *obj;
1373 struct ras_fs_if fs_info;
1376 * it won't be called in resume path, no need to check
1377 * suspend and gpu reset status
1379 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1382 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1384 list_for_each_entry(obj, &con->head, node) {
1385 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1386 (obj->attr_inuse == 1)) {
1387 sprintf(fs_info.debugfs_name, "%s_err_inject",
1388 ras_block_str(obj->head.block));
1389 fs_info.head = obj->head;
1390 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1398 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1399 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1400 static DEVICE_ATTR(features, S_IRUGO,
1401 amdgpu_ras_sysfs_features_read, NULL);
1402 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1404 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1405 struct attribute_group group = {
1406 .name = RAS_FS_NAME,
1408 struct attribute *attrs[] = {
1409 &con->features_attr.attr,
1412 struct bin_attribute *bin_attrs[] = {
1418 /* add features entry */
1419 con->features_attr = dev_attr_features;
1420 group.attrs = attrs;
1421 sysfs_attr_init(attrs[0]);
1423 if (amdgpu_bad_page_threshold != 0) {
1424 /* add bad_page_features entry */
1425 bin_attr_gpu_vram_bad_pages.private = NULL;
1426 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1427 bin_attrs[0] = &con->badpages_attr;
1428 group.bin_attrs = bin_attrs;
1429 sysfs_bin_attr_init(bin_attrs[0]);
1432 r = sysfs_create_group(&adev->dev->kobj, &group);
1434 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1439 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1441 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1442 struct ras_manager *con_obj, *ip_obj, *tmp;
1444 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1445 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1446 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1452 amdgpu_ras_sysfs_remove_all(adev);
1458 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1460 struct ras_ih_data *data = &obj->ih_data;
1461 struct amdgpu_iv_entry entry;
1463 struct ras_err_data err_data = {0, 0, 0, NULL};
1465 while (data->rptr != data->wptr) {
1467 memcpy(&entry, &data->ring[data->rptr],
1468 data->element_size);
1471 data->rptr = (data->aligned_element_size +
1472 data->rptr) % data->ring_size;
1474 /* Let IP handle its data, maybe we need get the output
1475 * from the callback to udpate the error type/count, etc
1478 ret = data->cb(obj->adev, &err_data, &entry);
1479 /* ue will trigger an interrupt, and in that case
1480 * we need do a reset to recovery the whole system.
1481 * But leave IP do that recovery, here we just dispatch
1484 if (ret == AMDGPU_RAS_SUCCESS) {
1485 /* these counts could be left as 0 if
1486 * some blocks do not count error number
1488 obj->err_data.ue_count += err_data.ue_count;
1489 obj->err_data.ce_count += err_data.ce_count;
1495 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1497 struct ras_ih_data *data =
1498 container_of(work, struct ras_ih_data, ih_work);
1499 struct ras_manager *obj =
1500 container_of(data, struct ras_manager, ih_data);
1502 amdgpu_ras_interrupt_handler(obj);
1505 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1506 struct ras_dispatch_if *info)
1508 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1509 struct ras_ih_data *data = &obj->ih_data;
1514 if (data->inuse == 0)
1517 /* Might be overflow... */
1518 memcpy(&data->ring[data->wptr], info->entry,
1519 data->element_size);
1522 data->wptr = (data->aligned_element_size +
1523 data->wptr) % data->ring_size;
1525 schedule_work(&data->ih_work);
1530 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1531 struct ras_ih_if *info)
1533 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1534 struct ras_ih_data *data;
1539 data = &obj->ih_data;
1540 if (data->inuse == 0)
1543 cancel_work_sync(&data->ih_work);
1546 memset(data, 0, sizeof(*data));
1552 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1553 struct ras_ih_if *info)
1555 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1556 struct ras_ih_data *data;
1559 /* in case we registe the IH before enable ras feature */
1560 obj = amdgpu_ras_create_obj(adev, &info->head);
1566 data = &obj->ih_data;
1567 /* add the callback.etc */
1568 *data = (struct ras_ih_data) {
1571 .element_size = sizeof(struct amdgpu_iv_entry),
1576 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1578 data->aligned_element_size = ALIGN(data->element_size, 8);
1579 /* the ring can store 64 iv entries. */
1580 data->ring_size = 64 * data->aligned_element_size;
1581 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1593 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1595 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1596 struct ras_manager *obj, *tmp;
1598 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1599 struct ras_ih_if info = {
1602 amdgpu_ras_interrupt_remove_handler(adev, &info);
1609 /* traversal all IPs except NBIO to query error counter */
1610 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1612 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1613 struct ras_manager *obj;
1615 if (!adev->ras_enabled || !con)
1618 list_for_each_entry(obj, &con->head, node) {
1619 struct ras_query_if info = {
1624 * PCIE_BIF IP has one different isr by ras controller
1625 * interrupt, the specific ras counter query will be
1626 * done in that isr. So skip such block from common
1627 * sync flood interrupt isr calling.
1629 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1632 amdgpu_ras_query_error_status(adev, &info);
1636 /* Parse RdRspStatus and WrRspStatus */
1637 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1638 struct ras_query_if *info)
1641 * Only two block need to query read/write
1642 * RspStatus at current state
1644 switch (info->head.block) {
1645 case AMDGPU_RAS_BLOCK__GFX:
1646 if (adev->gfx.ras_funcs &&
1647 adev->gfx.ras_funcs->query_ras_error_status)
1648 adev->gfx.ras_funcs->query_ras_error_status(adev);
1650 case AMDGPU_RAS_BLOCK__MMHUB:
1651 if (adev->mmhub.ras_funcs &&
1652 adev->mmhub.ras_funcs->query_ras_error_status)
1653 adev->mmhub.ras_funcs->query_ras_error_status(adev);
1660 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1662 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1663 struct ras_manager *obj;
1665 if (!adev->ras_enabled || !con)
1668 list_for_each_entry(obj, &con->head, node) {
1669 struct ras_query_if info = {
1673 amdgpu_ras_error_status_query(adev, &info);
1677 /* recovery begin */
1679 /* return 0 on success.
1680 * caller need free bps.
1682 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1683 struct ras_badpage **bps, unsigned int *count)
1685 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1686 struct ras_err_handler_data *data;
1688 int ret = 0, status;
1690 if (!con || !con->eh_data || !bps || !count)
1693 mutex_lock(&con->recovery_lock);
1694 data = con->eh_data;
1695 if (!data || data->count == 0) {
1701 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1707 for (; i < data->count; i++) {
1708 (*bps)[i] = (struct ras_badpage){
1709 .bp = data->bps[i].retired_page,
1710 .size = AMDGPU_GPU_PAGE_SIZE,
1711 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1713 status = amdgpu_vram_mgr_query_page_status(
1714 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1715 data->bps[i].retired_page);
1716 if (status == -EBUSY)
1717 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1718 else if (status == -ENOENT)
1719 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1722 *count = data->count;
1724 mutex_unlock(&con->recovery_lock);
1728 static void amdgpu_ras_do_recovery(struct work_struct *work)
1730 struct amdgpu_ras *ras =
1731 container_of(work, struct amdgpu_ras, recovery_work);
1732 struct amdgpu_device *remote_adev = NULL;
1733 struct amdgpu_device *adev = ras->adev;
1734 struct list_head device_list, *device_list_handle = NULL;
1736 if (!ras->disable_ras_err_cnt_harvest) {
1737 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1739 /* Build list of devices to query RAS related errors */
1740 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1741 device_list_handle = &hive->device_list;
1743 INIT_LIST_HEAD(&device_list);
1744 list_add_tail(&adev->gmc.xgmi.head, &device_list);
1745 device_list_handle = &device_list;
1748 list_for_each_entry(remote_adev,
1749 device_list_handle, gmc.xgmi.head) {
1750 amdgpu_ras_query_err_status(remote_adev);
1751 amdgpu_ras_log_on_err_counter(remote_adev);
1754 amdgpu_put_xgmi_hive(hive);
1757 if (amdgpu_device_should_recover_gpu(ras->adev))
1758 amdgpu_device_gpu_recover(ras->adev, NULL);
1759 atomic_set(&ras->in_recovery, 0);
1762 /* alloc/realloc bps array */
1763 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1764 struct ras_err_handler_data *data, int pages)
1766 unsigned int old_space = data->count + data->space_left;
1767 unsigned int new_space = old_space + pages;
1768 unsigned int align_space = ALIGN(new_space, 512);
1769 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1777 memcpy(bps, data->bps,
1778 data->count * sizeof(*data->bps));
1783 data->space_left += align_space - old_space;
1787 /* it deal with vram only. */
1788 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1789 struct eeprom_table_record *bps, int pages)
1791 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1792 struct ras_err_handler_data *data;
1796 if (!con || !con->eh_data || !bps || pages <= 0)
1799 mutex_lock(&con->recovery_lock);
1800 data = con->eh_data;
1804 for (i = 0; i < pages; i++) {
1805 if (amdgpu_ras_check_bad_page_unlock(con,
1806 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1809 if (!data->space_left &&
1810 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1815 amdgpu_vram_mgr_reserve_range(
1816 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1817 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1818 AMDGPU_GPU_PAGE_SIZE);
1820 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1825 mutex_unlock(&con->recovery_lock);
1831 * write error record array to eeprom, the function should be
1832 * protected by recovery_lock
1834 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1836 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1837 struct ras_err_handler_data *data;
1838 struct amdgpu_ras_eeprom_control *control;
1841 if (!con || !con->eh_data)
1844 control = &con->eeprom_control;
1845 data = con->eh_data;
1846 save_count = data->count - control->ras_num_recs;
1847 /* only new entries are saved */
1848 if (save_count > 0) {
1849 if (amdgpu_ras_eeprom_append(control,
1850 &data->bps[control->ras_num_recs],
1852 dev_err(adev->dev, "Failed to save EEPROM table data!");
1856 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1863 * read error record array in eeprom and reserve enough space for
1864 * storing new bad pages
1866 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1868 struct amdgpu_ras_eeprom_control *control =
1869 &adev->psp.ras.ras->eeprom_control;
1870 struct eeprom_table_record *bps;
1873 /* no bad page record, skip eeprom access */
1874 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
1877 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
1881 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
1883 dev_err(adev->dev, "Failed to load EEPROM table records!");
1885 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
1891 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1894 struct ras_err_handler_data *data = con->eh_data;
1897 addr >>= AMDGPU_GPU_PAGE_SHIFT;
1898 for (i = 0; i < data->count; i++)
1899 if (addr == data->bps[i].retired_page)
1906 * check if an address belongs to bad page
1908 * Note: this check is only for umc block
1910 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1913 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1916 if (!con || !con->eh_data)
1919 mutex_lock(&con->recovery_lock);
1920 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1921 mutex_unlock(&con->recovery_lock);
1925 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1928 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1931 * Justification of value bad_page_cnt_threshold in ras structure
1933 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1934 * in eeprom, and introduce two scenarios accordingly.
1936 * Bad page retirement enablement:
1937 * - If amdgpu_bad_page_threshold = -1,
1938 * bad_page_cnt_threshold = typical value by formula.
1940 * - When the value from user is 0 < amdgpu_bad_page_threshold <
1941 * max record length in eeprom, use it directly.
1943 * Bad page retirement disablement:
1944 * - If amdgpu_bad_page_threshold = 0, bad page retirement
1945 * functionality is disabled, and bad_page_cnt_threshold will
1949 if (amdgpu_bad_page_threshold < 0) {
1950 u64 val = adev->gmc.mc_vram_size;
1952 do_div(val, RAS_BAD_PAGE_COVER);
1953 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1956 con->bad_page_cnt_threshold = min_t(int, max_count,
1957 amdgpu_bad_page_threshold);
1961 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1963 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1964 struct ras_err_handler_data **data;
1965 u32 max_eeprom_records_count = 0;
1966 bool exc_err_limit = false;
1972 /* Allow access to RAS EEPROM via debugfs, when the ASIC
1973 * supports RAS and debugfs is enabled, but when
1974 * adev->ras_enabled is unset, i.e. when "ras_enable"
1975 * module parameter is set to 0.
1979 if (!adev->ras_enabled)
1982 data = &con->eh_data;
1983 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1989 mutex_init(&con->recovery_lock);
1990 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1991 atomic_set(&con->in_recovery, 0);
1993 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
1994 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
1996 /* Todo: During test the SMU might fail to read the eeprom through I2C
1997 * when the GPU is pending on XGMI reset during probe time
1998 * (Mostly after second bus reset), skip it now
2000 if (adev->gmc.xgmi.pending_reset)
2002 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2004 * This calling fails when exc_err_limit is true or
2007 if (exc_err_limit || ret)
2010 if (con->eeprom_control.ras_num_recs) {
2011 ret = amdgpu_ras_load_bad_pages(adev);
2015 if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
2016 adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
2022 kfree((*data)->bps);
2024 con->eh_data = NULL;
2026 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2029 * Except error threshold exceeding case, other failure cases in this
2030 * function would not fail amdgpu driver init.
2040 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2042 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2043 struct ras_err_handler_data *data = con->eh_data;
2045 /* recovery_init failed to init it, fini is useless */
2049 cancel_work_sync(&con->recovery_work);
2051 mutex_lock(&con->recovery_lock);
2052 con->eh_data = NULL;
2055 mutex_unlock(&con->recovery_lock);
2061 /* return 0 if ras will reset gpu and repost.*/
2062 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2065 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2070 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2074 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2076 return adev->asic_type == CHIP_VEGA10 ||
2077 adev->asic_type == CHIP_VEGA20 ||
2078 adev->asic_type == CHIP_ARCTURUS ||
2079 adev->asic_type == CHIP_ALDEBARAN ||
2080 adev->asic_type == CHIP_SIENNA_CICHLID;
2084 * this is workaround for vega20 workstation sku,
2085 * force enable gfx ras, ignore vbios gfx ras flag
2086 * due to GC EDC can not write
2088 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2090 struct atom_context *ctx = adev->mode_info.atom_context;
2095 if (strnstr(ctx->vbios_version, "D16406",
2096 sizeof(ctx->vbios_version)) ||
2097 strnstr(ctx->vbios_version, "D36002",
2098 sizeof(ctx->vbios_version)))
2099 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2103 * check hardware's ras ability which will be saved in hw_supported.
2104 * if hardware does not support ras, we can skip some ras initializtion and
2105 * forbid some ras operations from IP.
2106 * if software itself, say boot parameter, limit the ras ability. We still
2107 * need allow IP do some limited operations, like disable. In such case,
2108 * we have to initialize ras as normal. but need check if operation is
2109 * allowed or not in each function.
2111 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2113 adev->ras_hw_enabled = adev->ras_enabled = 0;
2115 if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2116 !amdgpu_ras_asic_supported(adev))
2119 if (!adev->gmc.xgmi.connected_to_cpu) {
2120 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2121 dev_info(adev->dev, "MEM ECC is active.\n");
2122 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2123 1 << AMDGPU_RAS_BLOCK__DF);
2125 dev_info(adev->dev, "MEM ECC is not presented.\n");
2128 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2129 dev_info(adev->dev, "SRAM ECC is active.\n");
2130 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2131 1 << AMDGPU_RAS_BLOCK__DF);
2133 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2136 /* driver only manages a few IP blocks RAS feature
2137 * when GPU is connected cpu through XGMI */
2138 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2139 1 << AMDGPU_RAS_BLOCK__SDMA |
2140 1 << AMDGPU_RAS_BLOCK__MMHUB);
2143 amdgpu_ras_get_quirks(adev);
2145 /* hw_supported needs to be aligned with RAS block mask. */
2146 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2148 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2149 adev->ras_hw_enabled & amdgpu_ras_mask;
2152 static void amdgpu_ras_counte_dw(struct work_struct *work)
2154 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2155 ras_counte_delay_work.work);
2156 struct amdgpu_device *adev = con->adev;
2157 struct drm_device *dev = adev_to_drm(adev);
2158 unsigned long ce_count, ue_count;
2161 res = pm_runtime_get_sync(dev->dev);
2165 /* Cache new values.
2167 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2168 atomic_set(&con->ras_ce_count, ce_count);
2169 atomic_set(&con->ras_ue_count, ue_count);
2172 pm_runtime_mark_last_busy(dev->dev);
2174 pm_runtime_put_autosuspend(dev->dev);
2177 int amdgpu_ras_init(struct amdgpu_device *adev)
2179 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2185 con = kmalloc(sizeof(struct amdgpu_ras) +
2186 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2187 GFP_KERNEL|__GFP_ZERO);
2192 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2193 atomic_set(&con->ras_ce_count, 0);
2194 atomic_set(&con->ras_ue_count, 0);
2196 con->objs = (struct ras_manager *)(con + 1);
2198 amdgpu_ras_set_context(adev, con);
2200 amdgpu_ras_check_supported(adev);
2202 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2203 /* set gfx block ras context feature for VEGA20 Gaming
2204 * send ras disable cmd to ras ta during ras late init.
2206 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2207 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2217 INIT_LIST_HEAD(&con->head);
2218 /* Might need get this flag from vbios. */
2219 con->flags = RAS_DEFAULT_FLAGS;
2221 /* initialize nbio ras function ahead of any other
2222 * ras functions so hardware fatal error interrupt
2223 * can be enabled as early as possible */
2224 switch (adev->asic_type) {
2227 case CHIP_ALDEBARAN:
2228 if (!adev->gmc.xgmi.connected_to_cpu)
2229 adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2232 /* nbio ras is not available */
2236 if (adev->nbio.ras_funcs &&
2237 adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2238 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2243 if (adev->nbio.ras_funcs &&
2244 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2245 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2250 if (amdgpu_ras_fs_init(adev)) {
2255 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2256 "hardware ability[%x] ras_mask[%x]\n",
2257 adev->ras_hw_enabled, adev->ras_enabled);
2261 amdgpu_ras_set_context(adev, NULL);
2267 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2269 if (adev->gmc.xgmi.connected_to_cpu)
2274 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2275 struct ras_common_if *ras_block)
2277 struct ras_query_if info = {
2281 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2284 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2285 DRM_WARN("RAS init harvest failure");
2287 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2288 DRM_WARN("RAS init harvest reset failure");
2293 /* helper function to handle common stuff in ip late init phase */
2294 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2295 struct ras_common_if *ras_block,
2296 struct ras_fs_if *fs_info,
2297 struct ras_ih_if *ih_info)
2299 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2300 unsigned long ue_count, ce_count;
2303 /* disable RAS feature per IP block if it is not supported */
2304 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2305 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2309 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2312 /* request gpu reset. will run again */
2313 amdgpu_ras_request_reset_on_boot(adev,
2316 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2317 /* in resume phase, if fail to enable ras,
2318 * clean up all ras fs nodes, and disable ras */
2324 /* check for errors on warm reset edc persisant supported ASIC */
2325 amdgpu_persistent_edc_harvesting(adev, ras_block);
2327 /* in resume phase, no need to create ras fs node */
2328 if (adev->in_suspend || amdgpu_in_reset(adev))
2332 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2337 r = amdgpu_ras_sysfs_create(adev, fs_info);
2341 /* Those are the cached values at init.
2343 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2344 atomic_set(&con->ras_ce_count, ce_count);
2345 atomic_set(&con->ras_ue_count, ue_count);
2350 amdgpu_ras_sysfs_remove(adev, ras_block);
2353 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2355 amdgpu_ras_feature_enable(adev, ras_block, 0);
2359 /* helper function to remove ras fs node and interrupt handler */
2360 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2361 struct ras_common_if *ras_block,
2362 struct ras_ih_if *ih_info)
2364 if (!ras_block || !ih_info)
2367 amdgpu_ras_sysfs_remove(adev, ras_block);
2369 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2370 amdgpu_ras_feature_enable(adev, ras_block, 0);
2373 /* do some init work after IP late init as dependence.
2374 * and it runs in resume/gpu reset/booting up cases.
2376 void amdgpu_ras_resume(struct amdgpu_device *adev)
2378 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2379 struct ras_manager *obj, *tmp;
2381 if (!adev->ras_enabled || !con) {
2382 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2383 amdgpu_release_ras_context(adev);
2388 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2389 /* Set up all other IPs which are not implemented. There is a
2390 * tricky thing that IP's actual ras error type should be
2391 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2392 * ERROR_NONE make sense anyway.
2394 amdgpu_ras_enable_all_features(adev, 1);
2396 /* We enable ras on all hw_supported block, but as boot
2397 * parameter might disable some of them and one or more IP has
2398 * not implemented yet. So we disable them on behalf.
2400 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2401 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2402 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2403 /* there should be no any reference. */
2404 WARN_ON(alive_obj(obj));
2409 if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2410 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2411 /* setup ras obj state as disabled.
2412 * for init_by_vbios case.
2413 * if we want to enable ras, just enable it in a normal way.
2414 * If we want do disable it, need setup ras obj as enabled,
2415 * then issue another TA disable cmd.
2416 * See feature_enable_on_boot
2418 amdgpu_ras_disable_all_features(adev, 1);
2419 amdgpu_ras_reset_gpu(adev);
2423 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2425 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2427 if (!adev->ras_enabled || !con)
2430 amdgpu_ras_disable_all_features(adev, 0);
2431 /* Make sure all ras objects are disabled. */
2433 amdgpu_ras_disable_all_features(adev, 1);
2436 /* do some fini work before IP fini as dependence */
2437 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2439 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2441 if (!adev->ras_enabled || !con)
2445 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2446 amdgpu_ras_disable_all_features(adev, 0);
2447 amdgpu_ras_recovery_fini(adev);
2451 int amdgpu_ras_fini(struct amdgpu_device *adev)
2453 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2455 if (!adev->ras_enabled || !con)
2458 amdgpu_ras_fs_fini(adev);
2459 amdgpu_ras_interrupt_remove_all(adev);
2461 WARN(con->features, "Feature mask is not cleared");
2464 amdgpu_ras_disable_all_features(adev, 1);
2466 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2468 amdgpu_ras_set_context(adev, NULL);
2474 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2476 amdgpu_ras_check_supported(adev);
2477 if (!adev->ras_hw_enabled)
2480 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2481 dev_info(adev->dev, "uncorrectable hardware error"
2482 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2484 amdgpu_ras_reset_gpu(adev);
2488 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2490 if (adev->asic_type == CHIP_VEGA20 &&
2491 adev->pm.fw_version <= 0x283400) {
2492 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2493 amdgpu_ras_intr_triggered();
2499 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2501 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2506 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2507 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2508 amdgpu_ras_set_context(adev, NULL);