2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __AMDGPU_PSP_H__
26 #define __AMDGPU_PSP_H__
29 #include "psp_gfx_if.h"
30 #include "ta_xgmi_if.h"
31 #include "ta_ras_if.h"
32 #include "ta_rap_if.h"
33 #include "ta_secureDisplay_if.h"
35 #define PSP_FENCE_BUFFER_SIZE 0x1000
36 #define PSP_CMD_BUFFER_SIZE 0x1000
37 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
38 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
39 #define PSP_1_MEG 0x100000
40 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
41 #define PSP_HDCP_SHARED_MEM_SIZE 0x4000
42 #define PSP_DTM_SHARED_MEM_SIZE 0x4000
43 #define PSP_RAP_SHARED_MEM_SIZE 0x4000
44 #define PSP_SECUREDISPLAY_SHARED_MEM_SIZE 0x4000
45 #define PSP_SHARED_MEM_SIZE 0x4000
46 #define PSP_FW_NAME_LEN 0x24
49 struct psp_xgmi_node_info;
50 struct psp_xgmi_topology_info;
53 enum psp_bootloader_cmd {
54 PSP_BL__LOAD_SYSDRV = 0x10000,
55 PSP_BL__LOAD_SOSDRV = 0x20000,
56 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
57 PSP_BL__LOAD_SOCDRV = 0xB0000,
58 PSP_BL__LOAD_INTFDRV = 0xC0000,
59 PSP_BL__LOAD_DBGDRV = 0xD0000,
60 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
61 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
62 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
67 PSP_RING_TYPE__INVALID = 0,
69 * These values map to the way the PSP kernel identifies the
72 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
73 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
78 enum psp_ring_type ring_type;
79 struct psp_gfx_rb_frame *ring_mem;
80 uint64_t ring_mem_mc_addr;
81 void *ring_mem_handle;
86 /* More registers may will be supported */
87 enum psp_reg_prog_id {
88 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
89 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
90 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
96 int (*init_microcode)(struct psp_context *psp);
97 int (*bootloader_load_kdb)(struct psp_context *psp);
98 int (*bootloader_load_spl)(struct psp_context *psp);
99 int (*bootloader_load_sysdrv)(struct psp_context *psp);
100 int (*bootloader_load_soc_drv)(struct psp_context *psp);
101 int (*bootloader_load_intf_drv)(struct psp_context *psp);
102 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
103 int (*bootloader_load_sos)(struct psp_context *psp);
104 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
105 int (*ring_create)(struct psp_context *psp,
106 enum psp_ring_type ring_type);
107 int (*ring_stop)(struct psp_context *psp,
108 enum psp_ring_type ring_type);
109 int (*ring_destroy)(struct psp_context *psp,
110 enum psp_ring_type ring_type);
111 bool (*smu_reload_quirk)(struct psp_context *psp);
112 int (*mode1_reset)(struct psp_context *psp);
113 int (*mem_training)(struct psp_context *psp, uint32_t ops);
114 uint32_t (*ring_get_wptr)(struct psp_context *psp);
115 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
116 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
117 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
120 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
121 struct psp_xgmi_node_info {
124 uint8_t is_sharing_enabled;
125 enum ta_xgmi_assigned_sdma_engine sdma_engine;
129 struct psp_xgmi_topology_info {
131 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
134 struct psp_asd_context {
135 bool asd_initialized;
139 struct ta_mem_context {
140 struct amdgpu_bo *shared_bo;
141 uint64_t shared_mc_addr;
148 struct ta_mem_context mem_context;
151 struct ta_cp_context {
152 struct ta_context context;
156 struct psp_xgmi_context {
157 struct ta_context context;
158 struct psp_xgmi_topology_info top_info;
159 bool supports_extended_data;
162 struct psp_ras_context {
163 struct ta_context context;
164 struct amdgpu_ras *ras;
167 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
168 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
169 #define GDDR6_MEM_TRAINING_OFFSET 0x8000
170 /*Define the VRAM size that will be encroached by BIST training.*/
171 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
173 enum psp_memory_training_init_flag {
174 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
175 PSP_MEM_TRAIN_SUPPORT = 0x1,
176 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
177 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
178 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
181 enum psp_memory_training_ops {
182 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
183 PSP_MEM_TRAIN_SAVE = 0x2,
184 PSP_MEM_TRAIN_RESTORE = 0x4,
185 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
186 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
187 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
190 struct psp_memory_training_context {
191 /*training data size*/
195 * cpu virtual address
196 * system memory buffer that used to store the training data.
200 /*vram offset of the p2c training data*/
201 u64 p2c_train_data_offset;
203 /*vram offset of the c2p training data*/
204 u64 c2p_train_data_offset;
205 struct amdgpu_bo *c2p_bo;
207 enum psp_memory_training_init_flag init;
209 bool enable_mem_training;
212 /** PSP runtime DB **/
213 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
214 #define PSP_RUNTIME_DB_OFFSET 0x100000
215 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
216 #define PSP_RUNTIME_DB_VER_1 0x0100
217 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
219 enum psp_runtime_entry_type {
220 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
221 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
222 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
223 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
224 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
225 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
228 /* PSP runtime DB header */
229 struct psp_runtime_data_header {
230 /* determine the existence of runtime db */
232 /* version of runtime db */
236 /* PSP runtime DB entry */
237 struct psp_runtime_entry {
238 /* type of runtime db entry */
240 /* offset of entry in bytes */
242 /* size of entry in bytes */
246 /* PSP runtime DB directory */
247 struct psp_runtime_data_directory {
248 /* number of valid entries */
249 uint16_t entry_count;
251 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
254 /* PSP runtime DB boot config feature bitmask */
255 enum psp_runtime_boot_cfg_feature {
256 BOOT_CFG_FEATURE_GECC = 0x1,
257 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
260 /* PSP runtime DB boot config entry */
261 struct psp_runtime_boot_cfg_entry {
262 uint32_t boot_cfg_bitmask;
266 struct psp_bin_desc {
268 uint32_t feature_version;
275 struct amdgpu_device *adev;
276 struct psp_ring km_ring;
277 struct psp_gfx_cmd_resp *cmd;
279 const struct psp_funcs *funcs;
281 /* firmware buffer */
282 struct amdgpu_bo *fw_pri_bo;
283 uint64_t fw_pri_mc_addr;
287 const struct firmware *sos_fw;
288 struct psp_bin_desc sys;
289 struct psp_bin_desc sos;
290 struct psp_bin_desc toc;
291 struct psp_bin_desc kdb;
292 struct psp_bin_desc spl;
293 struct psp_bin_desc rl;
294 struct psp_bin_desc soc_drv;
295 struct psp_bin_desc intf_drv;
296 struct psp_bin_desc dbg_drv;
299 struct amdgpu_bo *tmr_bo;
300 uint64_t tmr_mc_addr;
303 const struct firmware *asd_fw;
304 struct psp_bin_desc asd;
307 const struct firmware *toc_fw;
310 struct amdgpu_bo *fence_buf_bo;
311 uint64_t fence_buf_mc_addr;
315 struct amdgpu_bo *cmd_buf_bo;
316 uint64_t cmd_buf_mc_addr;
317 struct psp_gfx_cmd_resp *cmd_buf_mem;
319 /* fence value associated with cmd buffer */
320 atomic_t fence_value;
321 /* flag to mark whether gfx fw autoload is supported or not */
322 bool autoload_supported;
323 /* flag to mark whether df cstate management centralized to PMFW */
324 bool pmfw_centralized_cstate_management;
326 /* xgmi ta firmware and buffer */
327 const struct firmware *ta_fw;
328 uint32_t ta_fw_version;
329 struct psp_bin_desc xgmi;
330 struct psp_bin_desc ras;
331 struct psp_bin_desc hdcp;
332 struct psp_bin_desc dtm;
333 struct psp_bin_desc rap;
334 struct psp_bin_desc securedisplay;
336 struct psp_asd_context asd_context;
337 struct psp_xgmi_context xgmi_context;
338 struct psp_ras_context ras_context;
339 struct ta_cp_context hdcp_context;
340 struct ta_cp_context dtm_context;
341 struct ta_cp_context rap_context;
342 struct ta_cp_context securedisplay_context;
344 struct psp_memory_training_context mem_train_ctx;
346 uint32_t boot_cfg_bitmask;
349 struct amdgpu_psp_funcs {
350 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
351 enum AMDGPU_UCODE_ID);
355 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
356 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
357 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
358 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
359 #define psp_init_microcode(psp) \
360 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
361 #define psp_bootloader_load_kdb(psp) \
362 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
363 #define psp_bootloader_load_spl(psp) \
364 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
365 #define psp_bootloader_load_sysdrv(psp) \
366 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
367 #define psp_bootloader_load_soc_drv(psp) \
368 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
369 #define psp_bootloader_load_intf_drv(psp) \
370 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
371 #define psp_bootloader_load_dbg_drv(psp) \
372 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
373 #define psp_bootloader_load_sos(psp) \
374 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
375 #define psp_smu_reload_quirk(psp) \
376 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
377 #define psp_mode1_reset(psp) \
378 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
379 #define psp_mem_training(psp, ops) \
380 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
382 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
383 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
385 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
386 ((psp)->funcs->load_usbc_pd_fw ? \
387 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
389 #define psp_read_usbc_pd_fw(psp, fw_ver) \
390 ((psp)->funcs->read_usbc_pd_fw ? \
391 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
393 extern const struct amd_ip_funcs psp_ip_funcs;
395 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
396 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
397 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
398 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
399 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
400 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
402 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
403 uint32_t field_val, uint32_t mask, bool check_changed);
405 int psp_gpu_reset(struct amdgpu_device *adev);
406 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
407 uint64_t cmd_gpu_addr, int cmd_size);
409 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
410 int psp_xgmi_terminate(struct psp_context *psp);
411 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
412 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
413 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
414 int psp_xgmi_get_topology_info(struct psp_context *psp,
416 struct psp_xgmi_topology_info *topology,
417 bool get_extended_data);
418 int psp_xgmi_set_topology_info(struct psp_context *psp,
420 struct psp_xgmi_topology_info *topology);
422 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
423 int psp_ras_enable_features(struct psp_context *psp,
424 union ta_ras_cmd_input *info, bool enable);
425 int psp_ras_trigger_error(struct psp_context *psp,
426 struct ta_ras_trigger_error_input *info);
428 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
429 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
430 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
431 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
433 int psp_rlc_autoload_start(struct psp_context *psp);
435 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
437 int psp_ring_cmd_submit(struct psp_context *psp,
438 uint64_t cmd_buf_mc_addr,
439 uint64_t fence_mc_addr,
441 int psp_init_asd_microcode(struct psp_context *psp,
442 const char *chip_name);
443 int psp_init_toc_microcode(struct psp_context *psp,
444 const char *chip_name);
445 int psp_init_sos_microcode(struct psp_context *psp,
446 const char *chip_name);
447 int psp_init_ta_microcode(struct psp_context *psp,
448 const char *chip_name);
449 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
450 uint64_t *output_ptr);
452 int psp_load_fw_list(struct psp_context *psp,
453 struct amdgpu_firmware_info **ucode_list, int ucode_count);
454 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
456 int is_psp_fw_valid(struct psp_bin_desc bin);