2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
41 #include "amdgpu_ras.h"
42 #include "amdgpu_securedisplay.h"
43 #include "amdgpu_atomfirmware.h"
45 static int psp_sysfs_init(struct amdgpu_device *adev);
46 static void psp_sysfs_fini(struct amdgpu_device *adev);
48 static int psp_load_smu_fw(struct psp_context *psp);
51 * Due to DF Cstate management centralized to PMFW, the firmware
52 * loading sequence will be updated as below:
58 * - Load other non-psp fw
60 * - Load XGMI/RAS/HDCP/DTM TA if any
62 * This new sequence is required for
63 * - Arcturus and onwards
64 * - Navi12 and onwards
66 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
68 struct amdgpu_device *adev = psp->adev;
70 psp->pmfw_centralized_cstate_management = false;
72 if (amdgpu_sriov_vf(adev))
75 if (adev->flags & AMD_IS_APU)
78 if ((adev->asic_type >= CHIP_ARCTURUS) ||
79 (adev->asic_type >= CHIP_NAVI12))
80 psp->pmfw_centralized_cstate_management = true;
83 static int psp_early_init(void *handle)
85 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
86 struct psp_context *psp = &adev->psp;
88 switch (adev->asic_type) {
91 psp_v3_1_set_psp_funcs(psp);
92 psp->autoload_supported = false;
95 psp_v10_0_set_psp_funcs(psp);
96 psp->autoload_supported = false;
100 psp_v11_0_set_psp_funcs(psp);
101 psp->autoload_supported = false;
106 case CHIP_SIENNA_CICHLID:
107 case CHIP_NAVY_FLOUNDER:
109 case CHIP_DIMGREY_CAVEFISH:
110 case CHIP_BEIGE_GOBY:
111 psp_v11_0_set_psp_funcs(psp);
112 psp->autoload_supported = true;
115 psp_v12_0_set_psp_funcs(psp);
118 psp_v13_0_set_psp_funcs(psp);
120 case CHIP_YELLOW_CARP:
121 psp_v13_0_set_psp_funcs(psp);
122 psp->autoload_supported = true;
124 case CHIP_CYAN_SKILLFISH:
125 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
126 psp_v11_0_8_set_psp_funcs(psp);
127 psp->autoload_supported = false;
136 psp_check_pmfw_centralized_cstate_management(psp);
141 static void psp_memory_training_fini(struct psp_context *psp)
143 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
145 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
146 kfree(ctx->sys_cache);
147 ctx->sys_cache = NULL;
150 static int psp_memory_training_init(struct psp_context *psp)
153 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
155 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
156 DRM_DEBUG("memory training is not supported!\n");
160 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
161 if (ctx->sys_cache == NULL) {
162 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
167 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
168 ctx->train_data_size,
169 ctx->p2c_train_data_offset,
170 ctx->c2p_train_data_offset);
171 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
175 psp_memory_training_fini(psp);
180 * Helper funciton to query psp runtime database entry
182 * @adev: amdgpu_device pointer
183 * @entry_type: the type of psp runtime database entry
184 * @db_entry: runtime database entry pointer
186 * Return false if runtime database doesn't exit or entry is invalid
187 * or true if the specific database entry is found, and copy to @db_entry
189 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
190 enum psp_runtime_entry_type entry_type,
193 uint64_t db_header_pos, db_dir_pos;
194 struct psp_runtime_data_header db_header = {0};
195 struct psp_runtime_data_directory db_dir = {0};
199 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
200 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
202 /* read runtime db header from vram */
203 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
204 sizeof(struct psp_runtime_data_header), false);
206 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
207 /* runtime db doesn't exist, exit */
208 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
212 /* read runtime database entry from vram */
213 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
214 sizeof(struct psp_runtime_data_directory), false);
216 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
217 /* invalid db entry count, exit */
218 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
222 /* look up for requested entry type */
223 for (i = 0; i < db_dir.entry_count && !ret; i++) {
224 if (db_dir.entry_list[i].entry_type == entry_type) {
225 switch (entry_type) {
226 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
227 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
228 /* invalid db entry size */
229 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
232 /* read runtime database entry */
233 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
234 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
247 static int psp_sw_init(void *handle)
249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
250 struct psp_context *psp = &adev->psp;
252 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
253 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
255 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
257 DRM_ERROR("Failed to allocate memory to command buffer!\n");
261 if (!amdgpu_sriov_vf(adev)) {
262 ret = psp_init_microcode(psp);
264 DRM_ERROR("Failed to load psp firmware!\n");
267 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
268 ret = psp_init_ta_microcode(psp, "aldebaran");
270 DRM_ERROR("Failed to initialize ta microcode!\n");
275 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
276 if (psp_get_runtime_db_entry(adev,
277 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
279 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
280 if ((psp->boot_cfg_bitmask) &
281 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
282 /* If psp runtime database exists, then
283 * only enable two stage memory training
284 * when TWO_STAGE_DRAM_TRAINING bit is set
285 * in runtime database */
286 mem_training_ctx->enable_mem_training = true;
290 /* If psp runtime database doesn't exist or
291 * is invalid, force enable two stage memory
293 mem_training_ctx->enable_mem_training = true;
296 if (mem_training_ctx->enable_mem_training) {
297 ret = psp_memory_training_init(psp);
299 DRM_ERROR("Failed to initialize memory training!\n");
303 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
305 DRM_ERROR("Failed to process memory training!\n");
310 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
311 ret= psp_sysfs_init(adev);
320 static int psp_sw_fini(void *handle)
322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
323 struct psp_context *psp = &adev->psp;
324 struct psp_gfx_cmd_resp *cmd = psp->cmd;
326 psp_memory_training_fini(psp);
328 release_firmware(psp->sos_fw);
332 release_firmware(psp->asd_fw);
336 release_firmware(psp->ta_fw);
340 if (adev->asic_type == CHIP_NAVI10 ||
341 adev->asic_type == CHIP_SIENNA_CICHLID)
342 psp_sysfs_fini(adev);
350 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
351 uint32_t reg_val, uint32_t mask, bool check_changed)
355 struct amdgpu_device *adev = psp->adev;
357 if (psp->adev->no_hw_access)
360 for (i = 0; i < adev->usec_timeout; i++) {
361 val = RREG32(reg_index);
366 if ((val & mask) == reg_val)
375 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
378 case GFX_CMD_ID_LOAD_TA:
380 case GFX_CMD_ID_UNLOAD_TA:
382 case GFX_CMD_ID_INVOKE_CMD:
384 case GFX_CMD_ID_LOAD_ASD:
386 case GFX_CMD_ID_SETUP_TMR:
388 case GFX_CMD_ID_LOAD_IP_FW:
390 case GFX_CMD_ID_DESTROY_TMR:
391 return "DESTROY_TMR";
392 case GFX_CMD_ID_SAVE_RESTORE:
393 return "SAVE_RESTORE_IP_FW";
394 case GFX_CMD_ID_SETUP_VMR:
396 case GFX_CMD_ID_DESTROY_VMR:
397 return "DESTROY_VMR";
398 case GFX_CMD_ID_PROG_REG:
400 case GFX_CMD_ID_GET_FW_ATTESTATION:
401 return "GET_FW_ATTESTATION";
402 case GFX_CMD_ID_LOAD_TOC:
403 return "ID_LOAD_TOC";
404 case GFX_CMD_ID_AUTOLOAD_RLC:
405 return "AUTOLOAD_RLC";
406 case GFX_CMD_ID_BOOT_CFG:
409 return "UNKNOWN CMD";
414 psp_cmd_submit_buf(struct psp_context *psp,
415 struct amdgpu_firmware_info *ucode,
416 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
421 bool ras_intr = false;
422 bool skip_unsupport = false;
424 if (psp->adev->no_hw_access)
427 if (!drm_dev_enter(&psp->adev->ddev, &idx))
430 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
432 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
434 index = atomic_inc_return(&psp->fence_value);
435 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
437 atomic_dec(&psp->fence_value);
441 amdgpu_device_invalidate_hdp(psp->adev, NULL);
442 while (*((unsigned int *)psp->fence_buf) != index) {
446 * Shouldn't wait for timeout when err_event_athub occurs,
447 * because gpu reset thread triggered and lock resource should
448 * be released for psp resume sequence.
450 ras_intr = amdgpu_ras_intr_triggered();
453 usleep_range(10, 100);
454 amdgpu_device_invalidate_hdp(psp->adev, NULL);
457 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
458 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
459 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
461 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
463 /* In some cases, psp response status is not 0 even there is no
464 * problem while the command is submitted. Some version of PSP FW
465 * doesn't write 0 to that field.
466 * So here we would like to only print a warning instead of an error
467 * during psp initialization to avoid breaking hw_init and it doesn't
470 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
472 DRM_WARN("failed to load ucode (%s) ",
473 amdgpu_ucode_name(ucode->ucode_id));
474 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n",
475 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
476 psp->cmd_buf_mem->resp.status);
484 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
485 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
493 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
495 struct psp_gfx_cmd_resp *cmd = psp->cmd;
497 mutex_lock(&psp->mutex);
499 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
504 void release_psp_cmd_buf(struct psp_context *psp)
506 mutex_unlock(&psp->mutex);
509 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
510 struct psp_gfx_cmd_resp *cmd,
511 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
513 struct amdgpu_device *adev = psp->adev;
514 uint32_t size = amdgpu_bo_size(tmr_bo);
515 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
517 if (amdgpu_sriov_vf(psp->adev))
518 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
520 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
521 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
522 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
523 cmd->cmd.cmd_setup_tmr.buf_size = size;
524 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
525 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
526 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
529 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
530 uint64_t pri_buf_mc, uint32_t size)
532 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
533 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
534 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
535 cmd->cmd.cmd_load_toc.toc_size = size;
538 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
539 static int psp_load_toc(struct psp_context *psp,
543 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
545 /* Copy toc to psp firmware private buffer */
546 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
548 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
550 ret = psp_cmd_submit_buf(psp, NULL, cmd,
551 psp->fence_buf_mc_addr);
553 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
555 release_psp_cmd_buf(psp);
560 /* Set up Trusted Memory Region */
561 static int psp_tmr_init(struct psp_context *psp)
569 * According to HW engineer, they prefer the TMR address be "naturally
570 * aligned" , e.g. the start address be an integer divide of TMR size.
572 * Note: this memory need be reserved till the driver
575 tmr_size = PSP_TMR_SIZE(psp->adev);
577 /* For ASICs support RLC autoload, psp will parse the toc
578 * and calculate the total size of TMR needed */
579 if (!amdgpu_sriov_vf(psp->adev) &&
580 psp->toc.start_addr &&
581 psp->toc.size_bytes &&
583 ret = psp_load_toc(psp, &tmr_size);
585 DRM_ERROR("Failed to load toc\n");
590 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
591 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
592 AMDGPU_GEM_DOMAIN_VRAM,
593 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
598 static bool psp_skip_tmr(struct psp_context *psp)
600 switch (psp->adev->asic_type) {
602 case CHIP_SIENNA_CICHLID:
610 static int psp_tmr_load(struct psp_context *psp)
613 struct psp_gfx_cmd_resp *cmd;
615 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
616 * Already set up by host driver.
618 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
621 cmd = acquire_psp_cmd_buf(psp);
623 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
624 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
625 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
627 ret = psp_cmd_submit_buf(psp, NULL, cmd,
628 psp->fence_buf_mc_addr);
630 release_psp_cmd_buf(psp);
635 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
636 struct psp_gfx_cmd_resp *cmd)
638 if (amdgpu_sriov_vf(psp->adev))
639 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
641 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
644 static int psp_tmr_unload(struct psp_context *psp)
647 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
649 psp_prep_tmr_unload_cmd_buf(psp, cmd);
650 DRM_INFO("free PSP TMR buffer\n");
652 ret = psp_cmd_submit_buf(psp, NULL, cmd,
653 psp->fence_buf_mc_addr);
655 release_psp_cmd_buf(psp);
660 static int psp_tmr_terminate(struct psp_context *psp)
666 ret = psp_tmr_unload(psp);
670 /* free TMR memory buffer */
671 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
672 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
677 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
678 uint64_t *output_ptr)
681 struct psp_gfx_cmd_resp *cmd;
686 if (amdgpu_sriov_vf(psp->adev))
689 cmd = acquire_psp_cmd_buf(psp);
691 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
693 ret = psp_cmd_submit_buf(psp, NULL, cmd,
694 psp->fence_buf_mc_addr);
697 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
698 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
701 release_psp_cmd_buf(psp);
706 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
708 struct psp_context *psp = &adev->psp;
709 struct psp_gfx_cmd_resp *cmd;
712 if (amdgpu_sriov_vf(adev))
715 cmd = acquire_psp_cmd_buf(psp);
717 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
718 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
720 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
723 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
726 release_psp_cmd_buf(psp);
731 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
734 struct psp_context *psp = &adev->psp;
735 struct psp_gfx_cmd_resp *cmd;
737 if (amdgpu_sriov_vf(adev))
740 cmd = acquire_psp_cmd_buf(psp);
742 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
743 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
744 cmd->cmd.boot_cfg.boot_config = boot_cfg;
745 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
747 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
749 release_psp_cmd_buf(psp);
754 static int psp_rl_load(struct amdgpu_device *adev)
757 struct psp_context *psp = &adev->psp;
758 struct psp_gfx_cmd_resp *cmd;
760 if (!is_psp_fw_valid(psp->rl))
763 cmd = acquire_psp_cmd_buf(psp);
765 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
766 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
768 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
769 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
770 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
771 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
772 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
774 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
776 release_psp_cmd_buf(psp);
781 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
782 uint64_t asd_mc, uint32_t size)
784 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
785 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
786 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
787 cmd->cmd.cmd_load_ta.app_len = size;
789 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
790 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
791 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
794 static int psp_asd_load(struct psp_context *psp)
797 struct psp_gfx_cmd_resp *cmd;
799 /* If PSP version doesn't match ASD version, asd loading will be failed.
800 * add workaround to bypass it for sriov now.
801 * TODO: add version check to make it common
803 if (amdgpu_sriov_vf(psp->adev) || !psp->asd.size_bytes)
806 cmd = acquire_psp_cmd_buf(psp);
808 psp_copy_fw(psp, psp->asd.start_addr, psp->asd.size_bytes);
810 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
811 psp->asd.size_bytes);
813 ret = psp_cmd_submit_buf(psp, NULL, cmd,
814 psp->fence_buf_mc_addr);
816 psp->asd_context.asd_initialized = true;
817 psp->asd_context.session_id = cmd->resp.session_id;
820 release_psp_cmd_buf(psp);
825 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
828 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
829 cmd->cmd.cmd_unload_ta.session_id = session_id;
832 static int psp_asd_unload(struct psp_context *psp)
835 struct psp_gfx_cmd_resp *cmd;
837 if (amdgpu_sriov_vf(psp->adev))
840 if (!psp->asd_context.asd_initialized)
843 cmd = acquire_psp_cmd_buf(psp);
845 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
847 ret = psp_cmd_submit_buf(psp, NULL, cmd,
848 psp->fence_buf_mc_addr);
850 psp->asd_context.asd_initialized = false;
852 release_psp_cmd_buf(psp);
857 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
858 uint32_t id, uint32_t value)
860 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
861 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
862 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
865 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
868 struct psp_gfx_cmd_resp *cmd;
871 if (reg >= PSP_REG_LAST)
874 cmd = acquire_psp_cmd_buf(psp);
876 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
877 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
879 DRM_ERROR("PSP failed to program reg id %d", reg);
881 release_psp_cmd_buf(psp);
886 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
888 uint32_t ta_bin_size,
889 uint64_t ta_shared_mc,
890 uint32_t ta_shared_size)
892 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
893 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
894 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
895 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
897 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
898 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
899 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
902 static int psp_ta_init_shared_buf(struct psp_context *psp,
903 struct ta_mem_context *mem_ctx,
904 uint32_t shared_mem_size)
909 * Allocate 16k memory aligned to 4k from Frame Buffer (local
910 * physical) for ta to host memory
912 ret = amdgpu_bo_create_kernel(psp->adev, shared_mem_size, PAGE_SIZE,
913 AMDGPU_GEM_DOMAIN_VRAM,
915 &mem_ctx->shared_mc_addr,
916 &mem_ctx->shared_buf);
921 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
923 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
924 &mem_ctx->shared_buf);
927 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
929 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context,
930 PSP_XGMI_SHARED_MEM_SIZE);
933 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
937 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
938 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
939 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
942 static int psp_ta_invoke(struct psp_context *psp,
947 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
949 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
951 ret = psp_cmd_submit_buf(psp, NULL, cmd,
952 psp->fence_buf_mc_addr);
954 release_psp_cmd_buf(psp);
959 static int psp_xgmi_load(struct psp_context *psp)
962 struct psp_gfx_cmd_resp *cmd;
965 * TODO: bypass the loading in sriov for now
968 cmd = acquire_psp_cmd_buf(psp);
970 psp_copy_fw(psp, psp->xgmi.start_addr, psp->xgmi.size_bytes);
972 psp_prep_ta_load_cmd_buf(cmd,
974 psp->xgmi.size_bytes,
975 psp->xgmi_context.context.mem_context.shared_mc_addr,
976 PSP_XGMI_SHARED_MEM_SIZE);
978 ret = psp_cmd_submit_buf(psp, NULL, cmd,
979 psp->fence_buf_mc_addr);
982 psp->xgmi_context.context.initialized = true;
983 psp->xgmi_context.context.session_id = cmd->resp.session_id;
986 release_psp_cmd_buf(psp);
991 static int psp_xgmi_unload(struct psp_context *psp)
994 struct psp_gfx_cmd_resp *cmd;
995 struct amdgpu_device *adev = psp->adev;
997 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
998 if (adev->asic_type == CHIP_ARCTURUS ||
999 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
1003 * TODO: bypass the unloading in sriov for now
1006 cmd = acquire_psp_cmd_buf(psp);
1008 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.context.session_id);
1010 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1011 psp->fence_buf_mc_addr);
1013 release_psp_cmd_buf(psp);
1018 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1020 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.context.session_id);
1023 int psp_xgmi_terminate(struct psp_context *psp)
1027 if (!psp->xgmi_context.context.initialized)
1030 ret = psp_xgmi_unload(psp);
1034 psp->xgmi_context.context.initialized = false;
1036 /* free xgmi shared memory */
1037 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
1042 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1044 struct ta_xgmi_shared_memory *xgmi_cmd;
1048 !psp->xgmi.size_bytes ||
1049 !psp->xgmi.start_addr)
1055 if (!psp->xgmi_context.context.initialized) {
1056 ret = psp_xgmi_init_shared_buf(psp);
1062 ret = psp_xgmi_load(psp);
1067 /* Initialize XGMI session */
1068 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1069 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1070 xgmi_cmd->flag_extend_link_record = set_extended_data;
1071 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1073 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1078 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1080 struct ta_xgmi_shared_memory *xgmi_cmd;
1083 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1084 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1086 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1088 /* Invoke xgmi ta to get hive id */
1089 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1093 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1098 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1100 struct ta_xgmi_shared_memory *xgmi_cmd;
1103 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1104 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1106 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1108 /* Invoke xgmi ta to get the node id */
1109 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1113 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1118 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1120 return psp->adev->asic_type == CHIP_ALDEBARAN &&
1121 psp->xgmi.feature_version >= 0x2000000b;
1125 * Chips that support extended topology information require the driver to
1126 * reflect topology information in the opposite direction. This is
1127 * because the TA has already exceeded its link record limit and if the
1128 * TA holds bi-directional information, the driver would have to do
1129 * multiple fetches instead of just two.
1131 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1132 struct psp_xgmi_node_info node_info)
1134 struct amdgpu_device *mirror_adev;
1135 struct amdgpu_hive_info *hive;
1136 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1137 uint64_t dst_node_id = node_info.node_id;
1138 uint8_t dst_num_hops = node_info.num_hops;
1139 uint8_t dst_num_links = node_info.num_links;
1141 hive = amdgpu_get_xgmi_hive(psp->adev);
1142 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1143 struct psp_xgmi_topology_info *mirror_top_info;
1146 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1149 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1150 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1151 if (mirror_top_info->nodes[j].node_id != src_node_id)
1154 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1156 * prevent 0 num_links value re-reflection since reflection
1157 * criteria is based on num_hops (direct or indirect).
1161 mirror_top_info->nodes[j].num_links = dst_num_links;
1170 int psp_xgmi_get_topology_info(struct psp_context *psp,
1172 struct psp_xgmi_topology_info *topology,
1173 bool get_extended_data)
1175 struct ta_xgmi_shared_memory *xgmi_cmd;
1176 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1177 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1181 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1184 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1185 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1186 xgmi_cmd->flag_extend_link_record = get_extended_data;
1188 /* Fill in the shared memory with topology information as input */
1189 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1190 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1191 topology_info_input->num_nodes = number_devices;
1193 for (i = 0; i < topology_info_input->num_nodes; i++) {
1194 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1195 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1196 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1197 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1200 /* Invoke xgmi ta to get the topology information */
1201 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1205 /* Read the output topology information from the shared memory */
1206 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1207 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1208 for (i = 0; i < topology->num_nodes; i++) {
1209 /* extended data will either be 0 or equal to non-extended data */
1210 if (topology_info_output->nodes[i].num_hops)
1211 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1213 /* non-extended data gets everything here so no need to update */
1214 if (!get_extended_data) {
1215 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1216 topology->nodes[i].is_sharing_enabled =
1217 topology_info_output->nodes[i].is_sharing_enabled;
1218 topology->nodes[i].sdma_engine =
1219 topology_info_output->nodes[i].sdma_engine;
1224 /* Invoke xgmi ta again to get the link information */
1225 if (psp_xgmi_peer_link_info_supported(psp)) {
1226 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1228 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1230 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1235 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1236 for (i = 0; i < topology->num_nodes; i++) {
1237 /* accumulate num_links on extended data */
1238 topology->nodes[i].num_links = get_extended_data ?
1239 topology->nodes[i].num_links +
1240 link_info_output->nodes[i].num_links :
1241 link_info_output->nodes[i].num_links;
1243 /* reflect the topology information for bi-directionality */
1244 if (psp->xgmi_context.supports_extended_data &&
1245 get_extended_data && topology->nodes[i].num_hops)
1246 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1253 int psp_xgmi_set_topology_info(struct psp_context *psp,
1255 struct psp_xgmi_topology_info *topology)
1257 struct ta_xgmi_shared_memory *xgmi_cmd;
1258 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1261 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1264 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1265 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1267 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1268 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1269 topology_info_input->num_nodes = number_devices;
1271 for (i = 0; i < topology_info_input->num_nodes; i++) {
1272 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1273 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1274 topology_info_input->nodes[i].is_sharing_enabled = 1;
1275 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1278 /* Invoke xgmi ta to set topology information */
1279 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1283 static int psp_ras_init_shared_buf(struct psp_context *psp)
1285 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context,
1286 PSP_RAS_SHARED_MEM_SIZE);
1289 static int psp_ras_load(struct psp_context *psp)
1292 struct psp_gfx_cmd_resp *cmd;
1293 struct ta_ras_shared_memory *ras_cmd;
1296 * TODO: bypass the loading in sriov for now
1298 if (amdgpu_sriov_vf(psp->adev))
1301 psp_copy_fw(psp, psp->ras.start_addr, psp->ras.size_bytes);
1303 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1305 if (psp->adev->gmc.xgmi.connected_to_cpu)
1306 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1308 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1310 cmd = acquire_psp_cmd_buf(psp);
1312 psp_prep_ta_load_cmd_buf(cmd,
1313 psp->fw_pri_mc_addr,
1314 psp->ras.size_bytes,
1315 psp->ras_context.context.mem_context.shared_mc_addr,
1316 PSP_RAS_SHARED_MEM_SIZE);
1318 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1319 psp->fence_buf_mc_addr);
1322 psp->ras_context.context.session_id = cmd->resp.session_id;
1324 if (!ras_cmd->ras_status)
1325 psp->ras_context.context.initialized = true;
1327 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1330 release_psp_cmd_buf(psp);
1332 if (ret || ras_cmd->ras_status)
1333 amdgpu_ras_fini(psp->adev);
1338 static int psp_ras_unload(struct psp_context *psp)
1341 struct psp_gfx_cmd_resp *cmd;
1344 * TODO: bypass the unloading in sriov for now
1346 if (amdgpu_sriov_vf(psp->adev))
1349 cmd = acquire_psp_cmd_buf(psp);
1351 psp_prep_ta_unload_cmd_buf(cmd, psp->ras_context.context.session_id);
1353 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1354 psp->fence_buf_mc_addr);
1356 release_psp_cmd_buf(psp);
1361 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1363 struct ta_ras_shared_memory *ras_cmd;
1366 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1369 * TODO: bypass the loading in sriov for now
1371 if (amdgpu_sriov_vf(psp->adev))
1374 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras_context.context.session_id);
1376 if (amdgpu_ras_intr_triggered())
1379 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1381 DRM_WARN("RAS: Unsupported Interface");
1386 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1387 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1389 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1391 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1392 dev_warn(psp->adev->dev,
1393 "RAS internal register access blocked\n");
1399 static int psp_ras_status_to_errno(struct amdgpu_device *adev,
1400 enum ta_ras_status ras_status)
1404 switch (ras_status) {
1405 case TA_RAS_STATUS__SUCCESS:
1408 case TA_RAS_STATUS__RESET_NEEDED:
1411 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
1412 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
1414 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
1415 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
1418 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
1424 int psp_ras_enable_features(struct psp_context *psp,
1425 union ta_ras_cmd_input *info, bool enable)
1427 struct ta_ras_shared_memory *ras_cmd;
1430 if (!psp->ras_context.context.initialized)
1433 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1434 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1437 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1439 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1441 ras_cmd->ras_in_message = *info;
1443 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1447 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1450 static int psp_ras_terminate(struct psp_context *psp)
1455 * TODO: bypass the terminate in sriov for now
1457 if (amdgpu_sriov_vf(psp->adev))
1460 if (!psp->ras_context.context.initialized)
1463 ret = psp_ras_unload(psp);
1467 psp->ras_context.context.initialized = false;
1469 /* free ras shared memory */
1470 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
1475 static int psp_ras_initialize(struct psp_context *psp)
1478 uint32_t boot_cfg = 0xFF;
1479 struct amdgpu_device *adev = psp->adev;
1482 * TODO: bypass the initialize in sriov for now
1484 if (amdgpu_sriov_vf(adev))
1487 if (!adev->psp.ras.size_bytes ||
1488 !adev->psp.ras.start_addr) {
1489 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1493 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1494 /* query GECC enablement status from boot config
1495 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1497 ret = psp_boot_config_get(adev, &boot_cfg);
1499 dev_warn(adev->dev, "PSP get boot config failed\n");
1501 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1503 dev_info(adev->dev, "GECC is disabled\n");
1505 /* disable GECC in next boot cycle if ras is
1506 * disabled by module parameter amdgpu_ras_enable
1507 * and/or amdgpu_ras_mask, or boot_config_get call
1510 ret = psp_boot_config_set(adev, 0);
1512 dev_warn(adev->dev, "PSP set boot config failed\n");
1514 dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1515 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1518 if (1 == boot_cfg) {
1519 dev_info(adev->dev, "GECC is enabled\n");
1521 /* enable GECC in next boot cycle if it is disabled
1522 * in boot config, or force enable GECC if failed to
1523 * get boot configuration
1525 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1527 dev_warn(adev->dev, "PSP set boot config failed\n");
1529 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1534 if (!psp->ras_context.context.initialized) {
1535 ret = psp_ras_init_shared_buf(psp);
1540 ret = psp_ras_load(psp);
1547 int psp_ras_trigger_error(struct psp_context *psp,
1548 struct ta_ras_trigger_error_input *info)
1550 struct ta_ras_shared_memory *ras_cmd;
1553 if (!psp->ras_context.context.initialized)
1556 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1557 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1559 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1560 ras_cmd->ras_in_message.trigger_error = *info;
1562 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1566 /* If err_event_athub occurs error inject was successful, however
1567 return status from TA is no long reliable */
1568 if (amdgpu_ras_intr_triggered())
1571 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1576 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1578 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context,
1579 PSP_HDCP_SHARED_MEM_SIZE);
1582 static int psp_hdcp_load(struct psp_context *psp)
1585 struct psp_gfx_cmd_resp *cmd;
1588 * TODO: bypass the loading in sriov for now
1590 if (amdgpu_sriov_vf(psp->adev))
1593 psp_copy_fw(psp, psp->hdcp.start_addr,
1594 psp->hdcp.size_bytes);
1596 cmd = acquire_psp_cmd_buf(psp);
1598 psp_prep_ta_load_cmd_buf(cmd,
1599 psp->fw_pri_mc_addr,
1600 psp->hdcp.size_bytes,
1601 psp->hdcp_context.context.mem_context.shared_mc_addr,
1602 PSP_HDCP_SHARED_MEM_SIZE);
1604 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1607 psp->hdcp_context.context.initialized = true;
1608 psp->hdcp_context.context.session_id = cmd->resp.session_id;
1609 mutex_init(&psp->hdcp_context.mutex);
1612 release_psp_cmd_buf(psp);
1616 static int psp_hdcp_initialize(struct psp_context *psp)
1621 * TODO: bypass the initialize in sriov for now
1623 if (amdgpu_sriov_vf(psp->adev))
1626 if (!psp->hdcp.size_bytes ||
1627 !psp->hdcp.start_addr) {
1628 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1632 if (!psp->hdcp_context.context.initialized) {
1633 ret = psp_hdcp_init_shared_buf(psp);
1638 ret = psp_hdcp_load(psp);
1645 static int psp_hdcp_unload(struct psp_context *psp)
1648 struct psp_gfx_cmd_resp *cmd;
1651 * TODO: bypass the unloading in sriov for now
1653 if (amdgpu_sriov_vf(psp->adev))
1656 cmd = acquire_psp_cmd_buf(psp);
1658 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.context.session_id);
1660 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1662 release_psp_cmd_buf(psp);
1667 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1670 * TODO: bypass the loading in sriov for now
1672 if (amdgpu_sriov_vf(psp->adev))
1675 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.context.session_id);
1678 static int psp_hdcp_terminate(struct psp_context *psp)
1683 * TODO: bypass the terminate in sriov for now
1685 if (amdgpu_sriov_vf(psp->adev))
1688 if (!psp->hdcp_context.context.initialized) {
1689 if (psp->hdcp_context.context.mem_context.shared_buf)
1695 ret = psp_hdcp_unload(psp);
1699 psp->hdcp_context.context.initialized = false;
1702 /* free hdcp shared memory */
1703 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
1710 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1712 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context,
1713 PSP_DTM_SHARED_MEM_SIZE);
1716 static int psp_dtm_load(struct psp_context *psp)
1719 struct psp_gfx_cmd_resp *cmd;
1722 * TODO: bypass the loading in sriov for now
1724 if (amdgpu_sriov_vf(psp->adev))
1727 psp_copy_fw(psp, psp->dtm.start_addr, psp->dtm.size_bytes);
1729 cmd = acquire_psp_cmd_buf(psp);
1731 psp_prep_ta_load_cmd_buf(cmd,
1732 psp->fw_pri_mc_addr,
1733 psp->dtm.size_bytes,
1734 psp->dtm_context.context.mem_context.shared_mc_addr,
1735 PSP_DTM_SHARED_MEM_SIZE);
1737 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1740 psp->dtm_context.context.initialized = true;
1741 psp->dtm_context.context.session_id = cmd->resp.session_id;
1742 mutex_init(&psp->dtm_context.mutex);
1745 release_psp_cmd_buf(psp);
1750 static int psp_dtm_initialize(struct psp_context *psp)
1755 * TODO: bypass the initialize in sriov for now
1757 if (amdgpu_sriov_vf(psp->adev))
1760 if (!psp->dtm.size_bytes ||
1761 !psp->dtm.start_addr) {
1762 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1766 if (!psp->dtm_context.context.initialized) {
1767 ret = psp_dtm_init_shared_buf(psp);
1772 ret = psp_dtm_load(psp);
1779 static int psp_dtm_unload(struct psp_context *psp)
1782 struct psp_gfx_cmd_resp *cmd;
1785 * TODO: bypass the unloading in sriov for now
1787 if (amdgpu_sriov_vf(psp->adev))
1790 cmd = acquire_psp_cmd_buf(psp);
1792 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.context.session_id);
1794 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1796 release_psp_cmd_buf(psp);
1801 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1804 * TODO: bypass the loading in sriov for now
1806 if (amdgpu_sriov_vf(psp->adev))
1809 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.context.session_id);
1812 static int psp_dtm_terminate(struct psp_context *psp)
1817 * TODO: bypass the terminate in sriov for now
1819 if (amdgpu_sriov_vf(psp->adev))
1822 if (!psp->dtm_context.context.initialized) {
1823 if (psp->dtm_context.context.mem_context.shared_buf)
1829 ret = psp_dtm_unload(psp);
1833 psp->dtm_context.context.initialized = false;
1836 /* free dtm shared memory */
1837 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
1844 static int psp_rap_init_shared_buf(struct psp_context *psp)
1846 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context,
1847 PSP_RAP_SHARED_MEM_SIZE);
1850 static int psp_rap_load(struct psp_context *psp)
1853 struct psp_gfx_cmd_resp *cmd;
1855 psp_copy_fw(psp, psp->rap.start_addr, psp->rap.size_bytes);
1857 cmd = acquire_psp_cmd_buf(psp);
1859 psp_prep_ta_load_cmd_buf(cmd,
1860 psp->fw_pri_mc_addr,
1861 psp->rap.size_bytes,
1862 psp->rap_context.context.mem_context.shared_mc_addr,
1863 PSP_RAP_SHARED_MEM_SIZE);
1865 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1868 psp->rap_context.context.initialized = true;
1869 psp->rap_context.context.session_id = cmd->resp.session_id;
1870 mutex_init(&psp->rap_context.mutex);
1873 release_psp_cmd_buf(psp);
1878 static int psp_rap_unload(struct psp_context *psp)
1881 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1883 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.context.session_id);
1885 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1887 release_psp_cmd_buf(psp);
1892 static int psp_rap_initialize(struct psp_context *psp)
1895 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1898 * TODO: bypass the initialize in sriov for now
1900 if (amdgpu_sriov_vf(psp->adev))
1903 if (!psp->rap.size_bytes ||
1904 !psp->rap.start_addr) {
1905 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1909 if (!psp->rap_context.context.initialized) {
1910 ret = psp_rap_init_shared_buf(psp);
1915 ret = psp_rap_load(psp);
1919 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1920 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1921 psp_rap_unload(psp);
1923 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1925 psp->rap_context.context.initialized = false;
1927 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1936 static int psp_rap_terminate(struct psp_context *psp)
1940 if (!psp->rap_context.context.initialized)
1943 ret = psp_rap_unload(psp);
1945 psp->rap_context.context.initialized = false;
1947 /* free rap shared memory */
1948 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1953 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1955 struct ta_rap_shared_memory *rap_cmd;
1958 if (!psp->rap_context.context.initialized)
1961 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1962 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1965 mutex_lock(&psp->rap_context.mutex);
1967 rap_cmd = (struct ta_rap_shared_memory *)
1968 psp->rap_context.context.mem_context.shared_buf;
1969 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1971 rap_cmd->cmd_id = ta_cmd_id;
1972 rap_cmd->validation_method_id = METHOD_A;
1974 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.context.session_id);
1979 *status = rap_cmd->rap_status;
1982 mutex_unlock(&psp->rap_context.mutex);
1988 /* securedisplay start */
1989 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1991 return psp_ta_init_shared_buf(
1992 psp, &psp->securedisplay_context.context.mem_context,
1993 PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1996 static int psp_securedisplay_load(struct psp_context *psp)
1999 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2001 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
2002 memcpy(psp->fw_pri_buf, psp->securedisplay.start_addr, psp->securedisplay.size_bytes);
2004 psp_prep_ta_load_cmd_buf(cmd,
2005 psp->fw_pri_mc_addr,
2006 psp->securedisplay.size_bytes,
2007 psp->securedisplay_context.context.mem_context.shared_mc_addr,
2008 PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
2010 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2013 psp->securedisplay_context.context.initialized = true;
2014 psp->securedisplay_context.context.session_id = cmd->resp.session_id;
2015 mutex_init(&psp->securedisplay_context.mutex);
2018 release_psp_cmd_buf(psp);
2023 static int psp_securedisplay_unload(struct psp_context *psp)
2026 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2028 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.context.session_id);
2030 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2032 release_psp_cmd_buf(psp);
2037 static int psp_securedisplay_initialize(struct psp_context *psp)
2040 struct securedisplay_cmd *securedisplay_cmd;
2043 * TODO: bypass the initialize in sriov for now
2045 if (amdgpu_sriov_vf(psp->adev))
2048 if (!psp->securedisplay.size_bytes ||
2049 !psp->securedisplay.start_addr) {
2050 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2054 if (!psp->securedisplay_context.context.initialized) {
2055 ret = psp_securedisplay_init_shared_buf(psp);
2060 ret = psp_securedisplay_load(psp);
2064 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2065 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2067 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2069 psp_securedisplay_unload(psp);
2071 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2073 psp->securedisplay_context.context.initialized = false;
2075 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2079 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2080 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2081 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2082 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2088 static int psp_securedisplay_terminate(struct psp_context *psp)
2093 * TODO:bypass the terminate in sriov for now
2095 if (amdgpu_sriov_vf(psp->adev))
2098 if (!psp->securedisplay_context.context.initialized)
2101 ret = psp_securedisplay_unload(psp);
2105 psp->securedisplay_context.context.initialized = false;
2107 /* free securedisplay shared memory */
2108 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2113 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2117 if (!psp->securedisplay_context.context.initialized)
2120 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2121 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2124 mutex_lock(&psp->securedisplay_context.mutex);
2126 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.context.session_id);
2128 mutex_unlock(&psp->securedisplay_context.mutex);
2132 /* SECUREDISPLAY end */
2134 static int psp_hw_start(struct psp_context *psp)
2136 struct amdgpu_device *adev = psp->adev;
2139 if (!amdgpu_sriov_vf(adev)) {
2140 if ((is_psp_fw_valid(psp->kdb)) &&
2141 (psp->funcs->bootloader_load_kdb != NULL)) {
2142 ret = psp_bootloader_load_kdb(psp);
2144 DRM_ERROR("PSP load kdb failed!\n");
2149 if ((is_psp_fw_valid(psp->spl)) &&
2150 (psp->funcs->bootloader_load_spl != NULL)) {
2151 ret = psp_bootloader_load_spl(psp);
2153 DRM_ERROR("PSP load spl failed!\n");
2158 if ((is_psp_fw_valid(psp->sys)) &&
2159 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2160 ret = psp_bootloader_load_sysdrv(psp);
2162 DRM_ERROR("PSP load sys drv failed!\n");
2167 if ((is_psp_fw_valid(psp->soc_drv)) &&
2168 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2169 ret = psp_bootloader_load_soc_drv(psp);
2171 DRM_ERROR("PSP load soc drv failed!\n");
2176 if ((is_psp_fw_valid(psp->intf_drv)) &&
2177 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2178 ret = psp_bootloader_load_intf_drv(psp);
2180 DRM_ERROR("PSP load intf drv failed!\n");
2185 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2186 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2187 ret = psp_bootloader_load_dbg_drv(psp);
2189 DRM_ERROR("PSP load dbg drv failed!\n");
2194 if ((is_psp_fw_valid(psp->sos)) &&
2195 (psp->funcs->bootloader_load_sos != NULL)) {
2196 ret = psp_bootloader_load_sos(psp);
2198 DRM_ERROR("PSP load sos failed!\n");
2204 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2206 DRM_ERROR("PSP create ring failed!\n");
2210 ret = psp_tmr_init(psp);
2212 DRM_ERROR("PSP tmr init failed!\n");
2217 * For ASICs with DF Cstate management centralized
2218 * to PMFW, TMR setup should be performed after PMFW
2219 * loaded and before other non-psp firmware loaded.
2221 if (psp->pmfw_centralized_cstate_management) {
2222 ret = psp_load_smu_fw(psp);
2227 ret = psp_tmr_load(psp);
2229 DRM_ERROR("PSP load tmr failed!\n");
2236 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2237 enum psp_gfx_fw_type *type)
2239 switch (ucode->ucode_id) {
2240 case AMDGPU_UCODE_ID_SDMA0:
2241 *type = GFX_FW_TYPE_SDMA0;
2243 case AMDGPU_UCODE_ID_SDMA1:
2244 *type = GFX_FW_TYPE_SDMA1;
2246 case AMDGPU_UCODE_ID_SDMA2:
2247 *type = GFX_FW_TYPE_SDMA2;
2249 case AMDGPU_UCODE_ID_SDMA3:
2250 *type = GFX_FW_TYPE_SDMA3;
2252 case AMDGPU_UCODE_ID_SDMA4:
2253 *type = GFX_FW_TYPE_SDMA4;
2255 case AMDGPU_UCODE_ID_SDMA5:
2256 *type = GFX_FW_TYPE_SDMA5;
2258 case AMDGPU_UCODE_ID_SDMA6:
2259 *type = GFX_FW_TYPE_SDMA6;
2261 case AMDGPU_UCODE_ID_SDMA7:
2262 *type = GFX_FW_TYPE_SDMA7;
2264 case AMDGPU_UCODE_ID_CP_MES:
2265 *type = GFX_FW_TYPE_CP_MES;
2267 case AMDGPU_UCODE_ID_CP_MES_DATA:
2268 *type = GFX_FW_TYPE_MES_STACK;
2270 case AMDGPU_UCODE_ID_CP_CE:
2271 *type = GFX_FW_TYPE_CP_CE;
2273 case AMDGPU_UCODE_ID_CP_PFP:
2274 *type = GFX_FW_TYPE_CP_PFP;
2276 case AMDGPU_UCODE_ID_CP_ME:
2277 *type = GFX_FW_TYPE_CP_ME;
2279 case AMDGPU_UCODE_ID_CP_MEC1:
2280 *type = GFX_FW_TYPE_CP_MEC;
2282 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2283 *type = GFX_FW_TYPE_CP_MEC_ME1;
2285 case AMDGPU_UCODE_ID_CP_MEC2:
2286 *type = GFX_FW_TYPE_CP_MEC;
2288 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2289 *type = GFX_FW_TYPE_CP_MEC_ME2;
2291 case AMDGPU_UCODE_ID_RLC_G:
2292 *type = GFX_FW_TYPE_RLC_G;
2294 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2295 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2297 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2298 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2300 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2301 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2303 case AMDGPU_UCODE_ID_RLC_IRAM:
2304 *type = GFX_FW_TYPE_RLC_IRAM;
2306 case AMDGPU_UCODE_ID_RLC_DRAM:
2307 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2309 case AMDGPU_UCODE_ID_SMC:
2310 *type = GFX_FW_TYPE_SMU;
2312 case AMDGPU_UCODE_ID_UVD:
2313 *type = GFX_FW_TYPE_UVD;
2315 case AMDGPU_UCODE_ID_UVD1:
2316 *type = GFX_FW_TYPE_UVD1;
2318 case AMDGPU_UCODE_ID_VCE:
2319 *type = GFX_FW_TYPE_VCE;
2321 case AMDGPU_UCODE_ID_VCN:
2322 *type = GFX_FW_TYPE_VCN;
2324 case AMDGPU_UCODE_ID_VCN1:
2325 *type = GFX_FW_TYPE_VCN1;
2327 case AMDGPU_UCODE_ID_DMCU_ERAM:
2328 *type = GFX_FW_TYPE_DMCU_ERAM;
2330 case AMDGPU_UCODE_ID_DMCU_INTV:
2331 *type = GFX_FW_TYPE_DMCU_ISR;
2333 case AMDGPU_UCODE_ID_VCN0_RAM:
2334 *type = GFX_FW_TYPE_VCN0_RAM;
2336 case AMDGPU_UCODE_ID_VCN1_RAM:
2337 *type = GFX_FW_TYPE_VCN1_RAM;
2339 case AMDGPU_UCODE_ID_DMCUB:
2340 *type = GFX_FW_TYPE_DMUB;
2342 case AMDGPU_UCODE_ID_MAXIMUM:
2350 static void psp_print_fw_hdr(struct psp_context *psp,
2351 struct amdgpu_firmware_info *ucode)
2353 struct amdgpu_device *adev = psp->adev;
2354 struct common_firmware_header *hdr;
2356 switch (ucode->ucode_id) {
2357 case AMDGPU_UCODE_ID_SDMA0:
2358 case AMDGPU_UCODE_ID_SDMA1:
2359 case AMDGPU_UCODE_ID_SDMA2:
2360 case AMDGPU_UCODE_ID_SDMA3:
2361 case AMDGPU_UCODE_ID_SDMA4:
2362 case AMDGPU_UCODE_ID_SDMA5:
2363 case AMDGPU_UCODE_ID_SDMA6:
2364 case AMDGPU_UCODE_ID_SDMA7:
2365 hdr = (struct common_firmware_header *)
2366 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2367 amdgpu_ucode_print_sdma_hdr(hdr);
2369 case AMDGPU_UCODE_ID_CP_CE:
2370 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2371 amdgpu_ucode_print_gfx_hdr(hdr);
2373 case AMDGPU_UCODE_ID_CP_PFP:
2374 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2375 amdgpu_ucode_print_gfx_hdr(hdr);
2377 case AMDGPU_UCODE_ID_CP_ME:
2378 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2379 amdgpu_ucode_print_gfx_hdr(hdr);
2381 case AMDGPU_UCODE_ID_CP_MEC1:
2382 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2383 amdgpu_ucode_print_gfx_hdr(hdr);
2385 case AMDGPU_UCODE_ID_RLC_G:
2386 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2387 amdgpu_ucode_print_rlc_hdr(hdr);
2389 case AMDGPU_UCODE_ID_SMC:
2390 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2391 amdgpu_ucode_print_smc_hdr(hdr);
2398 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2399 struct psp_gfx_cmd_resp *cmd)
2402 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2404 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2405 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2406 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2407 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2409 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2411 DRM_ERROR("Unknown firmware type\n");
2416 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2417 struct amdgpu_firmware_info *ucode)
2420 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2422 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2424 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2425 psp->fence_buf_mc_addr);
2428 release_psp_cmd_buf(psp);
2433 static int psp_load_smu_fw(struct psp_context *psp)
2436 struct amdgpu_device *adev = psp->adev;
2437 struct amdgpu_firmware_info *ucode =
2438 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2439 struct amdgpu_ras *ras = psp->ras_context.ras;
2441 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2444 if ((amdgpu_in_reset(adev) &&
2445 ras && adev->ras_enabled &&
2446 (adev->asic_type == CHIP_ARCTURUS ||
2447 adev->asic_type == CHIP_VEGA20))) {
2448 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2450 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2454 ret = psp_execute_non_psp_fw_load(psp, ucode);
2457 DRM_ERROR("PSP load smu failed!\n");
2462 static bool fw_load_skip_check(struct psp_context *psp,
2463 struct amdgpu_firmware_info *ucode)
2468 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2469 (psp_smu_reload_quirk(psp) ||
2470 psp->autoload_supported ||
2471 psp->pmfw_centralized_cstate_management))
2474 if (amdgpu_sriov_vf(psp->adev) &&
2475 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2476 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2477 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2478 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2479 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2480 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2481 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2482 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2483 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2484 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2485 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2486 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2487 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2488 /*skip ucode loading in SRIOV VF */
2491 if (psp->autoload_supported &&
2492 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2493 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2494 /* skip mec JT when autoload is enabled */
2500 int psp_load_fw_list(struct psp_context *psp,
2501 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2504 struct amdgpu_firmware_info *ucode;
2506 for (i = 0; i < ucode_count; ++i) {
2507 ucode = ucode_list[i];
2508 psp_print_fw_hdr(psp, ucode);
2509 ret = psp_execute_non_psp_fw_load(psp, ucode);
2516 static int psp_load_non_psp_fw(struct psp_context *psp)
2519 struct amdgpu_firmware_info *ucode;
2520 struct amdgpu_device *adev = psp->adev;
2522 if (psp->autoload_supported &&
2523 !psp->pmfw_centralized_cstate_management) {
2524 ret = psp_load_smu_fw(psp);
2529 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2530 ucode = &adev->firmware.ucode[i];
2532 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2533 !fw_load_skip_check(psp, ucode)) {
2534 ret = psp_load_smu_fw(psp);
2540 if (fw_load_skip_check(psp, ucode))
2543 if (psp->autoload_supported &&
2544 (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2545 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2546 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2547 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2548 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2549 /* PSP only receive one SDMA fw for sienna_cichlid,
2550 * as all four sdma fw are same */
2553 psp_print_fw_hdr(psp, ucode);
2555 ret = psp_execute_non_psp_fw_load(psp, ucode);
2559 /* Start rlc autoload after psp recieved all the gfx firmware */
2560 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2561 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2562 ret = psp_rlc_autoload_start(psp);
2564 DRM_ERROR("Failed to start rlc autoload\n");
2573 static int psp_load_fw(struct amdgpu_device *adev)
2576 struct psp_context *psp = &adev->psp;
2578 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2579 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2583 if (amdgpu_sriov_vf(adev)) {
2584 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2585 AMDGPU_GEM_DOMAIN_VRAM,
2587 &psp->fw_pri_mc_addr,
2590 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2591 AMDGPU_GEM_DOMAIN_GTT,
2593 &psp->fw_pri_mc_addr,
2600 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2601 AMDGPU_GEM_DOMAIN_VRAM,
2603 &psp->fence_buf_mc_addr,
2608 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2609 AMDGPU_GEM_DOMAIN_VRAM,
2610 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2611 (void **)&psp->cmd_buf_mem);
2615 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2617 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2619 DRM_ERROR("PSP ring init failed!\n");
2624 ret = psp_hw_start(psp);
2628 ret = psp_load_non_psp_fw(psp);
2632 ret = psp_asd_load(psp);
2634 DRM_ERROR("PSP load asd failed!\n");
2638 ret = psp_rl_load(adev);
2640 DRM_ERROR("PSP load RL failed!\n");
2645 ret = psp_ras_initialize(psp);
2647 dev_err(psp->adev->dev,
2648 "RAS: Failed to initialize RAS\n");
2650 ret = psp_hdcp_initialize(psp);
2652 dev_err(psp->adev->dev,
2653 "HDCP: Failed to initialize HDCP\n");
2655 ret = psp_dtm_initialize(psp);
2657 dev_err(psp->adev->dev,
2658 "DTM: Failed to initialize DTM\n");
2660 ret = psp_rap_initialize(psp);
2662 dev_err(psp->adev->dev,
2663 "RAP: Failed to initialize RAP\n");
2665 ret = psp_securedisplay_initialize(psp);
2667 dev_err(psp->adev->dev,
2668 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2675 * all cleanup jobs (xgmi terminate, ras terminate,
2676 * ring destroy, cmd/fence/fw buffers destory,
2677 * psp->cmd destory) are delayed to psp_hw_fini
2682 static int psp_hw_init(void *handle)
2685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2687 mutex_lock(&adev->firmware.mutex);
2689 * This sequence is just used on hw_init only once, no need on
2692 ret = amdgpu_ucode_init_bo(adev);
2696 ret = psp_load_fw(adev);
2698 DRM_ERROR("PSP firmware loading failed\n");
2702 mutex_unlock(&adev->firmware.mutex);
2706 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2707 mutex_unlock(&adev->firmware.mutex);
2711 static int psp_hw_fini(void *handle)
2713 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2714 struct psp_context *psp = &adev->psp;
2717 psp_ras_terminate(psp);
2718 psp_securedisplay_terminate(psp);
2719 psp_rap_terminate(psp);
2720 psp_dtm_terminate(psp);
2721 psp_hdcp_terminate(psp);
2724 psp_asd_unload(psp);
2726 psp_tmr_terminate(psp);
2727 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2729 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2730 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2731 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2732 &psp->fence_buf_mc_addr, &psp->fence_buf);
2733 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2734 (void **)&psp->cmd_buf_mem);
2739 static int psp_suspend(void *handle)
2742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2743 struct psp_context *psp = &adev->psp;
2745 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2746 psp->xgmi_context.context.initialized) {
2747 ret = psp_xgmi_terminate(psp);
2749 DRM_ERROR("Failed to terminate xgmi ta\n");
2755 ret = psp_ras_terminate(psp);
2757 DRM_ERROR("Failed to terminate ras ta\n");
2760 ret = psp_hdcp_terminate(psp);
2762 DRM_ERROR("Failed to terminate hdcp ta\n");
2765 ret = psp_dtm_terminate(psp);
2767 DRM_ERROR("Failed to terminate dtm ta\n");
2770 ret = psp_rap_terminate(psp);
2772 DRM_ERROR("Failed to terminate rap ta\n");
2775 ret = psp_securedisplay_terminate(psp);
2777 DRM_ERROR("Failed to terminate securedisplay ta\n");
2782 ret = psp_asd_unload(psp);
2784 DRM_ERROR("Failed to unload asd\n");
2788 ret = psp_tmr_terminate(psp);
2790 DRM_ERROR("Failed to terminate tmr\n");
2794 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2796 DRM_ERROR("PSP ring stop failed\n");
2803 static int psp_resume(void *handle)
2806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2807 struct psp_context *psp = &adev->psp;
2809 DRM_INFO("PSP is resuming...\n");
2811 if (psp->mem_train_ctx.enable_mem_training) {
2812 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2814 DRM_ERROR("Failed to process memory training!\n");
2819 mutex_lock(&adev->firmware.mutex);
2821 ret = psp_hw_start(psp);
2825 ret = psp_load_non_psp_fw(psp);
2829 ret = psp_asd_load(psp);
2831 DRM_ERROR("PSP load asd failed!\n");
2835 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2836 ret = psp_xgmi_initialize(psp, false, true);
2837 /* Warning the XGMI seesion initialize failure
2838 * Instead of stop driver initialization
2841 dev_err(psp->adev->dev,
2842 "XGMI: Failed to initialize XGMI session\n");
2846 ret = psp_ras_initialize(psp);
2848 dev_err(psp->adev->dev,
2849 "RAS: Failed to initialize RAS\n");
2851 ret = psp_hdcp_initialize(psp);
2853 dev_err(psp->adev->dev,
2854 "HDCP: Failed to initialize HDCP\n");
2856 ret = psp_dtm_initialize(psp);
2858 dev_err(psp->adev->dev,
2859 "DTM: Failed to initialize DTM\n");
2861 ret = psp_rap_initialize(psp);
2863 dev_err(psp->adev->dev,
2864 "RAP: Failed to initialize RAP\n");
2866 ret = psp_securedisplay_initialize(psp);
2868 dev_err(psp->adev->dev,
2869 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2872 mutex_unlock(&adev->firmware.mutex);
2877 DRM_ERROR("PSP resume failed\n");
2878 mutex_unlock(&adev->firmware.mutex);
2882 int psp_gpu_reset(struct amdgpu_device *adev)
2886 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2889 mutex_lock(&adev->psp.mutex);
2890 ret = psp_mode1_reset(&adev->psp);
2891 mutex_unlock(&adev->psp.mutex);
2896 int psp_rlc_autoload_start(struct psp_context *psp)
2899 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2901 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2903 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2904 psp->fence_buf_mc_addr);
2906 release_psp_cmd_buf(psp);
2911 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2912 uint64_t cmd_gpu_addr, int cmd_size)
2914 struct amdgpu_firmware_info ucode = {0};
2916 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2917 AMDGPU_UCODE_ID_VCN0_RAM;
2918 ucode.mc_addr = cmd_gpu_addr;
2919 ucode.ucode_size = cmd_size;
2921 return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2924 int psp_ring_cmd_submit(struct psp_context *psp,
2925 uint64_t cmd_buf_mc_addr,
2926 uint64_t fence_mc_addr,
2929 unsigned int psp_write_ptr_reg = 0;
2930 struct psp_gfx_rb_frame *write_frame;
2931 struct psp_ring *ring = &psp->km_ring;
2932 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2933 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2934 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2935 struct amdgpu_device *adev = psp->adev;
2936 uint32_t ring_size_dw = ring->ring_size / 4;
2937 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2939 /* KM (GPCOM) prepare write pointer */
2940 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2942 /* Update KM RB frame pointer to new frame */
2943 /* write_frame ptr increments by size of rb_frame in bytes */
2944 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2945 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2946 write_frame = ring_buffer_start;
2948 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2949 /* Check invalid write_frame ptr address */
2950 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2951 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2952 ring_buffer_start, ring_buffer_end, write_frame);
2953 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2957 /* Initialize KM RB frame */
2958 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2960 /* Update KM RB frame */
2961 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2962 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2963 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2964 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2965 write_frame->fence_value = index;
2966 amdgpu_device_flush_hdp(adev, NULL);
2968 /* Update the write Pointer in DWORDs */
2969 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2970 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2974 int psp_init_asd_microcode(struct psp_context *psp,
2975 const char *chip_name)
2977 struct amdgpu_device *adev = psp->adev;
2978 char fw_name[PSP_FW_NAME_LEN];
2979 const struct psp_firmware_header_v1_0 *asd_hdr;
2983 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2987 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2988 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2992 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2996 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2997 adev->psp.asd.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2998 adev->psp.asd.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2999 adev->psp.asd.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3000 adev->psp.asd.start_addr = (uint8_t *)asd_hdr +
3001 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3004 dev_err(adev->dev, "fail to initialize asd microcode\n");
3005 release_firmware(adev->psp.asd_fw);
3006 adev->psp.asd_fw = NULL;
3010 int psp_init_toc_microcode(struct psp_context *psp,
3011 const char *chip_name)
3013 struct amdgpu_device *adev = psp->adev;
3014 char fw_name[PSP_FW_NAME_LEN];
3015 const struct psp_firmware_header_v1_0 *toc_hdr;
3019 dev_err(adev->dev, "invalid chip name for toc microcode\n");
3023 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3024 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
3028 err = amdgpu_ucode_validate(adev->psp.toc_fw);
3032 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3033 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3034 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3035 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3036 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3037 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3040 dev_err(adev->dev, "fail to request/validate toc microcode\n");
3041 release_firmware(adev->psp.toc_fw);
3042 adev->psp.toc_fw = NULL;
3046 static int parse_sos_bin_descriptor(struct psp_context *psp,
3047 const struct psp_fw_bin_desc *desc,
3048 const struct psp_firmware_header_v2_0 *sos_hdr)
3050 uint8_t *ucode_start_addr = NULL;
3052 if (!psp || !desc || !sos_hdr)
3055 ucode_start_addr = (uint8_t *)sos_hdr +
3056 le32_to_cpu(desc->offset_bytes) +
3057 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3059 switch (desc->fw_type) {
3060 case PSP_FW_TYPE_PSP_SOS:
3061 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3062 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3063 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3064 psp->sos.start_addr = ucode_start_addr;
3066 case PSP_FW_TYPE_PSP_SYS_DRV:
3067 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3068 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3069 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3070 psp->sys.start_addr = ucode_start_addr;
3072 case PSP_FW_TYPE_PSP_KDB:
3073 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3074 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3075 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3076 psp->kdb.start_addr = ucode_start_addr;
3078 case PSP_FW_TYPE_PSP_TOC:
3079 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3080 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3081 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3082 psp->toc.start_addr = ucode_start_addr;
3084 case PSP_FW_TYPE_PSP_SPL:
3085 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3086 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3087 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3088 psp->spl.start_addr = ucode_start_addr;
3090 case PSP_FW_TYPE_PSP_RL:
3091 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3092 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3093 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3094 psp->rl.start_addr = ucode_start_addr;
3096 case PSP_FW_TYPE_PSP_SOC_DRV:
3097 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3098 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3099 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3100 psp->soc_drv.start_addr = ucode_start_addr;
3102 case PSP_FW_TYPE_PSP_INTF_DRV:
3103 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3104 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3105 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3106 psp->intf_drv.start_addr = ucode_start_addr;
3108 case PSP_FW_TYPE_PSP_DBG_DRV:
3109 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3110 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3111 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3112 psp->dbg_drv.start_addr = ucode_start_addr;
3115 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3122 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3124 const struct psp_firmware_header_v1_0 *sos_hdr;
3125 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3126 uint8_t *ucode_array_start_addr;
3128 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3129 ucode_array_start_addr = (uint8_t *)sos_hdr +
3130 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3132 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
3133 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3134 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3136 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3137 adev->psp.sys.start_addr = ucode_array_start_addr;
3139 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3140 adev->psp.sos.start_addr = ucode_array_start_addr +
3141 le32_to_cpu(sos_hdr->sos.offset_bytes);
3142 adev->psp.xgmi_context.supports_extended_data = false;
3144 /* Load alternate PSP SOS FW */
3145 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3147 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3148 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3150 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3151 adev->psp.sys.start_addr = ucode_array_start_addr +
3152 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3154 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3155 adev->psp.sos.start_addr = ucode_array_start_addr +
3156 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3157 adev->psp.xgmi_context.supports_extended_data = true;
3160 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3161 dev_warn(adev->dev, "PSP SOS FW not available");
3168 int psp_init_sos_microcode(struct psp_context *psp,
3169 const char *chip_name)
3171 struct amdgpu_device *adev = psp->adev;
3172 char fw_name[PSP_FW_NAME_LEN];
3173 const struct psp_firmware_header_v1_0 *sos_hdr;
3174 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3175 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3176 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3177 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3179 uint8_t *ucode_array_start_addr;
3183 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3187 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3188 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3192 err = amdgpu_ucode_validate(adev->psp.sos_fw);
3196 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3197 ucode_array_start_addr = (uint8_t *)sos_hdr +
3198 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3199 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3201 switch (sos_hdr->header.header_version_major) {
3203 err = psp_init_sos_base_fw(adev);
3207 if (sos_hdr->header.header_version_minor == 1) {
3208 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3209 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3210 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3211 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3212 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3213 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3214 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3216 if (sos_hdr->header.header_version_minor == 2) {
3217 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3218 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3219 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3220 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3222 if (sos_hdr->header.header_version_minor == 3) {
3223 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3224 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3225 adev->psp.toc.start_addr = ucode_array_start_addr +
3226 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3227 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3228 adev->psp.kdb.start_addr = ucode_array_start_addr +
3229 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3230 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3231 adev->psp.spl.start_addr = ucode_array_start_addr +
3232 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3233 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3234 adev->psp.rl.start_addr = ucode_array_start_addr +
3235 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3239 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3241 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3242 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3247 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3248 err = parse_sos_bin_descriptor(psp,
3249 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3257 "unsupported psp sos firmware\n");
3265 "failed to init sos firmware\n");
3266 release_firmware(adev->psp.sos_fw);
3267 adev->psp.sos_fw = NULL;
3272 static int parse_ta_bin_descriptor(struct psp_context *psp,
3273 const struct psp_fw_bin_desc *desc,
3274 const struct ta_firmware_header_v2_0 *ta_hdr)
3276 uint8_t *ucode_start_addr = NULL;
3278 if (!psp || !desc || !ta_hdr)
3281 ucode_start_addr = (uint8_t *)ta_hdr +
3282 le32_to_cpu(desc->offset_bytes) +
3283 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3285 switch (desc->fw_type) {
3286 case TA_FW_TYPE_PSP_ASD:
3287 psp->asd.fw_version = le32_to_cpu(desc->fw_version);
3288 psp->asd.feature_version = le32_to_cpu(desc->fw_version);
3289 psp->asd.size_bytes = le32_to_cpu(desc->size_bytes);
3290 psp->asd.start_addr = ucode_start_addr;
3292 case TA_FW_TYPE_PSP_XGMI:
3293 psp->xgmi.feature_version = le32_to_cpu(desc->fw_version);
3294 psp->xgmi.size_bytes = le32_to_cpu(desc->size_bytes);
3295 psp->xgmi.start_addr = ucode_start_addr;
3297 case TA_FW_TYPE_PSP_RAS:
3298 psp->ras.feature_version = le32_to_cpu(desc->fw_version);
3299 psp->ras.size_bytes = le32_to_cpu(desc->size_bytes);
3300 psp->ras.start_addr = ucode_start_addr;
3302 case TA_FW_TYPE_PSP_HDCP:
3303 psp->hdcp.feature_version = le32_to_cpu(desc->fw_version);
3304 psp->hdcp.size_bytes = le32_to_cpu(desc->size_bytes);
3305 psp->hdcp.start_addr = ucode_start_addr;
3307 case TA_FW_TYPE_PSP_DTM:
3308 psp->dtm.feature_version = le32_to_cpu(desc->fw_version);
3309 psp->dtm.size_bytes = le32_to_cpu(desc->size_bytes);
3310 psp->dtm.start_addr = ucode_start_addr;
3312 case TA_FW_TYPE_PSP_RAP:
3313 psp->rap.feature_version = le32_to_cpu(desc->fw_version);
3314 psp->rap.size_bytes = le32_to_cpu(desc->size_bytes);
3315 psp->rap.start_addr = ucode_start_addr;
3317 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3318 psp->securedisplay.feature_version = le32_to_cpu(desc->fw_version);
3319 psp->securedisplay.size_bytes = le32_to_cpu(desc->size_bytes);
3320 psp->securedisplay.start_addr = ucode_start_addr;
3323 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3330 int psp_init_ta_microcode(struct psp_context *psp,
3331 const char *chip_name)
3333 struct amdgpu_device *adev = psp->adev;
3334 char fw_name[PSP_FW_NAME_LEN];
3335 const struct ta_firmware_header_v2_0 *ta_hdr;
3340 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3344 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3345 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3349 err = amdgpu_ucode_validate(adev->psp.ta_fw);
3353 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3355 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3356 dev_err(adev->dev, "unsupported TA header version\n");
3361 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3362 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3367 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3368 err = parse_ta_bin_descriptor(psp,
3369 &ta_hdr->ta_fw_bin[ta_index],
3377 dev_err(adev->dev, "fail to initialize ta microcode\n");
3378 release_firmware(adev->psp.ta_fw);
3379 adev->psp.ta_fw = NULL;
3383 static int psp_set_clockgating_state(void *handle,
3384 enum amd_clockgating_state state)
3389 static int psp_set_powergating_state(void *handle,
3390 enum amd_powergating_state state)
3395 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3396 struct device_attribute *attr,
3399 struct drm_device *ddev = dev_get_drvdata(dev);
3400 struct amdgpu_device *adev = drm_to_adev(ddev);
3404 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3405 DRM_INFO("PSP block is not ready yet.");
3409 mutex_lock(&adev->psp.mutex);
3410 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3411 mutex_unlock(&adev->psp.mutex);
3414 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3418 return sysfs_emit(buf, "%x\n", fw_ver);
3421 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3422 struct device_attribute *attr,
3426 struct drm_device *ddev = dev_get_drvdata(dev);
3427 struct amdgpu_device *adev = drm_to_adev(ddev);
3430 const struct firmware *usbc_pd_fw;
3431 struct amdgpu_bo *fw_buf_bo = NULL;
3432 uint64_t fw_pri_mc_addr;
3433 void *fw_pri_cpu_addr;
3435 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3436 DRM_INFO("PSP block is not ready yet.");
3440 if (!drm_dev_enter(ddev, &idx))
3443 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3444 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3448 /* LFB address which is aligned to 1MB boundary per PSP request */
3449 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3450 AMDGPU_GEM_DOMAIN_VRAM,
3457 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3459 mutex_lock(&adev->psp.mutex);
3460 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3461 mutex_unlock(&adev->psp.mutex);
3463 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3466 release_firmware(usbc_pd_fw);
3469 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3477 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3481 if (!drm_dev_enter(&psp->adev->ddev, &idx))
3484 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3485 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3490 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3491 psp_usbc_pd_fw_sysfs_read,
3492 psp_usbc_pd_fw_sysfs_write);
3494 int is_psp_fw_valid(struct psp_bin_desc bin)
3496 return bin.size_bytes;
3499 const struct amd_ip_funcs psp_ip_funcs = {
3501 .early_init = psp_early_init,
3503 .sw_init = psp_sw_init,
3504 .sw_fini = psp_sw_fini,
3505 .hw_init = psp_hw_init,
3506 .hw_fini = psp_hw_fini,
3507 .suspend = psp_suspend,
3508 .resume = psp_resume,
3510 .check_soft_reset = NULL,
3511 .wait_for_idle = NULL,
3513 .set_clockgating_state = psp_set_clockgating_state,
3514 .set_powergating_state = psp_set_powergating_state,
3517 static int psp_sysfs_init(struct amdgpu_device *adev)
3519 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3522 DRM_ERROR("Failed to create USBC PD FW control file!");
3527 static void psp_sysfs_fini(struct amdgpu_device *adev)
3529 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3532 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3534 .type = AMD_IP_BLOCK_TYPE_PSP,
3538 .funcs = &psp_ip_funcs,
3541 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3543 .type = AMD_IP_BLOCK_TYPE_PSP,
3547 .funcs = &psp_ip_funcs,
3550 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3552 .type = AMD_IP_BLOCK_TYPE_PSP,
3556 .funcs = &psp_ip_funcs,
3559 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3560 .type = AMD_IP_BLOCK_TYPE_PSP,
3564 .funcs = &psp_ip_funcs,
3567 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3569 .type = AMD_IP_BLOCK_TYPE_PSP,
3573 .funcs = &psp_ip_funcs,
3576 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3577 .type = AMD_IP_BLOCK_TYPE_PSP,
3581 .funcs = &psp_ip_funcs,