drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_jpeg.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15d.h"
  31 #include "soc15_common.h"
  32
  33 #define JPEG_IDLE_TIMEOUT       msecs_to_jiffies(1000)
  34
  35 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
  36
  37 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
  38 {
  39         INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
  40         mutex_init(&adev->jpeg.jpeg_pg_lock);
  41         atomic_set(&adev->jpeg.total_submission_cnt, 0);
  42
  43         return 0;
  44 }
  45
  46 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
  47 {
  48         int i;
  49
  50         cancel_delayed_work_sync(&adev->jpeg.idle_work);
  51
  52         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  53                 if (adev->jpeg.harvest_config & (1 << i))
  54                         continue;
  55
  56                 amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec);
  57         }
  58
  59         mutex_destroy(&adev->jpeg.jpeg_pg_lock);
  60
  61         return 0;
  62 }
  63
  64 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
  65 {
  66         cancel_delayed_work_sync(&adev->jpeg.idle_work);
  67
  68         return 0;
  69 }
  70
  71 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
  72 {
  73         return 0;
  74 }
  75
  76 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
  77 {
  78         struct amdgpu_device *adev =
  79                 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
  80         unsigned int fences = 0;
  81         unsigned int i;
  82
  83         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  84                 if (adev->jpeg.harvest_config & (1 << i))
  85                         continue;
  86
  87                 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec);
  88         }
  89
  90         if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
  91                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
  92                                                        AMD_PG_STATE_GATE);
  93         else
  94                 schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
  95 }
  96
  97 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
  98 {
  99         struct amdgpu_device *adev = ring->adev;
 100
 101         atomic_inc(&adev->jpeg.total_submission_cnt);
 102         cancel_delayed_work_sync(&adev->jpeg.idle_work);
 103
 104         mutex_lock(&adev->jpeg.jpeg_pg_lock);
 105         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
 106                                                        AMD_PG_STATE_UNGATE);
 107         mutex_unlock(&adev->jpeg.jpeg_pg_lock);
 108 }
 109
 110 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
 111 {
 112         atomic_dec(&ring->adev->jpeg.total_submission_cnt);
 113         schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
 114 }
 115
 116 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119         uint32_t tmp = 0;
 120         unsigned i;
 121         int r;
 122
 123         WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
 124         r = amdgpu_ring_alloc(ring, 3);
 125         if (r)
 126                 return r;
 127
 128         amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
 129         amdgpu_ring_write(ring, 0xDEADBEEF);
 130         amdgpu_ring_commit(ring);
 131
 132         for (i = 0; i < adev->usec_timeout; i++) {
 133                 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
 134                 if (tmp == 0xDEADBEEF)
 135                         break;
 136                 udelay(1);
 137         }
 138
 139         if (i >= adev->usec_timeout)
 140                 r = -ETIMEDOUT;
 141
 142         return r;
 143 }
 144
 145 static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 146                 struct dma_fence **fence)
 147 {
 148         struct amdgpu_device *adev = ring->adev;
 149         struct amdgpu_job *job;
 150         struct amdgpu_ib *ib;
 151         struct dma_fence *f = NULL;
 152         const unsigned ib_size_dw = 16;
 153         int i, r;
 154
 155         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 156                                         AMDGPU_IB_POOL_DIRECT, &job);
 157         if (r)
 158                 return r;
 159
 160         ib = &job->ibs[0];
 161
 162         ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
 163         ib->ptr[1] = 0xDEADBEEF;
 164         for (i = 2; i < 16; i += 2) {
 165                 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
 166                 ib->ptr[i+1] = 0;
 167         }
 168         ib->length_dw = 16;
 169
 170         r = amdgpu_job_submit_direct(job, ring, &f);
 171         if (r)
 172                 goto err;
 173
 174         if (fence)
 175                 *fence = dma_fence_get(f);
 176         dma_fence_put(f);
 177
 178         return 0;
 179
 180 err:
 181         amdgpu_job_free(job);
 182         return r;
 183 }
 184
 185 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 186 {
 187         struct amdgpu_device *adev = ring->adev;
 188         uint32_t tmp = 0;
 189         unsigned i;
 190         struct dma_fence *fence = NULL;
 191         long r = 0;
 192
 193         r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
 194         if (r)
 195                 goto error;
 196
 197         r = dma_fence_wait_timeout(fence, false, timeout);
 198         if (r == 0) {
 199                 r = -ETIMEDOUT;
 200                 goto error;
 201         } else if (r < 0) {
 202                 goto error;
 203         } else {
 204                 r = 0;
 205         }
 206
 207         for (i = 0; i < adev->usec_timeout; i++) {
 208                 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
 209                 if (tmp == 0xDEADBEEF)
 210                         break;
 211                 udelay(1);
 212         }
 213
 214         if (i >= adev->usec_timeout)
 215                 r = -ETIMEDOUT;
 216
 217         dma_fence_put(fence);
 218 error:
 219         return r;
 220 }