drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <drm/drm_drv.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42
  43 /*
  44  * Fences
  45  * Fences mark an event in the GPUs pipeline and are used
  46  * for GPU/CPU synchronization.  When the fence is written,
  47  * it is expected that all buffers associated with that fence
  48  * are no longer in use by the associated ring on the GPU and
  49  * that the the relevant GPU caches have been flushed.
  50  */
  51
  52 struct amdgpu_fence {
  53         struct dma_fence base;
  54
  55         /* RB, DMA, etc. */
  56         struct amdgpu_ring              *ring;
  57 };
  58
  59 static struct kmem_cache *amdgpu_fence_slab;
  60
  61 int amdgpu_fence_slab_init(void)
  62 {
  63         amdgpu_fence_slab = kmem_cache_create(
  64                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  65                 SLAB_HWCACHE_ALIGN, NULL);
  66         if (!amdgpu_fence_slab)
  67                 return -ENOMEM;
  68         return 0;
  69 }
  70
  71 void amdgpu_fence_slab_fini(void)
  72 {
  73         rcu_barrier();
  74         kmem_cache_destroy(amdgpu_fence_slab);
  75 }
  76 /*
  77  * Cast helper
  78  */
  79 static const struct dma_fence_ops amdgpu_fence_ops;
  80 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  81 {
  82         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  83
  84         if (__f->base.ops == &amdgpu_fence_ops)
  85                 return __f;
  86
  87         return NULL;
  88 }
  89
  90 /**
  91  * amdgpu_fence_write - write a fence value
  92  *
  93  * @ring: ring the fence is associated with
  94  * @seq: sequence number to write
  95  *
  96  * Writes a fence value to memory (all asics).
  97  */
  98 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  99 {
 100         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 101
 102         if (drv->cpu_addr)
 103                 *drv->cpu_addr = cpu_to_le32(seq);
 104 }
 105
 106 /**
 107  * amdgpu_fence_read - read a fence value
 108  *
 109  * @ring: ring the fence is associated with
 110  *
 111  * Reads a fence value from memory (all asics).
 112  * Returns the value of the fence read from memory.
 113  */
 114 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 115 {
 116         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 117         u32 seq = 0;
 118
 119         if (drv->cpu_addr)
 120                 seq = le32_to_cpu(*drv->cpu_addr);
 121         else
 122                 seq = atomic_read(&drv->last_seq);
 123
 124         return seq;
 125 }
 126
 127 /**
 128  * amdgpu_fence_emit - emit a fence on the requested ring
 129  *
 130  * @ring: ring the fence is associated with
 131  * @f: resulting fence object
 132  * @flags: flags to pass into the subordinate .emit_fence() call
 133  *
 134  * Emits a fence command on the requested ring (all asics).
 135  * Returns 0 on success, -ENOMEM on failure.
 136  */
 137 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
 138                       unsigned flags)
 139 {
 140         struct amdgpu_device *adev = ring->adev;
 141         struct amdgpu_fence *fence;
 142         struct dma_fence __rcu **ptr;
 143         uint32_t seq;
 144         int r;
 145
 146         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
 147         if (fence == NULL)
 148                 return -ENOMEM;
 149
 150         seq = ++ring->fence_drv.sync_seq;
 151         fence->ring = ring;
 152         dma_fence_init(&fence->base, &amdgpu_fence_ops,
 153                        &ring->fence_drv.lock,
 154                        adev->fence_context + ring->idx,
 155                        seq);
 156         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 157                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 158         pm_runtime_get_noresume(adev_to_drm(adev)->dev);
 159         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 160         if (unlikely(rcu_dereference_protected(*ptr, 1))) {
 161                 struct dma_fence *old;
 162
 163                 rcu_read_lock();
 164                 old = dma_fence_get_rcu_safe(ptr);
 165                 rcu_read_unlock();
 166
 167                 if (old) {
 168                         r = dma_fence_wait(old, false);
 169                         dma_fence_put(old);
 170                         if (r)
 171                                 return r;
 172                 }
 173         }
 174
 175         /* This function can't be called concurrently anyway, otherwise
 176          * emitting the fence would mess up the hardware ring buffer.
 177          */
 178         rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
 179
 180         *f = &fence->base;
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 187  *
 188  * @ring: ring the fence is associated with
 189  * @s: resulting sequence number
 190  * @timeout: the timeout for waiting in usecs
 191  *
 192  * Emits a fence command on the requested ring (all asics).
 193  * Used For polling fence.
 194  * Returns 0 on success, -ENOMEM on failure.
 195  */
 196 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
 197                               uint32_t timeout)
 198 {
 199         uint32_t seq;
 200         signed long r;
 201
 202         if (!s)
 203                 return -EINVAL;
 204
 205         seq = ++ring->fence_drv.sync_seq;
 206         r = amdgpu_fence_wait_polling(ring,
 207                                       seq - ring->fence_drv.num_fences_mask,
 208                                       timeout);
 209         if (r < 1)
 210                 return -ETIMEDOUT;
 211
 212         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 213                                seq, 0);
 214
 215         *s = seq;
 216
 217         return 0;
 218 }
 219
 220 /**
 221  * amdgpu_fence_schedule_fallback - schedule fallback check
 222  *
 223  * @ring: pointer to struct amdgpu_ring
 224  *
 225  * Start a timer as fallback to our interrupts.
 226  */
 227 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 228 {
 229         mod_timer(&ring->fence_drv.fallback_timer,
 230                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 231 }
 232
 233 /**
 234  * amdgpu_fence_process - check for fence activity
 235  *
 236  * @ring: pointer to struct amdgpu_ring
 237  *
 238  * Checks the current fence value and calculates the last
 239  * signalled fence value. Wakes the fence queue if the
 240  * sequence number has increased.
 241  *
 242  * Returns true if fence was processed
 243  */
 244 bool amdgpu_fence_process(struct amdgpu_ring *ring)
 245 {
 246         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 247         struct amdgpu_device *adev = ring->adev;
 248         uint32_t seq, last_seq;
 249         int r;
 250
 251         do {
 252                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 253                 seq = amdgpu_fence_read(ring);
 254
 255         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 256
 257         if (del_timer(&ring->fence_drv.fallback_timer) &&
 258             seq != ring->fence_drv.sync_seq)
 259                 amdgpu_fence_schedule_fallback(ring);
 260
 261         if (unlikely(seq == last_seq))
 262                 return false;
 263
 264         last_seq &= drv->num_fences_mask;
 265         seq &= drv->num_fences_mask;
 266
 267         do {
 268                 struct dma_fence *fence, **ptr;
 269
 270                 ++last_seq;
 271                 last_seq &= drv->num_fences_mask;
 272                 ptr = &drv->fences[last_seq];
 273
 274                 /* There is always exactly one thread signaling this fence slot */
 275                 fence = rcu_dereference_protected(*ptr, 1);
 276                 RCU_INIT_POINTER(*ptr, NULL);
 277
 278                 if (!fence)
 279                         continue;
 280
 281                 r = dma_fence_signal(fence);
 282                 if (!r)
 283                         DMA_FENCE_TRACE(fence, "signaled from irq context\n");
 284                 else
 285                         BUG();
 286
 287                 dma_fence_put(fence);
 288                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 289                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 290         } while (last_seq != seq);
 291
 292         return true;
 293 }
 294
 295 /**
 296  * amdgpu_fence_fallback - fallback for hardware interrupts
 297  *
 298  * @t: timer context used to obtain the pointer to ring structure
 299  *
 300  * Checks for fence activity.
 301  */
 302 static void amdgpu_fence_fallback(struct timer_list *t)
 303 {
 304         struct amdgpu_ring *ring = from_timer(ring, t,
 305                                               fence_drv.fallback_timer);
 306
 307         if (amdgpu_fence_process(ring))
 308                 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
 309 }
 310
 311 /**
 312  * amdgpu_fence_wait_empty - wait for all fences to signal
 313  *
 314  * @ring: ring index the fence is associated with
 315  *
 316  * Wait for all fences on the requested ring to signal (all asics).
 317  * Returns 0 if the fences have passed, error for all other cases.
 318  */
 319 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 320 {
 321         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 322         struct dma_fence *fence, **ptr;
 323         int r;
 324
 325         if (!seq)
 326                 return 0;
 327
 328         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 329         rcu_read_lock();
 330         fence = rcu_dereference(*ptr);
 331         if (!fence || !dma_fence_get_rcu(fence)) {
 332                 rcu_read_unlock();
 333                 return 0;
 334         }
 335         rcu_read_unlock();
 336
 337         r = dma_fence_wait(fence, false);
 338         dma_fence_put(fence);
 339         return r;
 340 }
 341
 342 /**
 343  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 344  *
 345  * @ring: ring index the fence is associated with
 346  * @wait_seq: sequence number to wait
 347  * @timeout: the timeout for waiting in usecs
 348  *
 349  * Wait for all fences on the requested ring to signal (all asics).
 350  * Returns left time if no timeout, 0 or minus if timeout.
 351  */
 352 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 353                                       uint32_t wait_seq,
 354                                       signed long timeout)
 355 {
 356         uint32_t seq;
 357
 358         do {
 359                 seq = amdgpu_fence_read(ring);
 360                 udelay(5);
 361                 timeout -= 5;
 362         } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 363
 364         return timeout > 0 ? timeout : 0;
 365 }
 366 /**
 367  * amdgpu_fence_count_emitted - get the count of emitted fences
 368  *
 369  * @ring: ring the fence is associated with
 370  *
 371  * Get the number of fences emitted on the requested ring (all asics).
 372  * Returns the number of emitted fences on the ring.  Used by the
 373  * dynpm code to ring track activity.
 374  */
 375 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 376 {
 377         uint64_t emitted;
 378
 379         /* We are not protected by ring lock when reading the last sequence
 380          * but it's ok to report slightly wrong fence count here.
 381          */
 382         amdgpu_fence_process(ring);
 383         emitted = 0x100000000ull;
 384         emitted -= atomic_read(&ring->fence_drv.last_seq);
 385         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 386         return lower_32_bits(emitted);
 387 }
 388
 389 /**
 390  * amdgpu_fence_driver_start_ring - make the fence driver
 391  * ready for use on the requested ring.
 392  *
 393  * @ring: ring to start the fence driver on
 394  * @irq_src: interrupt source to use for this ring
 395  * @irq_type: interrupt type to use for this ring
 396  *
 397  * Make the fence driver ready for processing (all asics).
 398  * Not all asics have all rings, so each asic will only
 399  * start the fence driver on the rings it has.
 400  * Returns 0 for success, errors for failure.
 401  */
 402 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 403                                    struct amdgpu_irq_src *irq_src,
 404                                    unsigned irq_type)
 405 {
 406         struct amdgpu_device *adev = ring->adev;
 407         uint64_t index;
 408
 409         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 410                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 411                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 412         } else {
 413                 /* put fence directly behind firmware */
 414                 index = ALIGN(adev->uvd.fw->size, 8);
 415                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 416                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 417         }
 418         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 419
 420         ring->fence_drv.irq_src = irq_src;
 421         ring->fence_drv.irq_type = irq_type;
 422         ring->fence_drv.initialized = true;
 423
 424         DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
 425                       ring->name, ring->fence_drv.gpu_addr);
 426         return 0;
 427 }
 428
 429 /**
 430  * amdgpu_fence_driver_init_ring - init the fence driver
 431  * for the requested ring.
 432  *
 433  * @ring: ring to init the fence driver on
 434  * @num_hw_submission: number of entries on the hardware queue
 435  * @sched_score: optional score atomic shared with other schedulers
 436  *
 437  * Init the fence driver for the requested ring (all asics).
 438  * Helper function for amdgpu_fence_driver_init().
 439  */
 440 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 441                                   unsigned num_hw_submission,
 442                                   atomic_t *sched_score)
 443 {
 444         struct amdgpu_device *adev = ring->adev;
 445         long timeout;
 446         int r;
 447
 448         if (!adev)
 449                 return -EINVAL;
 450
 451         if (!is_power_of_2(num_hw_submission))
 452                 return -EINVAL;
 453
 454         ring->fence_drv.cpu_addr = NULL;
 455         ring->fence_drv.gpu_addr = 0;
 456         ring->fence_drv.sync_seq = 0;
 457         atomic_set(&ring->fence_drv.last_seq, 0);
 458         ring->fence_drv.initialized = false;
 459
 460         timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
 461
 462         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 463         spin_lock_init(&ring->fence_drv.lock);
 464         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 465                                          GFP_KERNEL);
 466         if (!ring->fence_drv.fences)
 467                 return -ENOMEM;
 468
 469         /* No need to setup the GPU scheduler for rings that don't need it */
 470         if (ring->no_scheduler)
 471                 return 0;
 472
 473         switch (ring->funcs->type) {
 474         case AMDGPU_RING_TYPE_GFX:
 475                 timeout = adev->gfx_timeout;
 476                 break;
 477         case AMDGPU_RING_TYPE_COMPUTE:
 478                 timeout = adev->compute_timeout;
 479                 break;
 480         case AMDGPU_RING_TYPE_SDMA:
 481                 timeout = adev->sdma_timeout;
 482                 break;
 483         default:
 484                 timeout = adev->video_timeout;
 485                 break;
 486         }
 487
 488         r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
 489                            num_hw_submission, amdgpu_job_hang_limit,
 490                            timeout, NULL, sched_score, ring->name);
 491         if (r) {
 492                 DRM_ERROR("Failed to create scheduler on ring %s.\n",
 493                           ring->name);
 494                 return r;
 495         }
 496
 497         return 0;
 498 }
 499
 500 /**
 501  * amdgpu_fence_driver_sw_init - init the fence driver
 502  * for all possible rings.
 503  *
 504  * @adev: amdgpu device pointer
 505  *
 506  * Init the fence driver for all possible rings (all asics).
 507  * Not all asics have all rings, so each asic will only
 508  * start the fence driver on the rings it has using
 509  * amdgpu_fence_driver_start_ring().
 510  * Returns 0 for success.
 511  */
 512 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
 513 {
 514         return 0;
 515 }
 516
 517 /**
 518  * amdgpu_fence_driver_hw_fini - tear down the fence driver
 519  * for all possible rings.
 520  *
 521  * @adev: amdgpu device pointer
 522  *
 523  * Tear down the fence driver for all possible rings (all asics).
 524  */
 525 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
 526 {
 527         int i, r;
 528
 529         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 530                 struct amdgpu_ring *ring = adev->rings[i];
 531
 532                 if (!ring || !ring->fence_drv.initialized)
 533                         continue;
 534
 535                 /* You can't wait for HW to signal if it's gone */
 536                 if (!drm_dev_is_unplugged(&adev->ddev))
 537                         r = amdgpu_fence_wait_empty(ring);
 538                 else
 539                         r = -ENODEV;
 540                 /* no need to trigger GPU reset as we are unloading */
 541                 if (r)
 542                         amdgpu_fence_driver_force_completion(ring);
 543
 544                 if (ring->fence_drv.irq_src)
 545                         amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 546                                        ring->fence_drv.irq_type);
 547
 548                 del_timer_sync(&ring->fence_drv.fallback_timer);
 549         }
 550 }
 551
 552 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
 553 {
 554         unsigned int i, j;
 555
 556         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 557                 struct amdgpu_ring *ring = adev->rings[i];
 558
 559                 if (!ring || !ring->fence_drv.initialized)
 560                         continue;
 561
 562                 if (!ring->no_scheduler)
 563                         drm_sched_fini(&ring->sched);
 564
 565                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 566                         dma_fence_put(ring->fence_drv.fences[j]);
 567                 kfree(ring->fence_drv.fences);
 568                 ring->fence_drv.fences = NULL;
 569                 ring->fence_drv.initialized = false;
 570         }
 571 }
 572
 573 /**
 574  * amdgpu_fence_driver_hw_init - enable the fence driver
 575  * for all possible rings.
 576  *
 577  * @adev: amdgpu device pointer
 578  *
 579  * Enable the fence driver for all possible rings (all asics).
 580  * Not all asics have all rings, so each asic will only
 581  * start the fence driver on the rings it has using
 582  * amdgpu_fence_driver_start_ring().
 583  * Returns 0 for success.
 584  */
 585 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
 586 {
 587         int i;
 588
 589         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 590                 struct amdgpu_ring *ring = adev->rings[i];
 591                 if (!ring || !ring->fence_drv.initialized)
 592                         continue;
 593
 594                 /* enable the interrupt */
 595                 if (ring->fence_drv.irq_src)
 596                         amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 597                                        ring->fence_drv.irq_type);
 598         }
 599 }
 600
 601 /**
 602  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 603  *
 604  * @ring: fence of the ring to signal
 605  *
 606  */
 607 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 608 {
 609         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 610         amdgpu_fence_process(ring);
 611 }
 612
 613 /*
 614  * Common fence implementation
 615  */
 616
 617 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 618 {
 619         return "amdgpu";
 620 }
 621
 622 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 623 {
 624         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 625         return (const char *)fence->ring->name;
 626 }
 627
 628 /**
 629  * amdgpu_fence_enable_signaling - enable signalling on fence
 630  * @f: fence
 631  *
 632  * This function is called with fence_queue lock held, and adds a callback
 633  * to fence_queue that checks if this fence is signaled, and if so it
 634  * signals the fence and removes itself.
 635  */
 636 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 637 {
 638         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 639         struct amdgpu_ring *ring = fence->ring;
 640
 641         if (!timer_pending(&ring->fence_drv.fallback_timer))
 642                 amdgpu_fence_schedule_fallback(ring);
 643
 644         DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 645
 646         return true;
 647 }
 648
 649 /**
 650  * amdgpu_fence_free - free up the fence memory
 651  *
 652  * @rcu: RCU callback head
 653  *
 654  * Free up the fence memory after the RCU grace period.
 655  */
 656 static void amdgpu_fence_free(struct rcu_head *rcu)
 657 {
 658         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 659         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 660         kmem_cache_free(amdgpu_fence_slab, fence);
 661 }
 662
 663 /**
 664  * amdgpu_fence_release - callback that fence can be freed
 665  *
 666  * @f: fence
 667  *
 668  * This function is called when the reference count becomes zero.
 669  * It just RCU schedules freeing up the fence.
 670  */
 671 static void amdgpu_fence_release(struct dma_fence *f)
 672 {
 673         call_rcu(&f->rcu, amdgpu_fence_free);
 674 }
 675
 676 static const struct dma_fence_ops amdgpu_fence_ops = {
 677         .get_driver_name = amdgpu_fence_get_driver_name,
 678         .get_timeline_name = amdgpu_fence_get_timeline_name,
 679         .enable_signaling = amdgpu_fence_enable_signaling,
 680         .release = amdgpu_fence_release,
 681 };
 682
 683 /*
 684  * Fence debugfs
 685  */
 686 #if defined(CONFIG_DEBUG_FS)
 687 static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
 688 {
 689         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
 690         int i;
 691
 692         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 693                 struct amdgpu_ring *ring = adev->rings[i];
 694                 if (!ring || !ring->fence_drv.initialized)
 695                         continue;
 696
 697                 amdgpu_fence_process(ring);
 698
 699                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 700                 seq_printf(m, "Last signaled fence          0x%08x\n",
 701                            atomic_read(&ring->fence_drv.last_seq));
 702                 seq_printf(m, "Last emitted                 0x%08x\n",
 703                            ring->fence_drv.sync_seq);
 704
 705                 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
 706                     ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
 707                         seq_printf(m, "Last signaled trailing fence 0x%08x\n",
 708                                    le32_to_cpu(*ring->trail_fence_cpu_addr));
 709                         seq_printf(m, "Last emitted                 0x%08x\n",
 710                                    ring->trail_seq);
 711                 }
 712
 713                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 714                         continue;
 715
 716                 /* set in CP_VMID_PREEMPT and preemption occurred */
 717                 seq_printf(m, "Last preempted               0x%08x\n",
 718                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 719                 /* set in CP_VMID_RESET and reset occurred */
 720                 seq_printf(m, "Last reset                   0x%08x\n",
 721                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 722                 /* Both preemption and reset occurred */
 723                 seq_printf(m, "Last both                    0x%08x\n",
 724                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 725         }
 726         return 0;
 727 }
 728
 729 /*
 730  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 731  *
 732  * Manually trigger a gpu reset at the next fence wait.
 733  */
 734 static int gpu_recover_get(void *data, u64 *val)
 735 {
 736         struct amdgpu_device *adev = (struct amdgpu_device *)data;
 737         struct drm_device *dev = adev_to_drm(adev);
 738         int r;
 739
 740         r = pm_runtime_get_sync(dev->dev);
 741         if (r < 0) {
 742                 pm_runtime_put_autosuspend(dev->dev);
 743                 return 0;
 744         }
 745
 746         *val = amdgpu_device_gpu_recover(adev, NULL);
 747
 748         pm_runtime_mark_last_busy(dev->dev);
 749         pm_runtime_put_autosuspend(dev->dev);
 750
 751         return 0;
 752 }
 753
 754 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
 755 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
 756                          "%lld\n");
 757
 758 #endif
 759
 760 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 761 {
 762 #if defined(CONFIG_DEBUG_FS)
 763         struct drm_minor *minor = adev_to_drm(adev)->primary;
 764         struct dentry *root = minor->debugfs_root;
 765
 766         debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
 767                             &amdgpu_debugfs_fence_info_fops);
 768
 769         if (!amdgpu_sriov_vf(adev))
 770                 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
 771                                     &amdgpu_debugfs_gpu_recover_fops);
 772 #endif
 773 }
 774