drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <drm/drm_drv.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42
  43 /*
  44  * Fences
  45  * Fences mark an event in the GPUs pipeline and are used
  46  * for GPU/CPU synchronization.  When the fence is written,
  47  * it is expected that all buffers associated with that fence
  48  * are no longer in use by the associated ring on the GPU and
  49  * that the the relevant GPU caches have been flushed.
  50  */
  51
  52 struct amdgpu_fence {
  53         struct dma_fence base;
  54
  55         /* RB, DMA, etc. */
  56         struct amdgpu_ring              *ring;
  57 };
  58
  59 static struct kmem_cache *amdgpu_fence_slab;
  60
  61 int amdgpu_fence_slab_init(void)
  62 {
  63         amdgpu_fence_slab = kmem_cache_create(
  64                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  65                 SLAB_HWCACHE_ALIGN, NULL);
  66         if (!amdgpu_fence_slab)
  67                 return -ENOMEM;
  68         return 0;
  69 }
  70
  71 void amdgpu_fence_slab_fini(void)
  72 {
  73         rcu_barrier();
  74         kmem_cache_destroy(amdgpu_fence_slab);
  75 }
  76 /*
  77  * Cast helper
  78  */
  79 static const struct dma_fence_ops amdgpu_fence_ops;
  80 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  81 {
  82         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  83
  84         if (__f->base.ops == &amdgpu_fence_ops)
  85                 return __f;
  86
  87         return NULL;
  88 }
  89
  90 /**
  91  * amdgpu_fence_write - write a fence value
  92  *
  93  * @ring: ring the fence is associated with
  94  * @seq: sequence number to write
  95  *
  96  * Writes a fence value to memory (all asics).
  97  */
  98 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  99 {
 100         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 101
 102         if (drv->cpu_addr)
 103                 *drv->cpu_addr = cpu_to_le32(seq);
 104 }
 105
 106 /**
 107  * amdgpu_fence_read - read a fence value
 108  *
 109  * @ring: ring the fence is associated with
 110  *
 111  * Reads a fence value from memory (all asics).
 112  * Returns the value of the fence read from memory.
 113  */
 114 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 115 {
 116         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 117         u32 seq = 0;
 118
 119         if (drv->cpu_addr)
 120                 seq = le32_to_cpu(*drv->cpu_addr);
 121         else
 122                 seq = atomic_read(&drv->last_seq);
 123
 124         return seq;
 125 }
 126
 127 /**
 128  * amdgpu_fence_emit - emit a fence on the requested ring
 129  *
 130  * @ring: ring the fence is associated with
 131  * @f: resulting fence object
 132  * @job: job the fence is embedded in
 133  * @flags: flags to pass into the subordinate .emit_fence() call
 134  *
 135  * Emits a fence command on the requested ring (all asics).
 136  * Returns 0 on success, -ENOMEM on failure.
 137  */
 138 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,
 139                       unsigned flags)
 140 {
 141         struct amdgpu_device *adev = ring->adev;
 142         struct dma_fence *fence;
 143         struct amdgpu_fence *am_fence;
 144         struct dma_fence __rcu **ptr;
 145         uint32_t seq;
 146         int r;
 147
 148         if (job == NULL) {
 149                 /* create a sperate hw fence */
 150                 am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
 151                 if (am_fence == NULL)
 152                         return -ENOMEM;
 153                 fence = &am_fence->base;
 154                 am_fence->ring = ring;
 155         } else {
 156                 /* take use of job-embedded fence */
 157                 fence = &job->hw_fence;
 158         }
 159
 160         seq = ++ring->fence_drv.sync_seq;
 161         if (job != NULL && job->job_run_counter) {
 162                 /* reinit seq for resubmitted jobs */
 163                 fence->seqno = seq;
 164         } else {
 165                 dma_fence_init(fence, &amdgpu_fence_ops,
 166                                 &ring->fence_drv.lock,
 167                                 adev->fence_context + ring->idx,
 168                                 seq);
 169         }
 170
 171         if (job != NULL) {
 172                 /* mark this fence has a parent job */
 173                 set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &fence->flags);
 174         }
 175
 176         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 177                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 178         pm_runtime_get_noresume(adev_to_drm(adev)->dev);
 179         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 180         if (unlikely(rcu_dereference_protected(*ptr, 1))) {
 181                 struct dma_fence *old;
 182
 183                 rcu_read_lock();
 184                 old = dma_fence_get_rcu_safe(ptr);
 185                 rcu_read_unlock();
 186
 187                 if (old) {
 188                         r = dma_fence_wait(old, false);
 189                         dma_fence_put(old);
 190                         if (r)
 191                                 return r;
 192                 }
 193         }
 194
 195         /* This function can't be called concurrently anyway, otherwise
 196          * emitting the fence would mess up the hardware ring buffer.
 197          */
 198         rcu_assign_pointer(*ptr, dma_fence_get(fence));
 199
 200         *f = fence;
 201
 202         return 0;
 203 }
 204
 205 /**
 206  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 207  *
 208  * @ring: ring the fence is associated with
 209  * @s: resulting sequence number
 210  * @timeout: the timeout for waiting in usecs
 211  *
 212  * Emits a fence command on the requested ring (all asics).
 213  * Used For polling fence.
 214  * Returns 0 on success, -ENOMEM on failure.
 215  */
 216 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
 217                               uint32_t timeout)
 218 {
 219         uint32_t seq;
 220         signed long r;
 221
 222         if (!s)
 223                 return -EINVAL;
 224
 225         seq = ++ring->fence_drv.sync_seq;
 226         r = amdgpu_fence_wait_polling(ring,
 227                                       seq - ring->fence_drv.num_fences_mask,
 228                                       timeout);
 229         if (r < 1)
 230                 return -ETIMEDOUT;
 231
 232         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 233                                seq, 0);
 234
 235         *s = seq;
 236
 237         return 0;
 238 }
 239
 240 /**
 241  * amdgpu_fence_schedule_fallback - schedule fallback check
 242  *
 243  * @ring: pointer to struct amdgpu_ring
 244  *
 245  * Start a timer as fallback to our interrupts.
 246  */
 247 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 248 {
 249         mod_timer(&ring->fence_drv.fallback_timer,
 250                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 251 }
 252
 253 /**
 254  * amdgpu_fence_process - check for fence activity
 255  *
 256  * @ring: pointer to struct amdgpu_ring
 257  *
 258  * Checks the current fence value and calculates the last
 259  * signalled fence value. Wakes the fence queue if the
 260  * sequence number has increased.
 261  *
 262  * Returns true if fence was processed
 263  */
 264 bool amdgpu_fence_process(struct amdgpu_ring *ring)
 265 {
 266         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 267         struct amdgpu_device *adev = ring->adev;
 268         uint32_t seq, last_seq;
 269         int r;
 270
 271         do {
 272                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 273                 seq = amdgpu_fence_read(ring);
 274
 275         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 276
 277         if (del_timer(&ring->fence_drv.fallback_timer) &&
 278             seq != ring->fence_drv.sync_seq)
 279                 amdgpu_fence_schedule_fallback(ring);
 280
 281         if (unlikely(seq == last_seq))
 282                 return false;
 283
 284         last_seq &= drv->num_fences_mask;
 285         seq &= drv->num_fences_mask;
 286
 287         do {
 288                 struct dma_fence *fence, **ptr;
 289
 290                 ++last_seq;
 291                 last_seq &= drv->num_fences_mask;
 292                 ptr = &drv->fences[last_seq];
 293
 294                 /* There is always exactly one thread signaling this fence slot */
 295                 fence = rcu_dereference_protected(*ptr, 1);
 296                 RCU_INIT_POINTER(*ptr, NULL);
 297
 298                 if (!fence)
 299                         continue;
 300
 301                 r = dma_fence_signal(fence);
 302                 if (!r)
 303                         DMA_FENCE_TRACE(fence, "signaled from irq context\n");
 304                 else
 305                         BUG();
 306
 307                 dma_fence_put(fence);
 308                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 309                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 310         } while (last_seq != seq);
 311
 312         return true;
 313 }
 314
 315 /**
 316  * amdgpu_fence_fallback - fallback for hardware interrupts
 317  *
 318  * @t: timer context used to obtain the pointer to ring structure
 319  *
 320  * Checks for fence activity.
 321  */
 322 static void amdgpu_fence_fallback(struct timer_list *t)
 323 {
 324         struct amdgpu_ring *ring = from_timer(ring, t,
 325                                               fence_drv.fallback_timer);
 326
 327         if (amdgpu_fence_process(ring))
 328                 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
 329 }
 330
 331 /**
 332  * amdgpu_fence_wait_empty - wait for all fences to signal
 333  *
 334  * @ring: ring index the fence is associated with
 335  *
 336  * Wait for all fences on the requested ring to signal (all asics).
 337  * Returns 0 if the fences have passed, error for all other cases.
 338  */
 339 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 340 {
 341         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 342         struct dma_fence *fence, **ptr;
 343         int r;
 344
 345         if (!seq)
 346                 return 0;
 347
 348         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 349         rcu_read_lock();
 350         fence = rcu_dereference(*ptr);
 351         if (!fence || !dma_fence_get_rcu(fence)) {
 352                 rcu_read_unlock();
 353                 return 0;
 354         }
 355         rcu_read_unlock();
 356
 357         r = dma_fence_wait(fence, false);
 358         dma_fence_put(fence);
 359         return r;
 360 }
 361
 362 /**
 363  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 364  *
 365  * @ring: ring index the fence is associated with
 366  * @wait_seq: sequence number to wait
 367  * @timeout: the timeout for waiting in usecs
 368  *
 369  * Wait for all fences on the requested ring to signal (all asics).
 370  * Returns left time if no timeout, 0 or minus if timeout.
 371  */
 372 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 373                                       uint32_t wait_seq,
 374                                       signed long timeout)
 375 {
 376         uint32_t seq;
 377
 378         do {
 379                 seq = amdgpu_fence_read(ring);
 380                 udelay(5);
 381                 timeout -= 5;
 382         } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 383
 384         return timeout > 0 ? timeout : 0;
 385 }
 386 /**
 387  * amdgpu_fence_count_emitted - get the count of emitted fences
 388  *
 389  * @ring: ring the fence is associated with
 390  *
 391  * Get the number of fences emitted on the requested ring (all asics).
 392  * Returns the number of emitted fences on the ring.  Used by the
 393  * dynpm code to ring track activity.
 394  */
 395 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 396 {
 397         uint64_t emitted;
 398
 399         /* We are not protected by ring lock when reading the last sequence
 400          * but it's ok to report slightly wrong fence count here.
 401          */
 402         amdgpu_fence_process(ring);
 403         emitted = 0x100000000ull;
 404         emitted -= atomic_read(&ring->fence_drv.last_seq);
 405         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 406         return lower_32_bits(emitted);
 407 }
 408
 409 /**
 410  * amdgpu_fence_driver_start_ring - make the fence driver
 411  * ready for use on the requested ring.
 412  *
 413  * @ring: ring to start the fence driver on
 414  * @irq_src: interrupt source to use for this ring
 415  * @irq_type: interrupt type to use for this ring
 416  *
 417  * Make the fence driver ready for processing (all asics).
 418  * Not all asics have all rings, so each asic will only
 419  * start the fence driver on the rings it has.
 420  * Returns 0 for success, errors for failure.
 421  */
 422 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 423                                    struct amdgpu_irq_src *irq_src,
 424                                    unsigned irq_type)
 425 {
 426         struct amdgpu_device *adev = ring->adev;
 427         uint64_t index;
 428
 429         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 430                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 431                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 432         } else {
 433                 /* put fence directly behind firmware */
 434                 index = ALIGN(adev->uvd.fw->size, 8);
 435                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 436                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 437         }
 438         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 439
 440         ring->fence_drv.irq_src = irq_src;
 441         ring->fence_drv.irq_type = irq_type;
 442         ring->fence_drv.initialized = true;
 443
 444         DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
 445                       ring->name, ring->fence_drv.gpu_addr);
 446         return 0;
 447 }
 448
 449 /**
 450  * amdgpu_fence_driver_init_ring - init the fence driver
 451  * for the requested ring.
 452  *
 453  * @ring: ring to init the fence driver on
 454  * @num_hw_submission: number of entries on the hardware queue
 455  * @sched_score: optional score atomic shared with other schedulers
 456  *
 457  * Init the fence driver for the requested ring (all asics).
 458  * Helper function for amdgpu_fence_driver_init().
 459  */
 460 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 461                                   unsigned num_hw_submission,
 462                                   atomic_t *sched_score)
 463 {
 464         struct amdgpu_device *adev = ring->adev;
 465         long timeout;
 466         int r;
 467
 468         if (!adev)
 469                 return -EINVAL;
 470
 471         if (!is_power_of_2(num_hw_submission))
 472                 return -EINVAL;
 473
 474         ring->fence_drv.cpu_addr = NULL;
 475         ring->fence_drv.gpu_addr = 0;
 476         ring->fence_drv.sync_seq = 0;
 477         atomic_set(&ring->fence_drv.last_seq, 0);
 478         ring->fence_drv.initialized = false;
 479
 480         timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
 481
 482         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 483         spin_lock_init(&ring->fence_drv.lock);
 484         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 485                                          GFP_KERNEL);
 486         if (!ring->fence_drv.fences)
 487                 return -ENOMEM;
 488
 489         /* No need to setup the GPU scheduler for rings that don't need it */
 490         if (ring->no_scheduler)
 491                 return 0;
 492
 493         switch (ring->funcs->type) {
 494         case AMDGPU_RING_TYPE_GFX:
 495                 timeout = adev->gfx_timeout;
 496                 break;
 497         case AMDGPU_RING_TYPE_COMPUTE:
 498                 timeout = adev->compute_timeout;
 499                 break;
 500         case AMDGPU_RING_TYPE_SDMA:
 501                 timeout = adev->sdma_timeout;
 502                 break;
 503         default:
 504                 timeout = adev->video_timeout;
 505                 break;
 506         }
 507
 508         r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
 509                            num_hw_submission, amdgpu_job_hang_limit,
 510                            timeout, NULL, sched_score, ring->name);
 511         if (r) {
 512                 DRM_ERROR("Failed to create scheduler on ring %s.\n",
 513                           ring->name);
 514                 return r;
 515         }
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * amdgpu_fence_driver_sw_init - init the fence driver
 522  * for all possible rings.
 523  *
 524  * @adev: amdgpu device pointer
 525  *
 526  * Init the fence driver for all possible rings (all asics).
 527  * Not all asics have all rings, so each asic will only
 528  * start the fence driver on the rings it has using
 529  * amdgpu_fence_driver_start_ring().
 530  * Returns 0 for success.
 531  */
 532 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
 533 {
 534         return 0;
 535 }
 536
 537 /**
 538  * amdgpu_fence_driver_hw_fini - tear down the fence driver
 539  * for all possible rings.
 540  *
 541  * @adev: amdgpu device pointer
 542  *
 543  * Tear down the fence driver for all possible rings (all asics).
 544  */
 545 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
 546 {
 547         int i, r;
 548
 549         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 550                 struct amdgpu_ring *ring = adev->rings[i];
 551
 552                 if (!ring || !ring->fence_drv.initialized)
 553                         continue;
 554
 555                 /* You can't wait for HW to signal if it's gone */
 556                 if (!drm_dev_is_unplugged(&adev->ddev))
 557                         r = amdgpu_fence_wait_empty(ring);
 558                 else
 559                         r = -ENODEV;
 560                 /* no need to trigger GPU reset as we are unloading */
 561                 if (r)
 562                         amdgpu_fence_driver_force_completion(ring);
 563
 564                 if (ring->fence_drv.irq_src)
 565                         amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 566                                        ring->fence_drv.irq_type);
 567
 568                 del_timer_sync(&ring->fence_drv.fallback_timer);
 569         }
 570 }
 571
 572 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
 573 {
 574         unsigned int i, j;
 575
 576         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 577                 struct amdgpu_ring *ring = adev->rings[i];
 578
 579                 if (!ring || !ring->fence_drv.initialized)
 580                         continue;
 581
 582                 if (!ring->no_scheduler)
 583                         drm_sched_fini(&ring->sched);
 584
 585                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 586                         dma_fence_put(ring->fence_drv.fences[j]);
 587                 kfree(ring->fence_drv.fences);
 588                 ring->fence_drv.fences = NULL;
 589                 ring->fence_drv.initialized = false;
 590         }
 591 }
 592
 593 /**
 594  * amdgpu_fence_driver_hw_init - enable the fence driver
 595  * for all possible rings.
 596  *
 597  * @adev: amdgpu device pointer
 598  *
 599  * Enable the fence driver for all possible rings (all asics).
 600  * Not all asics have all rings, so each asic will only
 601  * start the fence driver on the rings it has using
 602  * amdgpu_fence_driver_start_ring().
 603  * Returns 0 for success.
 604  */
 605 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
 606 {
 607         int i;
 608
 609         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 610                 struct amdgpu_ring *ring = adev->rings[i];
 611                 if (!ring || !ring->fence_drv.initialized)
 612                         continue;
 613
 614                 /* enable the interrupt */
 615                 if (ring->fence_drv.irq_src)
 616                         amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 617                                        ring->fence_drv.irq_type);
 618         }
 619 }
 620
 621 /**
 622  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 623  *
 624  * @ring: fence of the ring to signal
 625  *
 626  */
 627 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 628 {
 629         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 630         amdgpu_fence_process(ring);
 631 }
 632
 633 /*
 634  * Common fence implementation
 635  */
 636
 637 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 638 {
 639         return "amdgpu";
 640 }
 641
 642 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 643 {
 644         struct amdgpu_ring *ring;
 645
 646         if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
 647                 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
 648
 649                 ring = to_amdgpu_ring(job->base.sched);
 650         } else {
 651                 ring = to_amdgpu_fence(f)->ring;
 652         }
 653         return (const char *)ring->name;
 654 }
 655
 656 /**
 657  * amdgpu_fence_enable_signaling - enable signalling on fence
 658  * @f: fence
 659  *
 660  * This function is called with fence_queue lock held, and adds a callback
 661  * to fence_queue that checks if this fence is signaled, and if so it
 662  * signals the fence and removes itself.
 663  */
 664 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 665 {
 666         struct amdgpu_ring *ring;
 667
 668         if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
 669                 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
 670
 671                 ring = to_amdgpu_ring(job->base.sched);
 672         } else {
 673                 ring = to_amdgpu_fence(f)->ring;
 674         }
 675
 676         if (!timer_pending(&ring->fence_drv.fallback_timer))
 677                 amdgpu_fence_schedule_fallback(ring);
 678
 679         DMA_FENCE_TRACE(f, "armed on ring %i!\n", ring->idx);
 680
 681         return true;
 682 }
 683
 684 /**
 685  * amdgpu_fence_free - free up the fence memory
 686  *
 687  * @rcu: RCU callback head
 688  *
 689  * Free up the fence memory after the RCU grace period.
 690  */
 691 static void amdgpu_fence_free(struct rcu_head *rcu)
 692 {
 693         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 694
 695         if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
 696         /* free job if fence has a parent job */
 697                 struct amdgpu_job *job;
 698
 699                 job = container_of(f, struct amdgpu_job, hw_fence);
 700                 kfree(job);
 701         } else {
 702         /* free fence_slab if it's separated fence*/
 703                 struct amdgpu_fence *fence;
 704
 705                 fence = to_amdgpu_fence(f);
 706                 kmem_cache_free(amdgpu_fence_slab, fence);
 707         }
 708 }
 709
 710 /**
 711  * amdgpu_fence_release - callback that fence can be freed
 712  *
 713  * @f: fence
 714  *
 715  * This function is called when the reference count becomes zero.
 716  * It just RCU schedules freeing up the fence.
 717  */
 718 static void amdgpu_fence_release(struct dma_fence *f)
 719 {
 720         call_rcu(&f->rcu, amdgpu_fence_free);
 721 }
 722
 723 static const struct dma_fence_ops amdgpu_fence_ops = {
 724         .get_driver_name = amdgpu_fence_get_driver_name,
 725         .get_timeline_name = amdgpu_fence_get_timeline_name,
 726         .enable_signaling = amdgpu_fence_enable_signaling,
 727         .release = amdgpu_fence_release,
 728 };
 729
 730
 731 /*
 732  * Fence debugfs
 733  */
 734 #if defined(CONFIG_DEBUG_FS)
 735 static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
 736 {
 737         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
 738         int i;
 739
 740         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 741                 struct amdgpu_ring *ring = adev->rings[i];
 742                 if (!ring || !ring->fence_drv.initialized)
 743                         continue;
 744
 745                 amdgpu_fence_process(ring);
 746
 747                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 748                 seq_printf(m, "Last signaled fence          0x%08x\n",
 749                            atomic_read(&ring->fence_drv.last_seq));
 750                 seq_printf(m, "Last emitted                 0x%08x\n",
 751                            ring->fence_drv.sync_seq);
 752
 753                 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
 754                     ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
 755                         seq_printf(m, "Last signaled trailing fence 0x%08x\n",
 756                                    le32_to_cpu(*ring->trail_fence_cpu_addr));
 757                         seq_printf(m, "Last emitted                 0x%08x\n",
 758                                    ring->trail_seq);
 759                 }
 760
 761                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 762                         continue;
 763
 764                 /* set in CP_VMID_PREEMPT and preemption occurred */
 765                 seq_printf(m, "Last preempted               0x%08x\n",
 766                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 767                 /* set in CP_VMID_RESET and reset occurred */
 768                 seq_printf(m, "Last reset                   0x%08x\n",
 769                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 770                 /* Both preemption and reset occurred */
 771                 seq_printf(m, "Last both                    0x%08x\n",
 772                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 773         }
 774         return 0;
 775 }
 776
 777 /*
 778  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 779  *
 780  * Manually trigger a gpu reset at the next fence wait.
 781  */
 782 static int gpu_recover_get(void *data, u64 *val)
 783 {
 784         struct amdgpu_device *adev = (struct amdgpu_device *)data;
 785         struct drm_device *dev = adev_to_drm(adev);
 786         int r;
 787
 788         r = pm_runtime_get_sync(dev->dev);
 789         if (r < 0) {
 790                 pm_runtime_put_autosuspend(dev->dev);
 791                 return 0;
 792         }
 793
 794         *val = amdgpu_device_gpu_recover(adev, NULL);
 795
 796         pm_runtime_mark_last_busy(dev->dev);
 797         pm_runtime_put_autosuspend(dev->dev);
 798
 799         return 0;
 800 }
 801
 802 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
 803 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
 804                          "%lld\n");
 805
 806 #endif
 807
 808 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 809 {
 810 #if defined(CONFIG_DEBUG_FS)
 811         struct drm_minor *minor = adev_to_drm(adev)->primary;
 812         struct dentry *root = minor->debugfs_root;
 813
 814         debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
 815                             &amdgpu_debugfs_fence_info_fops);
 816
 817         if (!amdgpu_sriov_vf(adev))
 818                 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
 819                                     &amdgpu_debugfs_gpu_recover_fops);
 820 #endif
 821 }
 822