drivers/dma/xilinx/xilinx_dma.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * DMA driver for Xilinx Video DMA Engine
   4  *
   5  * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
   6  *
   7  * Based on the Freescale DMA driver.
   8  *
   9  * Description:
  10  * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
  11  * core that provides high-bandwidth direct memory access between memory
  12  * and AXI4-Stream type video target peripherals. The core provides efficient
  13  * two dimensional DMA operations with independent asynchronous read (S2MM)
  14  * and write (MM2S) channel operation. It can be configured to have either
  15  * one channel or two channels. If configured as two channels, one is to
  16  * transmit to the video device (MM2S) and another is to receive from the
  17  * video device (S2MM). Initialization, status, interrupt and management
  18  * registers are accessed through an AXI4-Lite slave interface.
  19  *
  20  * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
  21  * provides high-bandwidth one dimensional direct memory access between memory
  22  * and AXI4-Stream target peripherals. It supports one receive and one
  23  * transmit channel, both of them optional at synthesis time.
  24  *
  25  * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
  26  * Access (DMA) between a memory-mapped source address and a memory-mapped
  27  * destination address.
  28  *
  29  * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft
  30  * Xilinx IP that provides high-bandwidth direct memory access between
  31  * memory and AXI4-Stream target peripherals. It provides scatter gather
  32  * (SG) interface with multiple channels independent configuration support.
  33  *
  34  */
  35
  36 #include <linux/bitops.h>
  37 #include <linux/dmapool.h>
  38 #include <linux/dma/xilinx_dma.h>
  39 #include <linux/init.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/io.h>
  42 #include <linux/iopoll.h>
  43 #include <linux/module.h>
  44 #include <linux/of_address.h>
  45 #include <linux/of_dma.h>
  46 #include <linux/of_platform.h>
  47 #include <linux/of_irq.h>
  48 #include <linux/slab.h>
  49 #include <linux/clk.h>
  50 #include <linux/io-64-nonatomic-lo-hi.h>
  51
  52 #include "../dmaengine.h"
  53
  54 /* Register/Descriptor Offsets */
  55 #define XILINX_DMA_MM2S_CTRL_OFFSET             0x0000
  56 #define XILINX_DMA_S2MM_CTRL_OFFSET             0x0030
  57 #define XILINX_VDMA_MM2S_DESC_OFFSET            0x0050
  58 #define XILINX_VDMA_S2MM_DESC_OFFSET            0x00a0
  59
  60 /* Control Registers */
  61 #define XILINX_DMA_REG_DMACR                    0x0000
  62 #define XILINX_DMA_DMACR_DELAY_MAX              0xff
  63 #define XILINX_DMA_DMACR_DELAY_SHIFT            24
  64 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX        0xff
  65 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT      16
  66 #define XILINX_DMA_DMACR_ERR_IRQ                BIT(14)
  67 #define XILINX_DMA_DMACR_DLY_CNT_IRQ            BIT(13)
  68 #define XILINX_DMA_DMACR_FRM_CNT_IRQ            BIT(12)
  69 #define XILINX_DMA_DMACR_MASTER_SHIFT           8
  70 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
  71 #define XILINX_DMA_DMACR_FRAMECNT_EN            BIT(4)
  72 #define XILINX_DMA_DMACR_GENLOCK_EN             BIT(3)
  73 #define XILINX_DMA_DMACR_RESET                  BIT(2)
  74 #define XILINX_DMA_DMACR_CIRC_EN                BIT(1)
  75 #define XILINX_DMA_DMACR_RUNSTOP                BIT(0)
  76 #define XILINX_DMA_DMACR_FSYNCSRC_MASK          GENMASK(6, 5)
  77 #define XILINX_DMA_DMACR_DELAY_MASK             GENMASK(31, 24)
  78 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK       GENMASK(23, 16)
  79 #define XILINX_DMA_DMACR_MASTER_MASK            GENMASK(11, 8)
  80
  81 #define XILINX_DMA_REG_DMASR                    0x0004
  82 #define XILINX_DMA_DMASR_EOL_LATE_ERR           BIT(15)
  83 #define XILINX_DMA_DMASR_ERR_IRQ                BIT(14)
  84 #define XILINX_DMA_DMASR_DLY_CNT_IRQ            BIT(13)
  85 #define XILINX_DMA_DMASR_FRM_CNT_IRQ            BIT(12)
  86 #define XILINX_DMA_DMASR_SOF_LATE_ERR           BIT(11)
  87 #define XILINX_DMA_DMASR_SG_DEC_ERR             BIT(10)
  88 #define XILINX_DMA_DMASR_SG_SLV_ERR             BIT(9)
  89 #define XILINX_DMA_DMASR_EOF_EARLY_ERR          BIT(8)
  90 #define XILINX_DMA_DMASR_SOF_EARLY_ERR          BIT(7)
  91 #define XILINX_DMA_DMASR_DMA_DEC_ERR            BIT(6)
  92 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR          BIT(5)
  93 #define XILINX_DMA_DMASR_DMA_INT_ERR            BIT(4)
  94 #define XILINX_DMA_DMASR_SG_MASK                BIT(3)
  95 #define XILINX_DMA_DMASR_IDLE                   BIT(1)
  96 #define XILINX_DMA_DMASR_HALTED         BIT(0)
  97 #define XILINX_DMA_DMASR_DELAY_MASK             GENMASK(31, 24)
  98 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK       GENMASK(23, 16)
  99
 100 #define XILINX_DMA_REG_CURDESC                  0x0008
 101 #define XILINX_DMA_REG_TAILDESC         0x0010
 102 #define XILINX_DMA_REG_REG_INDEX                0x0014
 103 #define XILINX_DMA_REG_FRMSTORE         0x0018
 104 #define XILINX_DMA_REG_THRESHOLD                0x001c
 105 #define XILINX_DMA_REG_FRMPTR_STS               0x0024
 106 #define XILINX_DMA_REG_PARK_PTR         0x0028
 107 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT        8
 108 #define XILINX_DMA_PARK_PTR_WR_REF_MASK         GENMASK(12, 8)
 109 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT        0
 110 #define XILINX_DMA_PARK_PTR_RD_REF_MASK         GENMASK(4, 0)
 111 #define XILINX_DMA_REG_VDMA_VERSION             0x002c
 112
 113 /* Register Direct Mode Registers */
 114 #define XILINX_DMA_REG_VSIZE                    0x0000
 115 #define XILINX_DMA_REG_HSIZE                    0x0004
 116
 117 #define XILINX_DMA_REG_FRMDLY_STRIDE            0x0008
 118 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT   24
 119 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT   0
 120
 121 #define XILINX_VDMA_REG_START_ADDRESS(n)        (0x000c + 4 * (n))
 122 #define XILINX_VDMA_REG_START_ADDRESS_64(n)     (0x000c + 8 * (n))
 123
 124 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP    0x00ec
 125 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP        BIT(0)
 126
 127 /* HW specific definitions */
 128 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE       0x20
 129 #define XILINX_DMA_MAX_CHANS_PER_DEVICE         0x2
 130 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE        0x1
 131
 132 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK   \
 133                 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
 134                  XILINX_DMA_DMASR_DLY_CNT_IRQ | \
 135                  XILINX_DMA_DMASR_ERR_IRQ)
 136
 137 #define XILINX_DMA_DMASR_ALL_ERR_MASK   \
 138                 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
 139                  XILINX_DMA_DMASR_SOF_LATE_ERR | \
 140                  XILINX_DMA_DMASR_SG_DEC_ERR | \
 141                  XILINX_DMA_DMASR_SG_SLV_ERR | \
 142                  XILINX_DMA_DMASR_EOF_EARLY_ERR | \
 143                  XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 144                  XILINX_DMA_DMASR_DMA_DEC_ERR | \
 145                  XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
 146                  XILINX_DMA_DMASR_DMA_INT_ERR)
 147
 148 /*
 149  * Recoverable errors are DMA Internal error, SOF Early, EOF Early
 150  * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
 151  * is enabled in the h/w system.
 152  */
 153 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK       \
 154                 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
 155                  XILINX_DMA_DMASR_EOF_EARLY_ERR | \
 156                  XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 157                  XILINX_DMA_DMASR_DMA_INT_ERR)
 158
 159 /* Axi VDMA Flush on Fsync bits */
 160 #define XILINX_DMA_FLUSH_S2MM           3
 161 #define XILINX_DMA_FLUSH_MM2S           2
 162 #define XILINX_DMA_FLUSH_BOTH           1
 163
 164 /* Delay loop counter to prevent hardware failure */
 165 #define XILINX_DMA_LOOP_COUNT           1000000
 166
 167 /* AXI DMA Specific Registers/Offsets */
 168 #define XILINX_DMA_REG_SRCDSTADDR       0x18
 169 #define XILINX_DMA_REG_BTT              0x28
 170
 171 /* AXI DMA Specific Masks/Bit fields */
 172 #define XILINX_DMA_MAX_TRANS_LEN_MIN    8
 173 #define XILINX_DMA_MAX_TRANS_LEN_MAX    23
 174 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
 175 #define XILINX_DMA_CR_COALESCE_MAX      GENMASK(23, 16)
 176 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
 177 #define XILINX_DMA_CR_COALESCE_SHIFT    16
 178 #define XILINX_DMA_BD_SOP               BIT(27)
 179 #define XILINX_DMA_BD_EOP               BIT(26)
 180 #define XILINX_DMA_COALESCE_MAX         255
 181 #define XILINX_DMA_NUM_DESCS            255
 182 #define XILINX_DMA_NUM_APP_WORDS        5
 183
 184 /* AXI CDMA Specific Registers/Offsets */
 185 #define XILINX_CDMA_REG_SRCADDR         0x18
 186 #define XILINX_CDMA_REG_DSTADDR         0x20
 187
 188 /* AXI CDMA Specific Masks */
 189 #define XILINX_CDMA_CR_SGMODE          BIT(3)
 190
 191 #define xilinx_prep_dma_addr_t(addr)    \
 192         ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
 193
 194 /* AXI MCDMA Specific Registers/Offsets */
 195 #define XILINX_MCDMA_MM2S_CTRL_OFFSET           0x0000
 196 #define XILINX_MCDMA_S2MM_CTRL_OFFSET           0x0500
 197 #define XILINX_MCDMA_CHEN_OFFSET                0x0008
 198 #define XILINX_MCDMA_CH_ERR_OFFSET              0x0010
 199 #define XILINX_MCDMA_RXINT_SER_OFFSET           0x0020
 200 #define XILINX_MCDMA_TXINT_SER_OFFSET           0x0028
 201 #define XILINX_MCDMA_CHAN_CR_OFFSET(x)          (0x40 + (x) * 0x40)
 202 #define XILINX_MCDMA_CHAN_SR_OFFSET(x)          (0x44 + (x) * 0x40)
 203 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x)       (0x48 + (x) * 0x40)
 204 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x)       (0x50 + (x) * 0x40)
 205
 206 /* AXI MCDMA Specific Masks/Shifts */
 207 #define XILINX_MCDMA_COALESCE_SHIFT             16
 208 #define XILINX_MCDMA_COALESCE_MAX               24
 209 #define XILINX_MCDMA_IRQ_ALL_MASK               GENMASK(7, 5)
 210 #define XILINX_MCDMA_COALESCE_MASK              GENMASK(23, 16)
 211 #define XILINX_MCDMA_CR_RUNSTOP_MASK            BIT(0)
 212 #define XILINX_MCDMA_IRQ_IOC_MASK               BIT(5)
 213 #define XILINX_MCDMA_IRQ_DELAY_MASK             BIT(6)
 214 #define XILINX_MCDMA_IRQ_ERR_MASK               BIT(7)
 215 #define XILINX_MCDMA_BD_EOP                     BIT(30)
 216 #define XILINX_MCDMA_BD_SOP                     BIT(31)
 217
 218 /**
 219  * struct xilinx_vdma_desc_hw - Hardware Descriptor
 220  * @next_desc: Next Descriptor Pointer @0x00
 221  * @pad1: Reserved @0x04
 222  * @buf_addr: Buffer address @0x08
 223  * @buf_addr_msb: MSB of Buffer address @0x0C
 224  * @vsize: Vertical Size @0x10
 225  * @hsize: Horizontal Size @0x14
 226  * @stride: Number of bytes between the first
 227  *          pixels of each horizontal line @0x18
 228  */
 229 struct xilinx_vdma_desc_hw {
 230         u32 next_desc;
 231         u32 pad1;
 232         u32 buf_addr;
 233         u32 buf_addr_msb;
 234         u32 vsize;
 235         u32 hsize;
 236         u32 stride;
 237 } __aligned(64);
 238
 239 /**
 240  * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
 241  * @next_desc: Next Descriptor Pointer @0x00
 242  * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
 243  * @buf_addr: Buffer address @0x08
 244  * @buf_addr_msb: MSB of Buffer address @0x0C
 245  * @reserved1: Reserved @0x10
 246  * @reserved2: Reserved @0x14
 247  * @control: Control field @0x18
 248  * @status: Status field @0x1C
 249  * @app: APP Fields @0x20 - 0x30
 250  */
 251 struct xilinx_axidma_desc_hw {
 252         u32 next_desc;
 253         u32 next_desc_msb;
 254         u32 buf_addr;
 255         u32 buf_addr_msb;
 256         u32 reserved1;
 257         u32 reserved2;
 258         u32 control;
 259         u32 status;
 260         u32 app[XILINX_DMA_NUM_APP_WORDS];
 261 } __aligned(64);
 262
 263 /**
 264  * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
 265  * @next_desc: Next Descriptor Pointer @0x00
 266  * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
 267  * @buf_addr: Buffer address @0x08
 268  * @buf_addr_msb: MSB of Buffer address @0x0C
 269  * @rsvd: Reserved field @0x10
 270  * @control: Control Information field @0x14
 271  * @status: Status field @0x18
 272  * @sideband_status: Status of sideband signals @0x1C
 273  * @app: APP Fields @0x20 - 0x30
 274  */
 275 struct xilinx_aximcdma_desc_hw {
 276         u32 next_desc;
 277         u32 next_desc_msb;
 278         u32 buf_addr;
 279         u32 buf_addr_msb;
 280         u32 rsvd;
 281         u32 control;
 282         u32 status;
 283         u32 sideband_status;
 284         u32 app[XILINX_DMA_NUM_APP_WORDS];
 285 } __aligned(64);
 286
 287 /**
 288  * struct xilinx_cdma_desc_hw - Hardware Descriptor
 289  * @next_desc: Next Descriptor Pointer @0x00
 290  * @next_desc_msb: Next Descriptor Pointer MSB @0x04
 291  * @src_addr: Source address @0x08
 292  * @src_addr_msb: Source address MSB @0x0C
 293  * @dest_addr: Destination address @0x10
 294  * @dest_addr_msb: Destination address MSB @0x14
 295  * @control: Control field @0x18
 296  * @status: Status field @0x1C
 297  */
 298 struct xilinx_cdma_desc_hw {
 299         u32 next_desc;
 300         u32 next_desc_msb;
 301         u32 src_addr;
 302         u32 src_addr_msb;
 303         u32 dest_addr;
 304         u32 dest_addr_msb;
 305         u32 control;
 306         u32 status;
 307 } __aligned(64);
 308
 309 /**
 310  * struct xilinx_vdma_tx_segment - Descriptor segment
 311  * @hw: Hardware descriptor
 312  * @node: Node in the descriptor segments list
 313  * @phys: Physical address of segment
 314  */
 315 struct xilinx_vdma_tx_segment {
 316         struct xilinx_vdma_desc_hw hw;
 317         struct list_head node;
 318         dma_addr_t phys;
 319 } __aligned(64);
 320
 321 /**
 322  * struct xilinx_axidma_tx_segment - Descriptor segment
 323  * @hw: Hardware descriptor
 324  * @node: Node in the descriptor segments list
 325  * @phys: Physical address of segment
 326  */
 327 struct xilinx_axidma_tx_segment {
 328         struct xilinx_axidma_desc_hw hw;
 329         struct list_head node;
 330         dma_addr_t phys;
 331 } __aligned(64);
 332
 333 /**
 334  * struct xilinx_aximcdma_tx_segment - Descriptor segment
 335  * @hw: Hardware descriptor
 336  * @node: Node in the descriptor segments list
 337  * @phys: Physical address of segment
 338  */
 339 struct xilinx_aximcdma_tx_segment {
 340         struct xilinx_aximcdma_desc_hw hw;
 341         struct list_head node;
 342         dma_addr_t phys;
 343 } __aligned(64);
 344
 345 /**
 346  * struct xilinx_cdma_tx_segment - Descriptor segment
 347  * @hw: Hardware descriptor
 348  * @node: Node in the descriptor segments list
 349  * @phys: Physical address of segment
 350  */
 351 struct xilinx_cdma_tx_segment {
 352         struct xilinx_cdma_desc_hw hw;
 353         struct list_head node;
 354         dma_addr_t phys;
 355 } __aligned(64);
 356
 357 /**
 358  * struct xilinx_dma_tx_descriptor - Per Transaction structure
 359  * @async_tx: Async transaction descriptor
 360  * @segments: TX segments list
 361  * @node: Node in the channel descriptors list
 362  * @cyclic: Check for cyclic transfers.
 363  * @err: Whether the descriptor has an error.
 364  * @residue: Residue of the completed descriptor
 365  */
 366 struct xilinx_dma_tx_descriptor {
 367         struct dma_async_tx_descriptor async_tx;
 368         struct list_head segments;
 369         struct list_head node;
 370         bool cyclic;
 371         bool err;
 372         u32 residue;
 373 };
 374
 375 /**
 376  * struct xilinx_dma_chan - Driver specific DMA channel structure
 377  * @xdev: Driver specific device structure
 378  * @ctrl_offset: Control registers offset
 379  * @desc_offset: TX descriptor registers offset
 380  * @lock: Descriptor operation lock
 381  * @pending_list: Descriptors waiting
 382  * @active_list: Descriptors ready to submit
 383  * @done_list: Complete descriptors
 384  * @free_seg_list: Free descriptors
 385  * @common: DMA common channel
 386  * @desc_pool: Descriptors pool
 387  * @dev: The dma device
 388  * @irq: Channel IRQ
 389  * @id: Channel ID
 390  * @direction: Transfer direction
 391  * @num_frms: Number of frames
 392  * @has_sg: Support scatter transfers
 393  * @cyclic: Check for cyclic transfers.
 394  * @genlock: Support genlock mode
 395  * @err: Channel has errors
 396  * @idle: Check for channel idle
 397  * @terminating: Check for channel being synchronized by user
 398  * @tasklet: Cleanup work after irq
 399  * @config: Device configuration info
 400  * @flush_on_fsync: Flush on Frame sync
 401  * @desc_pendingcount: Descriptor pending count
 402  * @ext_addr: Indicates 64 bit addressing is supported by dma channel
 403  * @desc_submitcount: Descriptor h/w submitted count
 404  * @seg_v: Statically allocated segments base
 405  * @seg_mv: Statically allocated segments base for MCDMA
 406  * @seg_p: Physical allocated segments base
 407  * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
 408  * @cyclic_seg_p: Physical allocated segments base for cyclic dma
 409  * @start_transfer: Differentiate b/w DMA IP's transfer
 410  * @stop_transfer: Differentiate b/w DMA IP's quiesce
 411  * @tdest: TDEST value for mcdma
 412  * @has_vflip: S2MM vertical flip
 413  */
 414 struct xilinx_dma_chan {
 415         struct xilinx_dma_device *xdev;
 416         u32 ctrl_offset;
 417         u32 desc_offset;
 418         spinlock_t lock;
 419         struct list_head pending_list;
 420         struct list_head active_list;
 421         struct list_head done_list;
 422         struct list_head free_seg_list;
 423         struct dma_chan common;
 424         struct dma_pool *desc_pool;
 425         struct device *dev;
 426         int irq;
 427         int id;
 428         enum dma_transfer_direction direction;
 429         int num_frms;
 430         bool has_sg;
 431         bool cyclic;
 432         bool genlock;
 433         bool err;
 434         bool idle;
 435         bool terminating;
 436         struct tasklet_struct tasklet;
 437         struct xilinx_vdma_config config;
 438         bool flush_on_fsync;
 439         u32 desc_pendingcount;
 440         bool ext_addr;
 441         u32 desc_submitcount;
 442         struct xilinx_axidma_tx_segment *seg_v;
 443         struct xilinx_aximcdma_tx_segment *seg_mv;
 444         dma_addr_t seg_p;
 445         struct xilinx_axidma_tx_segment *cyclic_seg_v;
 446         dma_addr_t cyclic_seg_p;
 447         void (*start_transfer)(struct xilinx_dma_chan *chan);
 448         int (*stop_transfer)(struct xilinx_dma_chan *chan);
 449         u16 tdest;
 450         bool has_vflip;
 451 };
 452
 453 /**
 454  * enum xdma_ip_type - DMA IP type.
 455  *
 456  * @XDMA_TYPE_AXIDMA: Axi dma ip.
 457  * @XDMA_TYPE_CDMA: Axi cdma ip.
 458  * @XDMA_TYPE_VDMA: Axi vdma ip.
 459  * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip.
 460  *
 461  */
 462 enum xdma_ip_type {
 463         XDMA_TYPE_AXIDMA = 0,
 464         XDMA_TYPE_CDMA,
 465         XDMA_TYPE_VDMA,
 466         XDMA_TYPE_AXIMCDMA
 467 };
 468
 469 struct xilinx_dma_config {
 470         enum xdma_ip_type dmatype;
 471         int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
 472                         struct clk **tx_clk, struct clk **txs_clk,
 473                         struct clk **rx_clk, struct clk **rxs_clk);
 474         irqreturn_t (*irq_handler)(int irq, void *data);
 475         const int max_channels;
 476 };
 477
 478 /**
 479  * struct xilinx_dma_device - DMA device structure
 480  * @regs: I/O mapped base address
 481  * @dev: Device Structure
 482  * @common: DMA device structure
 483  * @chan: Driver specific DMA channel
 484  * @flush_on_fsync: Flush on frame sync
 485  * @ext_addr: Indicates 64 bit addressing is supported by dma device
 486  * @pdev: Platform device structure pointer
 487  * @dma_config: DMA config structure
 488  * @axi_clk: DMA Axi4-lite interace clock
 489  * @tx_clk: DMA mm2s clock
 490  * @txs_clk: DMA mm2s stream clock
 491  * @rx_clk: DMA s2mm clock
 492  * @rxs_clk: DMA s2mm stream clock
 493  * @s2mm_chan_id: DMA s2mm channel identifier
 494  * @mm2s_chan_id: DMA mm2s channel identifier
 495  * @max_buffer_len: Max buffer length
 496  */
 497 struct xilinx_dma_device {
 498         void __iomem *regs;
 499         struct device *dev;
 500         struct dma_device common;
 501         struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
 502         u32 flush_on_fsync;
 503         bool ext_addr;
 504         struct platform_device  *pdev;
 505         const struct xilinx_dma_config *dma_config;
 506         struct clk *axi_clk;
 507         struct clk *tx_clk;
 508         struct clk *txs_clk;
 509         struct clk *rx_clk;
 510         struct clk *rxs_clk;
 511         u32 s2mm_chan_id;
 512         u32 mm2s_chan_id;
 513         u32 max_buffer_len;
 514 };
 515
 516 /* Macros */
 517 #define to_xilinx_chan(chan) \
 518         container_of(chan, struct xilinx_dma_chan, common)
 519 #define to_dma_tx_descriptor(tx) \
 520         container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
 521 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
 522         readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
 523                                   val, cond, delay_us, timeout_us)
 524
 525 /* IO accessors */
 526 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
 527 {
 528         return ioread32(chan->xdev->regs + reg);
 529 }
 530
 531 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
 532 {
 533         iowrite32(value, chan->xdev->regs + reg);
 534 }
 535
 536 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
 537                                    u32 value)
 538 {
 539         dma_write(chan, chan->desc_offset + reg, value);
 540 }
 541
 542 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
 543 {
 544         return dma_read(chan, chan->ctrl_offset + reg);
 545 }
 546
 547 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
 548                                    u32 value)
 549 {
 550         dma_write(chan, chan->ctrl_offset + reg, value);
 551 }
 552
 553 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
 554                                  u32 clr)
 555 {
 556         dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
 557 }
 558
 559 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
 560                                  u32 set)
 561 {
 562         dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
 563 }
 564
 565 /**
 566  * vdma_desc_write_64 - 64-bit descriptor write
 567  * @chan: Driver specific VDMA channel
 568  * @reg: Register to write
 569  * @value_lsb: lower address of the descriptor.
 570  * @value_msb: upper address of the descriptor.
 571  *
 572  * Since vdma driver is trying to write to a register offset which is not a
 573  * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
 574  * instead of a single 64 bit register write.
 575  */
 576 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
 577                                       u32 value_lsb, u32 value_msb)
 578 {
 579         /* Write the lsb 32 bits*/
 580         writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
 581
 582         /* Write the msb 32 bits */
 583         writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
 584 }
 585
 586 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
 587 {
 588         lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
 589 }
 590
 591 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
 592                                 dma_addr_t addr)
 593 {
 594         if (chan->ext_addr)
 595                 dma_writeq(chan, reg, addr);
 596         else
 597                 dma_ctrl_write(chan, reg, addr);
 598 }
 599
 600 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
 601                                      struct xilinx_axidma_desc_hw *hw,
 602                                      dma_addr_t buf_addr, size_t sg_used,
 603                                      size_t period_len)
 604 {
 605         if (chan->ext_addr) {
 606                 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
 607                 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
 608                                                  period_len);
 609         } else {
 610                 hw->buf_addr = buf_addr + sg_used + period_len;
 611         }
 612 }
 613
 614 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
 615                                        struct xilinx_aximcdma_desc_hw *hw,
 616                                        dma_addr_t buf_addr, size_t sg_used)
 617 {
 618         if (chan->ext_addr) {
 619                 hw->buf_addr = lower_32_bits(buf_addr + sg_used);
 620                 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used);
 621         } else {
 622                 hw->buf_addr = buf_addr + sg_used;
 623         }
 624 }
 625
 626 /* -----------------------------------------------------------------------------
 627  * Descriptors and segments alloc and free
 628  */
 629
 630 /**
 631  * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
 632  * @chan: Driver specific DMA channel
 633  *
 634  * Return: The allocated segment on success and NULL on failure.
 635  */
 636 static struct xilinx_vdma_tx_segment *
 637 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 638 {
 639         struct xilinx_vdma_tx_segment *segment;
 640         dma_addr_t phys;
 641
 642         segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
 643         if (!segment)
 644                 return NULL;
 645
 646         segment->phys = phys;
 647
 648         return segment;
 649 }
 650
 651 /**
 652  * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
 653  * @chan: Driver specific DMA channel
 654  *
 655  * Return: The allocated segment on success and NULL on failure.
 656  */
 657 static struct xilinx_cdma_tx_segment *
 658 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 659 {
 660         struct xilinx_cdma_tx_segment *segment;
 661         dma_addr_t phys;
 662
 663         segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
 664         if (!segment)
 665                 return NULL;
 666
 667         segment->phys = phys;
 668
 669         return segment;
 670 }
 671
 672 /**
 673  * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
 674  * @chan: Driver specific DMA channel
 675  *
 676  * Return: The allocated segment on success and NULL on failure.
 677  */
 678 static struct xilinx_axidma_tx_segment *
 679 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 680 {
 681         struct xilinx_axidma_tx_segment *segment = NULL;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&chan->lock, flags);
 685         if (!list_empty(&chan->free_seg_list)) {
 686                 segment = list_first_entry(&chan->free_seg_list,
 687                                            struct xilinx_axidma_tx_segment,
 688                                            node);
 689                 list_del(&segment->node);
 690         }
 691         spin_unlock_irqrestore(&chan->lock, flags);
 692
 693         if (!segment)
 694                 dev_dbg(chan->dev, "Could not find free tx segment\n");
 695
 696         return segment;
 697 }
 698
 699 /**
 700  * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
 701  * @chan: Driver specific DMA channel
 702  *
 703  * Return: The allocated segment on success and NULL on failure.
 704  */
 705 static struct xilinx_aximcdma_tx_segment *
 706 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 707 {
 708         struct xilinx_aximcdma_tx_segment *segment = NULL;
 709         unsigned long flags;
 710
 711         spin_lock_irqsave(&chan->lock, flags);
 712         if (!list_empty(&chan->free_seg_list)) {
 713                 segment = list_first_entry(&chan->free_seg_list,
 714                                            struct xilinx_aximcdma_tx_segment,
 715                                            node);
 716                 list_del(&segment->node);
 717         }
 718         spin_unlock_irqrestore(&chan->lock, flags);
 719
 720         return segment;
 721 }
 722
 723 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
 724 {
 725         u32 next_desc = hw->next_desc;
 726         u32 next_desc_msb = hw->next_desc_msb;
 727
 728         memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
 729
 730         hw->next_desc = next_desc;
 731         hw->next_desc_msb = next_desc_msb;
 732 }
 733
 734 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
 735 {
 736         u32 next_desc = hw->next_desc;
 737         u32 next_desc_msb = hw->next_desc_msb;
 738
 739         memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw));
 740
 741         hw->next_desc = next_desc;
 742         hw->next_desc_msb = next_desc_msb;
 743 }
 744
 745 /**
 746  * xilinx_dma_free_tx_segment - Free transaction segment
 747  * @chan: Driver specific DMA channel
 748  * @segment: DMA transaction segment
 749  */
 750 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
 751                                 struct xilinx_axidma_tx_segment *segment)
 752 {
 753         xilinx_dma_clean_hw_desc(&segment->hw);
 754
 755         list_add_tail(&segment->node, &chan->free_seg_list);
 756 }
 757
 758 /**
 759  * xilinx_mcdma_free_tx_segment - Free transaction segment
 760  * @chan: Driver specific DMA channel
 761  * @segment: DMA transaction segment
 762  */
 763 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan,
 764                                          struct xilinx_aximcdma_tx_segment *
 765                                          segment)
 766 {
 767         xilinx_mcdma_clean_hw_desc(&segment->hw);
 768
 769         list_add_tail(&segment->node, &chan->free_seg_list);
 770 }
 771
 772 /**
 773  * xilinx_cdma_free_tx_segment - Free transaction segment
 774  * @chan: Driver specific DMA channel
 775  * @segment: DMA transaction segment
 776  */
 777 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
 778                                 struct xilinx_cdma_tx_segment *segment)
 779 {
 780         dma_pool_free(chan->desc_pool, segment, segment->phys);
 781 }
 782
 783 /**
 784  * xilinx_vdma_free_tx_segment - Free transaction segment
 785  * @chan: Driver specific DMA channel
 786  * @segment: DMA transaction segment
 787  */
 788 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
 789                                         struct xilinx_vdma_tx_segment *segment)
 790 {
 791         dma_pool_free(chan->desc_pool, segment, segment->phys);
 792 }
 793
 794 /**
 795  * xilinx_dma_tx_descriptor - Allocate transaction descriptor
 796  * @chan: Driver specific DMA channel
 797  *
 798  * Return: The allocated descriptor on success and NULL on failure.
 799  */
 800 static struct xilinx_dma_tx_descriptor *
 801 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
 802 {
 803         struct xilinx_dma_tx_descriptor *desc;
 804
 805         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 806         if (!desc)
 807                 return NULL;
 808
 809         INIT_LIST_HEAD(&desc->segments);
 810
 811         return desc;
 812 }
 813
 814 /**
 815  * xilinx_dma_free_tx_descriptor - Free transaction descriptor
 816  * @chan: Driver specific DMA channel
 817  * @desc: DMA transaction descriptor
 818  */
 819 static void
 820 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
 821                                struct xilinx_dma_tx_descriptor *desc)
 822 {
 823         struct xilinx_vdma_tx_segment *segment, *next;
 824         struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
 825         struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
 826         struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next;
 827
 828         if (!desc)
 829                 return;
 830
 831         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
 832                 list_for_each_entry_safe(segment, next, &desc->segments, node) {
 833                         list_del(&segment->node);
 834                         xilinx_vdma_free_tx_segment(chan, segment);
 835                 }
 836         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
 837                 list_for_each_entry_safe(cdma_segment, cdma_next,
 838                                          &desc->segments, node) {
 839                         list_del(&cdma_segment->node);
 840                         xilinx_cdma_free_tx_segment(chan, cdma_segment);
 841                 }
 842         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 843                 list_for_each_entry_safe(axidma_segment, axidma_next,
 844                                          &desc->segments, node) {
 845                         list_del(&axidma_segment->node);
 846                         xilinx_dma_free_tx_segment(chan, axidma_segment);
 847                 }
 848         } else {
 849                 list_for_each_entry_safe(aximcdma_segment, aximcdma_next,
 850                                          &desc->segments, node) {
 851                         list_del(&aximcdma_segment->node);
 852                         xilinx_mcdma_free_tx_segment(chan, aximcdma_segment);
 853                 }
 854         }
 855
 856         kfree(desc);
 857 }
 858
 859 /* Required functions */
 860
 861 /**
 862  * xilinx_dma_free_desc_list - Free descriptors list
 863  * @chan: Driver specific DMA channel
 864  * @list: List to parse and delete the descriptor
 865  */
 866 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
 867                                         struct list_head *list)
 868 {
 869         struct xilinx_dma_tx_descriptor *desc, *next;
 870
 871         list_for_each_entry_safe(desc, next, list, node) {
 872                 list_del(&desc->node);
 873                 xilinx_dma_free_tx_descriptor(chan, desc);
 874         }
 875 }
 876
 877 /**
 878  * xilinx_dma_free_descriptors - Free channel descriptors
 879  * @chan: Driver specific DMA channel
 880  */
 881 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
 882 {
 883         unsigned long flags;
 884
 885         spin_lock_irqsave(&chan->lock, flags);
 886
 887         xilinx_dma_free_desc_list(chan, &chan->pending_list);
 888         xilinx_dma_free_desc_list(chan, &chan->done_list);
 889         xilinx_dma_free_desc_list(chan, &chan->active_list);
 890
 891         spin_unlock_irqrestore(&chan->lock, flags);
 892 }
 893
 894 /**
 895  * xilinx_dma_free_chan_resources - Free channel resources
 896  * @dchan: DMA channel
 897  */
 898 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
 899 {
 900         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
 901         unsigned long flags;
 902
 903         dev_dbg(chan->dev, "Free all channel resources.\n");
 904
 905         xilinx_dma_free_descriptors(chan);
 906
 907         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 908                 spin_lock_irqsave(&chan->lock, flags);
 909                 INIT_LIST_HEAD(&chan->free_seg_list);
 910                 spin_unlock_irqrestore(&chan->lock, flags);
 911
 912                 /* Free memory that is allocated for BD */
 913                 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
 914                                   XILINX_DMA_NUM_DESCS, chan->seg_v,
 915                                   chan->seg_p);
 916
 917                 /* Free Memory that is allocated for cyclic DMA Mode */
 918                 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
 919                                   chan->cyclic_seg_v, chan->cyclic_seg_p);
 920         }
 921
 922         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
 923                 spin_lock_irqsave(&chan->lock, flags);
 924                 INIT_LIST_HEAD(&chan->free_seg_list);
 925                 spin_unlock_irqrestore(&chan->lock, flags);
 926
 927                 /* Free memory that is allocated for BD */
 928                 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) *
 929                                   XILINX_DMA_NUM_DESCS, chan->seg_mv,
 930                                   chan->seg_p);
 931         }
 932
 933         if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA &&
 934             chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) {
 935                 dma_pool_destroy(chan->desc_pool);
 936                 chan->desc_pool = NULL;
 937         }
 938
 939 }
 940
 941 /**
 942  * xilinx_dma_get_residue - Compute residue for a given descriptor
 943  * @chan: Driver specific dma channel
 944  * @desc: dma transaction descriptor
 945  *
 946  * Return: The number of residue bytes for the descriptor.
 947  */
 948 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
 949                                   struct xilinx_dma_tx_descriptor *desc)
 950 {
 951         struct xilinx_cdma_tx_segment *cdma_seg;
 952         struct xilinx_axidma_tx_segment *axidma_seg;
 953         struct xilinx_aximcdma_tx_segment *aximcdma_seg;
 954         struct xilinx_cdma_desc_hw *cdma_hw;
 955         struct xilinx_axidma_desc_hw *axidma_hw;
 956         struct xilinx_aximcdma_desc_hw *aximcdma_hw;
 957         struct list_head *entry;
 958         u32 residue = 0;
 959
 960         list_for_each(entry, &desc->segments) {
 961                 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
 962                         cdma_seg = list_entry(entry,
 963                                               struct xilinx_cdma_tx_segment,
 964                                               node);
 965                         cdma_hw = &cdma_seg->hw;
 966                         residue += (cdma_hw->control - cdma_hw->status) &
 967                                    chan->xdev->max_buffer_len;
 968                 } else if (chan->xdev->dma_config->dmatype ==
 969                            XDMA_TYPE_AXIDMA) {
 970                         axidma_seg = list_entry(entry,
 971                                                 struct xilinx_axidma_tx_segment,
 972                                                 node);
 973                         axidma_hw = &axidma_seg->hw;
 974                         residue += (axidma_hw->control - axidma_hw->status) &
 975                                    chan->xdev->max_buffer_len;
 976                 } else {
 977                         aximcdma_seg =
 978                                 list_entry(entry,
 979                                            struct xilinx_aximcdma_tx_segment,
 980                                            node);
 981                         aximcdma_hw = &aximcdma_seg->hw;
 982                         residue +=
 983                                 (aximcdma_hw->control - aximcdma_hw->status) &
 984                                 chan->xdev->max_buffer_len;
 985                 }
 986         }
 987
 988         return residue;
 989 }
 990
 991 /**
 992  * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
 993  * @chan: Driver specific dma channel
 994  * @desc: dma transaction descriptor
 995  * @flags: flags for spin lock
 996  */
 997 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
 998                                           struct xilinx_dma_tx_descriptor *desc,
 999                                           unsigned long *flags)
1000 {
1001         dma_async_tx_callback callback;
1002         void *callback_param;
1003
1004         callback = desc->async_tx.callback;
1005         callback_param = desc->async_tx.callback_param;
1006         if (callback) {
1007                 spin_unlock_irqrestore(&chan->lock, *flags);
1008                 callback(callback_param);
1009                 spin_lock_irqsave(&chan->lock, *flags);
1010         }
1011 }
1012
1013 /**
1014  * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1015  * @chan: Driver specific DMA channel
1016  */
1017 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
1018 {
1019         struct xilinx_dma_tx_descriptor *desc, *next;
1020         unsigned long flags;
1021
1022         spin_lock_irqsave(&chan->lock, flags);
1023
1024         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
1025                 struct dmaengine_result result;
1026
1027                 if (desc->cyclic) {
1028                         xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
1029                         break;
1030                 }
1031
1032                 /* Remove from the list of running transactions */
1033                 list_del(&desc->node);
1034
1035                 if (unlikely(desc->err)) {
1036                         if (chan->direction == DMA_DEV_TO_MEM)
1037                                 result.result = DMA_TRANS_READ_FAILED;
1038                         else
1039                                 result.result = DMA_TRANS_WRITE_FAILED;
1040                 } else {
1041                         result.result = DMA_TRANS_NOERROR;
1042                 }
1043
1044                 result.residue = desc->residue;
1045
1046                 /* Run the link descriptor callback function */
1047                 spin_unlock_irqrestore(&chan->lock, flags);
1048                 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result);
1049                 spin_lock_irqsave(&chan->lock, flags);
1050
1051                 /* Run any dependencies, then free the descriptor */
1052                 dma_run_dependencies(&desc->async_tx);
1053                 xilinx_dma_free_tx_descriptor(chan, desc);
1054
1055                 /*
1056                  * While we ran a callback the user called a terminate function,
1057                  * which takes care of cleaning up any remaining descriptors
1058                  */
1059                 if (chan->terminating)
1060                         break;
1061         }
1062
1063         spin_unlock_irqrestore(&chan->lock, flags);
1064 }
1065
1066 /**
1067  * xilinx_dma_do_tasklet - Schedule completion tasklet
1068  * @t: Pointer to the Xilinx DMA channel structure
1069  */
1070 static void xilinx_dma_do_tasklet(struct tasklet_struct *t)
1071 {
1072         struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet);
1073
1074         xilinx_dma_chan_desc_cleanup(chan);
1075 }
1076
1077 /**
1078  * xilinx_dma_alloc_chan_resources - Allocate channel resources
1079  * @dchan: DMA channel
1080  *
1081  * Return: '0' on success and failure value on error
1082  */
1083 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
1084 {
1085         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1086         int i;
1087
1088         /* Has this channel already been allocated? */
1089         if (chan->desc_pool)
1090                 return 0;
1091
1092         /*
1093          * We need the descriptor to be aligned to 64bytes
1094          * for meeting Xilinx VDMA specification requirement.
1095          */
1096         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1097                 /* Allocate the buffer descriptors. */
1098                 chan->seg_v = dma_alloc_coherent(chan->dev,
1099                                                  sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
1100                                                  &chan->seg_p, GFP_KERNEL);
1101                 if (!chan->seg_v) {
1102                         dev_err(chan->dev,
1103                                 "unable to allocate channel %d descriptors\n",
1104                                 chan->id);
1105                         return -ENOMEM;
1106                 }
1107                 /*
1108                  * For cyclic DMA mode we need to program the tail Descriptor
1109                  * register with a value which is not a part of the BD chain
1110                  * so allocating a desc segment during channel allocation for
1111                  * programming tail descriptor.
1112                  */
1113                 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
1114                                                         sizeof(*chan->cyclic_seg_v),
1115                                                         &chan->cyclic_seg_p,
1116                                                         GFP_KERNEL);
1117                 if (!chan->cyclic_seg_v) {
1118                         dev_err(chan->dev,
1119                                 "unable to allocate desc segment for cyclic DMA\n");
1120                         dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
1121                                 XILINX_DMA_NUM_DESCS, chan->seg_v,
1122                                 chan->seg_p);
1123                         return -ENOMEM;
1124                 }
1125                 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
1126
1127                 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1128                         chan->seg_v[i].hw.next_desc =
1129                         lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1130                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1131                         chan->seg_v[i].hw.next_desc_msb =
1132                         upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1133                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1134                         chan->seg_v[i].phys = chan->seg_p +
1135                                 sizeof(*chan->seg_v) * i;
1136                         list_add_tail(&chan->seg_v[i].node,
1137                                       &chan->free_seg_list);
1138                 }
1139         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
1140                 /* Allocate the buffer descriptors. */
1141                 chan->seg_mv = dma_alloc_coherent(chan->dev,
1142                                                   sizeof(*chan->seg_mv) *
1143                                                   XILINX_DMA_NUM_DESCS,
1144                                                   &chan->seg_p, GFP_KERNEL);
1145                 if (!chan->seg_mv) {
1146                         dev_err(chan->dev,
1147                                 "unable to allocate channel %d descriptors\n",
1148                                 chan->id);
1149                         return -ENOMEM;
1150                 }
1151                 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1152                         chan->seg_mv[i].hw.next_desc =
1153                         lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1154                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1155                         chan->seg_mv[i].hw.next_desc_msb =
1156                         upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1157                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1158                         chan->seg_mv[i].phys = chan->seg_p +
1159                                 sizeof(*chan->seg_mv) * i;
1160                         list_add_tail(&chan->seg_mv[i].node,
1161                                       &chan->free_seg_list);
1162                 }
1163         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1164                 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
1165                                    chan->dev,
1166                                    sizeof(struct xilinx_cdma_tx_segment),
1167                                    __alignof__(struct xilinx_cdma_tx_segment),
1168                                    0);
1169         } else {
1170                 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
1171                                      chan->dev,
1172                                      sizeof(struct xilinx_vdma_tx_segment),
1173                                      __alignof__(struct xilinx_vdma_tx_segment),
1174                                      0);
1175         }
1176
1177         if (!chan->desc_pool &&
1178             ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) &&
1179                 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) {
1180                 dev_err(chan->dev,
1181                         "unable to allocate channel %d descriptor pool\n",
1182                         chan->id);
1183                 return -ENOMEM;
1184         }
1185
1186         dma_cookie_init(dchan);
1187
1188         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1189                 /* For AXI DMA resetting once channel will reset the
1190                  * other channel as well so enable the interrupts here.
1191                  */
1192                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1193                               XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1194         }
1195
1196         if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
1197                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1198                              XILINX_CDMA_CR_SGMODE);
1199
1200         return 0;
1201 }
1202
1203 /**
1204  * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1205  * @chan: Driver specific DMA channel
1206  * @size: Total data that needs to be copied
1207  * @done: Amount of data that has been already copied
1208  *
1209  * Return: Amount of data that has to be copied
1210  */
1211 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
1212                                     int size, int done)
1213 {
1214         size_t copy;
1215
1216         copy = min_t(size_t, size - done,
1217                      chan->xdev->max_buffer_len);
1218
1219         if ((copy + done < size) &&
1220             chan->xdev->common.copy_align) {
1221                 /*
1222                  * If this is not the last descriptor, make sure
1223                  * the next one will be properly aligned
1224                  */
1225                 copy = rounddown(copy,
1226                                  (1 << chan->xdev->common.copy_align));
1227         }
1228         return copy;
1229 }
1230
1231 /**
1232  * xilinx_dma_tx_status - Get DMA transaction status
1233  * @dchan: DMA channel
1234  * @cookie: Transaction identifier
1235  * @txstate: Transaction state
1236  *
1237  * Return: DMA transaction status
1238  */
1239 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
1240                                         dma_cookie_t cookie,
1241                                         struct dma_tx_state *txstate)
1242 {
1243         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1244         struct xilinx_dma_tx_descriptor *desc;
1245         enum dma_status ret;
1246         unsigned long flags;
1247         u32 residue = 0;
1248
1249         ret = dma_cookie_status(dchan, cookie, txstate);
1250         if (ret == DMA_COMPLETE || !txstate)
1251                 return ret;
1252
1253         spin_lock_irqsave(&chan->lock, flags);
1254         if (!list_empty(&chan->active_list)) {
1255                 desc = list_last_entry(&chan->active_list,
1256                                        struct xilinx_dma_tx_descriptor, node);
1257                 /*
1258                  * VDMA and simple mode do not support residue reporting, so the
1259                  * residue field will always be 0.
1260                  */
1261                 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
1262                         residue = xilinx_dma_get_residue(chan, desc);
1263         }
1264         spin_unlock_irqrestore(&chan->lock, flags);
1265
1266         dma_set_residue(txstate, residue);
1267
1268         return ret;
1269 }
1270
1271 /**
1272  * xilinx_dma_stop_transfer - Halt DMA channel
1273  * @chan: Driver specific DMA channel
1274  *
1275  * Return: '0' on success and failure value on error
1276  */
1277 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1278 {
1279         u32 val;
1280
1281         dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1282
1283         /* Wait for the hardware to halt */
1284         return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1285                                        val & XILINX_DMA_DMASR_HALTED, 0,
1286                                        XILINX_DMA_LOOP_COUNT);
1287 }
1288
1289 /**
1290  * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1291  * @chan: Driver specific DMA channel
1292  *
1293  * Return: '0' on success and failure value on error
1294  */
1295 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1296 {
1297         u32 val;
1298
1299         return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1300                                        val & XILINX_DMA_DMASR_IDLE, 0,
1301                                        XILINX_DMA_LOOP_COUNT);
1302 }
1303
1304 /**
1305  * xilinx_dma_start - Start DMA channel
1306  * @chan: Driver specific DMA channel
1307  */
1308 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1309 {
1310         int err;
1311         u32 val;
1312
1313         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1314
1315         /* Wait for the hardware to start */
1316         err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1317                                       !(val & XILINX_DMA_DMASR_HALTED), 0,
1318                                       XILINX_DMA_LOOP_COUNT);
1319
1320         if (err) {
1321                 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1322                         chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1323
1324                 chan->err = true;
1325         }
1326 }
1327
1328 /**
1329  * xilinx_vdma_start_transfer - Starts VDMA transfer
1330  * @chan: Driver specific channel struct pointer
1331  */
1332 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1333 {
1334         struct xilinx_vdma_config *config = &chan->config;
1335         struct xilinx_dma_tx_descriptor *desc;
1336         u32 reg, j;
1337         struct xilinx_vdma_tx_segment *segment, *last = NULL;
1338         int i = 0;
1339
1340         /* This function was invoked with lock held */
1341         if (chan->err)
1342                 return;
1343
1344         if (!chan->idle)
1345                 return;
1346
1347         if (list_empty(&chan->pending_list))
1348                 return;
1349
1350         desc = list_first_entry(&chan->pending_list,
1351                                 struct xilinx_dma_tx_descriptor, node);
1352
1353         /* Configure the hardware using info in the config structure */
1354         if (chan->has_vflip) {
1355                 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1356                 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1357                 reg |= config->vflip_en;
1358                 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1359                           reg);
1360         }
1361
1362         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1363
1364         if (config->frm_cnt_en)
1365                 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1366         else
1367                 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1368
1369         /* If not parking, enable circular mode */
1370         if (config->park)
1371                 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1372         else
1373                 reg |= XILINX_DMA_DMACR_CIRC_EN;
1374
1375         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1376
1377         j = chan->desc_submitcount;
1378         reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1379         if (chan->direction == DMA_MEM_TO_DEV) {
1380                 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1381                 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1382         } else {
1383                 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1384                 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1385         }
1386         dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1387
1388         /* Start the hardware */
1389         xilinx_dma_start(chan);
1390
1391         if (chan->err)
1392                 return;
1393
1394         /* Start the transfer */
1395         if (chan->desc_submitcount < chan->num_frms)
1396                 i = chan->desc_submitcount;
1397
1398         list_for_each_entry(segment, &desc->segments, node) {
1399                 if (chan->ext_addr)
1400                         vdma_desc_write_64(chan,
1401                                    XILINX_VDMA_REG_START_ADDRESS_64(i++),
1402                                    segment->hw.buf_addr,
1403                                    segment->hw.buf_addr_msb);
1404                 else
1405                         vdma_desc_write(chan,
1406                                         XILINX_VDMA_REG_START_ADDRESS(i++),
1407                                         segment->hw.buf_addr);
1408
1409                 last = segment;
1410         }
1411
1412         if (!last)
1413                 return;
1414
1415         /* HW expects these parameters to be same for one transaction */
1416         vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1417         vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1418                         last->hw.stride);
1419         vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1420
1421         chan->desc_submitcount++;
1422         chan->desc_pendingcount--;
1423         list_del(&desc->node);
1424         list_add_tail(&desc->node, &chan->active_list);
1425         if (chan->desc_submitcount == chan->num_frms)
1426                 chan->desc_submitcount = 0;
1427
1428         chan->idle = false;
1429 }
1430
1431 /**
1432  * xilinx_cdma_start_transfer - Starts cdma transfer
1433  * @chan: Driver specific channel struct pointer
1434  */
1435 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1436 {
1437         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1438         struct xilinx_cdma_tx_segment *tail_segment;
1439         u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1440
1441         if (chan->err)
1442                 return;
1443
1444         if (!chan->idle)
1445                 return;
1446
1447         if (list_empty(&chan->pending_list))
1448                 return;
1449
1450         head_desc = list_first_entry(&chan->pending_list,
1451                                      struct xilinx_dma_tx_descriptor, node);
1452         tail_desc = list_last_entry(&chan->pending_list,
1453                                     struct xilinx_dma_tx_descriptor, node);
1454         tail_segment = list_last_entry(&tail_desc->segments,
1455                                        struct xilinx_cdma_tx_segment, node);
1456
1457         if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1458                 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1459                 ctrl_reg |= chan->desc_pendingcount <<
1460                                 XILINX_DMA_CR_COALESCE_SHIFT;
1461                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1462         }
1463
1464         if (chan->has_sg) {
1465                 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1466                              XILINX_CDMA_CR_SGMODE);
1467
1468                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1469                              XILINX_CDMA_CR_SGMODE);
1470
1471                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1472                              head_desc->async_tx.phys);
1473
1474                 /* Update tail ptr register which will start the transfer */
1475                 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1476                              tail_segment->phys);
1477         } else {
1478                 /* In simple mode */
1479                 struct xilinx_cdma_tx_segment *segment;
1480                 struct xilinx_cdma_desc_hw *hw;
1481
1482                 segment = list_first_entry(&head_desc->segments,
1483                                            struct xilinx_cdma_tx_segment,
1484                                            node);
1485
1486                 hw = &segment->hw;
1487
1488                 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1489                              xilinx_prep_dma_addr_t(hw->src_addr));
1490                 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1491                              xilinx_prep_dma_addr_t(hw->dest_addr));
1492
1493                 /* Start the transfer */
1494                 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1495                                 hw->control & chan->xdev->max_buffer_len);
1496         }
1497
1498         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1499         chan->desc_pendingcount = 0;
1500         chan->idle = false;
1501 }
1502
1503 /**
1504  * xilinx_dma_start_transfer - Starts DMA transfer
1505  * @chan: Driver specific channel struct pointer
1506  */
1507 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1508 {
1509         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1510         struct xilinx_axidma_tx_segment *tail_segment;
1511         u32 reg;
1512
1513         if (chan->err)
1514                 return;
1515
1516         if (list_empty(&chan->pending_list))
1517                 return;
1518
1519         if (!chan->idle)
1520                 return;
1521
1522         head_desc = list_first_entry(&chan->pending_list,
1523                                      struct xilinx_dma_tx_descriptor, node);
1524         tail_desc = list_last_entry(&chan->pending_list,
1525                                     struct xilinx_dma_tx_descriptor, node);
1526         tail_segment = list_last_entry(&tail_desc->segments,
1527                                        struct xilinx_axidma_tx_segment, node);
1528
1529         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1530
1531         if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1532                 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1533                 reg |= chan->desc_pendingcount <<
1534                                   XILINX_DMA_CR_COALESCE_SHIFT;
1535                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1536         }
1537
1538         if (chan->has_sg)
1539                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1540                              head_desc->async_tx.phys);
1541
1542         xilinx_dma_start(chan);
1543
1544         if (chan->err)
1545                 return;
1546
1547         /* Start the transfer */
1548         if (chan->has_sg) {
1549                 if (chan->cyclic)
1550                         xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1551                                      chan->cyclic_seg_v->phys);
1552                 else
1553                         xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1554                                      tail_segment->phys);
1555         } else {
1556                 struct xilinx_axidma_tx_segment *segment;
1557                 struct xilinx_axidma_desc_hw *hw;
1558
1559                 segment = list_first_entry(&head_desc->segments,
1560                                            struct xilinx_axidma_tx_segment,
1561                                            node);
1562                 hw = &segment->hw;
1563
1564                 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1565                              xilinx_prep_dma_addr_t(hw->buf_addr));
1566
1567                 /* Start the transfer */
1568                 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1569                                hw->control & chan->xdev->max_buffer_len);
1570         }
1571
1572         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1573         chan->desc_pendingcount = 0;
1574         chan->idle = false;
1575 }
1576
1577 /**
1578  * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1579  * @chan: Driver specific channel struct pointer
1580  */
1581 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
1582 {
1583         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1584         struct xilinx_aximcdma_tx_segment *tail_segment;
1585         u32 reg;
1586
1587         /*
1588          * lock has been held by calling functions, so we don't need it
1589          * to take it here again.
1590          */
1591
1592         if (chan->err)
1593                 return;
1594
1595         if (!chan->idle)
1596                 return;
1597
1598         if (list_empty(&chan->pending_list))
1599                 return;
1600
1601         head_desc = list_first_entry(&chan->pending_list,
1602                                      struct xilinx_dma_tx_descriptor, node);
1603         tail_desc = list_last_entry(&chan->pending_list,
1604                                     struct xilinx_dma_tx_descriptor, node);
1605         tail_segment = list_last_entry(&tail_desc->segments,
1606                                        struct xilinx_aximcdma_tx_segment, node);
1607
1608         reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1609
1610         if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) {
1611                 reg &= ~XILINX_MCDMA_COALESCE_MASK;
1612                 reg |= chan->desc_pendingcount <<
1613                         XILINX_MCDMA_COALESCE_SHIFT;
1614         }
1615
1616         reg |= XILINX_MCDMA_IRQ_ALL_MASK;
1617         dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1618
1619         /* Program current descriptor */
1620         xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest),
1621                      head_desc->async_tx.phys);
1622
1623         /* Program channel enable register */
1624         reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET);
1625         reg |= BIT(chan->tdest);
1626         dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
1627
1628         /* Start the fetch of BDs for the channel */
1629         reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1630         reg |= XILINX_MCDMA_CR_RUNSTOP_MASK;
1631         dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1632
1633         xilinx_dma_start(chan);
1634
1635         if (chan->err)
1636                 return;
1637
1638         /* Start the transfer */
1639         xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest),
1640                      tail_segment->phys);
1641
1642         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1643         chan->desc_pendingcount = 0;
1644         chan->idle = false;
1645 }
1646
1647 /**
1648  * xilinx_dma_issue_pending - Issue pending transactions
1649  * @dchan: DMA channel
1650  */
1651 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1652 {
1653         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1654         unsigned long flags;
1655
1656         spin_lock_irqsave(&chan->lock, flags);
1657         chan->start_transfer(chan);
1658         spin_unlock_irqrestore(&chan->lock, flags);
1659 }
1660
1661 /**
1662  * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1663  * @chan : xilinx DMA channel
1664  *
1665  * CONTEXT: hardirq
1666  */
1667 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1668 {
1669         struct xilinx_dma_tx_descriptor *desc, *next;
1670
1671         /* This function was invoked with lock held */
1672         if (list_empty(&chan->active_list))
1673                 return;
1674
1675         list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1676                 if (chan->has_sg && chan->xdev->dma_config->dmatype !=
1677                     XDMA_TYPE_VDMA)
1678                         desc->residue = xilinx_dma_get_residue(chan, desc);
1679                 else
1680                         desc->residue = 0;
1681                 desc->err = chan->err;
1682
1683                 list_del(&desc->node);
1684                 if (!desc->cyclic)
1685                         dma_cookie_complete(&desc->async_tx);
1686                 list_add_tail(&desc->node, &chan->done_list);
1687         }
1688 }
1689
1690 /**
1691  * xilinx_dma_reset - Reset DMA channel
1692  * @chan: Driver specific DMA channel
1693  *
1694  * Return: '0' on success and failure value on error
1695  */
1696 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1697 {
1698         int err;
1699         u32 tmp;
1700
1701         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1702
1703         /* Wait for the hardware to finish reset */
1704         err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1705                                       !(tmp & XILINX_DMA_DMACR_RESET), 0,
1706                                       XILINX_DMA_LOOP_COUNT);
1707
1708         if (err) {
1709                 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1710                         dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1711                         dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1712                 return -ETIMEDOUT;
1713         }
1714
1715         chan->err = false;
1716         chan->idle = true;
1717         chan->desc_pendingcount = 0;
1718         chan->desc_submitcount = 0;
1719
1720         return err;
1721 }
1722
1723 /**
1724  * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1725  * @chan: Driver specific DMA channel
1726  *
1727  * Return: '0' on success and failure value on error
1728  */
1729 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1730 {
1731         int err;
1732
1733         /* Reset VDMA */
1734         err = xilinx_dma_reset(chan);
1735         if (err)
1736                 return err;
1737
1738         /* Enable interrupts */
1739         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1740                       XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1741
1742         return 0;
1743 }
1744
1745 /**
1746  * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1747  * @irq: IRQ number
1748  * @data: Pointer to the Xilinx MCDMA channel structure
1749  *
1750  * Return: IRQ_HANDLED/IRQ_NONE
1751  */
1752 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
1753 {
1754         struct xilinx_dma_chan *chan = data;
1755         u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id;
1756
1757         if (chan->direction == DMA_DEV_TO_MEM)
1758                 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET;
1759         else
1760                 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET;
1761
1762         /* Read the channel id raising the interrupt*/
1763         chan_sermask = dma_ctrl_read(chan, ser_offset);
1764         chan_id = ffs(chan_sermask);
1765
1766         if (!chan_id)
1767                 return IRQ_NONE;
1768
1769         if (chan->direction == DMA_DEV_TO_MEM)
1770                 chan_offset = chan->xdev->dma_config->max_channels / 2;
1771
1772         chan_offset = chan_offset + (chan_id - 1);
1773         chan = chan->xdev->chan[chan_offset];
1774         /* Read the status and ack the interrupts. */
1775         status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest));
1776         if (!(status & XILINX_MCDMA_IRQ_ALL_MASK))
1777                 return IRQ_NONE;
1778
1779         dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
1780                        status & XILINX_MCDMA_IRQ_ALL_MASK);
1781
1782         if (status & XILINX_MCDMA_IRQ_ERR_MASK) {
1783                 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n",
1784                         chan,
1785                         dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET),
1786                         dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET
1787                                       (chan->tdest)),
1788                         dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET
1789                                       (chan->tdest)));
1790                 chan->err = true;
1791         }
1792
1793         if (status & XILINX_MCDMA_IRQ_DELAY_MASK) {
1794                 /*
1795                  * Device takes too long to do the transfer when user requires
1796                  * responsiveness.
1797                  */
1798                 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1799         }
1800
1801         if (status & XILINX_MCDMA_IRQ_IOC_MASK) {
1802                 spin_lock(&chan->lock);
1803                 xilinx_dma_complete_descriptor(chan);
1804                 chan->idle = true;
1805                 chan->start_transfer(chan);
1806                 spin_unlock(&chan->lock);
1807         }
1808
1809         tasklet_schedule(&chan->tasklet);
1810         return IRQ_HANDLED;
1811 }
1812
1813 /**
1814  * xilinx_dma_irq_handler - DMA Interrupt handler
1815  * @irq: IRQ number
1816  * @data: Pointer to the Xilinx DMA channel structure
1817  *
1818  * Return: IRQ_HANDLED/IRQ_NONE
1819  */
1820 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1821 {
1822         struct xilinx_dma_chan *chan = data;
1823         u32 status;
1824
1825         /* Read the status and ack the interrupts. */
1826         status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1827         if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1828                 return IRQ_NONE;
1829
1830         dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1831                         status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1832
1833         if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1834                 /*
1835                  * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1836                  * error is recoverable, ignore it. Otherwise flag the error.
1837                  *
1838                  * Only recoverable errors can be cleared in the DMASR register,
1839                  * make sure not to write to other error bits to 1.
1840                  */
1841                 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1842
1843                 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1844                                 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1845
1846                 if (!chan->flush_on_fsync ||
1847                     (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1848                         dev_err(chan->dev,
1849                                 "Channel %p has errors %x, cdr %x tdr %x\n",
1850                                 chan, errors,
1851                                 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1852                                 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1853                         chan->err = true;
1854                 }
1855         }
1856
1857         if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1858                 /*
1859                  * Device takes too long to do the transfer when user requires
1860                  * responsiveness.
1861                  */
1862                 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1863         }
1864
1865         if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1866                 spin_lock(&chan->lock);
1867                 xilinx_dma_complete_descriptor(chan);
1868                 chan->idle = true;
1869                 chan->start_transfer(chan);
1870                 spin_unlock(&chan->lock);
1871         }
1872
1873         tasklet_schedule(&chan->tasklet);
1874         return IRQ_HANDLED;
1875 }
1876
1877 /**
1878  * append_desc_queue - Queuing descriptor
1879  * @chan: Driver specific dma channel
1880  * @desc: dma transaction descriptor
1881  */
1882 static void append_desc_queue(struct xilinx_dma_chan *chan,
1883                               struct xilinx_dma_tx_descriptor *desc)
1884 {
1885         struct xilinx_vdma_tx_segment *tail_segment;
1886         struct xilinx_dma_tx_descriptor *tail_desc;
1887         struct xilinx_axidma_tx_segment *axidma_tail_segment;
1888         struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment;
1889         struct xilinx_cdma_tx_segment *cdma_tail_segment;
1890
1891         if (list_empty(&chan->pending_list))
1892                 goto append;
1893
1894         /*
1895          * Add the hardware descriptor to the chain of hardware descriptors
1896          * that already exists in memory.
1897          */
1898         tail_desc = list_last_entry(&chan->pending_list,
1899                                     struct xilinx_dma_tx_descriptor, node);
1900         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1901                 tail_segment = list_last_entry(&tail_desc->segments,
1902                                                struct xilinx_vdma_tx_segment,
1903                                                node);
1904                 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1905         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1906                 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1907                                                 struct xilinx_cdma_tx_segment,
1908                                                 node);
1909                 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1910         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1911                 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1912                                                struct xilinx_axidma_tx_segment,
1913                                                node);
1914                 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1915         } else {
1916                 aximcdma_tail_segment =
1917                         list_last_entry(&tail_desc->segments,
1918                                         struct xilinx_aximcdma_tx_segment,
1919                                         node);
1920                 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1921         }
1922
1923         /*
1924          * Add the software descriptor and all children to the list
1925          * of pending transactions
1926          */
1927 append:
1928         list_add_tail(&desc->node, &chan->pending_list);
1929         chan->desc_pendingcount++;
1930
1931         if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1932             && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1933                 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1934                 chan->desc_pendingcount = chan->num_frms;
1935         }
1936 }
1937
1938 /**
1939  * xilinx_dma_tx_submit - Submit DMA transaction
1940  * @tx: Async transaction descriptor
1941  *
1942  * Return: cookie value on success and failure value on error
1943  */
1944 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1945 {
1946         struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1947         struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1948         dma_cookie_t cookie;
1949         unsigned long flags;
1950         int err;
1951
1952         if (chan->cyclic) {
1953                 xilinx_dma_free_tx_descriptor(chan, desc);
1954                 return -EBUSY;
1955         }
1956
1957         if (chan->err) {
1958                 /*
1959                  * If reset fails, need to hard reset the system.
1960                  * Channel is no longer functional
1961                  */
1962                 err = xilinx_dma_chan_reset(chan);
1963                 if (err < 0)
1964                         return err;
1965         }
1966
1967         spin_lock_irqsave(&chan->lock, flags);
1968
1969         cookie = dma_cookie_assign(tx);
1970
1971         /* Put this transaction onto the tail of the pending queue */
1972         append_desc_queue(chan, desc);
1973
1974         if (desc->cyclic)
1975                 chan->cyclic = true;
1976
1977         chan->terminating = false;
1978
1979         spin_unlock_irqrestore(&chan->lock, flags);
1980
1981         return cookie;
1982 }
1983
1984 /**
1985  * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1986  *      DMA_SLAVE transaction
1987  * @dchan: DMA channel
1988  * @xt: Interleaved template pointer
1989  * @flags: transfer ack flags
1990  *
1991  * Return: Async transaction descriptor on success and NULL on failure
1992  */
1993 static struct dma_async_tx_descriptor *
1994 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
1995                                  struct dma_interleaved_template *xt,
1996                                  unsigned long flags)
1997 {
1998         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1999         struct xilinx_dma_tx_descriptor *desc;
2000         struct xilinx_vdma_tx_segment *segment;
2001         struct xilinx_vdma_desc_hw *hw;
2002
2003         if (!is_slave_direction(xt->dir))
2004                 return NULL;
2005
2006         if (!xt->numf || !xt->sgl[0].size)
2007                 return NULL;
2008
2009         if (xt->frame_size != 1)
2010                 return NULL;
2011
2012         /* Allocate a transaction descriptor. */
2013         desc = xilinx_dma_alloc_tx_descriptor(chan);
2014         if (!desc)
2015                 return NULL;
2016
2017         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2018         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2019         async_tx_ack(&desc->async_tx);
2020
2021         /* Allocate the link descriptor from DMA pool */
2022         segment = xilinx_vdma_alloc_tx_segment(chan);
2023         if (!segment)
2024                 goto error;
2025
2026         /* Fill in the hardware descriptor */
2027         hw = &segment->hw;
2028         hw->vsize = xt->numf;
2029         hw->hsize = xt->sgl[0].size;
2030         hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
2031                         XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
2032         hw->stride |= chan->config.frm_dly <<
2033                         XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
2034
2035         if (xt->dir != DMA_MEM_TO_DEV) {
2036                 if (chan->ext_addr) {
2037                         hw->buf_addr = lower_32_bits(xt->dst_start);
2038                         hw->buf_addr_msb = upper_32_bits(xt->dst_start);
2039                 } else {
2040                         hw->buf_addr = xt->dst_start;
2041                 }
2042         } else {
2043                 if (chan->ext_addr) {
2044                         hw->buf_addr = lower_32_bits(xt->src_start);
2045                         hw->buf_addr_msb = upper_32_bits(xt->src_start);
2046                 } else {
2047                         hw->buf_addr = xt->src_start;
2048                 }
2049         }
2050
2051         /* Insert the segment into the descriptor segments list. */
2052         list_add_tail(&segment->node, &desc->segments);
2053
2054         /* Link the last hardware descriptor with the first. */
2055         segment = list_first_entry(&desc->segments,
2056                                    struct xilinx_vdma_tx_segment, node);
2057         desc->async_tx.phys = segment->phys;
2058
2059         return &desc->async_tx;
2060
2061 error:
2062         xilinx_dma_free_tx_descriptor(chan, desc);
2063         return NULL;
2064 }
2065
2066 /**
2067  * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2068  * @dchan: DMA channel
2069  * @dma_dst: destination address
2070  * @dma_src: source address
2071  * @len: transfer length
2072  * @flags: transfer ack flags
2073  *
2074  * Return: Async transaction descriptor on success and NULL on failure
2075  */
2076 static struct dma_async_tx_descriptor *
2077 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
2078                         dma_addr_t dma_src, size_t len, unsigned long flags)
2079 {
2080         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2081         struct xilinx_dma_tx_descriptor *desc;
2082         struct xilinx_cdma_tx_segment *segment;
2083         struct xilinx_cdma_desc_hw *hw;
2084
2085         if (!len || len > chan->xdev->max_buffer_len)
2086                 return NULL;
2087
2088         desc = xilinx_dma_alloc_tx_descriptor(chan);
2089         if (!desc)
2090                 return NULL;
2091
2092         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2093         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2094
2095         /* Allocate the link descriptor from DMA pool */
2096         segment = xilinx_cdma_alloc_tx_segment(chan);
2097         if (!segment)
2098                 goto error;
2099
2100         hw = &segment->hw;
2101         hw->control = len;
2102         hw->src_addr = dma_src;
2103         hw->dest_addr = dma_dst;
2104         if (chan->ext_addr) {
2105                 hw->src_addr_msb = upper_32_bits(dma_src);
2106                 hw->dest_addr_msb = upper_32_bits(dma_dst);
2107         }
2108
2109         /* Insert the segment into the descriptor segments list. */
2110         list_add_tail(&segment->node, &desc->segments);
2111
2112         desc->async_tx.phys = segment->phys;
2113         hw->next_desc = segment->phys;
2114
2115         return &desc->async_tx;
2116
2117 error:
2118         xilinx_dma_free_tx_descriptor(chan, desc);
2119         return NULL;
2120 }
2121
2122 /**
2123  * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2124  * @dchan: DMA channel
2125  * @sgl: scatterlist to transfer to/from
2126  * @sg_len: number of entries in @scatterlist
2127  * @direction: DMA direction
2128  * @flags: transfer ack flags
2129  * @context: APP words of the descriptor
2130  *
2131  * Return: Async transaction descriptor on success and NULL on failure
2132  */
2133 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
2134         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
2135         enum dma_transfer_direction direction, unsigned long flags,
2136         void *context)
2137 {
2138         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2139         struct xilinx_dma_tx_descriptor *desc;
2140         struct xilinx_axidma_tx_segment *segment = NULL;
2141         u32 *app_w = (u32 *)context;
2142         struct scatterlist *sg;
2143         size_t copy;
2144         size_t sg_used;
2145         unsigned int i;
2146
2147         if (!is_slave_direction(direction))
2148                 return NULL;
2149
2150         /* Allocate a transaction descriptor. */
2151         desc = xilinx_dma_alloc_tx_descriptor(chan);
2152         if (!desc)
2153                 return NULL;
2154
2155         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2156         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2157
2158         /* Build transactions using information in the scatter gather list */
2159         for_each_sg(sgl, sg, sg_len, i) {
2160                 sg_used = 0;
2161
2162                 /* Loop until the entire scatterlist entry is used */
2163                 while (sg_used < sg_dma_len(sg)) {
2164                         struct xilinx_axidma_desc_hw *hw;
2165
2166                         /* Get a free segment */
2167                         segment = xilinx_axidma_alloc_tx_segment(chan);
2168                         if (!segment)
2169                                 goto error;
2170
2171                         /*
2172                          * Calculate the maximum number of bytes to transfer,
2173                          * making sure it is less than the hw limit
2174                          */
2175                         copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
2176                                                         sg_used);
2177                         hw = &segment->hw;
2178
2179                         /* Fill in the descriptor */
2180                         xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
2181                                           sg_used, 0);
2182
2183                         hw->control = copy;
2184
2185                         if (chan->direction == DMA_MEM_TO_DEV) {
2186                                 if (app_w)
2187                                         memcpy(hw->app, app_w, sizeof(u32) *
2188                                                XILINX_DMA_NUM_APP_WORDS);
2189                         }
2190
2191                         sg_used += copy;
2192
2193                         /*
2194                          * Insert the segment into the descriptor segments
2195                          * list.
2196                          */
2197                         list_add_tail(&segment->node, &desc->segments);
2198                 }
2199         }
2200
2201         segment = list_first_entry(&desc->segments,
2202                                    struct xilinx_axidma_tx_segment, node);
2203         desc->async_tx.phys = segment->phys;
2204
2205         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2206         if (chan->direction == DMA_MEM_TO_DEV) {
2207                 segment->hw.control |= XILINX_DMA_BD_SOP;
2208                 segment = list_last_entry(&desc->segments,
2209                                           struct xilinx_axidma_tx_segment,
2210                                           node);
2211                 segment->hw.control |= XILINX_DMA_BD_EOP;
2212         }
2213
2214         return &desc->async_tx;
2215
2216 error:
2217         xilinx_dma_free_tx_descriptor(chan, desc);
2218         return NULL;
2219 }
2220
2221 /**
2222  * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2223  * @dchan: DMA channel
2224  * @buf_addr: Physical address of the buffer
2225  * @buf_len: Total length of the cyclic buffers
2226  * @period_len: length of individual cyclic buffer
2227  * @direction: DMA direction
2228  * @flags: transfer ack flags
2229  *
2230  * Return: Async transaction descriptor on success and NULL on failure
2231  */
2232 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
2233         struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
2234         size_t period_len, enum dma_transfer_direction direction,
2235         unsigned long flags)
2236 {
2237         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2238         struct xilinx_dma_tx_descriptor *desc;
2239         struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
2240         size_t copy, sg_used;
2241         unsigned int num_periods;
2242         int i;
2243         u32 reg;
2244
2245         if (!period_len)
2246                 return NULL;
2247
2248         num_periods = buf_len / period_len;
2249
2250         if (!num_periods)
2251                 return NULL;
2252
2253         if (!is_slave_direction(direction))
2254                 return NULL;
2255
2256         /* Allocate a transaction descriptor. */
2257         desc = xilinx_dma_alloc_tx_descriptor(chan);
2258         if (!desc)
2259                 return NULL;
2260
2261         chan->direction = direction;
2262         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2263         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2264
2265         for (i = 0; i < num_periods; ++i) {
2266                 sg_used = 0;
2267
2268                 while (sg_used < period_len) {
2269                         struct xilinx_axidma_desc_hw *hw;
2270
2271                         /* Get a free segment */
2272                         segment = xilinx_axidma_alloc_tx_segment(chan);
2273                         if (!segment)
2274                                 goto error;
2275
2276                         /*
2277                          * Calculate the maximum number of bytes to transfer,
2278                          * making sure it is less than the hw limit
2279                          */
2280                         copy = xilinx_dma_calc_copysize(chan, period_len,
2281                                                         sg_used);
2282                         hw = &segment->hw;
2283                         xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
2284                                           period_len * i);
2285                         hw->control = copy;
2286
2287                         if (prev)
2288                                 prev->hw.next_desc = segment->phys;
2289
2290                         prev = segment;
2291                         sg_used += copy;
2292
2293                         /*
2294                          * Insert the segment into the descriptor segments
2295                          * list.
2296                          */
2297                         list_add_tail(&segment->node, &desc->segments);
2298                 }
2299         }
2300
2301         head_segment = list_first_entry(&desc->segments,
2302                                    struct xilinx_axidma_tx_segment, node);
2303         desc->async_tx.phys = head_segment->phys;
2304
2305         desc->cyclic = true;
2306         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2307         reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2308         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2309
2310         segment = list_last_entry(&desc->segments,
2311                                   struct xilinx_axidma_tx_segment,
2312                                   node);
2313         segment->hw.next_desc = (u32) head_segment->phys;
2314
2315         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2316         if (direction == DMA_MEM_TO_DEV) {
2317                 head_segment->hw.control |= XILINX_DMA_BD_SOP;
2318                 segment->hw.control |= XILINX_DMA_BD_EOP;
2319         }
2320
2321         return &desc->async_tx;
2322
2323 error:
2324         xilinx_dma_free_tx_descriptor(chan, desc);
2325         return NULL;
2326 }
2327
2328 /**
2329  * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2330  * @dchan: DMA channel
2331  * @sgl: scatterlist to transfer to/from
2332  * @sg_len: number of entries in @scatterlist
2333  * @direction: DMA direction
2334  * @flags: transfer ack flags
2335  * @context: APP words of the descriptor
2336  *
2337  * Return: Async transaction descriptor on success and NULL on failure
2338  */
2339 static struct dma_async_tx_descriptor *
2340 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
2341                            unsigned int sg_len,
2342                            enum dma_transfer_direction direction,
2343                            unsigned long flags, void *context)
2344 {
2345         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2346         struct xilinx_dma_tx_descriptor *desc;
2347         struct xilinx_aximcdma_tx_segment *segment = NULL;
2348         u32 *app_w = (u32 *)context;
2349         struct scatterlist *sg;
2350         size_t copy;
2351         size_t sg_used;
2352         unsigned int i;
2353
2354         if (!is_slave_direction(direction))
2355                 return NULL;
2356
2357         /* Allocate a transaction descriptor. */
2358         desc = xilinx_dma_alloc_tx_descriptor(chan);
2359         if (!desc)
2360                 return NULL;
2361
2362         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2363         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2364
2365         /* Build transactions using information in the scatter gather list */
2366         for_each_sg(sgl, sg, sg_len, i) {
2367                 sg_used = 0;
2368
2369                 /* Loop until the entire scatterlist entry is used */
2370                 while (sg_used < sg_dma_len(sg)) {
2371                         struct xilinx_aximcdma_desc_hw *hw;
2372
2373                         /* Get a free segment */
2374                         segment = xilinx_aximcdma_alloc_tx_segment(chan);
2375                         if (!segment)
2376                                 goto error;
2377
2378                         /*
2379                          * Calculate the maximum number of bytes to transfer,
2380                          * making sure it is less than the hw limit
2381                          */
2382                         copy = min_t(size_t, sg_dma_len(sg) - sg_used,
2383                                      chan->xdev->max_buffer_len);
2384                         hw = &segment->hw;
2385
2386                         /* Fill in the descriptor */
2387                         xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg),
2388                                             sg_used);
2389                         hw->control = copy;
2390
2391                         if (chan->direction == DMA_MEM_TO_DEV && app_w) {
2392                                 memcpy(hw->app, app_w, sizeof(u32) *
2393                                        XILINX_DMA_NUM_APP_WORDS);
2394                         }
2395
2396                         sg_used += copy;
2397                         /*
2398                          * Insert the segment into the descriptor segments
2399                          * list.
2400                          */
2401                         list_add_tail(&segment->node, &desc->segments);
2402                 }
2403         }
2404
2405         segment = list_first_entry(&desc->segments,
2406                                    struct xilinx_aximcdma_tx_segment, node);
2407         desc->async_tx.phys = segment->phys;
2408
2409         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2410         if (chan->direction == DMA_MEM_TO_DEV) {
2411                 segment->hw.control |= XILINX_MCDMA_BD_SOP;
2412                 segment = list_last_entry(&desc->segments,
2413                                           struct xilinx_aximcdma_tx_segment,
2414                                           node);
2415                 segment->hw.control |= XILINX_MCDMA_BD_EOP;
2416         }
2417
2418         return &desc->async_tx;
2419
2420 error:
2421         xilinx_dma_free_tx_descriptor(chan, desc);
2422
2423         return NULL;
2424 }
2425
2426 /**
2427  * xilinx_dma_terminate_all - Halt the channel and free descriptors
2428  * @dchan: Driver specific DMA Channel pointer
2429  *
2430  * Return: '0' always.
2431  */
2432 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2433 {
2434         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2435         u32 reg;
2436         int err;
2437
2438         if (!chan->cyclic) {
2439                 err = chan->stop_transfer(chan);
2440                 if (err) {
2441                         dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2442                                 chan, dma_ctrl_read(chan,
2443                                 XILINX_DMA_REG_DMASR));
2444                         chan->err = true;
2445                 }
2446         }
2447
2448         xilinx_dma_chan_reset(chan);
2449         /* Remove and free all of the descriptors in the lists */
2450         chan->terminating = true;
2451         xilinx_dma_free_descriptors(chan);
2452         chan->idle = true;
2453
2454         if (chan->cyclic) {
2455                 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2456                 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2457                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2458                 chan->cyclic = false;
2459         }
2460
2461         if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2462                 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2463                              XILINX_CDMA_CR_SGMODE);
2464
2465         return 0;
2466 }
2467
2468 static void xilinx_dma_synchronize(struct dma_chan *dchan)
2469 {
2470         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2471
2472         tasklet_kill(&chan->tasklet);
2473 }
2474
2475 /**
2476  * xilinx_dma_channel_set_config - Configure VDMA channel
2477  * Run-time configuration for Axi VDMA, supports:
2478  * . halt the channel
2479  * . configure interrupt coalescing and inter-packet delay threshold
2480  * . start/stop parking
2481  * . enable genlock
2482  *
2483  * @dchan: DMA channel
2484  * @cfg: VDMA device configuration pointer
2485  *
2486  * Return: '0' on success and failure value on error
2487  */
2488 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2489                                         struct xilinx_vdma_config *cfg)
2490 {
2491         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2492         u32 dmacr;
2493
2494         if (cfg->reset)
2495                 return xilinx_dma_chan_reset(chan);
2496
2497         dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2498
2499         chan->config.frm_dly = cfg->frm_dly;
2500         chan->config.park = cfg->park;
2501
2502         /* genlock settings */
2503         chan->config.gen_lock = cfg->gen_lock;
2504         chan->config.master = cfg->master;
2505
2506         dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2507         if (cfg->gen_lock && chan->genlock) {
2508                 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2509                 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2510                 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2511         }
2512
2513         chan->config.frm_cnt_en = cfg->frm_cnt_en;
2514         chan->config.vflip_en = cfg->vflip_en;
2515
2516         if (cfg->park)
2517                 chan->config.park_frm = cfg->park_frm;
2518         else
2519                 chan->config.park_frm = -1;
2520
2521         chan->config.coalesc = cfg->coalesc;
2522         chan->config.delay = cfg->delay;
2523
2524         if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2525                 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2526                 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2527                 chan->config.coalesc = cfg->coalesc;
2528         }
2529
2530         if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2531                 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2532                 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2533                 chan->config.delay = cfg->delay;
2534         }
2535
2536         /* FSync Source selection */
2537         dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2538         dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2539
2540         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2541
2542         return 0;
2543 }
2544 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2545
2546 /* -----------------------------------------------------------------------------
2547  * Probe and remove
2548  */
2549
2550 /**
2551  * xilinx_dma_chan_remove - Per Channel remove function
2552  * @chan: Driver specific DMA channel
2553  */
2554 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2555 {
2556         /* Disable all interrupts */
2557         dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2558                       XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2559
2560         if (chan->irq > 0)
2561                 free_irq(chan->irq, chan);
2562
2563         tasklet_kill(&chan->tasklet);
2564
2565         list_del(&chan->common.device_node);
2566 }
2567
2568 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2569                             struct clk **tx_clk, struct clk **rx_clk,
2570                             struct clk **sg_clk, struct clk **tmp_clk)
2571 {
2572         int err;
2573
2574         *tmp_clk = NULL;
2575
2576         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2577         if (IS_ERR(*axi_clk))
2578                 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2579
2580         *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2581         if (IS_ERR(*tx_clk))
2582                 *tx_clk = NULL;
2583
2584         *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2585         if (IS_ERR(*rx_clk))
2586                 *rx_clk = NULL;
2587
2588         *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2589         if (IS_ERR(*sg_clk))
2590                 *sg_clk = NULL;
2591
2592         err = clk_prepare_enable(*axi_clk);
2593         if (err) {
2594                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2595                 return err;
2596         }
2597
2598         err = clk_prepare_enable(*tx_clk);
2599         if (err) {
2600                 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2601                 goto err_disable_axiclk;
2602         }
2603
2604         err = clk_prepare_enable(*rx_clk);
2605         if (err) {
2606                 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2607                 goto err_disable_txclk;
2608         }
2609
2610         err = clk_prepare_enable(*sg_clk);
2611         if (err) {
2612                 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2613                 goto err_disable_rxclk;
2614         }
2615
2616         return 0;
2617
2618 err_disable_rxclk:
2619         clk_disable_unprepare(*rx_clk);
2620 err_disable_txclk:
2621         clk_disable_unprepare(*tx_clk);
2622 err_disable_axiclk:
2623         clk_disable_unprepare(*axi_clk);
2624
2625         return err;
2626 }
2627
2628 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2629                             struct clk **dev_clk, struct clk **tmp_clk,
2630                             struct clk **tmp1_clk, struct clk **tmp2_clk)
2631 {
2632         int err;
2633
2634         *tmp_clk = NULL;
2635         *tmp1_clk = NULL;
2636         *tmp2_clk = NULL;
2637
2638         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2639         if (IS_ERR(*axi_clk))
2640                 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2641
2642         *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2643         if (IS_ERR(*dev_clk))
2644                 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n");
2645
2646         err = clk_prepare_enable(*axi_clk);
2647         if (err) {
2648                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2649                 return err;
2650         }
2651
2652         err = clk_prepare_enable(*dev_clk);
2653         if (err) {
2654                 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2655                 goto err_disable_axiclk;
2656         }
2657
2658         return 0;
2659
2660 err_disable_axiclk:
2661         clk_disable_unprepare(*axi_clk);
2662
2663         return err;
2664 }
2665
2666 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2667                             struct clk **tx_clk, struct clk **txs_clk,
2668                             struct clk **rx_clk, struct clk **rxs_clk)
2669 {
2670         int err;
2671
2672         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2673         if (IS_ERR(*axi_clk))
2674                 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2675
2676         *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2677         if (IS_ERR(*tx_clk))
2678                 *tx_clk = NULL;
2679
2680         *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2681         if (IS_ERR(*txs_clk))
2682                 *txs_clk = NULL;
2683
2684         *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2685         if (IS_ERR(*rx_clk))
2686                 *rx_clk = NULL;
2687
2688         *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2689         if (IS_ERR(*rxs_clk))
2690                 *rxs_clk = NULL;
2691
2692         err = clk_prepare_enable(*axi_clk);
2693         if (err) {
2694                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n",
2695                         err);
2696                 return err;
2697         }
2698
2699         err = clk_prepare_enable(*tx_clk);
2700         if (err) {
2701                 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2702                 goto err_disable_axiclk;
2703         }
2704
2705         err = clk_prepare_enable(*txs_clk);
2706         if (err) {
2707                 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2708                 goto err_disable_txclk;
2709         }
2710
2711         err = clk_prepare_enable(*rx_clk);
2712         if (err) {
2713                 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2714                 goto err_disable_txsclk;
2715         }
2716
2717         err = clk_prepare_enable(*rxs_clk);
2718         if (err) {
2719                 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2720                 goto err_disable_rxclk;
2721         }
2722
2723         return 0;
2724
2725 err_disable_rxclk:
2726         clk_disable_unprepare(*rx_clk);
2727 err_disable_txsclk:
2728         clk_disable_unprepare(*txs_clk);
2729 err_disable_txclk:
2730         clk_disable_unprepare(*tx_clk);
2731 err_disable_axiclk:
2732         clk_disable_unprepare(*axi_clk);
2733
2734         return err;
2735 }
2736
2737 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2738 {
2739         clk_disable_unprepare(xdev->rxs_clk);
2740         clk_disable_unprepare(xdev->rx_clk);
2741         clk_disable_unprepare(xdev->txs_clk);
2742         clk_disable_unprepare(xdev->tx_clk);
2743         clk_disable_unprepare(xdev->axi_clk);
2744 }
2745
2746 /**
2747  * xilinx_dma_chan_probe - Per Channel Probing
2748  * It get channel features from the device tree entry and
2749  * initialize special channel handling routines
2750  *
2751  * @xdev: Driver specific device structure
2752  * @node: Device node
2753  *
2754  * Return: '0' on success and failure value on error
2755  */
2756 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2757                                   struct device_node *node)
2758 {
2759         struct xilinx_dma_chan *chan;
2760         bool has_dre = false;
2761         u32 value, width;
2762         int err;
2763
2764         /* Allocate and initialize the channel structure */
2765         chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2766         if (!chan)
2767                 return -ENOMEM;
2768
2769         chan->dev = xdev->dev;
2770         chan->xdev = xdev;
2771         chan->desc_pendingcount = 0x0;
2772         chan->ext_addr = xdev->ext_addr;
2773         /* This variable ensures that descriptors are not
2774          * Submitted when dma engine is in progress. This variable is
2775          * Added to avoid polling for a bit in the status register to
2776          * Know dma state in the driver hot path.
2777          */
2778         chan->idle = true;
2779
2780         spin_lock_init(&chan->lock);
2781         INIT_LIST_HEAD(&chan->pending_list);
2782         INIT_LIST_HEAD(&chan->done_list);
2783         INIT_LIST_HEAD(&chan->active_list);
2784         INIT_LIST_HEAD(&chan->free_seg_list);
2785
2786         /* Retrieve the channel properties from the device tree */
2787         has_dre = of_property_read_bool(node, "xlnx,include-dre");
2788
2789         chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2790
2791         err = of_property_read_u32(node, "xlnx,datawidth", &value);
2792         if (err) {
2793                 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2794                 return err;
2795         }
2796         width = value >> 3; /* Convert bits to bytes */
2797
2798         /* If data width is greater than 8 bytes, DRE is not in hw */
2799         if (width > 8)
2800                 has_dre = false;
2801
2802         if (!has_dre)
2803                 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2804
2805         if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2806             of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2807             of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2808                 chan->direction = DMA_MEM_TO_DEV;
2809                 chan->id = xdev->mm2s_chan_id++;
2810                 chan->tdest = chan->id;
2811
2812                 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2813                 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2814                         chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2815                         chan->config.park = 1;
2816
2817                         if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2818                             xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2819                                 chan->flush_on_fsync = true;
2820                 }
2821         } else if (of_device_is_compatible(node,
2822                                            "xlnx,axi-vdma-s2mm-channel") ||
2823                    of_device_is_compatible(node,
2824                                            "xlnx,axi-dma-s2mm-channel")) {
2825                 chan->direction = DMA_DEV_TO_MEM;
2826                 chan->id = xdev->s2mm_chan_id++;
2827                 chan->tdest = chan->id - xdev->dma_config->max_channels / 2;
2828                 chan->has_vflip = of_property_read_bool(node,
2829                                         "xlnx,enable-vert-flip");
2830                 if (chan->has_vflip) {
2831                         chan->config.vflip_en = dma_read(chan,
2832                                 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2833                                 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2834                 }
2835
2836                 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
2837                         chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET;
2838                 else
2839                         chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2840
2841                 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2842                         chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2843                         chan->config.park = 1;
2844
2845                         if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2846                             xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2847                                 chan->flush_on_fsync = true;
2848                 }
2849         } else {
2850                 dev_err(xdev->dev, "Invalid channel compatible node\n");
2851                 return -EINVAL;
2852         }
2853
2854         /* Request the interrupt */
2855         chan->irq = irq_of_parse_and_map(node, chan->tdest);
2856         err = request_irq(chan->irq, xdev->dma_config->irq_handler,
2857                           IRQF_SHARED, "xilinx-dma-controller", chan);
2858         if (err) {
2859                 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2860                 return err;
2861         }
2862
2863         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2864                 chan->start_transfer = xilinx_dma_start_transfer;
2865                 chan->stop_transfer = xilinx_dma_stop_transfer;
2866         } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
2867                 chan->start_transfer = xilinx_mcdma_start_transfer;
2868                 chan->stop_transfer = xilinx_dma_stop_transfer;
2869         } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2870                 chan->start_transfer = xilinx_cdma_start_transfer;
2871                 chan->stop_transfer = xilinx_cdma_stop_transfer;
2872         } else {
2873                 chan->start_transfer = xilinx_vdma_start_transfer;
2874                 chan->stop_transfer = xilinx_dma_stop_transfer;
2875         }
2876
2877         /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */
2878         if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) {
2879                 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA ||
2880                     dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
2881                             XILINX_DMA_DMASR_SG_MASK)
2882                         chan->has_sg = true;
2883                 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2884                         chan->has_sg ? "enabled" : "disabled");
2885         }
2886
2887         /* Initialize the tasklet */
2888         tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet);
2889
2890         /*
2891          * Initialize the DMA channel and add it to the DMA engine channels
2892          * list.
2893          */
2894         chan->common.device = &xdev->common;
2895
2896         list_add_tail(&chan->common.device_node, &xdev->common.channels);
2897         xdev->chan[chan->id] = chan;
2898
2899         /* Reset the channel */
2900         err = xilinx_dma_chan_reset(chan);
2901         if (err < 0) {
2902                 dev_err(xdev->dev, "Reset channel failed\n");
2903                 return err;
2904         }
2905
2906         return 0;
2907 }
2908
2909 /**
2910  * xilinx_dma_child_probe - Per child node probe
2911  * It get number of dma-channels per child node from
2912  * device-tree and initializes all the channels.
2913  *
2914  * @xdev: Driver specific device structure
2915  * @node: Device node
2916  *
2917  * Return: 0 always.
2918  */
2919 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2920                                     struct device_node *node)
2921 {
2922         int ret, i;
2923         u32 nr_channels = 1;
2924
2925         ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2926         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0)
2927                 dev_warn(xdev->dev, "missing dma-channels property\n");
2928
2929         for (i = 0; i < nr_channels; i++)
2930                 xilinx_dma_chan_probe(xdev, node);
2931
2932         return 0;
2933 }
2934
2935 /**
2936  * of_dma_xilinx_xlate - Translation function
2937  * @dma_spec: Pointer to DMA specifier as found in the device tree
2938  * @ofdma: Pointer to DMA controller data
2939  *
2940  * Return: DMA channel pointer on success and NULL on error
2941  */
2942 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2943                                                 struct of_dma *ofdma)
2944 {
2945         struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2946         int chan_id = dma_spec->args[0];
2947
2948         if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id])
2949                 return NULL;
2950
2951         return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2952 }
2953
2954 static const struct xilinx_dma_config axidma_config = {
2955         .dmatype = XDMA_TYPE_AXIDMA,
2956         .clk_init = axidma_clk_init,
2957         .irq_handler = xilinx_dma_irq_handler,
2958         .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
2959 };
2960
2961 static const struct xilinx_dma_config aximcdma_config = {
2962         .dmatype = XDMA_TYPE_AXIMCDMA,
2963         .clk_init = axidma_clk_init,
2964         .irq_handler = xilinx_mcdma_irq_handler,
2965         .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE,
2966 };
2967 static const struct xilinx_dma_config axicdma_config = {
2968         .dmatype = XDMA_TYPE_CDMA,
2969         .clk_init = axicdma_clk_init,
2970         .irq_handler = xilinx_dma_irq_handler,
2971         .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE,
2972 };
2973
2974 static const struct xilinx_dma_config axivdma_config = {
2975         .dmatype = XDMA_TYPE_VDMA,
2976         .clk_init = axivdma_clk_init,
2977         .irq_handler = xilinx_dma_irq_handler,
2978         .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
2979 };
2980
2981 static const struct of_device_id xilinx_dma_of_ids[] = {
2982         { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2983         { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2984         { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2985         { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
2986         {}
2987 };
2988 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
2989
2990 /**
2991  * xilinx_dma_probe - Driver probe function
2992  * @pdev: Pointer to the platform_device structure
2993  *
2994  * Return: '0' on success and failure value on error
2995  */
2996 static int xilinx_dma_probe(struct platform_device *pdev)
2997 {
2998         int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
2999                         struct clk **, struct clk **, struct clk **)
3000                                         = axivdma_clk_init;
3001         struct device_node *node = pdev->dev.of_node;
3002         struct xilinx_dma_device *xdev;
3003         struct device_node *child, *np = pdev->dev.of_node;
3004         u32 num_frames, addr_width, len_width;
3005         int i, err;
3006
3007         /* Allocate and initialize the DMA engine structure */
3008         xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
3009         if (!xdev)
3010                 return -ENOMEM;
3011
3012         xdev->dev = &pdev->dev;
3013         if (np) {
3014                 const struct of_device_id *match;
3015
3016                 match = of_match_node(xilinx_dma_of_ids, np);
3017                 if (match && match->data) {
3018                         xdev->dma_config = match->data;
3019                         clk_init = xdev->dma_config->clk_init;
3020                 }
3021         }
3022
3023         err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
3024                        &xdev->rx_clk, &xdev->rxs_clk);
3025         if (err)
3026                 return err;
3027
3028         /* Request and map I/O memory */
3029         xdev->regs = devm_platform_ioremap_resource(pdev, 0);
3030         if (IS_ERR(xdev->regs))
3031                 return PTR_ERR(xdev->regs);
3032
3033         /* Retrieve the DMA engine properties from the device tree */
3034         xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
3035         xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
3036
3037         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
3038             xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3039                 if (!of_property_read_u32(node, "xlnx,sg-length-width",
3040                                           &len_width)) {
3041                         if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
3042                             len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
3043                                 dev_warn(xdev->dev,
3044                                          "invalid xlnx,sg-length-width property value. Using default width\n");
3045                         } else {
3046                                 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
3047                                         dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
3048                                 xdev->max_buffer_len =
3049                                         GENMASK(len_width - 1, 0);
3050                         }
3051                 }
3052         }
3053
3054         if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3055                 err = of_property_read_u32(node, "xlnx,num-fstores",
3056                                            &num_frames);
3057                 if (err < 0) {
3058                         dev_err(xdev->dev,
3059                                 "missing xlnx,num-fstores property\n");
3060                         return err;
3061                 }
3062
3063                 err = of_property_read_u32(node, "xlnx,flush-fsync",
3064                                            &xdev->flush_on_fsync);
3065                 if (err < 0)
3066                         dev_warn(xdev->dev,
3067                                  "missing xlnx,flush-fsync property\n");
3068         }
3069
3070         err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
3071         if (err < 0)
3072                 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
3073
3074         if (addr_width > 32)
3075                 xdev->ext_addr = true;
3076         else
3077                 xdev->ext_addr = false;
3078
3079         /* Set the dma mask bits */
3080         dma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width));
3081
3082         /* Initialize the DMA engine */
3083         xdev->common.dev = &pdev->dev;
3084
3085         INIT_LIST_HEAD(&xdev->common.channels);
3086         if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
3087                 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
3088                 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
3089         }
3090
3091         xdev->common.device_alloc_chan_resources =
3092                                 xilinx_dma_alloc_chan_resources;
3093         xdev->common.device_free_chan_resources =
3094                                 xilinx_dma_free_chan_resources;
3095         xdev->common.device_terminate_all = xilinx_dma_terminate_all;
3096         xdev->common.device_synchronize = xilinx_dma_synchronize;
3097         xdev->common.device_tx_status = xilinx_dma_tx_status;
3098         xdev->common.device_issue_pending = xilinx_dma_issue_pending;
3099         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
3100                 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
3101                 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
3102                 xdev->common.device_prep_dma_cyclic =
3103                                           xilinx_dma_prep_dma_cyclic;
3104                 /* Residue calculation is supported by only AXI DMA and CDMA */
3105                 xdev->common.residue_granularity =
3106                                           DMA_RESIDUE_GRANULARITY_SEGMENT;
3107         } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
3108                 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
3109                 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
3110                 /* Residue calculation is supported by only AXI DMA and CDMA */
3111                 xdev->common.residue_granularity =
3112                                           DMA_RESIDUE_GRANULARITY_SEGMENT;
3113         } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3114                 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg;
3115         } else {
3116                 xdev->common.device_prep_interleaved_dma =
3117                                 xilinx_vdma_dma_prep_interleaved;
3118         }
3119
3120         platform_set_drvdata(pdev, xdev);
3121
3122         /* Initialize the channels */
3123         for_each_child_of_node(node, child) {
3124                 err = xilinx_dma_child_probe(xdev, child);
3125                 if (err < 0)
3126                         goto disable_clks;
3127         }
3128
3129         if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3130                 for (i = 0; i < xdev->dma_config->max_channels; i++)
3131                         if (xdev->chan[i])
3132                                 xdev->chan[i]->num_frms = num_frames;
3133         }
3134
3135         /* Register the DMA engine with the core */
3136         err = dma_async_device_register(&xdev->common);
3137         if (err) {
3138                 dev_err(xdev->dev, "failed to register the dma device\n");
3139                 goto error;
3140         }
3141
3142         err = of_dma_controller_register(node, of_dma_xilinx_xlate,
3143                                          xdev);
3144         if (err < 0) {
3145                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
3146                 dma_async_device_unregister(&xdev->common);
3147                 goto error;
3148         }
3149
3150         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
3151                 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
3152         else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
3153                 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
3154         else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
3155                 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n");
3156         else
3157                 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
3158
3159         return 0;
3160
3161 disable_clks:
3162         xdma_disable_allclks(xdev);
3163 error:
3164         for (i = 0; i < xdev->dma_config->max_channels; i++)
3165                 if (xdev->chan[i])
3166                         xilinx_dma_chan_remove(xdev->chan[i]);
3167
3168         return err;
3169 }
3170
3171 /**
3172  * xilinx_dma_remove - Driver remove function
3173  * @pdev: Pointer to the platform_device structure
3174  *
3175  * Return: Always '0'
3176  */
3177 static int xilinx_dma_remove(struct platform_device *pdev)
3178 {
3179         struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
3180         int i;
3181
3182         of_dma_controller_free(pdev->dev.of_node);
3183
3184         dma_async_device_unregister(&xdev->common);
3185
3186         for (i = 0; i < xdev->dma_config->max_channels; i++)
3187                 if (xdev->chan[i])
3188                         xilinx_dma_chan_remove(xdev->chan[i]);
3189
3190         xdma_disable_allclks(xdev);
3191
3192         return 0;
3193 }
3194
3195 static struct platform_driver xilinx_vdma_driver = {
3196         .driver = {
3197                 .name = "xilinx-vdma",
3198                 .of_match_table = xilinx_dma_of_ids,
3199         },
3200         .probe = xilinx_dma_probe,
3201         .remove = xilinx_dma_remove,
3202 };
3203
3204 module_platform_driver(xilinx_vdma_driver);
3205
3206 MODULE_AUTHOR("Xilinx, Inc.");
3207 MODULE_DESCRIPTION("Xilinx VDMA driver");
3208 MODULE_LICENSE("GPL v2");