drivers/dma/ti/k3-psil-j721e.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
   4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  */
   6
   7 #include <linux/kernel.h>
   8
   9 #include "k3-psil-priv.h"
  10
  11 #define PSIL_PDMA_XY_TR(x)                              \
  12         {                                               \
  13                 .thread_id = x,                         \
  14                 .ep_config = {                          \
  15                         .ep_type = PSIL_EP_PDMA_XY,     \
  16                 },                                      \
  17         }
  18
  19 #define PSIL_PDMA_XY_PKT(x)                             \
  20         {                                               \
  21                 .thread_id = x,                         \
  22                 .ep_config = {                          \
  23                         .ep_type = PSIL_EP_PDMA_XY,     \
  24                         .pkt_mode = 1,                  \
  25                 },                                      \
  26         }
  27
  28 #define PSIL_PDMA_MCASP(x)                              \
  29         {                                               \
  30                 .thread_id = x,                         \
  31                 .ep_config = {                          \
  32                         .ep_type = PSIL_EP_PDMA_XY,     \
  33                         .pdma_acc32 = 1,                \
  34                         .pdma_burst = 1,                \
  35                 },                                      \
  36         }
  37
  38 #define PSIL_ETHERNET(x)                                \
  39         {                                               \
  40                 .thread_id = x,                         \
  41                 .ep_config = {                          \
  42                         .ep_type = PSIL_EP_NATIVE,      \
  43                         .pkt_mode = 1,                  \
  44                         .needs_epib = 1,                \
  45                         .psd_size = 16,                 \
  46                 },                                      \
  47         }
  48
  49 #define PSIL_SA2UL(x, tx)                               \
  50         {                                               \
  51                 .thread_id = x,                         \
  52                 .ep_config = {                          \
  53                         .ep_type = PSIL_EP_NATIVE,      \
  54                         .pkt_mode = 1,                  \
  55                         .needs_epib = 1,                \
  56                         .psd_size = 64,                 \
  57                         .notdpkt = tx,                  \
  58                 },                                      \
  59         }
  60
  61 #define PSIL_CSI2RX(x)                                  \
  62         {                                               \
  63                 .thread_id = x,                         \
  64                 .ep_config = {                          \
  65                         .ep_type = PSIL_EP_NATIVE,      \
  66                 },                                      \
  67         }
  68
  69 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
  70 static struct psil_ep j721e_src_ep_map[] = {
  71         /* SA2UL */
  72         PSIL_SA2UL(0x4000, 0),
  73         PSIL_SA2UL(0x4001, 0),
  74         PSIL_SA2UL(0x4002, 0),
  75         PSIL_SA2UL(0x4003, 0),
  76         /* PRU_ICSSG0 */
  77         PSIL_ETHERNET(0x4100),
  78         PSIL_ETHERNET(0x4101),
  79         PSIL_ETHERNET(0x4102),
  80         PSIL_ETHERNET(0x4103),
  81         /* PRU_ICSSG1 */
  82         PSIL_ETHERNET(0x4200),
  83         PSIL_ETHERNET(0x4201),
  84         PSIL_ETHERNET(0x4202),
  85         PSIL_ETHERNET(0x4203),
  86         /* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
  87         PSIL_PDMA_MCASP(0x4400),
  88         PSIL_PDMA_MCASP(0x4401),
  89         PSIL_PDMA_MCASP(0x4402),
  90         /* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
  91         PSIL_PDMA_MCASP(0x4500),
  92         PSIL_PDMA_MCASP(0x4501),
  93         PSIL_PDMA_MCASP(0x4502),
  94         PSIL_PDMA_MCASP(0x4503),
  95         PSIL_PDMA_MCASP(0x4504),
  96         PSIL_PDMA_MCASP(0x4505),
  97         PSIL_PDMA_MCASP(0x4506),
  98         PSIL_PDMA_MCASP(0x4507),
  99         PSIL_PDMA_MCASP(0x4508),
 100         /* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
 101         PSIL_PDMA_XY_PKT(0x4600),
 102         PSIL_PDMA_XY_PKT(0x4601),
 103         PSIL_PDMA_XY_PKT(0x4602),
 104         PSIL_PDMA_XY_PKT(0x4603),
 105         PSIL_PDMA_XY_PKT(0x4604),
 106         PSIL_PDMA_XY_PKT(0x4605),
 107         PSIL_PDMA_XY_PKT(0x4606),
 108         PSIL_PDMA_XY_PKT(0x4607),
 109         /* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
 110         PSIL_PDMA_XY_PKT(0x460c),
 111         PSIL_PDMA_XY_PKT(0x460d),
 112         PSIL_PDMA_XY_PKT(0x460e),
 113         PSIL_PDMA_XY_PKT(0x460f),
 114         PSIL_PDMA_XY_PKT(0x4610),
 115         PSIL_PDMA_XY_PKT(0x4611),
 116         PSIL_PDMA_XY_PKT(0x4612),
 117         PSIL_PDMA_XY_PKT(0x4613),
 118         /* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
 119         PSIL_PDMA_XY_PKT(0x4618),
 120         PSIL_PDMA_XY_PKT(0x4619),
 121         PSIL_PDMA_XY_PKT(0x461a),
 122         PSIL_PDMA_XY_PKT(0x461b),
 123         PSIL_PDMA_XY_PKT(0x461c),
 124         PSIL_PDMA_XY_PKT(0x461d),
 125         PSIL_PDMA_XY_PKT(0x461e),
 126         PSIL_PDMA_XY_PKT(0x461f),
 127         /* PDMA11 (PDMA_MISC_G3) */
 128         PSIL_PDMA_XY_PKT(0x4624),
 129         PSIL_PDMA_XY_PKT(0x4625),
 130         PSIL_PDMA_XY_PKT(0x4626),
 131         PSIL_PDMA_XY_PKT(0x4627),
 132         PSIL_PDMA_XY_PKT(0x4628),
 133         PSIL_PDMA_XY_PKT(0x4629),
 134         PSIL_PDMA_XY_PKT(0x4630),
 135         PSIL_PDMA_XY_PKT(0x463a),
 136         /* PDMA13 (PDMA_USART_G0) - UART0-1 */
 137         PSIL_PDMA_XY_PKT(0x4700),
 138         PSIL_PDMA_XY_PKT(0x4701),
 139         /* PDMA14 (PDMA_USART_G1) - UART2-3 */
 140         PSIL_PDMA_XY_PKT(0x4702),
 141         PSIL_PDMA_XY_PKT(0x4703),
 142         /* PDMA15 (PDMA_USART_G2) - UART4-9 */
 143         PSIL_PDMA_XY_PKT(0x4704),
 144         PSIL_PDMA_XY_PKT(0x4705),
 145         PSIL_PDMA_XY_PKT(0x4706),
 146         PSIL_PDMA_XY_PKT(0x4707),
 147         PSIL_PDMA_XY_PKT(0x4708),
 148         PSIL_PDMA_XY_PKT(0x4709),
 149         /* CSI2RX */
 150         PSIL_CSI2RX(0x4940),
 151         PSIL_CSI2RX(0x4941),
 152         PSIL_CSI2RX(0x4942),
 153         PSIL_CSI2RX(0x4943),
 154         PSIL_CSI2RX(0x4944),
 155         PSIL_CSI2RX(0x4945),
 156         PSIL_CSI2RX(0x4946),
 157         PSIL_CSI2RX(0x4947),
 158         PSIL_CSI2RX(0x4948),
 159         PSIL_CSI2RX(0x4949),
 160         PSIL_CSI2RX(0x494a),
 161         PSIL_CSI2RX(0x494b),
 162         PSIL_CSI2RX(0x494c),
 163         PSIL_CSI2RX(0x494d),
 164         PSIL_CSI2RX(0x494e),
 165         PSIL_CSI2RX(0x494f),
 166         PSIL_CSI2RX(0x4950),
 167         PSIL_CSI2RX(0x4951),
 168         PSIL_CSI2RX(0x4952),
 169         PSIL_CSI2RX(0x4953),
 170         PSIL_CSI2RX(0x4954),
 171         PSIL_CSI2RX(0x4955),
 172         PSIL_CSI2RX(0x4956),
 173         PSIL_CSI2RX(0x4957),
 174         PSIL_CSI2RX(0x4958),
 175         PSIL_CSI2RX(0x4959),
 176         PSIL_CSI2RX(0x495a),
 177         PSIL_CSI2RX(0x495b),
 178         PSIL_CSI2RX(0x495c),
 179         PSIL_CSI2RX(0x495d),
 180         PSIL_CSI2RX(0x495e),
 181         PSIL_CSI2RX(0x495f),
 182         PSIL_CSI2RX(0x4960),
 183         PSIL_CSI2RX(0x4961),
 184         PSIL_CSI2RX(0x4962),
 185         PSIL_CSI2RX(0x4963),
 186         PSIL_CSI2RX(0x4964),
 187         PSIL_CSI2RX(0x4965),
 188         PSIL_CSI2RX(0x4966),
 189         PSIL_CSI2RX(0x4967),
 190         PSIL_CSI2RX(0x4968),
 191         PSIL_CSI2RX(0x4969),
 192         PSIL_CSI2RX(0x496a),
 193         PSIL_CSI2RX(0x496b),
 194         PSIL_CSI2RX(0x496c),
 195         PSIL_CSI2RX(0x496d),
 196         PSIL_CSI2RX(0x496e),
 197         PSIL_CSI2RX(0x496f),
 198         PSIL_CSI2RX(0x4970),
 199         PSIL_CSI2RX(0x4971),
 200         PSIL_CSI2RX(0x4972),
 201         PSIL_CSI2RX(0x4973),
 202         PSIL_CSI2RX(0x4974),
 203         PSIL_CSI2RX(0x4975),
 204         PSIL_CSI2RX(0x4976),
 205         PSIL_CSI2RX(0x4977),
 206         PSIL_CSI2RX(0x4978),
 207         PSIL_CSI2RX(0x4979),
 208         PSIL_CSI2RX(0x497a),
 209         PSIL_CSI2RX(0x497b),
 210         PSIL_CSI2RX(0x497c),
 211         PSIL_CSI2RX(0x497d),
 212         PSIL_CSI2RX(0x497e),
 213         PSIL_CSI2RX(0x497f),
 214         /* CPSW9 */
 215         PSIL_ETHERNET(0x4a00),
 216         /* CPSW0 */
 217         PSIL_ETHERNET(0x7000),
 218         /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
 219         PSIL_PDMA_XY_PKT(0x7100),
 220         PSIL_PDMA_XY_PKT(0x7101),
 221         PSIL_PDMA_XY_PKT(0x7102),
 222         PSIL_PDMA_XY_PKT(0x7103),
 223         /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
 224         PSIL_PDMA_XY_PKT(0x7200),
 225         PSIL_PDMA_XY_PKT(0x7201),
 226         PSIL_PDMA_XY_PKT(0x7202),
 227         PSIL_PDMA_XY_PKT(0x7203),
 228         PSIL_PDMA_XY_PKT(0x7204),
 229         PSIL_PDMA_XY_PKT(0x7205),
 230         PSIL_PDMA_XY_PKT(0x7206),
 231         PSIL_PDMA_XY_PKT(0x7207),
 232         /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
 233         PSIL_PDMA_XY_PKT(0x7300),
 234         /* MCU_PDMA_ADC - ADC0-1 */
 235         PSIL_PDMA_XY_TR(0x7400),
 236         PSIL_PDMA_XY_TR(0x7401),
 237         PSIL_PDMA_XY_TR(0x7402),
 238         PSIL_PDMA_XY_TR(0x7403),
 239         /* SA2UL */
 240         PSIL_SA2UL(0x7500, 0),
 241         PSIL_SA2UL(0x7501, 0),
 242         PSIL_SA2UL(0x7502, 0),
 243         PSIL_SA2UL(0x7503, 0),
 244 };
 245
 246 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
 247 static struct psil_ep j721e_dst_ep_map[] = {
 248         /* SA2UL */
 249         PSIL_SA2UL(0xc000, 1),
 250         PSIL_SA2UL(0xc001, 1),
 251         /* PRU_ICSSG0 */
 252         PSIL_ETHERNET(0xc100),
 253         PSIL_ETHERNET(0xc101),
 254         PSIL_ETHERNET(0xc102),
 255         PSIL_ETHERNET(0xc103),
 256         PSIL_ETHERNET(0xc104),
 257         PSIL_ETHERNET(0xc105),
 258         PSIL_ETHERNET(0xc106),
 259         PSIL_ETHERNET(0xc107),
 260         /* PRU_ICSSG1 */
 261         PSIL_ETHERNET(0xc200),
 262         PSIL_ETHERNET(0xc201),
 263         PSIL_ETHERNET(0xc202),
 264         PSIL_ETHERNET(0xc203),
 265         PSIL_ETHERNET(0xc204),
 266         PSIL_ETHERNET(0xc205),
 267         PSIL_ETHERNET(0xc206),
 268         PSIL_ETHERNET(0xc207),
 269         /* CPSW9 */
 270         PSIL_ETHERNET(0xca00),
 271         PSIL_ETHERNET(0xca01),
 272         PSIL_ETHERNET(0xca02),
 273         PSIL_ETHERNET(0xca03),
 274         PSIL_ETHERNET(0xca04),
 275         PSIL_ETHERNET(0xca05),
 276         PSIL_ETHERNET(0xca06),
 277         PSIL_ETHERNET(0xca07),
 278         /* CPSW0 */
 279         PSIL_ETHERNET(0xf000),
 280         PSIL_ETHERNET(0xf001),
 281         PSIL_ETHERNET(0xf002),
 282         PSIL_ETHERNET(0xf003),
 283         PSIL_ETHERNET(0xf004),
 284         PSIL_ETHERNET(0xf005),
 285         PSIL_ETHERNET(0xf006),
 286         PSIL_ETHERNET(0xf007),
 287         /* SA2UL */
 288         PSIL_SA2UL(0xf500, 1),
 289         PSIL_SA2UL(0xf501, 1),
 290 };
 291
 292 struct psil_ep_map j721e_ep_map = {
 293         .name = "j721e",
 294         .src = j721e_src_ep_map,
 295         .src_count = ARRAY_SIZE(j721e_src_ep_map),
 296         .dst = j721e_dst_ep_map,
 297         .dst_count = ARRAY_SIZE(j721e_dst_ep_map),
 298 };