1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5 * Synopsys DesignWare AXI DMA Controller driver.
7 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
10 #ifndef _AXI_DMA_PLATFORM_H
11 #define _AXI_DMA_PLATFORM_H
13 #include <linux/bitops.h>
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/dmaengine.h>
17 #include <linux/types.h>
19 #include "../virt-dma.h"
21 #define DMAC_MAX_CHANNELS 8
22 #define DMAC_MAX_MASTERS 2
23 #define DMAC_MAX_BLK_SIZE 0x200000
25 struct dw_axi_dma_hcfg {
29 u32 block_size[DMAC_MAX_CHANNELS];
30 u32 priority[DMAC_MAX_CHANNELS];
31 /* maximum supported axi burst length */
33 bool restrict_axi_burst_len;
37 struct axi_dma_chip *chip;
38 void __iomem *chan_regs;
41 atomic_t descs_allocated;
43 struct dma_pool *desc_pool;
44 struct virt_dma_chan vc;
46 struct axi_dma_desc *desc;
47 struct dma_slave_config config;
48 enum dma_transfer_direction direction;
50 /* these other elements are all protected by vc.lock */
55 struct dma_device dma;
56 struct dw_axi_dma_hcfg *hdata;
57 struct device_dma_parameters dma_parms;
60 struct axi_dma_chan *chan;
67 void __iomem *apb_regs;
70 struct dw_axi_dma *dw;
73 /* LLI == Linked List Item */
74 struct __packed axi_dma_lli {
90 struct axi_dma_hw_desc {
91 struct axi_dma_lli *lli;
97 struct axi_dma_hw_desc *hw_desc;
99 struct virt_dma_desc vd;
100 struct axi_dma_chan *chan;
101 u32 completed_blocks;
106 static inline struct device *dchan2dev(struct dma_chan *dchan)
108 return &dchan->dev->device;
111 static inline struct device *chan2dev(struct axi_dma_chan *chan)
113 return &chan->vc.chan.dev->device;
116 static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
118 return container_of(vd, struct axi_dma_desc, vd);
121 static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
123 return container_of(vc, struct axi_dma_chan, vc);
126 static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
128 return vc_to_axi_dma_chan(to_virt_chan(dchan));
132 #define COMMON_REG_LEN 0x100
133 #define CHAN_REG_LEN 0x100
135 /* Common registers offset */
136 #define DMAC_ID 0x000 /* R DMAC ID */
137 #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
138 #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
139 #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
140 #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
141 #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
142 #define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
143 #define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
144 #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
145 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
146 #define DMAC_COMMON_INTSTATUS 0x050 /* R DMAC Interrupt Status */
147 #define DMAC_RESET 0x058 /* R DMAC Reset Register1 */
149 /* DMA channel registers offset */
150 #define CH_SAR 0x000 /* R/W Chan Source Address */
151 #define CH_DAR 0x008 /* R/W Chan Destination Address */
152 #define CH_BLOCK_TS 0x010 /* R/W Chan Block Transfer Size */
153 #define CH_CTL 0x018 /* R/W Chan Control */
154 #define CH_CTL_L 0x018 /* R/W Chan Control 00-31 */
155 #define CH_CTL_H 0x01C /* R/W Chan Control 32-63 */
156 #define CH_CFG 0x020 /* R/W Chan Configuration */
157 #define CH_CFG_L 0x020 /* R/W Chan Configuration 00-31 */
158 #define CH_CFG_H 0x024 /* R/W Chan Configuration 32-63 */
159 #define CH_LLP 0x028 /* R/W Chan Linked List Pointer */
160 #define CH_STATUS 0x030 /* R Chan Status */
161 #define CH_SWHSSRC 0x038 /* R/W Chan SW Handshake Source */
162 #define CH_SWHSDST 0x040 /* R/W Chan SW Handshake Destination */
163 #define CH_BLK_TFR_RESUMEREQ 0x048 /* W Chan Block Transfer Resume Req */
164 #define CH_AXI_ID 0x050 /* R/W Chan AXI ID */
165 #define CH_AXI_QOS 0x058 /* R/W Chan AXI QOS */
166 #define CH_SSTAT 0x060 /* R Chan Source Status */
167 #define CH_DSTAT 0x068 /* R Chan Destination Status */
168 #define CH_SSTATAR 0x070 /* R/W Chan Source Status Fetch Addr */
169 #define CH_DSTATAR 0x078 /* R/W Chan Destination Status Fetch Addr */
170 #define CH_INTSTATUS_ENA 0x080 /* R/W Chan Interrupt Status Enable */
171 #define CH_INTSTATUS 0x088 /* R/W Chan Interrupt Status */
172 #define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
173 #define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
175 /* These Apb registers are used by Intel KeemBay SoC */
176 #define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
177 #define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
178 #define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
179 #define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
180 #define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
181 #define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
182 #define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
183 #define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
184 #define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
186 #define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
187 #define DMA_APB_HS_SEL_BIT_SIZE 0x08 /* HW handshake bits per channel */
188 #define DMA_APB_HS_SEL_MASK 0xFF /* HW handshake select masks */
189 #define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
192 #define DMAC_EN_POS 0
193 #define DMAC_EN_MASK BIT(DMAC_EN_POS)
196 #define INT_EN_MASK BIT(INT_EN_POS)
198 #define DMAC_CHAN_EN_SHIFT 0
199 #define DMAC_CHAN_EN_WE_SHIFT 8
201 #define DMAC_CHAN_SUSP_SHIFT 16
202 #define DMAC_CHAN_SUSP_WE_SHIFT 24
205 #define CH_CTL_H_ARLEN_EN BIT(6)
206 #define CH_CTL_H_ARLEN_POS 7
207 #define CH_CTL_H_AWLEN_EN BIT(15)
208 #define CH_CTL_H_AWLEN_POS 16
211 DWAXIDMAC_ARWLEN_1 = 0,
212 DWAXIDMAC_ARWLEN_2 = 1,
213 DWAXIDMAC_ARWLEN_4 = 3,
214 DWAXIDMAC_ARWLEN_8 = 7,
215 DWAXIDMAC_ARWLEN_16 = 15,
216 DWAXIDMAC_ARWLEN_32 = 31,
217 DWAXIDMAC_ARWLEN_64 = 63,
218 DWAXIDMAC_ARWLEN_128 = 127,
219 DWAXIDMAC_ARWLEN_256 = 255,
220 DWAXIDMAC_ARWLEN_MIN = DWAXIDMAC_ARWLEN_1,
221 DWAXIDMAC_ARWLEN_MAX = DWAXIDMAC_ARWLEN_256
224 #define CH_CTL_H_LLI_LAST BIT(30)
225 #define CH_CTL_H_LLI_VALID BIT(31)
228 #define CH_CTL_L_LAST_WRITE_EN BIT(30)
230 #define CH_CTL_L_DST_MSIZE_POS 18
231 #define CH_CTL_L_SRC_MSIZE_POS 14
234 DWAXIDMAC_BURST_TRANS_LEN_1 = 0,
235 DWAXIDMAC_BURST_TRANS_LEN_4,
236 DWAXIDMAC_BURST_TRANS_LEN_8,
237 DWAXIDMAC_BURST_TRANS_LEN_16,
238 DWAXIDMAC_BURST_TRANS_LEN_32,
239 DWAXIDMAC_BURST_TRANS_LEN_64,
240 DWAXIDMAC_BURST_TRANS_LEN_128,
241 DWAXIDMAC_BURST_TRANS_LEN_256,
242 DWAXIDMAC_BURST_TRANS_LEN_512,
243 DWAXIDMAC_BURST_TRANS_LEN_1024
246 #define CH_CTL_L_DST_WIDTH_POS 11
247 #define CH_CTL_L_SRC_WIDTH_POS 8
249 #define CH_CTL_L_DST_INC_POS 6
250 #define CH_CTL_L_SRC_INC_POS 4
252 DWAXIDMAC_CH_CTL_L_INC = 0,
253 DWAXIDMAC_CH_CTL_L_NOINC
256 #define CH_CTL_L_DST_MAST BIT(2)
257 #define CH_CTL_L_SRC_MAST BIT(0)
260 #define CH_CFG_H_PRIORITY_POS 17
261 #define CH_CFG_H_DST_PER_POS 12
262 #define CH_CFG_H_SRC_PER_POS 7
263 #define CH_CFG_H_HS_SEL_DST_POS 4
264 #define CH_CFG_H_HS_SEL_SRC_POS 3
266 DWAXIDMAC_HS_SEL_HW = 0,
270 #define CH_CFG_H_TT_FC_POS 0
272 DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0,
273 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
274 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
275 DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
276 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
277 DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
278 DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
279 DWAXIDMAC_TT_FC_PER_TO_PER_DST
283 #define CH_CFG_L_DST_MULTBLK_TYPE_POS 2
284 #define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0
286 DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0,
287 DWAXIDMAC_MBLK_TYPE_RELOAD,
288 DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
289 DWAXIDMAC_MBLK_TYPE_LL
293 * DW AXI DMA channel interrupts
295 * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
296 * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
297 * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
298 * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
299 * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
300 * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
301 * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
302 * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
303 * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
304 * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
305 * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
306 * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
307 * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
308 * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
309 * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
310 * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
311 * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
312 * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
313 * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
314 * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
315 * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
316 * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
317 * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
318 * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
319 * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
320 * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
321 * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
322 * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
325 DWAXIDMAC_IRQ_NONE = 0,
326 DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0),
327 DWAXIDMAC_IRQ_DMA_TRF = BIT(1),
328 DWAXIDMAC_IRQ_SRC_TRAN = BIT(3),
329 DWAXIDMAC_IRQ_DST_TRAN = BIT(4),
330 DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5),
331 DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6),
332 DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7),
333 DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8),
334 DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9),
335 DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10),
336 DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11),
337 DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12),
338 DWAXIDMAC_IRQ_INVALID_ERR = BIT(13),
339 DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14),
340 DWAXIDMAC_IRQ_DEC_ERR = BIT(16),
341 DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17),
342 DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18),
343 DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19),
344 DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20),
345 DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21),
346 DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27),
347 DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28),
348 DWAXIDMAC_IRQ_SUSPENDED = BIT(29),
349 DWAXIDMAC_IRQ_DISABLED = BIT(30),
350 DWAXIDMAC_IRQ_ABORTED = BIT(31),
351 DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) | GENMASK(14, 5)),
352 DWAXIDMAC_IRQ_ALL = GENMASK(31, 0)
356 DWAXIDMAC_TRANS_WIDTH_8 = 0,
357 DWAXIDMAC_TRANS_WIDTH_16,
358 DWAXIDMAC_TRANS_WIDTH_32,
359 DWAXIDMAC_TRANS_WIDTH_64,
360 DWAXIDMAC_TRANS_WIDTH_128,
361 DWAXIDMAC_TRANS_WIDTH_256,
362 DWAXIDMAC_TRANS_WIDTH_512,
363 DWAXIDMAC_TRANS_WIDTH_MAX = DWAXIDMAC_TRANS_WIDTH_512
366 #endif /* _AXI_DMA_PLATFORM_H */