drivers/clk/ux500/u8500_of_clk.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Clock definitions for u8500 platform.
   4  *
   5  * Copyright (C) 2012 ST-Ericsson SA
   6  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   7  */
   8
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/mfd/dbx500-prcmu.h>
  13 #include "clk.h"
  14
  15 #define PRCC_NUM_PERIPH_CLUSTERS 6
  16 #define PRCC_PERIPHS_PER_CLUSTER 32
  17
  18 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
  19 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  20 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  21
  22 #define PRCC_SHOW(clk, base, bit) \
  23         clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
  24 #define PRCC_PCLK_STORE(clk, base, bit) \
  25         prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  26 #define PRCC_KCLK_STORE(clk, base, bit)        \
  27         prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  28
  29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
  30                                      void *data)
  31 {
  32         struct clk **clk_data = data;
  33         unsigned int base, bit;
  34
  35         if (clkspec->args_count != 2)
  36                 return  ERR_PTR(-EINVAL);
  37
  38         base = clkspec->args[0];
  39         bit = clkspec->args[1];
  40
  41         if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
  42                 pr_err("%s: invalid PRCC base %d\n", __func__, base);
  43                 return ERR_PTR(-EINVAL);
  44         }
  45
  46         return PRCC_SHOW(clk_data, base, bit);
  47 }
  48
  49 /* CLKRST4 is missing making it hard to index things */
  50 enum clkrst_index {
  51         CLKRST1_INDEX = 0,
  52         CLKRST2_INDEX,
  53         CLKRST3_INDEX,
  54         CLKRST5_INDEX,
  55         CLKRST6_INDEX,
  56         CLKRST_MAX,
  57 };
  58
  59 static void u8500_clk_init(struct device_node *np)
  60 {
  61         struct prcmu_fw_version *fw_version;
  62         struct device_node *child = NULL;
  63         const char *sgaclk_parent = NULL;
  64         struct clk *clk, *rtc_clk, *twd_clk;
  65         u32 bases[CLKRST_MAX];
  66         int i;
  67
  68         for (i = 0; i < ARRAY_SIZE(bases); i++) {
  69                 struct resource r;
  70
  71                 if (of_address_to_resource(np, i, &r))
  72                         /* Not much choice but to continue */
  73                         pr_err("failed to get CLKRST %d base address\n",
  74                                i + 1);
  75                 bases[i] = r.start;
  76         }
  77
  78         /* Clock sources */
  79         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  80                                 CLK_IGNORE_UNUSED);
  81         prcmu_clk[PRCMU_PLLSOC0] = clk;
  82
  83         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  84                                 CLK_IGNORE_UNUSED);
  85         prcmu_clk[PRCMU_PLLSOC1] = clk;
  86
  87         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  88                                 CLK_IGNORE_UNUSED);
  89         prcmu_clk[PRCMU_PLLDDR] = clk;
  90
  91         /* FIXME: Add sys, ulp and int clocks here. */
  92
  93         rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
  94                                 CLK_IGNORE_UNUSED,
  95                                 32768);
  96
  97         /* PRCMU clocks */
  98         fw_version = prcmu_get_fw_version();
  99         if (fw_version != NULL) {
 100                 switch (fw_version->project) {
 101                 case PRCMU_FW_PROJECT_U8500_C2:
 102                 case PRCMU_FW_PROJECT_U8500_SSG1:
 103                 case PRCMU_FW_PROJECT_U8520:
 104                 case PRCMU_FW_PROJECT_U8420:
 105                 case PRCMU_FW_PROJECT_U8420_SYSCLK:
 106                 case PRCMU_FW_PROJECT_U8500_SSG2:
 107                         sgaclk_parent = "soc0_pll";
 108                         break;
 109                 default:
 110                         break;
 111                 }
 112         }
 113
 114         if (sgaclk_parent)
 115                 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
 116                                         PRCMU_SGACLK, 0);
 117         else
 118                 clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
 119         prcmu_clk[PRCMU_SGACLK] = clk;
 120
 121         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
 122         prcmu_clk[PRCMU_UARTCLK] = clk;
 123
 124         clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
 125         prcmu_clk[PRCMU_MSP02CLK] = clk;
 126
 127         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
 128         prcmu_clk[PRCMU_MSP1CLK] = clk;
 129
 130         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
 131         prcmu_clk[PRCMU_I2CCLK] = clk;
 132
 133         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
 134         prcmu_clk[PRCMU_SLIMCLK] = clk;
 135
 136         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
 137         prcmu_clk[PRCMU_PER1CLK] = clk;
 138
 139         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
 140         prcmu_clk[PRCMU_PER2CLK] = clk;
 141
 142         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
 143         prcmu_clk[PRCMU_PER3CLK] = clk;
 144
 145         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
 146         prcmu_clk[PRCMU_PER5CLK] = clk;
 147
 148         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
 149         prcmu_clk[PRCMU_PER6CLK] = clk;
 150
 151         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
 152         prcmu_clk[PRCMU_PER7CLK] = clk;
 153
 154         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 155                                 CLK_SET_RATE_GATE);
 156         prcmu_clk[PRCMU_LCDCLK] = clk;
 157
 158         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
 159         prcmu_clk[PRCMU_BMLCLK] = clk;
 160
 161         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 162                                 CLK_SET_RATE_GATE);
 163         prcmu_clk[PRCMU_HSITXCLK] = clk;
 164
 165         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 166                                 CLK_SET_RATE_GATE);
 167         prcmu_clk[PRCMU_HSIRXCLK] = clk;
 168
 169         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 170                                 CLK_SET_RATE_GATE);
 171         prcmu_clk[PRCMU_HDMICLK] = clk;
 172
 173         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
 174         prcmu_clk[PRCMU_APEATCLK] = clk;
 175
 176         clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
 177                                 CLK_SET_RATE_GATE);
 178         prcmu_clk[PRCMU_APETRACECLK] = clk;
 179
 180         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
 181         prcmu_clk[PRCMU_MCDECLK] = clk;
 182
 183         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
 184         prcmu_clk[PRCMU_IPI2CCLK] = clk;
 185
 186         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
 187         prcmu_clk[PRCMU_DSIALTCLK] = clk;
 188
 189         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
 190         prcmu_clk[PRCMU_DMACLK] = clk;
 191
 192         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
 193         prcmu_clk[PRCMU_B2R2CLK] = clk;
 194
 195         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 196                                 CLK_SET_RATE_GATE);
 197         prcmu_clk[PRCMU_TVCLK] = clk;
 198
 199         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
 200         prcmu_clk[PRCMU_SSPCLK] = clk;
 201
 202         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
 203         prcmu_clk[PRCMU_RNGCLK] = clk;
 204
 205         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
 206         prcmu_clk[PRCMU_UICCCLK] = clk;
 207
 208         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
 209         prcmu_clk[PRCMU_TIMCLK] = clk;
 210
 211         clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
 212         prcmu_clk[PRCMU_SYSCLK] = clk;
 213
 214         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 215                                         100000000, CLK_SET_RATE_GATE);
 216         prcmu_clk[PRCMU_SDMMCCLK] = clk;
 217
 218         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 219                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 220         prcmu_clk[PRCMU_PLLDSI] = clk;
 221
 222         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 223                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 224         prcmu_clk[PRCMU_DSI0CLK] = clk;
 225
 226         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 227                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 228         prcmu_clk[PRCMU_DSI1CLK] = clk;
 229
 230         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 231                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 232         prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
 233
 234         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 235                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 236         prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
 237
 238         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 239                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 240         prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
 241
 242         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 243                                 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
 244         prcmu_clk[PRCMU_ARMSS] = clk;
 245
 246         twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 247                                 CLK_IGNORE_UNUSED, 1, 2);
 248
 249         /*
 250          * FIXME: Add special handled PRCMU clocks here:
 251          * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 252          * 2. ab9540_clkout1yuv, see clkout0yuv
 253          */
 254
 255         /* PRCC P-clocks */
 256         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
 257                                 BIT(0), 0);
 258         PRCC_PCLK_STORE(clk, 1, 0);
 259
 260         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
 261                                 BIT(1), 0);
 262         PRCC_PCLK_STORE(clk, 1, 1);
 263
 264         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
 265                                 BIT(2), 0);
 266         PRCC_PCLK_STORE(clk, 1, 2);
 267
 268         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
 269                                 BIT(3), 0);
 270         PRCC_PCLK_STORE(clk, 1, 3);
 271
 272         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
 273                                 BIT(4), 0);
 274         PRCC_PCLK_STORE(clk, 1, 4);
 275
 276         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
 277                                 BIT(5), 0);
 278         PRCC_PCLK_STORE(clk, 1, 5);
 279
 280         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
 281                                 BIT(6), 0);
 282         PRCC_PCLK_STORE(clk, 1, 6);
 283
 284         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
 285                                 BIT(7), 0);
 286         PRCC_PCLK_STORE(clk, 1, 7);
 287
 288         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
 289                                 BIT(8), 0);
 290         PRCC_PCLK_STORE(clk, 1, 8);
 291
 292         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
 293                                 BIT(9), 0);
 294         PRCC_PCLK_STORE(clk, 1, 9);
 295
 296         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
 297                                 BIT(10), 0);
 298         PRCC_PCLK_STORE(clk, 1, 10);
 299
 300         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
 301                                 BIT(11), 0);
 302         PRCC_PCLK_STORE(clk, 1, 11);
 303
 304         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
 305                                 BIT(0), 0);
 306         PRCC_PCLK_STORE(clk, 2, 0);
 307
 308         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
 309                                 BIT(1), 0);
 310         PRCC_PCLK_STORE(clk, 2, 1);
 311
 312         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
 313                                 BIT(2), 0);
 314         PRCC_PCLK_STORE(clk, 2, 2);
 315
 316         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
 317                                 BIT(3), 0);
 318         PRCC_PCLK_STORE(clk, 2, 3);
 319
 320         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
 321                                 BIT(4), 0);
 322         PRCC_PCLK_STORE(clk, 2, 4);
 323
 324         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
 325                                 BIT(5), 0);
 326         PRCC_PCLK_STORE(clk, 2, 5);
 327
 328         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
 329                                 BIT(6), 0);
 330         PRCC_PCLK_STORE(clk, 2, 6);
 331
 332         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
 333                                 BIT(7), 0);
 334         PRCC_PCLK_STORE(clk, 2, 7);
 335
 336         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
 337                                 BIT(8), 0);
 338         PRCC_PCLK_STORE(clk, 2, 8);
 339
 340         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
 341                                 BIT(9), 0);
 342         PRCC_PCLK_STORE(clk, 2, 9);
 343
 344         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
 345                                 BIT(10), 0);
 346         PRCC_PCLK_STORE(clk, 2, 10);
 347
 348         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
 349                                 BIT(11), 0);
 350         PRCC_PCLK_STORE(clk, 2, 11);
 351
 352         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
 353                                 BIT(12), 0);
 354         PRCC_PCLK_STORE(clk, 2, 12);
 355
 356         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
 357                                 BIT(0), 0);
 358         PRCC_PCLK_STORE(clk, 3, 0);
 359
 360         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
 361                                 BIT(1), 0);
 362         PRCC_PCLK_STORE(clk, 3, 1);
 363
 364         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
 365                                 BIT(2), 0);
 366         PRCC_PCLK_STORE(clk, 3, 2);
 367
 368         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
 369                                 BIT(3), 0);
 370         PRCC_PCLK_STORE(clk, 3, 3);
 371
 372         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
 373                                 BIT(4), 0);
 374         PRCC_PCLK_STORE(clk, 3, 4);
 375
 376         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
 377                                 BIT(5), 0);
 378         PRCC_PCLK_STORE(clk, 3, 5);
 379
 380         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
 381                                 BIT(6), 0);
 382         PRCC_PCLK_STORE(clk, 3, 6);
 383
 384         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
 385                                 BIT(7), 0);
 386         PRCC_PCLK_STORE(clk, 3, 7);
 387
 388         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
 389                                 BIT(8), 0);
 390         PRCC_PCLK_STORE(clk, 3, 8);
 391
 392         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
 393                                 BIT(0), 0);
 394         PRCC_PCLK_STORE(clk, 5, 0);
 395
 396         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
 397                                 BIT(1), 0);
 398         PRCC_PCLK_STORE(clk, 5, 1);
 399
 400         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
 401                                 BIT(0), 0);
 402         PRCC_PCLK_STORE(clk, 6, 0);
 403
 404         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
 405                                 BIT(1), 0);
 406         PRCC_PCLK_STORE(clk, 6, 1);
 407
 408         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
 409                                 BIT(2), 0);
 410         PRCC_PCLK_STORE(clk, 6, 2);
 411
 412         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
 413                                 BIT(3), 0);
 414         PRCC_PCLK_STORE(clk, 6, 3);
 415
 416         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
 417                                 BIT(4), 0);
 418         PRCC_PCLK_STORE(clk, 6, 4);
 419
 420         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
 421                                 BIT(5), 0);
 422         PRCC_PCLK_STORE(clk, 6, 5);
 423
 424         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
 425                                 BIT(6), 0);
 426         PRCC_PCLK_STORE(clk, 6, 6);
 427
 428         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
 429                                 BIT(7), 0);
 430         PRCC_PCLK_STORE(clk, 6, 7);
 431
 432         /* PRCC K-clocks
 433          *
 434          * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 435          * by enabling just the K-clock, even if it is not a valid parent to
 436          * the K-clock. Until drivers get fixed we might need some kind of
 437          * "parent muxed join".
 438          */
 439
 440         /* Periph1 */
 441         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 442                         bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
 443         PRCC_KCLK_STORE(clk, 1, 0);
 444
 445         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 446                         bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
 447         PRCC_KCLK_STORE(clk, 1, 1);
 448
 449         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 450                         bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
 451         PRCC_KCLK_STORE(clk, 1, 2);
 452
 453         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 454                         bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
 455         PRCC_KCLK_STORE(clk, 1, 3);
 456
 457         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 458                         bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
 459         PRCC_KCLK_STORE(clk, 1, 4);
 460
 461         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 462                         bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
 463         PRCC_KCLK_STORE(clk, 1, 5);
 464
 465         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 466                         bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
 467         PRCC_KCLK_STORE(clk, 1, 6);
 468
 469         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 470                         bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
 471         PRCC_KCLK_STORE(clk, 1, 8);
 472
 473         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 474                         bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
 475         PRCC_KCLK_STORE(clk, 1, 9);
 476
 477         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 478                         bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
 479         PRCC_KCLK_STORE(clk, 1, 10);
 480
 481         /* Periph2 */
 482         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 483                         bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
 484         PRCC_KCLK_STORE(clk, 2, 0);
 485
 486         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 487                         bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
 488         PRCC_KCLK_STORE(clk, 2, 2);
 489
 490         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 491                         bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
 492         PRCC_KCLK_STORE(clk, 2, 3);
 493
 494         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 495                         bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
 496         PRCC_KCLK_STORE(clk, 2, 4);
 497
 498         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 499                         bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
 500         PRCC_KCLK_STORE(clk, 2, 5);
 501
 502         /* Note that rate is received from parent. */
 503         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 504                         bases[CLKRST2_INDEX], BIT(6),
 505                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 506         PRCC_KCLK_STORE(clk, 2, 6);
 507
 508         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 509                         bases[CLKRST2_INDEX], BIT(7),
 510                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 511         PRCC_KCLK_STORE(clk, 2, 7);
 512
 513         /* Periph3 */
 514         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 515                         bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
 516         PRCC_KCLK_STORE(clk, 3, 1);
 517
 518         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 519                         bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
 520         PRCC_KCLK_STORE(clk, 3, 2);
 521
 522         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 523                         bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
 524         PRCC_KCLK_STORE(clk, 3, 3);
 525
 526         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 527                         bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
 528         PRCC_KCLK_STORE(clk, 3, 4);
 529
 530         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 531                         bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
 532         PRCC_KCLK_STORE(clk, 3, 5);
 533
 534         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 535                         bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
 536         PRCC_KCLK_STORE(clk, 3, 6);
 537
 538         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 539                         bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
 540         PRCC_KCLK_STORE(clk, 3, 7);
 541
 542         /* Periph6 */
 543         clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 544                         bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
 545         PRCC_KCLK_STORE(clk, 6, 0);
 546
 547         for_each_child_of_node(np, child) {
 548                 static struct clk_onecell_data clk_data;
 549
 550                 if (of_node_name_eq(child, "prcmu-clock")) {
 551                         clk_data.clks = prcmu_clk;
 552                         clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
 553                         of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
 554                 }
 555                 if (of_node_name_eq(child, "prcc-periph-clock"))
 556                         of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
 557
 558                 if (of_node_name_eq(child, "prcc-kernel-clock"))
 559                         of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
 560
 561                 if (of_node_name_eq(child, "rtc32k-clock"))
 562                         of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
 563
 564                 if (of_node_name_eq(child, "smp-twd-clock"))
 565                         of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
 566         }
 567 }
 568 CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);