drivers/clk/qcom/clk-smd-rpm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, Linaro Limited
   4  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/soc/qcom/smd-rpm.h>
  18
  19 #include <dt-bindings/clock/qcom,rpmcc.h>
  20 #include <dt-bindings/mfd/qcom-rpm.h>
  21
  22 #define QCOM_RPM_KEY_SOFTWARE_ENABLE                    0x6e657773
  23 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY     0x62636370
  24 #define QCOM_RPM_SMD_KEY_RATE                           0x007a484b
  25 #define QCOM_RPM_SMD_KEY_ENABLE                         0x62616e45
  26 #define QCOM_RPM_SMD_KEY_STATE                          0x54415453
  27 #define QCOM_RPM_SCALING_ENABLE_ID                      0x2
  28
  29 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id,  \
  30                              key)                                             \
  31         static struct clk_smd_rpm _platform##_##_active;                      \
  32         static struct clk_smd_rpm _platform##_##_name = {                     \
  33                 .rpm_res_type = (type),                                       \
  34                 .rpm_clk_id = (r_id),                                         \
  35                 .rpm_status_id = (stat_id),                                   \
  36                 .rpm_key = (key),                                             \
  37                 .peer = &_platform##_##_active,                               \
  38                 .rate = INT_MAX,                                              \
  39                 .hw.init = &(struct clk_init_data){                           \
  40                         .ops = &clk_smd_rpm_ops,                              \
  41                         .name = #_name,                                       \
  42                         .parent_data =  &(const struct clk_parent_data){ \
  43                                         .fw_name = "xo",                \
  44                                         .name = "xo_board",             \
  45                         },                                              \
  46                         .num_parents = 1,                                     \
  47                 },                                                            \
  48         };                                                                    \
  49         static struct clk_smd_rpm _platform##_##_active = {                   \
  50                 .rpm_res_type = (type),                                       \
  51                 .rpm_clk_id = (r_id),                                         \
  52                 .rpm_status_id = (stat_id),                                   \
  53                 .active_only = true,                                          \
  54                 .rpm_key = (key),                                             \
  55                 .peer = &_platform##_##_name,                                 \
  56                 .rate = INT_MAX,                                              \
  57                 .hw.init = &(struct clk_init_data){                           \
  58                         .ops = &clk_smd_rpm_ops,                              \
  59                         .name = #_active,                                     \
  60                         .parent_data =  &(const struct clk_parent_data){ \
  61                                         .fw_name = "xo",                \
  62                                         .name = "xo_board",             \
  63                         },                                              \
  64                         .num_parents = 1,                                     \
  65                 },                                                            \
  66         }
  67
  68 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id,    \
  69                                     stat_id, r, key)                          \
  70         static struct clk_smd_rpm _platform##_##_active;                      \
  71         static struct clk_smd_rpm _platform##_##_name = {                     \
  72                 .rpm_res_type = (type),                                       \
  73                 .rpm_clk_id = (r_id),                                         \
  74                 .rpm_status_id = (stat_id),                                   \
  75                 .rpm_key = (key),                                             \
  76                 .branch = true,                                               \
  77                 .peer = &_platform##_##_active,                               \
  78                 .rate = (r),                                                  \
  79                 .hw.init = &(struct clk_init_data){                           \
  80                         .ops = &clk_smd_rpm_branch_ops,                       \
  81                         .name = #_name,                                       \
  82                         .parent_data =  &(const struct clk_parent_data){ \
  83                                         .fw_name = "xo",                \
  84                                         .name = "xo_board",             \
  85                         },                                              \
  86                         .num_parents = 1,                                     \
  87                 },                                                            \
  88         };                                                                    \
  89         static struct clk_smd_rpm _platform##_##_active = {                   \
  90                 .rpm_res_type = (type),                                       \
  91                 .rpm_clk_id = (r_id),                                         \
  92                 .rpm_status_id = (stat_id),                                   \
  93                 .active_only = true,                                          \
  94                 .rpm_key = (key),                                             \
  95                 .branch = true,                                               \
  96                 .peer = &_platform##_##_name,                                 \
  97                 .rate = (r),                                                  \
  98                 .hw.init = &(struct clk_init_data){                           \
  99                         .ops = &clk_smd_rpm_branch_ops,                       \
 100                         .name = #_active,                                     \
 101                         .parent_data =  &(const struct clk_parent_data){ \
 102                                         .fw_name = "xo",                \
 103                                         .name = "xo_board",             \
 104                         },                                              \
 105                         .num_parents = 1,                                     \
 106                 },                                                            \
 107         }
 108
 109 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id)             \
 110                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 111                 0, QCOM_RPM_SMD_KEY_RATE)
 112
 113 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r)   \
 114                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type,  \
 115                 r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
 116
 117 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id)        \
 118                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 119                 0, QCOM_RPM_SMD_KEY_STATE)
 120
 121 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id)         \
 122                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 123                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000,                        \
 124                 QCOM_RPM_KEY_SOFTWARE_ENABLE)
 125
 126 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
 127                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 128                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000,                        \
 129                 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
 130
 131 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
 132
 133 struct clk_smd_rpm {
 134         const int rpm_res_type;
 135         const int rpm_key;
 136         const int rpm_clk_id;
 137         const int rpm_status_id;
 138         const bool active_only;
 139         bool enabled;
 140         bool branch;
 141         struct clk_smd_rpm *peer;
 142         struct clk_hw hw;
 143         unsigned long rate;
 144         struct qcom_smd_rpm *rpm;
 145 };
 146
 147 struct clk_smd_rpm_req {
 148         __le32 key;
 149         __le32 nbytes;
 150         __le32 value;
 151 };
 152
 153 struct rpm_cc {
 154         struct qcom_rpm *rpm;
 155         struct clk_smd_rpm **clks;
 156         size_t num_clks;
 157 };
 158
 159 struct rpm_smd_clk_desc {
 160         struct clk_smd_rpm **clks;
 161         size_t num_clks;
 162 };
 163
 164 static DEFINE_MUTEX(rpm_smd_clk_lock);
 165
 166 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
 167 {
 168         int ret;
 169         struct clk_smd_rpm_req req = {
 170                 .key = cpu_to_le32(r->rpm_key),
 171                 .nbytes = cpu_to_le32(sizeof(u32)),
 172                 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
 173         };
 174
 175         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 176                                  r->rpm_res_type, r->rpm_clk_id, &req,
 177                                  sizeof(req));
 178         if (ret)
 179                 return ret;
 180         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 181                                  r->rpm_res_type, r->rpm_clk_id, &req,
 182                                  sizeof(req));
 183         if (ret)
 184                 return ret;
 185
 186         return 0;
 187 }
 188
 189 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
 190                                        unsigned long rate)
 191 {
 192         struct clk_smd_rpm_req req = {
 193                 .key = cpu_to_le32(r->rpm_key),
 194                 .nbytes = cpu_to_le32(sizeof(u32)),
 195                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 196         };
 197
 198         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 199                                   r->rpm_res_type, r->rpm_clk_id, &req,
 200                                   sizeof(req));
 201 }
 202
 203 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
 204                                       unsigned long rate)
 205 {
 206         struct clk_smd_rpm_req req = {
 207                 .key = cpu_to_le32(r->rpm_key),
 208                 .nbytes = cpu_to_le32(sizeof(u32)),
 209                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 210         };
 211
 212         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 213                                   r->rpm_res_type, r->rpm_clk_id, &req,
 214                                   sizeof(req));
 215 }
 216
 217 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
 218                             unsigned long *active, unsigned long *sleep)
 219 {
 220         *active = rate;
 221
 222         /*
 223          * Active-only clocks don't care what the rate is during sleep. So,
 224          * they vote for zero.
 225          */
 226         if (r->active_only)
 227                 *sleep = 0;
 228         else
 229                 *sleep = *active;
 230 }
 231
 232 static int clk_smd_rpm_prepare(struct clk_hw *hw)
 233 {
 234         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 235         struct clk_smd_rpm *peer = r->peer;
 236         unsigned long this_rate = 0, this_sleep_rate = 0;
 237         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 238         unsigned long active_rate, sleep_rate;
 239         int ret = 0;
 240
 241         mutex_lock(&rpm_smd_clk_lock);
 242
 243         /* Don't send requests to the RPM if the rate has not been set. */
 244         if (!r->rate)
 245                 goto out;
 246
 247         to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
 248
 249         /* Take peer clock's rate into account only if it's enabled. */
 250         if (peer->enabled)
 251                 to_active_sleep(peer, peer->rate,
 252                                 &peer_rate, &peer_sleep_rate);
 253
 254         active_rate = max(this_rate, peer_rate);
 255
 256         if (r->branch)
 257                 active_rate = !!active_rate;
 258
 259         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 260         if (ret)
 261                 goto out;
 262
 263         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 264         if (r->branch)
 265                 sleep_rate = !!sleep_rate;
 266
 267         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 268         if (ret)
 269                 /* Undo the active set vote and restore it */
 270                 ret = clk_smd_rpm_set_rate_active(r, peer_rate);
 271
 272 out:
 273         if (!ret)
 274                 r->enabled = true;
 275
 276         mutex_unlock(&rpm_smd_clk_lock);
 277
 278         return ret;
 279 }
 280
 281 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
 282 {
 283         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 284         struct clk_smd_rpm *peer = r->peer;
 285         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 286         unsigned long active_rate, sleep_rate;
 287         int ret;
 288
 289         mutex_lock(&rpm_smd_clk_lock);
 290
 291         if (!r->rate)
 292                 goto out;
 293
 294         /* Take peer clock's rate into account only if it's enabled. */
 295         if (peer->enabled)
 296                 to_active_sleep(peer, peer->rate, &peer_rate,
 297                                 &peer_sleep_rate);
 298
 299         active_rate = r->branch ? !!peer_rate : peer_rate;
 300         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 301         if (ret)
 302                 goto out;
 303
 304         sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
 305         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 306         if (ret)
 307                 goto out;
 308
 309         r->enabled = false;
 310
 311 out:
 312         mutex_unlock(&rpm_smd_clk_lock);
 313 }
 314
 315 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
 316                                 unsigned long parent_rate)
 317 {
 318         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 319         struct clk_smd_rpm *peer = r->peer;
 320         unsigned long active_rate, sleep_rate;
 321         unsigned long this_rate = 0, this_sleep_rate = 0;
 322         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 323         int ret = 0;
 324
 325         mutex_lock(&rpm_smd_clk_lock);
 326
 327         if (!r->enabled)
 328                 goto out;
 329
 330         to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
 331
 332         /* Take peer clock's rate into account only if it's enabled. */
 333         if (peer->enabled)
 334                 to_active_sleep(peer, peer->rate,
 335                                 &peer_rate, &peer_sleep_rate);
 336
 337         active_rate = max(this_rate, peer_rate);
 338         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 339         if (ret)
 340                 goto out;
 341
 342         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 343         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 344         if (ret)
 345                 goto out;
 346
 347         r->rate = rate;
 348
 349 out:
 350         mutex_unlock(&rpm_smd_clk_lock);
 351
 352         return ret;
 353 }
 354
 355 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
 356                                    unsigned long *parent_rate)
 357 {
 358         /*
 359          * RPM handles rate rounding and we don't have a way to
 360          * know what the rate will be, so just return whatever
 361          * rate is requested.
 362          */
 363         return rate;
 364 }
 365
 366 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
 367                                              unsigned long parent_rate)
 368 {
 369         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 370
 371         /*
 372          * RPM handles rate rounding and we don't have a way to
 373          * know what the rate will be, so just return whatever
 374          * rate was set.
 375          */
 376         return r->rate;
 377 }
 378
 379 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
 380 {
 381         int ret;
 382         struct clk_smd_rpm_req req = {
 383                 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
 384                 .nbytes = cpu_to_le32(sizeof(u32)),
 385                 .value = cpu_to_le32(1),
 386         };
 387
 388         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
 389                                  QCOM_SMD_RPM_MISC_CLK,
 390                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 391         if (ret) {
 392                 pr_err("RPM clock scaling (sleep set) not enabled!\n");
 393                 return ret;
 394         }
 395
 396         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 397                                  QCOM_SMD_RPM_MISC_CLK,
 398                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 399         if (ret) {
 400                 pr_err("RPM clock scaling (active set) not enabled!\n");
 401                 return ret;
 402         }
 403
 404         pr_debug("%s: RPM clock scaling is enabled\n", __func__);
 405         return 0;
 406 }
 407
 408 static const struct clk_ops clk_smd_rpm_ops = {
 409         .prepare        = clk_smd_rpm_prepare,
 410         .unprepare      = clk_smd_rpm_unprepare,
 411         .set_rate       = clk_smd_rpm_set_rate,
 412         .round_rate     = clk_smd_rpm_round_rate,
 413         .recalc_rate    = clk_smd_rpm_recalc_rate,
 414 };
 415
 416 static const struct clk_ops clk_smd_rpm_branch_ops = {
 417         .prepare        = clk_smd_rpm_prepare,
 418         .unprepare      = clk_smd_rpm_unprepare,
 419 };
 420
 421 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 422 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 423 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 424 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 425 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
 426 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
 427 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
 428 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
 429 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
 430 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
 431 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
 432 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
 433
 434 static struct clk_smd_rpm *msm8916_clks[] = {
 435         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 436         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 437         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 438         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 439         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 440         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 441         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 442         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 443         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 444         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 445         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 446         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 447         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 448         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 449         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 450         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 451         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 452         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 453         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 454         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 455         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 456         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 457         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 458         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 459 };
 460
 461 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 462         .clks = msm8916_clks,
 463         .num_clks = ARRAY_SIZE(msm8916_clks),
 464 };
 465
 466 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 467
 468 static struct clk_smd_rpm *msm8936_clks[] = {
 469         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 470         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 471         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 472         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 473         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 474         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 475         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
 476         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
 477         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 478         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 479         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 480         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 481         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 482         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 483         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 484         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 485         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 486         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 487         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 488         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 489         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 490         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 491         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 492         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 493         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 494         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 495 };
 496
 497 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
 498                 .clks = msm8936_clks,
 499                 .num_clks = ARRAY_SIZE(msm8936_clks),
 500 };
 501
 502 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 503 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
 504 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
 505 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 506 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
 507 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
 508 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
 509 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);
 510 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);
 511 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);
 512 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);
 513 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);
 514 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);
 515 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);
 516 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);
 517 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
 518 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
 519
 520 static struct clk_smd_rpm *msm8974_clks[] = {
 521         [RPM_SMD_PNOC_CLK]              = &msm8916_pcnoc_clk,
 522         [RPM_SMD_PNOC_A_CLK]            = &msm8916_pcnoc_a_clk,
 523         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 524         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 525         [RPM_SMD_CNOC_CLK]              = &msm8974_cnoc_clk,
 526         [RPM_SMD_CNOC_A_CLK]            = &msm8974_cnoc_a_clk,
 527         [RPM_SMD_MMSSNOC_AHB_CLK]       = &msm8974_mmssnoc_ahb_clk,
 528         [RPM_SMD_MMSSNOC_AHB_A_CLK]     = &msm8974_mmssnoc_ahb_a_clk,
 529         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 530         [RPM_SMD_GFX3D_CLK_SRC]         = &msm8974_gfx3d_clk_src,
 531         [RPM_SMD_GFX3D_A_CLK_SRC]       = &msm8974_gfx3d_a_clk_src,
 532         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 533         [RPM_SMD_OCMEMGX_CLK]           = &msm8974_ocmemgx_clk,
 534         [RPM_SMD_OCMEMGX_A_CLK]         = &msm8974_ocmemgx_a_clk,
 535         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 536         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 537         [RPM_SMD_CXO_D0]                = &msm8974_cxo_d0,
 538         [RPM_SMD_CXO_D0_A]              = &msm8974_cxo_d0_a,
 539         [RPM_SMD_CXO_D1]                = &msm8974_cxo_d1,
 540         [RPM_SMD_CXO_D1_A]              = &msm8974_cxo_d1_a,
 541         [RPM_SMD_CXO_A0]                = &msm8974_cxo_a0,
 542         [RPM_SMD_CXO_A0_A]              = &msm8974_cxo_a0_a,
 543         [RPM_SMD_CXO_A1]                = &msm8974_cxo_a1,
 544         [RPM_SMD_CXO_A1_A]              = &msm8974_cxo_a1_a,
 545         [RPM_SMD_CXO_A2]                = &msm8974_cxo_a2,
 546         [RPM_SMD_CXO_A2_A]              = &msm8974_cxo_a2_a,
 547         [RPM_SMD_DIFF_CLK]              = &msm8974_diff_clk,
 548         [RPM_SMD_DIFF_A_CLK]            = &msm8974_diff_a_clk,
 549         [RPM_SMD_DIV_CLK1]              = &msm8974_div_clk1,
 550         [RPM_SMD_DIV_A_CLK1]            = &msm8974_div_a_clk1,
 551         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
 552         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
 553         [RPM_SMD_CXO_D0_PIN]            = &msm8974_cxo_d0_pin,
 554         [RPM_SMD_CXO_D0_A_PIN]          = &msm8974_cxo_d0_a_pin,
 555         [RPM_SMD_CXO_D1_PIN]            = &msm8974_cxo_d1_pin,
 556         [RPM_SMD_CXO_D1_A_PIN]          = &msm8974_cxo_d1_a_pin,
 557         [RPM_SMD_CXO_A0_PIN]            = &msm8974_cxo_a0_pin,
 558         [RPM_SMD_CXO_A0_A_PIN]          = &msm8974_cxo_a0_a_pin,
 559         [RPM_SMD_CXO_A1_PIN]            = &msm8974_cxo_a1_pin,
 560         [RPM_SMD_CXO_A1_A_PIN]          = &msm8974_cxo_a1_a_pin,
 561         [RPM_SMD_CXO_A2_PIN]            = &msm8974_cxo_a2_pin,
 562         [RPM_SMD_CXO_A2_A_PIN]          = &msm8974_cxo_a2_a_pin,
 563 };
 564
 565 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
 566         .clks = msm8974_clks,
 567         .num_clks = ARRAY_SIZE(msm8974_clks),
 568 };
 569
 570 DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
 571                    QCOM_SMD_RPM_BUS_CLK, 2);
 572 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
 573
 574 static struct clk_smd_rpm *msm8976_clks[] = {
 575         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 576         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 577         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 578         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 579         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 580         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 581         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 582         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 583         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 584         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 585         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 586         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 587         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 588         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 589         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 590         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 591         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 592         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 593         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
 594         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
 595         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 596         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 597         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 598         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 599 };
 600
 601 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
 602         .clks = msm8976_clks,
 603         .num_clks = ARRAY_SIZE(msm8976_clks),
 604 };
 605
 606 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13);
 607 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
 608
 609 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
 610 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
 611
 612 static struct clk_smd_rpm *msm8992_clks[] = {
 613         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 614         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 615         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 616         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 617         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 618         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 619         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 620         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 621         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 622         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 623         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 624         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 625         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 626         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 627         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 628         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 629         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 630         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 631         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 632         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 633         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 634         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 635         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 636         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 637         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 638         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 639         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 640         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 641         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 642         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 643         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 644         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 645         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 646         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 647         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 648         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 649         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 650         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 651         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 652         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 653         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 654         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 655         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 656         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 657         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 658         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 659 };
 660
 661 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
 662         .clks = msm8992_clks,
 663         .num_clks = ARRAY_SIZE(msm8992_clks),
 664 };
 665
 666 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
 667
 668 static struct clk_smd_rpm *msm8994_clks[] = {
 669         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 670         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 671         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 672         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 673         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 674         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 675         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 676         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 677         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 678         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 679         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 680         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 681         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 682         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 683         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 684         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 685         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 686         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 687         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 688         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 689         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 690         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 691         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 692         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 693         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 694         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 695         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 696         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 697         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 698         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 699         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 700         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 701         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 702         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 703         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 704         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 705         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 706         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 707         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 708         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 709         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 710         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 711         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 712         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 713         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 714         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 715         [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
 716         [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
 717 };
 718
 719 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
 720         .clks = msm8994_clks,
 721         .num_clks = ARRAY_SIZE(msm8994_clks),
 722 };
 723
 724 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
 725                    QCOM_SMD_RPM_MMAXI_CLK, 0);
 726 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
 727                           QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
 728 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
 729                           QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
 730
 731 static struct clk_smd_rpm *msm8996_clks[] = {
 732         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 733         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 734         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 735         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 736         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 737         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 738         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 739         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 740         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 741         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 742         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 743         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 744         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 745         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 746         [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
 747         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
 748         [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
 749         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
 750         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 751         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 752         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 753         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 754         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 755         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 756         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 757         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 758         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 759         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 760         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 761         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 762         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 763         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 764         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 765         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 766         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 767         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 768         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 769         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 770         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 771         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 772         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 773         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 774         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 775         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 776 };
 777
 778 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 779         .clks = msm8996_clks,
 780         .num_clks = ARRAY_SIZE(msm8996_clks),
 781 };
 782
 783 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 784 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
 785 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);
 786
 787 static struct clk_smd_rpm *qcs404_clks[] = {
 788         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 789         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 790         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 791         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 792         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 793         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 794         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 795         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 796         [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
 797         [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
 798         [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
 799         [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
 800         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 801         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 802         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 803         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 804         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 805         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 806 };
 807
 808 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
 809         .clks = qcs404_clks,
 810         .num_clks = ARRAY_SIZE(qcs404_clks),
 811 };
 812
 813 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
 814                                      3);
 815 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
 816                    QCOM_SMD_RPM_AGGR_CLK, 1);
 817 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
 818                    QCOM_SMD_RPM_AGGR_CLK, 2);
 819 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
 820 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
 821 static struct clk_smd_rpm *msm8998_clks[] = {
 822         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 823         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 824         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 825         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 826         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 827         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 828         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 829         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 830         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 831         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 832         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 833         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 834         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 835         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 836         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
 837         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
 838         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 839         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 840         [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
 841         [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
 842         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 843         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 844         [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
 845         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
 846         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 847         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 848         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 849         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 850         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 851         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 852         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 853         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 854         [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
 855         [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
 856         [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
 857         [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
 858 };
 859
 860 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
 861         .clks = msm8998_clks,
 862         .num_clks = ARRAY_SIZE(msm8998_clks),
 863 };
 864
 865 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
 866                                                                 19200000);
 867 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3);
 868 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3);
 869
 870 static struct clk_smd_rpm *sdm660_clks[] = {
 871         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 872         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 873         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 874         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 875         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 876         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 877         [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk,
 878         [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk,
 879         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 880         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 881         [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 882         [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk,
 883         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 884         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 885         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 886         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 887         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 888         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 889         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 890         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 891         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 892         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 893         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 894         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 895         [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1,
 896         [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
 897         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 898         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 899         [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
 900         [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
 901         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 902         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 903         [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 904         [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 905         [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 906         [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 907         [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
 908         [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
 909 };
 910
 911 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
 912         .clks = sdm660_clks,
 913         .num_clks = ARRAY_SIZE(sdm660_clks),
 914 };
 915
 916 static const struct of_device_id rpm_smd_clk_match_table[] = {
 917         { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
 918         { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
 919         { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
 920         { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
 921         { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
 922         { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
 923         { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
 924         { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
 925         { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
 926         { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
 927         { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
 928         { }
 929 };
 930 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
 931
 932 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
 933                                              void *data)
 934 {
 935         struct rpm_cc *rcc = data;
 936         unsigned int idx = clkspec->args[0];
 937
 938         if (idx >= rcc->num_clks) {
 939                 pr_err("%s: invalid index %u\n", __func__, idx);
 940                 return ERR_PTR(-EINVAL);
 941         }
 942
 943         return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
 944 }
 945
 946 static int rpm_smd_clk_probe(struct platform_device *pdev)
 947 {
 948         struct rpm_cc *rcc;
 949         int ret;
 950         size_t num_clks, i;
 951         struct qcom_smd_rpm *rpm;
 952         struct clk_smd_rpm **rpm_smd_clks;
 953         const struct rpm_smd_clk_desc *desc;
 954
 955         rpm = dev_get_drvdata(pdev->dev.parent);
 956         if (!rpm) {
 957                 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
 958                 return -ENODEV;
 959         }
 960
 961         desc = of_device_get_match_data(&pdev->dev);
 962         if (!desc)
 963                 return -EINVAL;
 964
 965         rpm_smd_clks = desc->clks;
 966         num_clks = desc->num_clks;
 967
 968         rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
 969         if (!rcc)
 970                 return -ENOMEM;
 971
 972         rcc->clks = rpm_smd_clks;
 973         rcc->num_clks = num_clks;
 974
 975         for (i = 0; i < num_clks; i++) {
 976                 if (!rpm_smd_clks[i])
 977                         continue;
 978
 979                 rpm_smd_clks[i]->rpm = rpm;
 980
 981                 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
 982                 if (ret)
 983                         goto err;
 984         }
 985
 986         ret = clk_smd_rpm_enable_scaling(rpm);
 987         if (ret)
 988                 goto err;
 989
 990         for (i = 0; i < num_clks; i++) {
 991                 if (!rpm_smd_clks[i])
 992                         continue;
 993
 994                 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
 995                 if (ret)
 996                         goto err;
 997         }
 998
 999         ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1000                                      rcc);
1001         if (ret)
1002                 goto err;
1003
1004         return 0;
1005 err:
1006         dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1007         return ret;
1008 }
1009
1010 static struct platform_driver rpm_smd_clk_driver = {
1011         .driver = {
1012                 .name = "qcom-clk-smd-rpm",
1013                 .of_match_table = rpm_smd_clk_match_table,
1014         },
1015         .probe = rpm_smd_clk_probe,
1016 };
1017
1018 static int __init rpm_smd_clk_init(void)
1019 {
1020         return platform_driver_register(&rpm_smd_clk_driver);
1021 }
1022 core_initcall(rpm_smd_clk_init);
1023
1024 static void __exit rpm_smd_clk_exit(void)
1025 {
1026         platform_driver_unregister(&rpm_smd_clk_driver);
1027 }
1028 module_exit(rpm_smd_clk_exit);
1029
1030 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
1031 MODULE_LICENSE("GPL v2");
1032 MODULE_ALIAS("platform:qcom-clk-smd-rpm");