drivers/clk/imx/clk-imx6q.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  */
   6
   7 #include <linux/init.h>
   8 #include <linux/types.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <soc/imx/revision.h>
  19 #include <dt-bindings/clock/imx6qdl-clock.h>
  20
  21 #include "clk.h"
  22
  23 static const char *step_sels[]  = { "osc", "pll2_pfd2_396m", };
  24 static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
  25 static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
  26 static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", "osc", "dummy", };
  27 static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
  28 static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
  29 static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
  30 static const char *axi_sels[]           = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
  31 static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
  32 static const char *gpu_axi_sels[]       = { "axi", "ahb", };
  33 static const char *pre_axi_sels[]       = { "axi", "ahb", };
  34 static const char *gpu2d_core_sels[]    = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
  35 static const char *gpu2d_core_sels_2[]  = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",};
  36 static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
  37 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
  38 static const char *ipu_sels[]           = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
  39 static const char *ldb_di_sels[]        = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
  40 static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
  41 static const char *ipu1_di0_sels[]      = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
  42 static const char *ipu1_di1_sels[]      = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
  43 static const char *ipu2_di0_sels[]      = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
  44 static const char *ipu2_di1_sels[]      = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
  45 static const char *ipu1_di0_sels_2[]    = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
  46 static const char *ipu1_di1_sels_2[]    = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
  47 static const char *ipu2_di0_sels_2[]    = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
  48 static const char *ipu2_di1_sels_2[]    = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
  49 static const char *hsi_tx_sels[]        = { "pll3_120m", "pll2_pfd2_396m", };
  50 static const char *pcie_axi_sels[]      = { "axi", "ahb", };
  51 static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
  52 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
  53 static const char *enfc_sels[]  = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
  54 static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", };
  55 static const char *eim_sels[]           = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
  56 static const char *eim_slow_sels[]      = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
  57 static const char *vdo_axi_sels[]       = { "axi", "ahb", };
  58 static const char *vpu_axi_sels[]       = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
  59 static const char *uart_sels[] = { "pll3_80m", "osc", };
  60 static const char *ipg_per_sels[] = { "ipg", "osc", };
  61 static const char *ecspi_sels[] = { "pll3_60m", "osc", };
  62 static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", };
  63 static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
  64                                     "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
  65                                     "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
  66 static const char *cko2_sels[] = {
  67         "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
  68         "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
  69         "usdhc3", "dummy", "arm", "ipu1",
  70         "ipu2", "vdo_axi", "osc", "gpu2d_core",
  71         "gpu3d_core", "usdhc2", "ssi1", "ssi2",
  72         "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
  73         "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
  74         "uart_serial", "spdif", "asrc", "hsi_tx",
  75 };
  76 static const char *cko_sels[] = { "cko1", "cko2", };
  77 static const char *lvds_sels[] = {
  78         "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
  79         "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
  80         "pcie_ref_125m", "sata_ref_100m",  "usbphy1", "usbphy2",
  81         "dummy", "dummy", "dummy", "dummy", "osc",
  82 };
  83 static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
  84 static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
  85 static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
  86 static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
  87 static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
  88 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
  89 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
  90 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
  91
  92 static struct clk_hw **hws;
  93 static struct clk_hw_onecell_data *clk_hw_data;
  94
  95 static struct clk_div_table clk_enet_ref_table[] = {
  96         { .val = 0, .div = 20, },
  97         { .val = 1, .div = 10, },
  98         { .val = 2, .div = 5, },
  99         { .val = 3, .div = 4, },
 100         { /* sentinel */ }
 101 };
 102
 103 static struct clk_div_table post_div_table[] = {
 104         { .val = 2, .div = 1, },
 105         { .val = 1, .div = 2, },
 106         { .val = 0, .div = 4, },
 107         { /* sentinel */ }
 108 };
 109
 110 static struct clk_div_table video_div_table[] = {
 111         { .val = 0, .div = 1, },
 112         { .val = 1, .div = 2, },
 113         { .val = 2, .div = 1, },
 114         { .val = 3, .div = 4, },
 115         { /* sentinel */ }
 116 };
 117
 118 static unsigned int share_count_esai;
 119 static unsigned int share_count_asrc;
 120 static unsigned int share_count_ssi1;
 121 static unsigned int share_count_ssi2;
 122 static unsigned int share_count_ssi3;
 123 static unsigned int share_count_mipi_core_cfg;
 124 static unsigned int share_count_spdif;
 125 static unsigned int share_count_prg0;
 126 static unsigned int share_count_prg1;
 127
 128 static inline int clk_on_imx6q(void)
 129 {
 130         return of_machine_is_compatible("fsl,imx6q");
 131 }
 132
 133 static inline int clk_on_imx6qp(void)
 134 {
 135         return of_machine_is_compatible("fsl,imx6qp");
 136 }
 137
 138 static inline int clk_on_imx6dl(void)
 139 {
 140         return of_machine_is_compatible("fsl,imx6dl");
 141 }
 142
 143 static int ldb_di_sel_by_clock_id(int clock_id)
 144 {
 145         switch (clock_id) {
 146         case IMX6QDL_CLK_PLL5_VIDEO_DIV:
 147                 if (clk_on_imx6q() &&
 148                     imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
 149                         return -ENOENT;
 150                 return 0;
 151         case IMX6QDL_CLK_PLL2_PFD0_352M:
 152                 return 1;
 153         case IMX6QDL_CLK_PLL2_PFD2_396M:
 154                 return 2;
 155         case IMX6QDL_CLK_MMDC_CH1_AXI:
 156                 return 3;
 157         case IMX6QDL_CLK_PLL3_USB_OTG:
 158                 return 4;
 159         default:
 160                 return -ENOENT;
 161         }
 162 }
 163
 164 static void of_assigned_ldb_sels(struct device_node *node,
 165                                  unsigned int *ldb_di0_sel,
 166                                  unsigned int *ldb_di1_sel)
 167 {
 168         struct of_phandle_args clkspec;
 169         int index, rc, num_parents;
 170         int parent, child, sel;
 171
 172         num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
 173                                                  "#clock-cells");
 174         for (index = 0; index < num_parents; index++) {
 175                 rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
 176                                         "#clock-cells", index, &clkspec);
 177                 if (rc < 0) {
 178                         /* skip empty (null) phandles */
 179                         if (rc == -ENOENT)
 180                                 continue;
 181                         else
 182                                 return;
 183                 }
 184                 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
 185                         pr_err("ccm: parent clock %d not in ccm\n", index);
 186                         return;
 187                 }
 188                 parent = clkspec.args[0];
 189
 190                 rc = of_parse_phandle_with_args(node, "assigned-clocks",
 191                                 "#clock-cells", index, &clkspec);
 192                 if (rc < 0)
 193                         return;
 194                 if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
 195                         pr_err("ccm: child clock %d not in ccm\n", index);
 196                         return;
 197                 }
 198                 child = clkspec.args[0];
 199
 200                 if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
 201                     child != IMX6QDL_CLK_LDB_DI1_SEL)
 202                         continue;
 203
 204                 sel = ldb_di_sel_by_clock_id(parent);
 205                 if (sel < 0) {
 206                         pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
 207                                child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
 208                         continue;
 209                 }
 210
 211                 if (child == IMX6QDL_CLK_LDB_DI0_SEL)
 212                         *ldb_di0_sel = sel;
 213                 if (child == IMX6QDL_CLK_LDB_DI1_SEL)
 214                         *ldb_di1_sel = sel;
 215         }
 216 }
 217
 218 static bool pll6_bypassed(struct device_node *node)
 219 {
 220         int index, ret, num_clocks;
 221         struct of_phandle_args clkspec;
 222
 223         num_clocks = of_count_phandle_with_args(node, "assigned-clocks",
 224                                                 "#clock-cells");
 225         if (num_clocks < 0)
 226                 return false;
 227
 228         for (index = 0; index < num_clocks; index++) {
 229                 ret = of_parse_phandle_with_args(node, "assigned-clocks",
 230                                                  "#clock-cells", index,
 231                                                  &clkspec);
 232                 if (ret < 0)
 233                         return false;
 234
 235                 if (clkspec.np == node &&
 236                     clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
 237                         break;
 238         }
 239
 240         /* PLL6 bypass is not part of the assigned clock list */
 241         if (index == num_clocks)
 242                 return false;
 243
 244         ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
 245                                          "#clock-cells", index, &clkspec);
 246
 247         if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
 248                 return true;
 249
 250         return false;
 251 }
 252
 253 #define CCM_CCSR                0x0c
 254 #define CCM_CS2CDR              0x2c
 255
 256 #define CCSR_PLL3_SW_CLK_SEL            BIT(0)
 257
 258 #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT    9
 259 #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT    12
 260
 261 /*
 262  * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk
 263  * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
 264  * bypass clock source, since there is no CG bit for mmdc_ch1.
 265  */
 266 static void mmdc_ch1_disable(void __iomem *ccm_base)
 267 {
 268         unsigned int reg;
 269
 270         clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk,
 271                        hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
 272
 273         /* Disable pll3_sw_clk by selecting the bypass clock source */
 274         reg = readl_relaxed(ccm_base + CCM_CCSR);
 275         reg |= CCSR_PLL3_SW_CLK_SEL;
 276         writel_relaxed(reg, ccm_base + CCM_CCSR);
 277 }
 278
 279 static void mmdc_ch1_reenable(void __iomem *ccm_base)
 280 {
 281         unsigned int reg;
 282
 283         /* Enable pll3_sw_clk by disabling the bypass */
 284         reg = readl_relaxed(ccm_base + CCM_CCSR);
 285         reg &= ~CCSR_PLL3_SW_CLK_SEL;
 286         writel_relaxed(reg, ccm_base + CCM_CCSR);
 287 }
 288
 289 /*
 290  * We have to follow a strict procedure when changing the LDB clock source,
 291  * otherwise we risk introducing a glitch that can lock up the LDB divider.
 292  * Things to keep in mind:
 293  *
 294  * 1. The current and new parent clock inputs to the mux must be disabled.
 295  * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which
 296  *    has no CG bit.
 297  * 3. pll2_pfd2_396m can not be gated if it is used as memory clock.
 298  * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four
 299  *    options are in one mux and the PLL3 option along with three unused
 300  *    inputs is in a second mux. There is a third mux with two inputs used
 301  *    to decide between the first and second 4-port mux:
 302  *
 303  *    pll5_video_div 0 --|\
 304  *    pll2_pfd0_352m 1 --| |_
 305  *    pll2_pfd2_396m 2 --| | `-|\
 306  *    mmdc_ch1_axi   3 --|/    | |
 307  *                             | |--
 308  *    pll3_usb_otg   4 --|\    | |
 309  *                   5 --| |_,-|/
 310  *                   6 --| |
 311  *                   7 --|/
 312  *
 313  * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
 314  * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
 315  * switches the parent to the bottom mux first and then manipulates the top
 316  * mux to ensure that no glitch will enter the divider.
 317  */
 318 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
 319 {
 320         unsigned int reg;
 321         unsigned int sel[2][4];
 322         int i;
 323
 324         reg = readl_relaxed(ccm_base + CCM_CS2CDR);
 325         sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7;
 326         sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7;
 327
 328         sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
 329         sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
 330
 331         of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
 332
 333         for (i = 0; i < 2; i++) {
 334                 /* Print a notice if a glitch might have been introduced already */
 335                 if (sel[i][0] != 3) {
 336                         pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n",
 337                                   i, sel[i][0]);
 338                 }
 339
 340                 if (sel[i][0] == sel[i][3])
 341                         continue;
 342
 343                 /* Only switch to or from pll2_pfd2_396m if it is disabled */
 344                 if ((sel[i][0] == 2 || sel[i][3] == 2) &&
 345                     (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
 346                      hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) {
 347                         pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n",
 348                                i);
 349                         sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0];
 350                         continue;
 351                 }
 352
 353                 /* First switch to the bottom mux */
 354                 sel[i][1] = sel[i][0] | 4;
 355
 356                 /* Then configure the top mux before switching back to it */
 357                 sel[i][2] = sel[i][3] | 4;
 358
 359                 pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,
 360                          sel[i][0], sel[i][1], sel[i][2], sel[i][3]);
 361         }
 362
 363         if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3])
 364                 return;
 365
 366         mmdc_ch1_disable(ccm_base);
 367
 368         for (i = 1; i < 4; i++) {
 369                 reg = readl_relaxed(ccm_base + CCM_CS2CDR);
 370                 reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
 371                          (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
 372                 reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
 373                         (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
 374                 writel_relaxed(reg, ccm_base + CCM_CS2CDR);
 375         }
 376
 377         mmdc_ch1_reenable(ccm_base);
 378 }
 379
 380 #define CCM_ANALOG_PLL_VIDEO    0xa0
 381 #define CCM_ANALOG_PFD_480      0xf0
 382 #define CCM_ANALOG_PFD_528      0x100
 383
 384 #define PLL_ENABLE              BIT(13)
 385
 386 #define PFD0_CLKGATE            BIT(7)
 387 #define PFD1_CLKGATE            BIT(15)
 388 #define PFD2_CLKGATE            BIT(23)
 389 #define PFD3_CLKGATE            BIT(31)
 390
 391 static void disable_anatop_clocks(void __iomem *anatop_base)
 392 {
 393         unsigned int reg;
 394
 395         /* Make sure PLL2 PFDs 0-2 are gated */
 396         reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528);
 397         /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */
 398         if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
 399             hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)
 400                 reg |= PFD0_CLKGATE | PFD1_CLKGATE;
 401         else
 402                 reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE;
 403         writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
 404
 405         /* Make sure PLL3 PFDs 0-3 are gated */
 406         reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480);
 407         reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE;
 408         writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
 409
 410         /* Make sure PLL5 is disabled */
 411         reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO);
 412         reg &= ~PLL_ENABLE;
 413         writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
 414 }
 415
 416 static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np,
 417                                                         const char *name,
 418                                                         unsigned long rate)
 419 {
 420         struct clk *clk = of_clk_get_by_name(np, name);
 421         struct clk_hw *hw;
 422
 423         if (IS_ERR(clk))
 424                 hw = imx_obtain_fixed_clock_hw(name, rate);
 425         else
 426                 hw = __clk_get_hw(clk);
 427
 428         return hw;
 429 }
 430
 431 static void __init imx6q_clocks_init(struct device_node *ccm_node)
 432 {
 433         struct device_node *np;
 434         void __iomem *anatop_base, *base;
 435         int ret;
 436
 437         clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
 438                                           IMX6QDL_CLK_END), GFP_KERNEL);
 439         if (WARN_ON(!clk_hw_data))
 440                 return;
 441
 442         clk_hw_data->num = IMX6QDL_CLK_END;
 443         hws = clk_hw_data->hws;
 444
 445         hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
 446
 447         hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckil", 0);
 448         hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckih1", 0);
 449         hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0);
 450
 451         /* Clock source from external clock via CLK1/2 PADs */
 452         hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0);
 453         hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0);
 454
 455         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
 456         anatop_base = base = of_iomap(np, 0);
 457         WARN_ON(!base);
 458         of_node_put(np);
 459
 460         /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
 461         if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
 462                 post_div_table[1].div = 1;
 463                 post_div_table[2].div = 1;
 464                 video_div_table[1].div = 1;
 465                 video_div_table[3].div = 1;
 466         }
 467
 468         hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 469         hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 470         hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 471         hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 472         hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 473         hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 474         hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
 475
 476         /*                                    type               name    parent_name        base         div_mask */
 477         hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,     "pll1", "osc", base + 0x00, 0x7f);
 478         hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
 479         hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll3", "osc", base + 0x10, 0x3);
 480         hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll4", "osc", base + 0x70, 0x7f);
 481         hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll5", "osc", base + 0xa0, 0x7f);
 482         hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,    "pll6", "osc", base + 0xe0, 0x3);
 483         hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll7", "osc", base + 0x20, 0x3);
 484
 485         hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
 486         hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
 487         hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
 488         hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
 489         hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
 490         hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
 491         hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
 492
 493         /* Do not bypass PLLs initially */
 494         clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk);
 495         clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk);
 496         clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk);
 497         clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk);
 498         clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk);
 499         clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk);
 500         clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk);
 501
 502         hws[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_hw_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
 503         hws[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_hw_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
 504         hws[IMX6QDL_CLK_PLL3_USB_OTG]  = imx_clk_hw_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
 505         hws[IMX6QDL_CLK_PLL4_AUDIO]    = imx_clk_hw_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
 506         hws[IMX6QDL_CLK_PLL5_VIDEO]    = imx_clk_hw_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
 507         hws[IMX6QDL_CLK_PLL6_ENET]     = imx_clk_hw_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
 508         hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
 509
 510         /*
 511          * Bit 20 is the reserved and read-only bit, we do this only for:
 512          * - Do nothing for usbphy clk_enable/disable
 513          * - Keep refcount when do usbphy clk_enable/disable, in that case,
 514          * the clk framework may need to enable/disable usbphy's parent
 515          */
 516         hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
 517         hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
 518
 519         /*
 520          * usbphy*_gate needs to be on after system boots up, and software
 521          * never needs to control it anymore.
 522          */
 523         hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
 524         hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
 525
 526         /*
 527          * The ENET PLL is special in that is has multiple outputs with
 528          * different post-dividers that are all affected by the single bypass
 529          * bit, so a single mux bit affects 3 independent branches of the clock
 530          * tree. There is no good way to model this in the clock framework and
 531          * dynamically changing the bypass bit, will yield unexpected results.
 532          * So we treat any configuration that bypasses the ENET PLL as
 533          * essentially static with the divider ratios reflecting the bypass
 534          * status.
 535          *
 536          */
 537         if (!pll6_bypassed(ccm_node)) {
 538                 hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 5);
 539                 hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 540                 hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
 541                                                 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
 542                                                 &imx_ccm_lock);
 543         } else {
 544                 hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 1);
 545                 hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 1);
 546                 hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor("enet_ref", "pll6_enet", 1, 1);
 547         }
 548
 549         hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
 550         hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 551
 552         hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
 553         hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
 554
 555         /*
 556          * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
 557          * independently configured as clock inputs or outputs.  We treat
 558          * the "output_enable" bit as a gate, even though it's really just
 559          * enabling clock output. Initially the gate bits are cleared, as
 560          * otherwise the exclusive configuration gets locked in the setup done
 561          * by software running before the clock driver, with no way to change
 562          * it.
 563          */
 564         writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
 565         hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
 566         hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
 567
 568         hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
 569         hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
 570
 571         /*                                            name              parent_name        reg       idx */
 572         hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
 573         hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
 574         hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
 575         hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
 576         hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
 577         hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
 578         hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
 579
 580         /*                                                name         parent_name     mult div */
 581         hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
 582         hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
 583         hws[IMX6QDL_CLK_PLL3_80M]  = imx_clk_hw_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
 584         hws[IMX6QDL_CLK_PLL3_60M]  = imx_clk_hw_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
 585         hws[IMX6QDL_CLK_TWD]       = imx_clk_hw_fixed_factor("twd",       "arm",            1, 2);
 586         hws[IMX6QDL_CLK_GPT_3M]    = imx_clk_hw_fixed_factor("gpt_3m",    "osc",            1, 8);
 587         hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
 588         if (clk_on_imx6dl() || clk_on_imx6qp()) {
 589                 hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
 590                 hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
 591         }
 592
 593         hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
 594         if (clk_on_imx6q() || clk_on_imx6qp())
 595                 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor("pll4_audio_div", "pll4_post_div", 1, 1);
 596         else
 597                 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
 598         hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
 599         hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 600
 601         np = ccm_node;
 602         base = of_iomap(np, 0);
 603         WARN_ON(!base);
 604
 605         /*                                              name                reg       shift width parent_names     num_parents */
 606         hws[IMX6QDL_CLK_STEP]             = imx_clk_hw_mux("step",                  base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
 607         hws[IMX6QDL_CLK_PLL1_SW]          = imx_clk_hw_mux("pll1_sw",       base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
 608         hws[IMX6QDL_CLK_PERIPH_PRE]       = imx_clk_hw_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
 609         hws[IMX6QDL_CLK_PERIPH2_PRE]      = imx_clk_hw_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
 610         hws[IMX6QDL_CLK_PERIPH_CLK2_SEL]  = imx_clk_hw_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
 611         hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
 612         hws[IMX6QDL_CLK_AXI_SEL]          = imx_clk_hw_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
 613         hws[IMX6QDL_CLK_ESAI_SEL]         = imx_clk_hw_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
 614         hws[IMX6QDL_CLK_ASRC_SEL]         = imx_clk_hw_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
 615         hws[IMX6QDL_CLK_SPDIF_SEL]        = imx_clk_hw_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
 616         if (clk_on_imx6q()) {
 617                 hws[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_hw_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
 618                 hws[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_hw_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
 619         }
 620         if (clk_on_imx6qp()) {
 621                 hws[IMX6QDL_CLK_CAN_SEL]   = imx_clk_hw_mux("can_sel",  base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
 622                 hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel",        base + 0x38, 18, 1, ecspi_sels,  ARRAY_SIZE(ecspi_sels));
 623                 hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels));
 624                 hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
 625                 hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2));
 626         } else if (clk_on_imx6dl()) {
 627                 hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
 628         } else {
 629                 hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
 630         }
 631         hws[IMX6QDL_CLK_GPU3D_CORE_SEL]   = imx_clk_hw_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
 632         if (clk_on_imx6dl())
 633                 hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
 634         else
 635                 hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
 636         hws[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_hw_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 637         hws[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_hw_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 638
 639         disable_anatop_clocks(anatop_base);
 640
 641         imx_mmdc_mask_handshake(base, 1);
 642
 643         if (clk_on_imx6qp()) {
 644                 hws[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
 645                 hws[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
 646         } else {
 647                 /*
 648                  * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
 649                  * bug. Set the muxes to the requested values before registering the
 650                  * ldb_di_sel clocks.
 651                  */
 652                 init_ldb_clks(np, base);
 653
 654                 hws[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels));
 655                 hws[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels));
 656         }
 657
 658         hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
 659         hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
 660         hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
 661         hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
 662         hws[IMX6QDL_CLK_HSI_TX_SEL]       = imx_clk_hw_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
 663         hws[IMX6QDL_CLK_PCIE_AXI_SEL]     = imx_clk_hw_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
 664
 665         if (clk_on_imx6qp()) {
 666                 hws[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_hw_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels_2,     ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT);
 667                 hws[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_hw_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels_2,     ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT);
 668                 hws[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_hw_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels_2,     ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT);
 669                 hws[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_hw_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels_2,     ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT);
 670                 hws[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_hw_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
 671                 hws[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_hw_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
 672                 hws[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_hw_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
 673                 hws[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 674                 hws[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 675                 hws[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 676                 hws[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 677                 hws[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_hw_mux("enfc_sel",         base + 0x2c, 15, 3, enfc_sels_2,         ARRAY_SIZE(enfc_sels_2));
 678                 hws[IMX6QDL_CLK_EIM_SEL]          = imx_clk_hw_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels));
 679                 hws[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels));
 680                 hws[IMX6QDL_CLK_PRE_AXI]          = imx_clk_hw_mux("pre_axi",   base + 0x18, 1,  1, pre_axi_sels,    ARRAY_SIZE(pre_axi_sels));
 681         } else {
 682                 hws[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_hw_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
 683                 hws[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_hw_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
 684                 hws[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_hw_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
 685                 hws[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_hw_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
 686                 hws[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_hw_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
 687                 hws[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_hw_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
 688                 hws[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_hw_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
 689                 hws[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
 690                 hws[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
 691                 hws[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
 692                 hws[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
 693                 hws[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_hw_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
 694                 hws[IMX6QDL_CLK_EIM_SEL]          = imx_clk_hw_fixup_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
 695                 hws[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
 696         }
 697
 698         hws[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_hw_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
 699         hws[IMX6QDL_CLK_VPU_AXI_SEL]      = imx_clk_hw_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
 700         hws[IMX6QDL_CLK_CKO1_SEL]         = imx_clk_hw_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
 701         hws[IMX6QDL_CLK_CKO2_SEL]         = imx_clk_hw_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
 702         hws[IMX6QDL_CLK_CKO]              = imx_clk_hw_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
 703
 704         /*                                          name         reg      shift width busy: reg, shift parent_names  num_parents */
 705         hws[IMX6QDL_CLK_PERIPH]  = imx_clk_hw_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
 706         hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
 707
 708         /*                                                  name                parent_name          reg       shift width */
 709         hws[IMX6QDL_CLK_PERIPH_CLK2]      = imx_clk_hw_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
 710         hws[IMX6QDL_CLK_PERIPH2_CLK2]     = imx_clk_hw_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
 711         hws[IMX6QDL_CLK_IPG]              = imx_clk_hw_divider("ipg",              "ahb",               base + 0x14, 8,  2);
 712         hws[IMX6QDL_CLK_ESAI_PRED]        = imx_clk_hw_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
 713         hws[IMX6QDL_CLK_ESAI_PODF]        = imx_clk_hw_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
 714         hws[IMX6QDL_CLK_ASRC_PRED]        = imx_clk_hw_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
 715         hws[IMX6QDL_CLK_ASRC_PODF]        = imx_clk_hw_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
 716         hws[IMX6QDL_CLK_SPDIF_PRED]       = imx_clk_hw_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
 717         hws[IMX6QDL_CLK_SPDIF_PODF]       = imx_clk_hw_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
 718
 719         if (clk_on_imx6qp()) {
 720                 hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6);
 721                 hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
 722                 hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6);
 723                 hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
 724                 hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
 725                 hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
 726         } else {
 727                 hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
 728                 hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
 729                 hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
 730                 hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
 731                 hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
 732                 hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
 733         }
 734
 735         if (clk_on_imx6dl())
 736                 hws[IMX6QDL_CLK_MLB_PODF]  = imx_clk_hw_divider("mlb_podf",  "mlb_sel",    base + 0x18, 23, 3);
 737         else
 738                 hws[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_hw_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
 739         hws[IMX6QDL_CLK_GPU3D_CORE_PODF]  = imx_clk_hw_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
 740         if (clk_on_imx6dl())
 741                 hws[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_hw_divider("gpu2d_core_podf",     "gpu2d_core_sel",  base + 0x18, 29, 3);
 742         else
 743                 hws[IMX6QDL_CLK_GPU3D_SHADER]     = imx_clk_hw_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
 744         hws[IMX6QDL_CLK_IPU1_PODF]        = imx_clk_hw_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
 745         hws[IMX6QDL_CLK_IPU2_PODF]        = imx_clk_hw_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
 746         hws[IMX6QDL_CLK_LDB_DI0_PODF]     = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
 747         hws[IMX6QDL_CLK_LDB_DI1_PODF]     = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
 748         hws[IMX6QDL_CLK_IPU1_DI0_PRE]     = imx_clk_hw_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
 749         hws[IMX6QDL_CLK_IPU1_DI1_PRE]     = imx_clk_hw_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
 750         hws[IMX6QDL_CLK_IPU2_DI0_PRE]     = imx_clk_hw_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
 751         hws[IMX6QDL_CLK_IPU2_DI1_PRE]     = imx_clk_hw_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
 752         hws[IMX6QDL_CLK_HSI_TX_PODF]      = imx_clk_hw_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
 753         hws[IMX6QDL_CLK_SSI1_PRED]        = imx_clk_hw_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
 754         hws[IMX6QDL_CLK_SSI1_PODF]        = imx_clk_hw_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
 755         hws[IMX6QDL_CLK_SSI2_PRED]        = imx_clk_hw_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
 756         hws[IMX6QDL_CLK_SSI2_PODF]        = imx_clk_hw_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
 757         hws[IMX6QDL_CLK_SSI3_PRED]        = imx_clk_hw_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
 758         hws[IMX6QDL_CLK_SSI3_PODF]        = imx_clk_hw_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
 759         hws[IMX6QDL_CLK_USDHC1_PODF]      = imx_clk_hw_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
 760         hws[IMX6QDL_CLK_USDHC2_PODF]      = imx_clk_hw_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
 761         hws[IMX6QDL_CLK_USDHC3_PODF]      = imx_clk_hw_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
 762         hws[IMX6QDL_CLK_USDHC4_PODF]      = imx_clk_hw_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
 763         hws[IMX6QDL_CLK_ENFC_PRED]        = imx_clk_hw_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
 764         hws[IMX6QDL_CLK_ENFC_PODF]        = imx_clk_hw_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
 765         if (clk_on_imx6qp()) {
 766                 hws[IMX6QDL_CLK_EIM_PODF]         = imx_clk_hw_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3);
 767                 hws[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3);
 768         } else {
 769                 hws[IMX6QDL_CLK_EIM_PODF]         = imx_clk_hw_fixup_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
 770                 hws[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
 771         }
 772
 773         hws[IMX6QDL_CLK_VPU_AXI_PODF]     = imx_clk_hw_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
 774         hws[IMX6QDL_CLK_CKO1_PODF]        = imx_clk_hw_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
 775         hws[IMX6QDL_CLK_CKO2_PODF]        = imx_clk_hw_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
 776
 777         /*                                                        name                 parent_name    reg        shift width busy: reg, shift */
 778         hws[IMX6QDL_CLK_AXI]               = imx_clk_hw_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
 779         hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
 780         if (clk_on_imx6qp()) {
 781                 hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18);
 782                 hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2);
 783         } else {
 784                 hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
 785         }
 786         hws[IMX6QDL_CLK_ARM]               = imx_clk_hw_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
 787         hws[IMX6QDL_CLK_AHB]               = imx_clk_hw_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
 788
 789         /*                                            name             parent_name          reg         shift */
 790         hws[IMX6QDL_CLK_APBH_DMA]     = imx_clk_hw_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
 791         hws[IMX6QDL_CLK_ASRC]         = imx_clk_hw_gate2_shared("asrc",         "asrc_podf",   base + 0x68, 6, &share_count_asrc);
 792         hws[IMX6QDL_CLK_ASRC_IPG]     = imx_clk_hw_gate2_shared("asrc_ipg",     "ahb",         base + 0x68, 6, &share_count_asrc);
 793         hws[IMX6QDL_CLK_ASRC_MEM]     = imx_clk_hw_gate2_shared("asrc_mem",     "ahb",         base + 0x68, 6, &share_count_asrc);
 794         hws[IMX6QDL_CLK_CAAM_MEM]     = imx_clk_hw_gate2("caam_mem",      "ahb",               base + 0x68, 8);
 795         hws[IMX6QDL_CLK_CAAM_ACLK]    = imx_clk_hw_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
 796         hws[IMX6QDL_CLK_CAAM_IPG]     = imx_clk_hw_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
 797         hws[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_hw_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
 798         hws[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_hw_gate2("can1_serial",   "can_root",          base + 0x68, 16);
 799         hws[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_hw_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
 800         hws[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_hw_gate2("can2_serial",   "can_root",          base + 0x68, 20);
 801         hws[IMX6QDL_CLK_DCIC1]        = imx_clk_hw_gate2("dcic1",         "ipu1_podf",         base + 0x68, 24);
 802         hws[IMX6QDL_CLK_DCIC2]        = imx_clk_hw_gate2("dcic2",         "ipu2_podf",         base + 0x68, 26);
 803         hws[IMX6QDL_CLK_ECSPI1]       = imx_clk_hw_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
 804         hws[IMX6QDL_CLK_ECSPI2]       = imx_clk_hw_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
 805         hws[IMX6QDL_CLK_ECSPI3]       = imx_clk_hw_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
 806         hws[IMX6QDL_CLK_ECSPI4]       = imx_clk_hw_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
 807         if (clk_on_imx6dl())
 808                 hws[IMX6DL_CLK_I2C4]  = imx_clk_hw_gate2("i2c4",          "ipg_per",           base + 0x6c, 8);
 809         else
 810                 hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
 811         hws[IMX6QDL_CLK_ENET]         = imx_clk_hw_gate2("enet",          "ipg",               base + 0x6c, 10);
 812         hws[IMX6QDL_CLK_EPIT1]        = imx_clk_hw_gate2("epit1",         "ipg",               base + 0x6c, 12);
 813         hws[IMX6QDL_CLK_EPIT2]        = imx_clk_hw_gate2("epit2",         "ipg",               base + 0x6c, 14);
 814         hws[IMX6QDL_CLK_ESAI_EXTAL]   = imx_clk_hw_gate2_shared("esai_extal",   "esai_podf",   base + 0x6c, 16, &share_count_esai);
 815         hws[IMX6QDL_CLK_ESAI_IPG]     = imx_clk_hw_gate2_shared("esai_ipg",   "ahb",           base + 0x6c, 16, &share_count_esai);
 816         hws[IMX6QDL_CLK_ESAI_MEM]     = imx_clk_hw_gate2_shared("esai_mem", "ahb",             base + 0x6c, 16, &share_count_esai);
 817         hws[IMX6QDL_CLK_GPT_IPG]      = imx_clk_hw_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
 818         hws[IMX6QDL_CLK_GPT_IPG_PER]  = imx_clk_hw_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
 819         hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
 820         hws[IMX6QDL_CLK_GPU3D_CORE]   = imx_clk_hw_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
 821         hws[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_hw_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
 822         hws[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_hw_gate2("hdmi_isfr",     "mipi_core_cfg",     base + 0x70, 4);
 823         hws[IMX6QDL_CLK_I2C1]         = imx_clk_hw_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
 824         hws[IMX6QDL_CLK_I2C2]         = imx_clk_hw_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
 825         hws[IMX6QDL_CLK_I2C3]         = imx_clk_hw_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
 826         hws[IMX6QDL_CLK_IIM]          = imx_clk_hw_gate2("iim",           "ipg",               base + 0x70, 12);
 827         hws[IMX6QDL_CLK_ENFC]         = imx_clk_hw_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
 828         hws[IMX6QDL_CLK_VDOA]         = imx_clk_hw_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
 829         hws[IMX6QDL_CLK_IPU1]         = imx_clk_hw_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
 830         hws[IMX6QDL_CLK_IPU1_DI0]     = imx_clk_hw_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
 831         hws[IMX6QDL_CLK_IPU1_DI1]     = imx_clk_hw_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
 832         hws[IMX6QDL_CLK_IPU2]         = imx_clk_hw_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
 833         hws[IMX6QDL_CLK_IPU2_DI0]     = imx_clk_hw_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
 834         if (clk_on_imx6qp()) {
 835                 hws[IMX6QDL_CLK_LDB_DI0]      = imx_clk_hw_gate2("ldb_di0",       "ldb_di0_sel",      base + 0x74, 12);
 836                 hws[IMX6QDL_CLK_LDB_DI1]      = imx_clk_hw_gate2("ldb_di1",       "ldb_di1_sel",      base + 0x74, 14);
 837         } else {
 838                 hws[IMX6QDL_CLK_LDB_DI0]      = imx_clk_hw_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
 839                 hws[IMX6QDL_CLK_LDB_DI1]      = imx_clk_hw_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
 840         }
 841         hws[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_hw_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
 842         hws[IMX6QDL_CLK_HSI_TX]       = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf",       base + 0x74, 16, &share_count_mipi_core_cfg);
 843         hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
 844         hws[IMX6QDL_CLK_MIPI_IPG]     = imx_clk_hw_gate2_shared("mipi_ipg", "ipg",             base + 0x74, 16, &share_count_mipi_core_cfg);
 845
 846         if (clk_on_imx6dl())
 847                 /*
 848                  * The multiplexer and divider of the imx6q clock gpu2d get
 849                  * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
 850                  */
 851                 hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb",            "mlb_podf",   base + 0x74, 18);
 852         else
 853                 hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb",            "axi",               base + 0x74, 18);
 854         hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);
 855         hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
 856         hws[IMX6QDL_CLK_MMDC_P0_IPG]  = imx_clk_hw_gate2_flags("mmdc_p0_ipg",   "ipg",         base + 0x74, 24, CLK_IS_CRITICAL);
 857         hws[IMX6QDL_CLK_OCRAM]        = imx_clk_hw_gate2("ocram",         "ahb",               base + 0x74, 28);
 858         hws[IMX6QDL_CLK_OPENVG_AXI]   = imx_clk_hw_gate2("openvg_axi",    "axi",               base + 0x74, 30);
 859         hws[IMX6QDL_CLK_PCIE_AXI]     = imx_clk_hw_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
 860         hws[IMX6QDL_CLK_PER1_BCH]     = imx_clk_hw_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
 861         hws[IMX6QDL_CLK_PWM1]         = imx_clk_hw_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
 862         hws[IMX6QDL_CLK_PWM2]         = imx_clk_hw_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
 863         hws[IMX6QDL_CLK_PWM3]         = imx_clk_hw_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
 864         hws[IMX6QDL_CLK_PWM4]         = imx_clk_hw_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
 865         hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
 866         hws[IMX6QDL_CLK_GPMI_BCH]     = imx_clk_hw_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
 867         hws[IMX6QDL_CLK_GPMI_IO]      = imx_clk_hw_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
 868         hws[IMX6QDL_CLK_GPMI_APB]     = imx_clk_hw_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
 869         hws[IMX6QDL_CLK_ROM]          = imx_clk_hw_gate2_flags("rom",     "ahb",               base + 0x7c, 0, CLK_IS_CRITICAL);
 870         hws[IMX6QDL_CLK_SATA]         = imx_clk_hw_gate2("sata",          "ahb",               base + 0x7c, 4);
 871         hws[IMX6QDL_CLK_SDMA]         = imx_clk_hw_gate2("sdma",          "ahb",               base + 0x7c, 6);
 872         hws[IMX6QDL_CLK_SPBA]         = imx_clk_hw_gate2("spba",          "ipg",               base + 0x7c, 12);
 873         hws[IMX6QDL_CLK_SPDIF]        = imx_clk_hw_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
 874         hws[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_hw_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
 875         hws[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_hw_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
 876         hws[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_hw_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
 877         hws[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_hw_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
 878         hws[IMX6QDL_CLK_SSI1]         = imx_clk_hw_gate2_shared("ssi1",          "ssi1_podf",  base + 0x7c, 18, &share_count_ssi1);
 879         hws[IMX6QDL_CLK_SSI2]         = imx_clk_hw_gate2_shared("ssi2",          "ssi2_podf",  base + 0x7c, 20, &share_count_ssi2);
 880         hws[IMX6QDL_CLK_SSI3]         = imx_clk_hw_gate2_shared("ssi3",          "ssi3_podf",  base + 0x7c, 22, &share_count_ssi3);
 881         hws[IMX6QDL_CLK_UART_IPG]     = imx_clk_hw_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
 882         hws[IMX6QDL_CLK_UART_SERIAL]  = imx_clk_hw_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
 883         hws[IMX6QDL_CLK_USBOH3]       = imx_clk_hw_gate2("usboh3",        "ipg",               base + 0x80, 0);
 884         hws[IMX6QDL_CLK_USDHC1]       = imx_clk_hw_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
 885         hws[IMX6QDL_CLK_USDHC2]       = imx_clk_hw_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
 886         hws[IMX6QDL_CLK_USDHC3]       = imx_clk_hw_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
 887         hws[IMX6QDL_CLK_USDHC4]       = imx_clk_hw_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
 888         hws[IMX6QDL_CLK_EIM_SLOW]     = imx_clk_hw_gate2("eim_slow",      "eim_slow_podf",     base + 0x80, 10);
 889         hws[IMX6QDL_CLK_VDO_AXI]      = imx_clk_hw_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
 890         hws[IMX6QDL_CLK_VPU_AXI]      = imx_clk_hw_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
 891         if (clk_on_imx6qp()) {
 892                 hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0",               "pre_axi",           base + 0x80, 16);
 893                 hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1",               "pre_axi",           base + 0x80, 18);
 894                 hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2",               "pre_axi",         base + 0x80, 20);
 895                 hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3",               "pre_axi",           base + 0x80, 22);
 896                 hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi",  "ipu1_podf",  base + 0x80, 24, &share_count_prg0);
 897                 hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi",  "ipu2_podf",  base + 0x80, 26, &share_count_prg1);
 898                 hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb",  "ipg",     base + 0x80, 24, &share_count_prg0);
 899                 hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb",  "ipg",     base + 0x80, 26, &share_count_prg1);
 900         }
 901         hws[IMX6QDL_CLK_CKO1]         = imx_clk_hw_gate("cko1",           "cko1_podf",         base + 0x60, 7);
 902         hws[IMX6QDL_CLK_CKO2]         = imx_clk_hw_gate("cko2",           "cko2_podf",         base + 0x60, 24);
 903
 904         /*
 905          * The gpt_3m clock is not available on i.MX6Q TO1.0.  Let's point it
 906          * to clock gpt_ipg_per to ease the gpt driver code.
 907          */
 908         if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
 909                 hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];
 910
 911         imx_check_clk_hws(hws, IMX6QDL_CLK_END);
 912
 913         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
 914
 915         clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
 916
 917         clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000);
 918         if (clk_on_imx6dl())
 919                 clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);
 920
 921         clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
 922         clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
 923         clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
 924         clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
 925         clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk);
 926         clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk);
 927         clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk);
 928         clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk);
 929
 930         /*
 931          * The gpmi needs 100MHz frequency in the EDO/Sync mode,
 932          * We can not get the 100MHz from the pll2_pfd0_352m.
 933          * So choose pll2_pfd2_396m as enfc_sel's parent.
 934          */
 935         clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk);
 936
 937         if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
 938                 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk);
 939                 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk);
 940         }
 941
 942         /*
 943          * Let's initially set up CLKO with OSC24M, since this configuration
 944          * is widely used by imx6q board designs to clock audio codec.
 945          */
 946         ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk);
 947         if (!ret)
 948                 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk);
 949         if (ret)
 950                 pr_warn("failed to set up CLKO: %d\n", ret);
 951
 952         /* Audio-related clocks configuration */
 953         clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk);
 954
 955         /* All existing boards with PCIe use LVDS1 */
 956         if (IS_ENABLED(CONFIG_PCI_IMX6))
 957                 clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk);
 958
 959         /*
 960          * Initialize the GPU clock muxes, so that the maximum specified clock
 961          * rates for the respective SoC are not exceeded.
 962          */
 963         if (clk_on_imx6dl()) {
 964                 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
 965                                hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
 966                 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
 967                                hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
 968         } else if (clk_on_imx6q()) {
 969                 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
 970                                hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);
 971                 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk,
 972                                hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
 973                 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
 974                                hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
 975         }
 976
 977         imx_register_uart_clocks(2);
 978 }
 979 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);