arch/x86/net/bpf_jit_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * bpf_jit_comp.c: BPF JIT compiler
   4  *
   5  * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
   6  * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
   7  */
   8 #include <linux/netdevice.h>
   9 #include <linux/filter.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/bpf.h>
  12 #include <linux/memory.h>
  13 #include <linux/sort.h>
  14 #include <asm/extable.h>
  15 #include <asm/set_memory.h>
  16 #include <asm/nospec-branch.h>
  17 #include <asm/text-patching.h>
  18 #include <asm/asm-prototypes.h>
  19
  20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  21 {
  22         if (len == 1)
  23                 *ptr = bytes;
  24         else if (len == 2)
  25                 *(u16 *)ptr = bytes;
  26         else {
  27                 *(u32 *)ptr = bytes;
  28                 barrier();
  29         }
  30         return ptr + len;
  31 }
  32
  33 #define EMIT(bytes, len) \
  34         do { prog = emit_code(prog, bytes, len); } while (0)
  35
  36 #define EMIT1(b1)               EMIT(b1, 1)
  37 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  38 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  39 #define EMIT4(b1, b2, b3, b4)   EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  40
  41 #define EMIT1_off32(b1, off) \
  42         do { EMIT1(b1); EMIT(off, 4); } while (0)
  43 #define EMIT2_off32(b1, b2, off) \
  44         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  45 #define EMIT3_off32(b1, b2, b3, off) \
  46         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  47 #define EMIT4_off32(b1, b2, b3, b4, off) \
  48         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  49
  50 static bool is_imm8(int value)
  51 {
  52         return value <= 127 && value >= -128;
  53 }
  54
  55 static bool is_simm32(s64 value)
  56 {
  57         return value == (s64)(s32)value;
  58 }
  59
  60 static bool is_uimm32(u64 value)
  61 {
  62         return value == (u64)(u32)value;
  63 }
  64
  65 /* mov dst, src */
  66 #define EMIT_mov(DST, SRC)                                                               \
  67         do {                                                                             \
  68                 if (DST != SRC)                                                          \
  69                         EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
  70         } while (0)
  71
  72 static int bpf_size_to_x86_bytes(int bpf_size)
  73 {
  74         if (bpf_size == BPF_W)
  75                 return 4;
  76         else if (bpf_size == BPF_H)
  77                 return 2;
  78         else if (bpf_size == BPF_B)
  79                 return 1;
  80         else if (bpf_size == BPF_DW)
  81                 return 4; /* imm32 */
  82         else
  83                 return 0;
  84 }
  85
  86 /*
  87  * List of x86 cond jumps opcodes (. + s8)
  88  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
  89  */
  90 #define X86_JB  0x72
  91 #define X86_JAE 0x73
  92 #define X86_JE  0x74
  93 #define X86_JNE 0x75
  94 #define X86_JBE 0x76
  95 #define X86_JA  0x77
  96 #define X86_JL  0x7C
  97 #define X86_JGE 0x7D
  98 #define X86_JLE 0x7E
  99 #define X86_JG  0x7F
 100
 101 /* Pick a register outside of BPF range for JIT internal work */
 102 #define AUX_REG (MAX_BPF_JIT_REG + 1)
 103 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
 104
 105 /*
 106  * The following table maps BPF registers to x86-64 registers.
 107  *
 108  * x86-64 register R12 is unused, since if used as base address
 109  * register in load/store instructions, it always needs an
 110  * extra byte of encoding and is callee saved.
 111  *
 112  * x86-64 register R9 is not used by BPF programs, but can be used by BPF
 113  * trampoline. x86-64 register R10 is used for blinding (if enabled).
 114  */
 115 static const int reg2hex[] = {
 116         [BPF_REG_0] = 0,  /* RAX */
 117         [BPF_REG_1] = 7,  /* RDI */
 118         [BPF_REG_2] = 6,  /* RSI */
 119         [BPF_REG_3] = 2,  /* RDX */
 120         [BPF_REG_4] = 1,  /* RCX */
 121         [BPF_REG_5] = 0,  /* R8  */
 122         [BPF_REG_6] = 3,  /* RBX callee saved */
 123         [BPF_REG_7] = 5,  /* R13 callee saved */
 124         [BPF_REG_8] = 6,  /* R14 callee saved */
 125         [BPF_REG_9] = 7,  /* R15 callee saved */
 126         [BPF_REG_FP] = 5, /* RBP readonly */
 127         [BPF_REG_AX] = 2, /* R10 temp register */
 128         [AUX_REG] = 3,    /* R11 temp register */
 129         [X86_REG_R9] = 1, /* R9 register, 6th function argument */
 130 };
 131
 132 static const int reg2pt_regs[] = {
 133         [BPF_REG_0] = offsetof(struct pt_regs, ax),
 134         [BPF_REG_1] = offsetof(struct pt_regs, di),
 135         [BPF_REG_2] = offsetof(struct pt_regs, si),
 136         [BPF_REG_3] = offsetof(struct pt_regs, dx),
 137         [BPF_REG_4] = offsetof(struct pt_regs, cx),
 138         [BPF_REG_5] = offsetof(struct pt_regs, r8),
 139         [BPF_REG_6] = offsetof(struct pt_regs, bx),
 140         [BPF_REG_7] = offsetof(struct pt_regs, r13),
 141         [BPF_REG_8] = offsetof(struct pt_regs, r14),
 142         [BPF_REG_9] = offsetof(struct pt_regs, r15),
 143 };
 144
 145 /*
 146  * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
 147  * which need extra byte of encoding.
 148  * rax,rcx,...,rbp have simpler encoding
 149  */
 150 static bool is_ereg(u32 reg)
 151 {
 152         return (1 << reg) & (BIT(BPF_REG_5) |
 153                              BIT(AUX_REG) |
 154                              BIT(BPF_REG_7) |
 155                              BIT(BPF_REG_8) |
 156                              BIT(BPF_REG_9) |
 157                              BIT(X86_REG_R9) |
 158                              BIT(BPF_REG_AX));
 159 }
 160
 161 /*
 162  * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
 163  * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
 164  * of encoding. al,cl,dl,bl have simpler encoding.
 165  */
 166 static bool is_ereg_8l(u32 reg)
 167 {
 168         return is_ereg(reg) ||
 169             (1 << reg) & (BIT(BPF_REG_1) |
 170                           BIT(BPF_REG_2) |
 171                           BIT(BPF_REG_FP));
 172 }
 173
 174 static bool is_axreg(u32 reg)
 175 {
 176         return reg == BPF_REG_0;
 177 }
 178
 179 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
 180 static u8 add_1mod(u8 byte, u32 reg)
 181 {
 182         if (is_ereg(reg))
 183                 byte |= 1;
 184         return byte;
 185 }
 186
 187 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
 188 {
 189         if (is_ereg(r1))
 190                 byte |= 1;
 191         if (is_ereg(r2))
 192                 byte |= 4;
 193         return byte;
 194 }
 195
 196 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
 197 static u8 add_1reg(u8 byte, u32 dst_reg)
 198 {
 199         return byte + reg2hex[dst_reg];
 200 }
 201
 202 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
 203 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 204 {
 205         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 206 }
 207
 208 /* Some 1-byte opcodes for binary ALU operations */
 209 static u8 simple_alu_opcodes[] = {
 210         [BPF_ADD] = 0x01,
 211         [BPF_SUB] = 0x29,
 212         [BPF_AND] = 0x21,
 213         [BPF_OR] = 0x09,
 214         [BPF_XOR] = 0x31,
 215         [BPF_LSH] = 0xE0,
 216         [BPF_RSH] = 0xE8,
 217         [BPF_ARSH] = 0xF8,
 218 };
 219
 220 static void jit_fill_hole(void *area, unsigned int size)
 221 {
 222         /* Fill whole space with INT3 instructions */
 223         memset(area, 0xcc, size);
 224 }
 225
 226 struct jit_context {
 227         int cleanup_addr; /* Epilogue code offset */
 228 };
 229
 230 /* Maximum number of bytes emitted while JITing one eBPF insn */
 231 #define BPF_MAX_INSN_SIZE       128
 232 #define BPF_INSN_SAFETY         64
 233
 234 /* Number of bytes emit_patch() needs to generate instructions */
 235 #define X86_PATCH_SIZE          5
 236 /* Number of bytes that will be skipped on tailcall */
 237 #define X86_TAIL_CALL_OFFSET    11
 238
 239 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
 240 {
 241         u8 *prog = *pprog;
 242
 243         if (callee_regs_used[0])
 244                 EMIT1(0x53);         /* push rbx */
 245         if (callee_regs_used[1])
 246                 EMIT2(0x41, 0x55);   /* push r13 */
 247         if (callee_regs_used[2])
 248                 EMIT2(0x41, 0x56);   /* push r14 */
 249         if (callee_regs_used[3])
 250                 EMIT2(0x41, 0x57);   /* push r15 */
 251         *pprog = prog;
 252 }
 253
 254 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
 255 {
 256         u8 *prog = *pprog;
 257
 258         if (callee_regs_used[3])
 259                 EMIT2(0x41, 0x5F);   /* pop r15 */
 260         if (callee_regs_used[2])
 261                 EMIT2(0x41, 0x5E);   /* pop r14 */
 262         if (callee_regs_used[1])
 263                 EMIT2(0x41, 0x5D);   /* pop r13 */
 264         if (callee_regs_used[0])
 265                 EMIT1(0x5B);         /* pop rbx */
 266         *pprog = prog;
 267 }
 268
 269 /*
 270  * Emit x86-64 prologue code for BPF program.
 271  * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
 272  * while jumping to another program
 273  */
 274 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
 275                           bool tail_call_reachable, bool is_subprog)
 276 {
 277         u8 *prog = *pprog;
 278
 279         /* BPF trampoline can be made to work without these nops,
 280          * but let's waste 5 bytes for now and optimize later
 281          */
 282         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 283         prog += X86_PATCH_SIZE;
 284         if (!ebpf_from_cbpf) {
 285                 if (tail_call_reachable && !is_subprog)
 286                         EMIT2(0x31, 0xC0); /* xor eax, eax */
 287                 else
 288                         EMIT2(0x66, 0x90); /* nop2 */
 289         }
 290         EMIT1(0x55);             /* push rbp */
 291         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
 292         /* sub rsp, rounded_stack_depth */
 293         if (stack_depth)
 294                 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
 295         if (tail_call_reachable)
 296                 EMIT1(0x50);         /* push rax */
 297         *pprog = prog;
 298 }
 299
 300 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
 301 {
 302         u8 *prog = *pprog;
 303         s64 offset;
 304
 305         offset = func - (ip + X86_PATCH_SIZE);
 306         if (!is_simm32(offset)) {
 307                 pr_err("Target call %p is out of range\n", func);
 308                 return -ERANGE;
 309         }
 310         EMIT1_off32(opcode, offset);
 311         *pprog = prog;
 312         return 0;
 313 }
 314
 315 static int emit_call(u8 **pprog, void *func, void *ip)
 316 {
 317         return emit_patch(pprog, func, ip, 0xE8);
 318 }
 319
 320 static int emit_jump(u8 **pprog, void *func, void *ip)
 321 {
 322         return emit_patch(pprog, func, ip, 0xE9);
 323 }
 324
 325 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 326                                 void *old_addr, void *new_addr,
 327                                 const bool text_live)
 328 {
 329         const u8 *nop_insn = x86_nops[5];
 330         u8 old_insn[X86_PATCH_SIZE];
 331         u8 new_insn[X86_PATCH_SIZE];
 332         u8 *prog;
 333         int ret;
 334
 335         memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
 336         if (old_addr) {
 337                 prog = old_insn;
 338                 ret = t == BPF_MOD_CALL ?
 339                       emit_call(&prog, old_addr, ip) :
 340                       emit_jump(&prog, old_addr, ip);
 341                 if (ret)
 342                         return ret;
 343         }
 344
 345         memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
 346         if (new_addr) {
 347                 prog = new_insn;
 348                 ret = t == BPF_MOD_CALL ?
 349                       emit_call(&prog, new_addr, ip) :
 350                       emit_jump(&prog, new_addr, ip);
 351                 if (ret)
 352                         return ret;
 353         }
 354
 355         ret = -EBUSY;
 356         mutex_lock(&text_mutex);
 357         if (memcmp(ip, old_insn, X86_PATCH_SIZE))
 358                 goto out;
 359         ret = 1;
 360         if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
 361                 if (text_live)
 362                         text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
 363                 else
 364                         memcpy(ip, new_insn, X86_PATCH_SIZE);
 365                 ret = 0;
 366         }
 367 out:
 368         mutex_unlock(&text_mutex);
 369         return ret;
 370 }
 371
 372 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 373                        void *old_addr, void *new_addr)
 374 {
 375         if (!is_kernel_text((long)ip) &&
 376             !is_bpf_text_address((long)ip))
 377                 /* BPF poking in modules is not supported */
 378                 return -EINVAL;
 379
 380         return __bpf_arch_text_poke(ip, t, old_addr, new_addr, true);
 381 }
 382
 383 static int get_pop_bytes(bool *callee_regs_used)
 384 {
 385         int bytes = 0;
 386
 387         if (callee_regs_used[3])
 388                 bytes += 2;
 389         if (callee_regs_used[2])
 390                 bytes += 2;
 391         if (callee_regs_used[1])
 392                 bytes += 2;
 393         if (callee_regs_used[0])
 394                 bytes += 1;
 395
 396         return bytes;
 397 }
 398
 399 /*
 400  * Generate the following code:
 401  *
 402  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
 403  *   if (index >= array->map.max_entries)
 404  *     goto out;
 405  *   if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
 406  *     goto out;
 407  *   prog = array->ptrs[index];
 408  *   if (prog == NULL)
 409  *     goto out;
 410  *   goto *(prog->bpf_func + prologue_size);
 411  * out:
 412  */
 413 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
 414                                         u32 stack_depth)
 415 {
 416         int tcc_off = -4 - round_up(stack_depth, 8);
 417         u8 *prog = *pprog;
 418         int pop_bytes = 0;
 419         int off1 = 42;
 420         int off2 = 31;
 421         int off3 = 9;
 422
 423         /* count the additional bytes used for popping callee regs from stack
 424          * that need to be taken into account for each of the offsets that
 425          * are used for bailing out of the tail call
 426          */
 427         pop_bytes = get_pop_bytes(callee_regs_used);
 428         off1 += pop_bytes;
 429         off2 += pop_bytes;
 430         off3 += pop_bytes;
 431
 432         if (stack_depth) {
 433                 off1 += 7;
 434                 off2 += 7;
 435                 off3 += 7;
 436         }
 437
 438         /*
 439          * rdi - pointer to ctx
 440          * rsi - pointer to bpf_array
 441          * rdx - index in bpf_array
 442          */
 443
 444         /*
 445          * if (index >= array->map.max_entries)
 446          *      goto out;
 447          */
 448         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
 449         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 450               offsetof(struct bpf_array, map.max_entries));
 451 #define OFFSET1 (off1 + RETPOLINE_RCX_BPF_JIT_SIZE) /* Number of bytes to jump */
 452         EMIT2(X86_JBE, OFFSET1);                  /* jbe out */
 453
 454         /*
 455          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
 456          *      goto out;
 457          */
 458         EMIT2_off32(0x8B, 0x85, tcc_off);         /* mov eax, dword ptr [rbp - tcc_off] */
 459         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
 460 #define OFFSET2 (off2 + RETPOLINE_RCX_BPF_JIT_SIZE)
 461         EMIT2(X86_JA, OFFSET2);                   /* ja out */
 462         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
 463         EMIT2_off32(0x89, 0x85, tcc_off);         /* mov dword ptr [rbp - tcc_off], eax */
 464
 465         /* prog = array->ptrs[index]; */
 466         EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6,       /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
 467                     offsetof(struct bpf_array, ptrs));
 468
 469         /*
 470          * if (prog == NULL)
 471          *      goto out;
 472          */
 473         EMIT3(0x48, 0x85, 0xC9);                  /* test rcx,rcx */
 474 #define OFFSET3 (off3 + RETPOLINE_RCX_BPF_JIT_SIZE)
 475         EMIT2(X86_JE, OFFSET3);                   /* je out */
 476
 477         *pprog = prog;
 478         pop_callee_regs(pprog, callee_regs_used);
 479         prog = *pprog;
 480
 481         EMIT1(0x58);                              /* pop rax */
 482         if (stack_depth)
 483                 EMIT3_off32(0x48, 0x81, 0xC4,     /* add rsp, sd */
 484                             round_up(stack_depth, 8));
 485
 486         /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
 487         EMIT4(0x48, 0x8B, 0x49,                   /* mov rcx, qword ptr [rcx + 32] */
 488               offsetof(struct bpf_prog, bpf_func));
 489         EMIT4(0x48, 0x83, 0xC1,                   /* add rcx, X86_TAIL_CALL_OFFSET */
 490               X86_TAIL_CALL_OFFSET);
 491         /*
 492          * Now we're ready to jump into next BPF program
 493          * rdi == ctx (1st arg)
 494          * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
 495          */
 496         RETPOLINE_RCX_BPF_JIT();
 497
 498         /* out: */
 499         *pprog = prog;
 500 }
 501
 502 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
 503                                       u8 **pprog, int addr, u8 *image,
 504                                       bool *callee_regs_used, u32 stack_depth)
 505 {
 506         int tcc_off = -4 - round_up(stack_depth, 8);
 507         u8 *prog = *pprog;
 508         int pop_bytes = 0;
 509         int off1 = 20;
 510         int poke_off;
 511
 512         /* count the additional bytes used for popping callee regs to stack
 513          * that need to be taken into account for jump offset that is used for
 514          * bailing out from of the tail call when limit is reached
 515          */
 516         pop_bytes = get_pop_bytes(callee_regs_used);
 517         off1 += pop_bytes;
 518
 519         /*
 520          * total bytes for:
 521          * - nop5/ jmpq $off
 522          * - pop callee regs
 523          * - sub rsp, $val if depth > 0
 524          * - pop rax
 525          */
 526         poke_off = X86_PATCH_SIZE + pop_bytes + 1;
 527         if (stack_depth) {
 528                 poke_off += 7;
 529                 off1 += 7;
 530         }
 531
 532         /*
 533          * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
 534          *      goto out;
 535          */
 536         EMIT2_off32(0x8B, 0x85, tcc_off);             /* mov eax, dword ptr [rbp - tcc_off] */
 537         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);         /* cmp eax, MAX_TAIL_CALL_CNT */
 538         EMIT2(X86_JA, off1);                          /* ja out */
 539         EMIT3(0x83, 0xC0, 0x01);                      /* add eax, 1 */
 540         EMIT2_off32(0x89, 0x85, tcc_off);             /* mov dword ptr [rbp - tcc_off], eax */
 541
 542         poke->tailcall_bypass = image + (addr - poke_off - X86_PATCH_SIZE);
 543         poke->adj_off = X86_TAIL_CALL_OFFSET;
 544         poke->tailcall_target = image + (addr - X86_PATCH_SIZE);
 545         poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
 546
 547         emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
 548                   poke->tailcall_bypass);
 549
 550         *pprog = prog;
 551         pop_callee_regs(pprog, callee_regs_used);
 552         prog = *pprog;
 553         EMIT1(0x58);                                  /* pop rax */
 554         if (stack_depth)
 555                 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
 556
 557         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 558         prog += X86_PATCH_SIZE;
 559         /* out: */
 560
 561         *pprog = prog;
 562 }
 563
 564 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
 565 {
 566         struct bpf_jit_poke_descriptor *poke;
 567         struct bpf_array *array;
 568         struct bpf_prog *target;
 569         int i, ret;
 570
 571         for (i = 0; i < prog->aux->size_poke_tab; i++) {
 572                 poke = &prog->aux->poke_tab[i];
 573                 if (poke->aux && poke->aux != prog->aux)
 574                         continue;
 575
 576                 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
 577
 578                 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
 579                         continue;
 580
 581                 array = container_of(poke->tail_call.map, struct bpf_array, map);
 582                 mutex_lock(&array->aux->poke_mutex);
 583                 target = array->ptrs[poke->tail_call.key];
 584                 if (target) {
 585                         /* Plain memcpy is used when image is not live yet
 586                          * and still not locked as read-only. Once poke
 587                          * location is active (poke->tailcall_target_stable),
 588                          * any parallel bpf_arch_text_poke() might occur
 589                          * still on the read-write image until we finally
 590                          * locked it as read-only. Both modifications on
 591                          * the given image are under text_mutex to avoid
 592                          * interference.
 593                          */
 594                         ret = __bpf_arch_text_poke(poke->tailcall_target,
 595                                                    BPF_MOD_JUMP, NULL,
 596                                                    (u8 *)target->bpf_func +
 597                                                    poke->adj_off, false);
 598                         BUG_ON(ret < 0);
 599                         ret = __bpf_arch_text_poke(poke->tailcall_bypass,
 600                                                    BPF_MOD_JUMP,
 601                                                    (u8 *)poke->tailcall_target +
 602                                                    X86_PATCH_SIZE, NULL, false);
 603                         BUG_ON(ret < 0);
 604                 }
 605                 WRITE_ONCE(poke->tailcall_target_stable, true);
 606                 mutex_unlock(&array->aux->poke_mutex);
 607         }
 608 }
 609
 610 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
 611                            u32 dst_reg, const u32 imm32)
 612 {
 613         u8 *prog = *pprog;
 614         u8 b1, b2, b3;
 615
 616         /*
 617          * Optimization: if imm32 is positive, use 'mov %eax, imm32'
 618          * (which zero-extends imm32) to save 2 bytes.
 619          */
 620         if (sign_propagate && (s32)imm32 < 0) {
 621                 /* 'mov %rax, imm32' sign extends imm32 */
 622                 b1 = add_1mod(0x48, dst_reg);
 623                 b2 = 0xC7;
 624                 b3 = 0xC0;
 625                 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
 626                 goto done;
 627         }
 628
 629         /*
 630          * Optimization: if imm32 is zero, use 'xor %eax, %eax'
 631          * to save 3 bytes.
 632          */
 633         if (imm32 == 0) {
 634                 if (is_ereg(dst_reg))
 635                         EMIT1(add_2mod(0x40, dst_reg, dst_reg));
 636                 b2 = 0x31; /* xor */
 637                 b3 = 0xC0;
 638                 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
 639                 goto done;
 640         }
 641
 642         /* mov %eax, imm32 */
 643         if (is_ereg(dst_reg))
 644                 EMIT1(add_1mod(0x40, dst_reg));
 645         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
 646 done:
 647         *pprog = prog;
 648 }
 649
 650 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
 651                            const u32 imm32_hi, const u32 imm32_lo)
 652 {
 653         u8 *prog = *pprog;
 654
 655         if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
 656                 /*
 657                  * For emitting plain u32, where sign bit must not be
 658                  * propagated LLVM tends to load imm64 over mov32
 659                  * directly, so save couple of bytes by just doing
 660                  * 'mov %eax, imm32' instead.
 661                  */
 662                 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
 663         } else {
 664                 /* movabsq %rax, imm64 */
 665                 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
 666                 EMIT(imm32_lo, 4);
 667                 EMIT(imm32_hi, 4);
 668         }
 669
 670         *pprog = prog;
 671 }
 672
 673 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
 674 {
 675         u8 *prog = *pprog;
 676
 677         if (is64) {
 678                 /* mov dst, src */
 679                 EMIT_mov(dst_reg, src_reg);
 680         } else {
 681                 /* mov32 dst, src */
 682                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 683                         EMIT1(add_2mod(0x40, dst_reg, src_reg));
 684                 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
 685         }
 686
 687         *pprog = prog;
 688 }
 689
 690 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
 691 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
 692 {
 693         u8 *prog = *pprog;
 694
 695         if (is_imm8(off)) {
 696                 /* 1-byte signed displacement.
 697                  *
 698                  * If off == 0 we could skip this and save one extra byte, but
 699                  * special case of x86 R13 which always needs an offset is not
 700                  * worth the hassle
 701                  */
 702                 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
 703         } else {
 704                 /* 4-byte signed displacement */
 705                 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
 706         }
 707         *pprog = prog;
 708 }
 709
 710 /*
 711  * Emit a REX byte if it will be necessary to address these registers
 712  */
 713 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
 714 {
 715         u8 *prog = *pprog;
 716
 717         if (is64)
 718                 EMIT1(add_2mod(0x48, dst_reg, src_reg));
 719         else if (is_ereg(dst_reg) || is_ereg(src_reg))
 720                 EMIT1(add_2mod(0x40, dst_reg, src_reg));
 721         *pprog = prog;
 722 }
 723
 724 /* LDX: dst_reg = *(u8*)(src_reg + off) */
 725 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 726 {
 727         u8 *prog = *pprog;
 728
 729         switch (size) {
 730         case BPF_B:
 731                 /* Emit 'movzx rax, byte ptr [rax + off]' */
 732                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
 733                 break;
 734         case BPF_H:
 735                 /* Emit 'movzx rax, word ptr [rax + off]' */
 736                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
 737                 break;
 738         case BPF_W:
 739                 /* Emit 'mov eax, dword ptr [rax+0x14]' */
 740                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 741                         EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
 742                 else
 743                         EMIT1(0x8B);
 744                 break;
 745         case BPF_DW:
 746                 /* Emit 'mov rax, qword ptr [rax+0x14]' */
 747                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
 748                 break;
 749         }
 750         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 751         *pprog = prog;
 752 }
 753
 754 /* STX: *(u8*)(dst_reg + off) = src_reg */
 755 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 756 {
 757         u8 *prog = *pprog;
 758
 759         switch (size) {
 760         case BPF_B:
 761                 /* Emit 'mov byte ptr [rax + off], al' */
 762                 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
 763                         /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
 764                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
 765                 else
 766                         EMIT1(0x88);
 767                 break;
 768         case BPF_H:
 769                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 770                         EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
 771                 else
 772                         EMIT2(0x66, 0x89);
 773                 break;
 774         case BPF_W:
 775                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 776                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
 777                 else
 778                         EMIT1(0x89);
 779                 break;
 780         case BPF_DW:
 781                 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
 782                 break;
 783         }
 784         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 785         *pprog = prog;
 786 }
 787
 788 static int emit_atomic(u8 **pprog, u8 atomic_op,
 789                        u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
 790 {
 791         u8 *prog = *pprog;
 792
 793         EMIT1(0xF0); /* lock prefix */
 794
 795         maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
 796
 797         /* emit opcode */
 798         switch (atomic_op) {
 799         case BPF_ADD:
 800         case BPF_SUB:
 801         case BPF_AND:
 802         case BPF_OR:
 803         case BPF_XOR:
 804                 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
 805                 EMIT1(simple_alu_opcodes[atomic_op]);
 806                 break;
 807         case BPF_ADD | BPF_FETCH:
 808                 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
 809                 EMIT2(0x0F, 0xC1);
 810                 break;
 811         case BPF_XCHG:
 812                 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
 813                 EMIT1(0x87);
 814                 break;
 815         case BPF_CMPXCHG:
 816                 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
 817                 EMIT2(0x0F, 0xB1);
 818                 break;
 819         default:
 820                 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
 821                 return -EFAULT;
 822         }
 823
 824         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 825
 826         *pprog = prog;
 827         return 0;
 828 }
 829
 830 static bool ex_handler_bpf(const struct exception_table_entry *x,
 831                            struct pt_regs *regs, int trapnr,
 832                            unsigned long error_code, unsigned long fault_addr)
 833 {
 834         u32 reg = x->fixup >> 8;
 835
 836         /* jump over faulting load and clear dest register */
 837         *(unsigned long *)((void *)regs + reg) = 0;
 838         regs->ip += x->fixup & 0xff;
 839         return true;
 840 }
 841
 842 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
 843                              bool *regs_used, bool *tail_call_seen)
 844 {
 845         int i;
 846
 847         for (i = 1; i <= insn_cnt; i++, insn++) {
 848                 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
 849                         *tail_call_seen = true;
 850                 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
 851                         regs_used[0] = true;
 852                 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
 853                         regs_used[1] = true;
 854                 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
 855                         regs_used[2] = true;
 856                 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
 857                         regs_used[3] = true;
 858         }
 859 }
 860
 861 static void emit_nops(u8 **pprog, int len)
 862 {
 863         u8 *prog = *pprog;
 864         int i, noplen;
 865
 866         while (len > 0) {
 867                 noplen = len;
 868
 869                 if (noplen > ASM_NOP_MAX)
 870                         noplen = ASM_NOP_MAX;
 871
 872                 for (i = 0; i < noplen; i++)
 873                         EMIT1(x86_nops[noplen][i]);
 874                 len -= noplen;
 875         }
 876
 877         *pprog = prog;
 878 }
 879
 880 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
 881
 882 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
 883                   int oldproglen, struct jit_context *ctx, bool jmp_padding)
 884 {
 885         bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
 886         struct bpf_insn *insn = bpf_prog->insnsi;
 887         bool callee_regs_used[4] = {};
 888         int insn_cnt = bpf_prog->len;
 889         bool tail_call_seen = false;
 890         bool seen_exit = false;
 891         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
 892         int i, excnt = 0;
 893         int ilen, proglen = 0;
 894         u8 *prog = temp;
 895         int err;
 896
 897         detect_reg_usage(insn, insn_cnt, callee_regs_used,
 898                          &tail_call_seen);
 899
 900         /* tail call's presence in current prog implies it is reachable */
 901         tail_call_reachable |= tail_call_seen;
 902
 903         emit_prologue(&prog, bpf_prog->aux->stack_depth,
 904                       bpf_prog_was_classic(bpf_prog), tail_call_reachable,
 905                       bpf_prog->aux->func_idx != 0);
 906         push_callee_regs(&prog, callee_regs_used);
 907
 908         ilen = prog - temp;
 909         if (image)
 910                 memcpy(image + proglen, temp, ilen);
 911         proglen += ilen;
 912         addrs[0] = proglen;
 913         prog = temp;
 914
 915         for (i = 1; i <= insn_cnt; i++, insn++) {
 916                 const s32 imm32 = insn->imm;
 917                 u32 dst_reg = insn->dst_reg;
 918                 u32 src_reg = insn->src_reg;
 919                 u8 b2 = 0, b3 = 0;
 920                 u8 *start_of_ldx;
 921                 s64 jmp_offset;
 922                 u8 jmp_cond;
 923                 u8 *func;
 924                 int nops;
 925
 926                 switch (insn->code) {
 927                         /* ALU */
 928                 case BPF_ALU | BPF_ADD | BPF_X:
 929                 case BPF_ALU | BPF_SUB | BPF_X:
 930                 case BPF_ALU | BPF_AND | BPF_X:
 931                 case BPF_ALU | BPF_OR | BPF_X:
 932                 case BPF_ALU | BPF_XOR | BPF_X:
 933                 case BPF_ALU64 | BPF_ADD | BPF_X:
 934                 case BPF_ALU64 | BPF_SUB | BPF_X:
 935                 case BPF_ALU64 | BPF_AND | BPF_X:
 936                 case BPF_ALU64 | BPF_OR | BPF_X:
 937                 case BPF_ALU64 | BPF_XOR | BPF_X:
 938                         maybe_emit_mod(&prog, dst_reg, src_reg,
 939                                        BPF_CLASS(insn->code) == BPF_ALU64);
 940                         b2 = simple_alu_opcodes[BPF_OP(insn->code)];
 941                         EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
 942                         break;
 943
 944                 case BPF_ALU64 | BPF_MOV | BPF_X:
 945                 case BPF_ALU | BPF_MOV | BPF_X:
 946                         emit_mov_reg(&prog,
 947                                      BPF_CLASS(insn->code) == BPF_ALU64,
 948                                      dst_reg, src_reg);
 949                         break;
 950
 951                         /* neg dst */
 952                 case BPF_ALU | BPF_NEG:
 953                 case BPF_ALU64 | BPF_NEG:
 954                         if (BPF_CLASS(insn->code) == BPF_ALU64)
 955                                 EMIT1(add_1mod(0x48, dst_reg));
 956                         else if (is_ereg(dst_reg))
 957                                 EMIT1(add_1mod(0x40, dst_reg));
 958                         EMIT2(0xF7, add_1reg(0xD8, dst_reg));
 959                         break;
 960
 961                 case BPF_ALU | BPF_ADD | BPF_K:
 962                 case BPF_ALU | BPF_SUB | BPF_K:
 963                 case BPF_ALU | BPF_AND | BPF_K:
 964                 case BPF_ALU | BPF_OR | BPF_K:
 965                 case BPF_ALU | BPF_XOR | BPF_K:
 966                 case BPF_ALU64 | BPF_ADD | BPF_K:
 967                 case BPF_ALU64 | BPF_SUB | BPF_K:
 968                 case BPF_ALU64 | BPF_AND | BPF_K:
 969                 case BPF_ALU64 | BPF_OR | BPF_K:
 970                 case BPF_ALU64 | BPF_XOR | BPF_K:
 971                         if (BPF_CLASS(insn->code) == BPF_ALU64)
 972                                 EMIT1(add_1mod(0x48, dst_reg));
 973                         else if (is_ereg(dst_reg))
 974                                 EMIT1(add_1mod(0x40, dst_reg));
 975
 976                         /*
 977                          * b3 holds 'normal' opcode, b2 short form only valid
 978                          * in case dst is eax/rax.
 979                          */
 980                         switch (BPF_OP(insn->code)) {
 981                         case BPF_ADD:
 982                                 b3 = 0xC0;
 983                                 b2 = 0x05;
 984                                 break;
 985                         case BPF_SUB:
 986                                 b3 = 0xE8;
 987                                 b2 = 0x2D;
 988                                 break;
 989                         case BPF_AND:
 990                                 b3 = 0xE0;
 991                                 b2 = 0x25;
 992                                 break;
 993                         case BPF_OR:
 994                                 b3 = 0xC8;
 995                                 b2 = 0x0D;
 996                                 break;
 997                         case BPF_XOR:
 998                                 b3 = 0xF0;
 999                                 b2 = 0x35;
1000                                 break;
1001                         }
1002
1003                         if (is_imm8(imm32))
1004                                 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1005                         else if (is_axreg(dst_reg))
1006                                 EMIT1_off32(b2, imm32);
1007                         else
1008                                 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1009                         break;
1010
1011                 case BPF_ALU64 | BPF_MOV | BPF_K:
1012                 case BPF_ALU | BPF_MOV | BPF_K:
1013                         emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1014                                        dst_reg, imm32);
1015                         break;
1016
1017                 case BPF_LD | BPF_IMM | BPF_DW:
1018                         emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1019                         insn++;
1020                         i++;
1021                         break;
1022
1023                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1024                 case BPF_ALU | BPF_MOD | BPF_X:
1025                 case BPF_ALU | BPF_DIV | BPF_X:
1026                 case BPF_ALU | BPF_MOD | BPF_K:
1027                 case BPF_ALU | BPF_DIV | BPF_K:
1028                 case BPF_ALU64 | BPF_MOD | BPF_X:
1029                 case BPF_ALU64 | BPF_DIV | BPF_X:
1030                 case BPF_ALU64 | BPF_MOD | BPF_K:
1031                 case BPF_ALU64 | BPF_DIV | BPF_K:
1032                         EMIT1(0x50); /* push rax */
1033                         EMIT1(0x52); /* push rdx */
1034
1035                         if (BPF_SRC(insn->code) == BPF_X)
1036                                 /* mov r11, src_reg */
1037                                 EMIT_mov(AUX_REG, src_reg);
1038                         else
1039                                 /* mov r11, imm32 */
1040                                 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1041
1042                         /* mov rax, dst_reg */
1043                         EMIT_mov(BPF_REG_0, dst_reg);
1044
1045                         /*
1046                          * xor edx, edx
1047                          * equivalent to 'xor rdx, rdx', but one byte less
1048                          */
1049                         EMIT2(0x31, 0xd2);
1050
1051                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1052                                 /* div r11 */
1053                                 EMIT3(0x49, 0xF7, 0xF3);
1054                         else
1055                                 /* div r11d */
1056                                 EMIT3(0x41, 0xF7, 0xF3);
1057
1058                         if (BPF_OP(insn->code) == BPF_MOD)
1059                                 /* mov r11, rdx */
1060                                 EMIT3(0x49, 0x89, 0xD3);
1061                         else
1062                                 /* mov r11, rax */
1063                                 EMIT3(0x49, 0x89, 0xC3);
1064
1065                         EMIT1(0x5A); /* pop rdx */
1066                         EMIT1(0x58); /* pop rax */
1067
1068                         /* mov dst_reg, r11 */
1069                         EMIT_mov(dst_reg, AUX_REG);
1070                         break;
1071
1072                 case BPF_ALU | BPF_MUL | BPF_K:
1073                 case BPF_ALU | BPF_MUL | BPF_X:
1074                 case BPF_ALU64 | BPF_MUL | BPF_K:
1075                 case BPF_ALU64 | BPF_MUL | BPF_X:
1076                 {
1077                         bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1078
1079                         if (dst_reg != BPF_REG_0)
1080                                 EMIT1(0x50); /* push rax */
1081                         if (dst_reg != BPF_REG_3)
1082                                 EMIT1(0x52); /* push rdx */
1083
1084                         /* mov r11, dst_reg */
1085                         EMIT_mov(AUX_REG, dst_reg);
1086
1087                         if (BPF_SRC(insn->code) == BPF_X)
1088                                 emit_mov_reg(&prog, is64, BPF_REG_0, src_reg);
1089                         else
1090                                 emit_mov_imm32(&prog, is64, BPF_REG_0, imm32);
1091
1092                         if (is64)
1093                                 EMIT1(add_1mod(0x48, AUX_REG));
1094                         else if (is_ereg(AUX_REG))
1095                                 EMIT1(add_1mod(0x40, AUX_REG));
1096                         /* mul(q) r11 */
1097                         EMIT2(0xF7, add_1reg(0xE0, AUX_REG));
1098
1099                         if (dst_reg != BPF_REG_3)
1100                                 EMIT1(0x5A); /* pop rdx */
1101                         if (dst_reg != BPF_REG_0) {
1102                                 /* mov dst_reg, rax */
1103                                 EMIT_mov(dst_reg, BPF_REG_0);
1104                                 EMIT1(0x58); /* pop rax */
1105                         }
1106                         break;
1107                 }
1108                         /* Shifts */
1109                 case BPF_ALU | BPF_LSH | BPF_K:
1110                 case BPF_ALU | BPF_RSH | BPF_K:
1111                 case BPF_ALU | BPF_ARSH | BPF_K:
1112                 case BPF_ALU64 | BPF_LSH | BPF_K:
1113                 case BPF_ALU64 | BPF_RSH | BPF_K:
1114                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1115                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1116                                 EMIT1(add_1mod(0x48, dst_reg));
1117                         else if (is_ereg(dst_reg))
1118                                 EMIT1(add_1mod(0x40, dst_reg));
1119
1120                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1121                         if (imm32 == 1)
1122                                 EMIT2(0xD1, add_1reg(b3, dst_reg));
1123                         else
1124                                 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1125                         break;
1126
1127                 case BPF_ALU | BPF_LSH | BPF_X:
1128                 case BPF_ALU | BPF_RSH | BPF_X:
1129                 case BPF_ALU | BPF_ARSH | BPF_X:
1130                 case BPF_ALU64 | BPF_LSH | BPF_X:
1131                 case BPF_ALU64 | BPF_RSH | BPF_X:
1132                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1133
1134                         /* Check for bad case when dst_reg == rcx */
1135                         if (dst_reg == BPF_REG_4) {
1136                                 /* mov r11, dst_reg */
1137                                 EMIT_mov(AUX_REG, dst_reg);
1138                                 dst_reg = AUX_REG;
1139                         }
1140
1141                         if (src_reg != BPF_REG_4) { /* common case */
1142                                 EMIT1(0x51); /* push rcx */
1143
1144                                 /* mov rcx, src_reg */
1145                                 EMIT_mov(BPF_REG_4, src_reg);
1146                         }
1147
1148                         /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1149                         if (BPF_CLASS(insn->code) == BPF_ALU64)
1150                                 EMIT1(add_1mod(0x48, dst_reg));
1151                         else if (is_ereg(dst_reg))
1152                                 EMIT1(add_1mod(0x40, dst_reg));
1153
1154                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1155                         EMIT2(0xD3, add_1reg(b3, dst_reg));
1156
1157                         if (src_reg != BPF_REG_4)
1158                                 EMIT1(0x59); /* pop rcx */
1159
1160                         if (insn->dst_reg == BPF_REG_4)
1161                                 /* mov dst_reg, r11 */
1162                                 EMIT_mov(insn->dst_reg, AUX_REG);
1163                         break;
1164
1165                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1166                         switch (imm32) {
1167                         case 16:
1168                                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1169                                 EMIT1(0x66);
1170                                 if (is_ereg(dst_reg))
1171                                         EMIT1(0x41);
1172                                 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1173
1174                                 /* Emit 'movzwl eax, ax' */
1175                                 if (is_ereg(dst_reg))
1176                                         EMIT3(0x45, 0x0F, 0xB7);
1177                                 else
1178                                         EMIT2(0x0F, 0xB7);
1179                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1180                                 break;
1181                         case 32:
1182                                 /* Emit 'bswap eax' to swap lower 4 bytes */
1183                                 if (is_ereg(dst_reg))
1184                                         EMIT2(0x41, 0x0F);
1185                                 else
1186                                         EMIT1(0x0F);
1187                                 EMIT1(add_1reg(0xC8, dst_reg));
1188                                 break;
1189                         case 64:
1190                                 /* Emit 'bswap rax' to swap 8 bytes */
1191                                 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1192                                       add_1reg(0xC8, dst_reg));
1193                                 break;
1194                         }
1195                         break;
1196
1197                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1198                         switch (imm32) {
1199                         case 16:
1200                                 /*
1201                                  * Emit 'movzwl eax, ax' to zero extend 16-bit
1202                                  * into 64 bit
1203                                  */
1204                                 if (is_ereg(dst_reg))
1205                                         EMIT3(0x45, 0x0F, 0xB7);
1206                                 else
1207                                         EMIT2(0x0F, 0xB7);
1208                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1209                                 break;
1210                         case 32:
1211                                 /* Emit 'mov eax, eax' to clear upper 32-bits */
1212                                 if (is_ereg(dst_reg))
1213                                         EMIT1(0x45);
1214                                 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1215                                 break;
1216                         case 64:
1217                                 /* nop */
1218                                 break;
1219                         }
1220                         break;
1221
1222                         /* speculation barrier */
1223                 case BPF_ST | BPF_NOSPEC:
1224                         if (boot_cpu_has(X86_FEATURE_XMM2))
1225                                 /* Emit 'lfence' */
1226                                 EMIT3(0x0F, 0xAE, 0xE8);
1227                         break;
1228
1229                         /* ST: *(u8*)(dst_reg + off) = imm */
1230                 case BPF_ST | BPF_MEM | BPF_B:
1231                         if (is_ereg(dst_reg))
1232                                 EMIT2(0x41, 0xC6);
1233                         else
1234                                 EMIT1(0xC6);
1235                         goto st;
1236                 case BPF_ST | BPF_MEM | BPF_H:
1237                         if (is_ereg(dst_reg))
1238                                 EMIT3(0x66, 0x41, 0xC7);
1239                         else
1240                                 EMIT2(0x66, 0xC7);
1241                         goto st;
1242                 case BPF_ST | BPF_MEM | BPF_W:
1243                         if (is_ereg(dst_reg))
1244                                 EMIT2(0x41, 0xC7);
1245                         else
1246                                 EMIT1(0xC7);
1247                         goto st;
1248                 case BPF_ST | BPF_MEM | BPF_DW:
1249                         EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1250
1251 st:                     if (is_imm8(insn->off))
1252                                 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1253                         else
1254                                 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1255
1256                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1257                         break;
1258
1259                         /* STX: *(u8*)(dst_reg + off) = src_reg */
1260                 case BPF_STX | BPF_MEM | BPF_B:
1261                 case BPF_STX | BPF_MEM | BPF_H:
1262                 case BPF_STX | BPF_MEM | BPF_W:
1263                 case BPF_STX | BPF_MEM | BPF_DW:
1264                         emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1265                         break;
1266
1267                         /* LDX: dst_reg = *(u8*)(src_reg + off) */
1268                 case BPF_LDX | BPF_MEM | BPF_B:
1269                 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1270                 case BPF_LDX | BPF_MEM | BPF_H:
1271                 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1272                 case BPF_LDX | BPF_MEM | BPF_W:
1273                 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1274                 case BPF_LDX | BPF_MEM | BPF_DW:
1275                 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1276                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1277                                 /* test src_reg, src_reg */
1278                                 maybe_emit_mod(&prog, src_reg, src_reg, true); /* always 1 byte */
1279                                 EMIT2(0x85, add_2reg(0xC0, src_reg, src_reg));
1280                                 /* jne start_of_ldx */
1281                                 EMIT2(X86_JNE, 0);
1282                                 /* xor dst_reg, dst_reg */
1283                                 emit_mov_imm32(&prog, false, dst_reg, 0);
1284                                 /* jmp byte_after_ldx */
1285                                 EMIT2(0xEB, 0);
1286
1287                                 /* populate jmp_offset for JNE above */
1288                                 temp[4] = prog - temp - 5 /* sizeof(test + jne) */;
1289                                 start_of_ldx = prog;
1290                         }
1291                         emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1292                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1293                                 struct exception_table_entry *ex;
1294                                 u8 *_insn = image + proglen + (start_of_ldx - temp);
1295                                 s64 delta;
1296
1297                                 /* populate jmp_offset for JMP above */
1298                                 start_of_ldx[-1] = prog - start_of_ldx;
1299
1300                                 if (!bpf_prog->aux->extable)
1301                                         break;
1302
1303                                 if (excnt >= bpf_prog->aux->num_exentries) {
1304                                         pr_err("ex gen bug\n");
1305                                         return -EFAULT;
1306                                 }
1307                                 ex = &bpf_prog->aux->extable[excnt++];
1308
1309                                 delta = _insn - (u8 *)&ex->insn;
1310                                 if (!is_simm32(delta)) {
1311                                         pr_err("extable->insn doesn't fit into 32-bit\n");
1312                                         return -EFAULT;
1313                                 }
1314                                 ex->insn = delta;
1315
1316                                 delta = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
1317                                 if (!is_simm32(delta)) {
1318                                         pr_err("extable->handler doesn't fit into 32-bit\n");
1319                                         return -EFAULT;
1320                                 }
1321                                 ex->handler = delta;
1322
1323                                 if (dst_reg > BPF_REG_9) {
1324                                         pr_err("verifier error\n");
1325                                         return -EFAULT;
1326                                 }
1327                                 /*
1328                                  * Compute size of x86 insn and its target dest x86 register.
1329                                  * ex_handler_bpf() will use lower 8 bits to adjust
1330                                  * pt_regs->ip to jump over this x86 instruction
1331                                  * and upper bits to figure out which pt_regs to zero out.
1332                                  * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1333                                  * of 4 bytes will be ignored and rbx will be zero inited.
1334                                  */
1335                                 ex->fixup = (prog - temp) | (reg2pt_regs[dst_reg] << 8);
1336                         }
1337                         break;
1338
1339                 case BPF_STX | BPF_ATOMIC | BPF_W:
1340                 case BPF_STX | BPF_ATOMIC | BPF_DW:
1341                         if (insn->imm == (BPF_AND | BPF_FETCH) ||
1342                             insn->imm == (BPF_OR | BPF_FETCH) ||
1343                             insn->imm == (BPF_XOR | BPF_FETCH)) {
1344                                 u8 *branch_target;
1345                                 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1346                                 u32 real_src_reg = src_reg;
1347
1348                                 /*
1349                                  * Can't be implemented with a single x86 insn.
1350                                  * Need to do a CMPXCHG loop.
1351                                  */
1352
1353                                 /* Will need RAX as a CMPXCHG operand so save R0 */
1354                                 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1355                                 if (src_reg == BPF_REG_0)
1356                                         real_src_reg = BPF_REG_AX;
1357
1358                                 branch_target = prog;
1359                                 /* Load old value */
1360                                 emit_ldx(&prog, BPF_SIZE(insn->code),
1361                                          BPF_REG_0, dst_reg, insn->off);
1362                                 /*
1363                                  * Perform the (commutative) operation locally,
1364                                  * put the result in the AUX_REG.
1365                                  */
1366                                 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1367                                 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1368                                 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1369                                       add_2reg(0xC0, AUX_REG, real_src_reg));
1370                                 /* Attempt to swap in new value */
1371                                 err = emit_atomic(&prog, BPF_CMPXCHG,
1372                                                   dst_reg, AUX_REG, insn->off,
1373                                                   BPF_SIZE(insn->code));
1374                                 if (WARN_ON(err))
1375                                         return err;
1376                                 /*
1377                                  * ZF tells us whether we won the race. If it's
1378                                  * cleared we need to try again.
1379                                  */
1380                                 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1381                                 /* Return the pre-modification value */
1382                                 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1383                                 /* Restore R0 after clobbering RAX */
1384                                 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1385                                 break;
1386
1387                         }
1388
1389                         err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1390                                                   insn->off, BPF_SIZE(insn->code));
1391                         if (err)
1392                                 return err;
1393                         break;
1394
1395                         /* call */
1396                 case BPF_JMP | BPF_CALL:
1397                         func = (u8 *) __bpf_call_base + imm32;
1398                         if (tail_call_reachable) {
1399                                 EMIT3_off32(0x48, 0x8B, 0x85,
1400                                             -(bpf_prog->aux->stack_depth + 8));
1401                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
1402                                         return -EINVAL;
1403                         } else {
1404                                 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1]))
1405                                         return -EINVAL;
1406                         }
1407                         break;
1408
1409                 case BPF_JMP | BPF_TAIL_CALL:
1410                         if (imm32)
1411                                 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1412                                                           &prog, addrs[i], image,
1413                                                           callee_regs_used,
1414                                                           bpf_prog->aux->stack_depth);
1415                         else
1416                                 emit_bpf_tail_call_indirect(&prog,
1417                                                             callee_regs_used,
1418                                                             bpf_prog->aux->stack_depth);
1419                         break;
1420
1421                         /* cond jump */
1422                 case BPF_JMP | BPF_JEQ | BPF_X:
1423                 case BPF_JMP | BPF_JNE | BPF_X:
1424                 case BPF_JMP | BPF_JGT | BPF_X:
1425                 case BPF_JMP | BPF_JLT | BPF_X:
1426                 case BPF_JMP | BPF_JGE | BPF_X:
1427                 case BPF_JMP | BPF_JLE | BPF_X:
1428                 case BPF_JMP | BPF_JSGT | BPF_X:
1429                 case BPF_JMP | BPF_JSLT | BPF_X:
1430                 case BPF_JMP | BPF_JSGE | BPF_X:
1431                 case BPF_JMP | BPF_JSLE | BPF_X:
1432                 case BPF_JMP32 | BPF_JEQ | BPF_X:
1433                 case BPF_JMP32 | BPF_JNE | BPF_X:
1434                 case BPF_JMP32 | BPF_JGT | BPF_X:
1435                 case BPF_JMP32 | BPF_JLT | BPF_X:
1436                 case BPF_JMP32 | BPF_JGE | BPF_X:
1437                 case BPF_JMP32 | BPF_JLE | BPF_X:
1438                 case BPF_JMP32 | BPF_JSGT | BPF_X:
1439                 case BPF_JMP32 | BPF_JSLT | BPF_X:
1440                 case BPF_JMP32 | BPF_JSGE | BPF_X:
1441                 case BPF_JMP32 | BPF_JSLE | BPF_X:
1442                         /* cmp dst_reg, src_reg */
1443                         maybe_emit_mod(&prog, dst_reg, src_reg,
1444                                        BPF_CLASS(insn->code) == BPF_JMP);
1445                         EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1446                         goto emit_cond_jmp;
1447
1448                 case BPF_JMP | BPF_JSET | BPF_X:
1449                 case BPF_JMP32 | BPF_JSET | BPF_X:
1450                         /* test dst_reg, src_reg */
1451                         maybe_emit_mod(&prog, dst_reg, src_reg,
1452                                        BPF_CLASS(insn->code) == BPF_JMP);
1453                         EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1454                         goto emit_cond_jmp;
1455
1456                 case BPF_JMP | BPF_JSET | BPF_K:
1457                 case BPF_JMP32 | BPF_JSET | BPF_K:
1458                         /* test dst_reg, imm32 */
1459                         if (BPF_CLASS(insn->code) == BPF_JMP)
1460                                 EMIT1(add_1mod(0x48, dst_reg));
1461                         else if (is_ereg(dst_reg))
1462                                 EMIT1(add_1mod(0x40, dst_reg));
1463                         EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1464                         goto emit_cond_jmp;
1465
1466                 case BPF_JMP | BPF_JEQ | BPF_K:
1467                 case BPF_JMP | BPF_JNE | BPF_K:
1468                 case BPF_JMP | BPF_JGT | BPF_K:
1469                 case BPF_JMP | BPF_JLT | BPF_K:
1470                 case BPF_JMP | BPF_JGE | BPF_K:
1471                 case BPF_JMP | BPF_JLE | BPF_K:
1472                 case BPF_JMP | BPF_JSGT | BPF_K:
1473                 case BPF_JMP | BPF_JSLT | BPF_K:
1474                 case BPF_JMP | BPF_JSGE | BPF_K:
1475                 case BPF_JMP | BPF_JSLE | BPF_K:
1476                 case BPF_JMP32 | BPF_JEQ | BPF_K:
1477                 case BPF_JMP32 | BPF_JNE | BPF_K:
1478                 case BPF_JMP32 | BPF_JGT | BPF_K:
1479                 case BPF_JMP32 | BPF_JLT | BPF_K:
1480                 case BPF_JMP32 | BPF_JGE | BPF_K:
1481                 case BPF_JMP32 | BPF_JLE | BPF_K:
1482                 case BPF_JMP32 | BPF_JSGT | BPF_K:
1483                 case BPF_JMP32 | BPF_JSLT | BPF_K:
1484                 case BPF_JMP32 | BPF_JSGE | BPF_K:
1485                 case BPF_JMP32 | BPF_JSLE | BPF_K:
1486                         /* test dst_reg, dst_reg to save one extra byte */
1487                         if (imm32 == 0) {
1488                                 maybe_emit_mod(&prog, dst_reg, dst_reg,
1489                                                BPF_CLASS(insn->code) == BPF_JMP);
1490                                 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1491                                 goto emit_cond_jmp;
1492                         }
1493
1494                         /* cmp dst_reg, imm8/32 */
1495                         if (BPF_CLASS(insn->code) == BPF_JMP)
1496                                 EMIT1(add_1mod(0x48, dst_reg));
1497                         else if (is_ereg(dst_reg))
1498                                 EMIT1(add_1mod(0x40, dst_reg));
1499
1500                         if (is_imm8(imm32))
1501                                 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1502                         else
1503                                 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1504
1505 emit_cond_jmp:          /* Convert BPF opcode to x86 */
1506                         switch (BPF_OP(insn->code)) {
1507                         case BPF_JEQ:
1508                                 jmp_cond = X86_JE;
1509                                 break;
1510                         case BPF_JSET:
1511                         case BPF_JNE:
1512                                 jmp_cond = X86_JNE;
1513                                 break;
1514                         case BPF_JGT:
1515                                 /* GT is unsigned '>', JA in x86 */
1516                                 jmp_cond = X86_JA;
1517                                 break;
1518                         case BPF_JLT:
1519                                 /* LT is unsigned '<', JB in x86 */
1520                                 jmp_cond = X86_JB;
1521                                 break;
1522                         case BPF_JGE:
1523                                 /* GE is unsigned '>=', JAE in x86 */
1524                                 jmp_cond = X86_JAE;
1525                                 break;
1526                         case BPF_JLE:
1527                                 /* LE is unsigned '<=', JBE in x86 */
1528                                 jmp_cond = X86_JBE;
1529                                 break;
1530                         case BPF_JSGT:
1531                                 /* Signed '>', GT in x86 */
1532                                 jmp_cond = X86_JG;
1533                                 break;
1534                         case BPF_JSLT:
1535                                 /* Signed '<', LT in x86 */
1536                                 jmp_cond = X86_JL;
1537                                 break;
1538                         case BPF_JSGE:
1539                                 /* Signed '>=', GE in x86 */
1540                                 jmp_cond = X86_JGE;
1541                                 break;
1542                         case BPF_JSLE:
1543                                 /* Signed '<=', LE in x86 */
1544                                 jmp_cond = X86_JLE;
1545                                 break;
1546                         default: /* to silence GCC warning */
1547                                 return -EFAULT;
1548                         }
1549                         jmp_offset = addrs[i + insn->off] - addrs[i];
1550                         if (is_imm8(jmp_offset)) {
1551                                 if (jmp_padding) {
1552                                         /* To keep the jmp_offset valid, the extra bytes are
1553                                          * padded before the jump insn, so we subtract the
1554                                          * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1555                                          *
1556                                          * If the previous pass already emits an imm8
1557                                          * jmp_cond, then this BPF insn won't shrink, so
1558                                          * "nops" is 0.
1559                                          *
1560                                          * On the other hand, if the previous pass emits an
1561                                          * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1562                                          * keep the image from shrinking further.
1563                                          *
1564                                          * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1565                                          *     is 2 bytes, so the size difference is 4 bytes.
1566                                          */
1567                                         nops = INSN_SZ_DIFF - 2;
1568                                         if (nops != 0 && nops != 4) {
1569                                                 pr_err("unexpected jmp_cond padding: %d bytes\n",
1570                                                        nops);
1571                                                 return -EFAULT;
1572                                         }
1573                                         emit_nops(&prog, nops);
1574                                 }
1575                                 EMIT2(jmp_cond, jmp_offset);
1576                         } else if (is_simm32(jmp_offset)) {
1577                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1578                         } else {
1579                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1580                                 return -EFAULT;
1581                         }
1582
1583                         break;
1584
1585                 case BPF_JMP | BPF_JA:
1586                         if (insn->off == -1)
1587                                 /* -1 jmp instructions will always jump
1588                                  * backwards two bytes. Explicitly handling
1589                                  * this case avoids wasting too many passes
1590                                  * when there are long sequences of replaced
1591                                  * dead code.
1592                                  */
1593                                 jmp_offset = -2;
1594                         else
1595                                 jmp_offset = addrs[i + insn->off] - addrs[i];
1596
1597                         if (!jmp_offset) {
1598                                 /*
1599                                  * If jmp_padding is enabled, the extra nops will
1600                                  * be inserted. Otherwise, optimize out nop jumps.
1601                                  */
1602                                 if (jmp_padding) {
1603                                         /* There are 3 possible conditions.
1604                                          * (1) This BPF_JA is already optimized out in
1605                                          *     the previous run, so there is no need
1606                                          *     to pad any extra byte (0 byte).
1607                                          * (2) The previous pass emits an imm8 jmp,
1608                                          *     so we pad 2 bytes to match the previous
1609                                          *     insn size.
1610                                          * (3) Similarly, the previous pass emits an
1611                                          *     imm32 jmp, and 5 bytes is padded.
1612                                          */
1613                                         nops = INSN_SZ_DIFF;
1614                                         if (nops != 0 && nops != 2 && nops != 5) {
1615                                                 pr_err("unexpected nop jump padding: %d bytes\n",
1616                                                        nops);
1617                                                 return -EFAULT;
1618                                         }
1619                                         emit_nops(&prog, nops);
1620                                 }
1621                                 break;
1622                         }
1623 emit_jmp:
1624                         if (is_imm8(jmp_offset)) {
1625                                 if (jmp_padding) {
1626                                         /* To avoid breaking jmp_offset, the extra bytes
1627                                          * are padded before the actual jmp insn, so
1628                                          * 2 bytes is subtracted from INSN_SZ_DIFF.
1629                                          *
1630                                          * If the previous pass already emits an imm8
1631                                          * jmp, there is nothing to pad (0 byte).
1632                                          *
1633                                          * If it emits an imm32 jmp (5 bytes) previously
1634                                          * and now an imm8 jmp (2 bytes), then we pad
1635                                          * (5 - 2 = 3) bytes to stop the image from
1636                                          * shrinking further.
1637                                          */
1638                                         nops = INSN_SZ_DIFF - 2;
1639                                         if (nops != 0 && nops != 3) {
1640                                                 pr_err("unexpected jump padding: %d bytes\n",
1641                                                        nops);
1642                                                 return -EFAULT;
1643                                         }
1644                                         emit_nops(&prog, INSN_SZ_DIFF - 2);
1645                                 }
1646                                 EMIT2(0xEB, jmp_offset);
1647                         } else if (is_simm32(jmp_offset)) {
1648                                 EMIT1_off32(0xE9, jmp_offset);
1649                         } else {
1650                                 pr_err("jmp gen bug %llx\n", jmp_offset);
1651                                 return -EFAULT;
1652                         }
1653                         break;
1654
1655                 case BPF_JMP | BPF_EXIT:
1656                         if (seen_exit) {
1657                                 jmp_offset = ctx->cleanup_addr - addrs[i];
1658                                 goto emit_jmp;
1659                         }
1660                         seen_exit = true;
1661                         /* Update cleanup_addr */
1662                         ctx->cleanup_addr = proglen;
1663                         pop_callee_regs(&prog, callee_regs_used);
1664                         EMIT1(0xC9);         /* leave */
1665                         EMIT1(0xC3);         /* ret */
1666                         break;
1667
1668                 default:
1669                         /*
1670                          * By design x86-64 JIT should support all BPF instructions.
1671                          * This error will be seen if new instruction was added
1672                          * to the interpreter, but not to the JIT, or if there is
1673                          * junk in bpf_prog.
1674                          */
1675                         pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1676                         return -EINVAL;
1677                 }
1678
1679                 ilen = prog - temp;
1680                 if (ilen > BPF_MAX_INSN_SIZE) {
1681                         pr_err("bpf_jit: fatal insn size error\n");
1682                         return -EFAULT;
1683                 }
1684
1685                 if (image) {
1686                         /*
1687                          * When populating the image, assert that:
1688                          *
1689                          *  i) We do not write beyond the allocated space, and
1690                          * ii) addrs[i] did not change from the prior run, in order
1691                          *     to validate assumptions made for computing branch
1692                          *     displacements.
1693                          */
1694                         if (unlikely(proglen + ilen > oldproglen ||
1695                                      proglen + ilen != addrs[i])) {
1696                                 pr_err("bpf_jit: fatal error\n");
1697                                 return -EFAULT;
1698                         }
1699                         memcpy(image + proglen, temp, ilen);
1700                 }
1701                 proglen += ilen;
1702                 addrs[i] = proglen;
1703                 prog = temp;
1704         }
1705
1706         if (image && excnt != bpf_prog->aux->num_exentries) {
1707                 pr_err("extable is not populated\n");
1708                 return -EFAULT;
1709         }
1710         return proglen;
1711 }
1712
1713 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1714                       int stack_size)
1715 {
1716         int i;
1717         /* Store function arguments to stack.
1718          * For a function that accepts two pointers the sequence will be:
1719          * mov QWORD PTR [rbp-0x10],rdi
1720          * mov QWORD PTR [rbp-0x8],rsi
1721          */
1722         for (i = 0; i < min(nr_args, 6); i++)
1723                 emit_stx(prog, bytes_to_bpf_size(m->arg_size[i]),
1724                          BPF_REG_FP,
1725                          i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1726                          -(stack_size - i * 8));
1727 }
1728
1729 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1730                          int stack_size)
1731 {
1732         int i;
1733
1734         /* Restore function arguments from stack.
1735          * For a function that accepts two pointers the sequence will be:
1736          * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1737          * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1738          */
1739         for (i = 0; i < min(nr_args, 6); i++)
1740                 emit_ldx(prog, bytes_to_bpf_size(m->arg_size[i]),
1741                          i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1742                          BPF_REG_FP,
1743                          -(stack_size - i * 8));
1744 }
1745
1746 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1747                            struct bpf_prog *p, int stack_size, bool mod_ret)
1748 {
1749         u8 *prog = *pprog;
1750         u8 *jmp_insn;
1751
1752         /* arg1: mov rdi, progs[i] */
1753         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1754         if (emit_call(&prog,
1755                       p->aux->sleepable ? __bpf_prog_enter_sleepable :
1756                       __bpf_prog_enter, prog))
1757                         return -EINVAL;
1758         /* remember prog start time returned by __bpf_prog_enter */
1759         emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1760
1761         /* if (__bpf_prog_enter*(prog) == 0)
1762          *      goto skip_exec_of_prog;
1763          */
1764         EMIT3(0x48, 0x85, 0xC0);  /* test rax,rax */
1765         /* emit 2 nops that will be replaced with JE insn */
1766         jmp_insn = prog;
1767         emit_nops(&prog, 2);
1768
1769         /* arg1: lea rdi, [rbp - stack_size] */
1770         EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1771         /* arg2: progs[i]->insnsi for interpreter */
1772         if (!p->jited)
1773                 emit_mov_imm64(&prog, BPF_REG_2,
1774                                (long) p->insnsi >> 32,
1775                                (u32) (long) p->insnsi);
1776         /* call JITed bpf program or interpreter */
1777         if (emit_call(&prog, p->bpf_func, prog))
1778                 return -EINVAL;
1779
1780         /* BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1781          * of the previous call which is then passed on the stack to
1782          * the next BPF program.
1783          */
1784         if (mod_ret)
1785                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1786
1787         /* replace 2 nops with JE insn, since jmp target is known */
1788         jmp_insn[0] = X86_JE;
1789         jmp_insn[1] = prog - jmp_insn - 2;
1790
1791         /* arg1: mov rdi, progs[i] */
1792         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1793         /* arg2: mov rsi, rbx <- start time in nsec */
1794         emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1795         if (emit_call(&prog,
1796                       p->aux->sleepable ? __bpf_prog_exit_sleepable :
1797                       __bpf_prog_exit, prog))
1798                         return -EINVAL;
1799
1800         *pprog = prog;
1801         return 0;
1802 }
1803
1804 static void emit_align(u8 **pprog, u32 align)
1805 {
1806         u8 *target, *prog = *pprog;
1807
1808         target = PTR_ALIGN(prog, align);
1809         if (target != prog)
1810                 emit_nops(&prog, target - prog);
1811
1812         *pprog = prog;
1813 }
1814
1815 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
1816 {
1817         u8 *prog = *pprog;
1818         s64 offset;
1819
1820         offset = func - (ip + 2 + 4);
1821         if (!is_simm32(offset)) {
1822                 pr_err("Target %p is out of range\n", func);
1823                 return -EINVAL;
1824         }
1825         EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
1826         *pprog = prog;
1827         return 0;
1828 }
1829
1830 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
1831                       struct bpf_tramp_progs *tp, int stack_size)
1832 {
1833         int i;
1834         u8 *prog = *pprog;
1835
1836         for (i = 0; i < tp->nr_progs; i++) {
1837                 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, false))
1838                         return -EINVAL;
1839         }
1840         *pprog = prog;
1841         return 0;
1842 }
1843
1844 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
1845                               struct bpf_tramp_progs *tp, int stack_size,
1846                               u8 **branches)
1847 {
1848         u8 *prog = *pprog;
1849         int i;
1850
1851         /* The first fmod_ret program will receive a garbage return value.
1852          * Set this to 0 to avoid confusing the program.
1853          */
1854         emit_mov_imm32(&prog, false, BPF_REG_0, 0);
1855         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1856         for (i = 0; i < tp->nr_progs; i++) {
1857                 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, true))
1858                         return -EINVAL;
1859
1860                 /* mod_ret prog stored return value into [rbp - 8]. Emit:
1861                  * if (*(u64 *)(rbp - 8) !=  0)
1862                  *      goto do_fexit;
1863                  */
1864                 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
1865                 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
1866
1867                 /* Save the location of the branch and Generate 6 nops
1868                  * (4 bytes for an offset and 2 bytes for the jump) These nops
1869                  * are replaced with a conditional jump once do_fexit (i.e. the
1870                  * start of the fexit invocation) is finalized.
1871                  */
1872                 branches[i] = prog;
1873                 emit_nops(&prog, 4 + 2);
1874         }
1875
1876         *pprog = prog;
1877         return 0;
1878 }
1879
1880 /* Example:
1881  * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
1882  * its 'struct btf_func_model' will be nr_args=2
1883  * The assembly code when eth_type_trans is executing after trampoline:
1884  *
1885  * push rbp
1886  * mov rbp, rsp
1887  * sub rsp, 16                     // space for skb and dev
1888  * push rbx                        // temp regs to pass start time
1889  * mov qword ptr [rbp - 16], rdi   // save skb pointer to stack
1890  * mov qword ptr [rbp - 8], rsi    // save dev pointer to stack
1891  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1892  * mov rbx, rax                    // remember start time in bpf stats are enabled
1893  * lea rdi, [rbp - 16]             // R1==ctx of bpf prog
1894  * call addr_of_jited_FENTRY_prog
1895  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1896  * mov rsi, rbx                    // prog start time
1897  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1898  * mov rdi, qword ptr [rbp - 16]   // restore skb pointer from stack
1899  * mov rsi, qword ptr [rbp - 8]    // restore dev pointer from stack
1900  * pop rbx
1901  * leave
1902  * ret
1903  *
1904  * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
1905  * replaced with 'call generated_bpf_trampoline'. When it returns
1906  * eth_type_trans will continue executing with original skb and dev pointers.
1907  *
1908  * The assembly code when eth_type_trans is called from trampoline:
1909  *
1910  * push rbp
1911  * mov rbp, rsp
1912  * sub rsp, 24                     // space for skb, dev, return value
1913  * push rbx                        // temp regs to pass start time
1914  * mov qword ptr [rbp - 24], rdi   // save skb pointer to stack
1915  * mov qword ptr [rbp - 16], rsi   // save dev pointer to stack
1916  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1917  * mov rbx, rax                    // remember start time if bpf stats are enabled
1918  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
1919  * call addr_of_jited_FENTRY_prog  // bpf prog can access skb and dev
1920  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1921  * mov rsi, rbx                    // prog start time
1922  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1923  * mov rdi, qword ptr [rbp - 24]   // restore skb pointer from stack
1924  * mov rsi, qword ptr [rbp - 16]   // restore dev pointer from stack
1925  * call eth_type_trans+5           // execute body of eth_type_trans
1926  * mov qword ptr [rbp - 8], rax    // save return value
1927  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
1928  * mov rbx, rax                    // remember start time in bpf stats are enabled
1929  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
1930  * call addr_of_jited_FEXIT_prog   // bpf prog can access skb, dev, return value
1931  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
1932  * mov rsi, rbx                    // prog start time
1933  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
1934  * mov rax, qword ptr [rbp - 8]    // restore eth_type_trans's return value
1935  * pop rbx
1936  * leave
1937  * add rsp, 8                      // skip eth_type_trans's frame
1938  * ret                             // return to its caller
1939  */
1940 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
1941                                 const struct btf_func_model *m, u32 flags,
1942                                 struct bpf_tramp_progs *tprogs,
1943                                 void *orig_call)
1944 {
1945         int ret, i, nr_args = m->nr_args;
1946         int stack_size = nr_args * 8;
1947         struct bpf_tramp_progs *fentry = &tprogs[BPF_TRAMP_FENTRY];
1948         struct bpf_tramp_progs *fexit = &tprogs[BPF_TRAMP_FEXIT];
1949         struct bpf_tramp_progs *fmod_ret = &tprogs[BPF_TRAMP_MODIFY_RETURN];
1950         u8 **branches = NULL;
1951         u8 *prog;
1952
1953         /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
1954         if (nr_args > 6)
1955                 return -ENOTSUPP;
1956
1957         if ((flags & BPF_TRAMP_F_RESTORE_REGS) &&
1958             (flags & BPF_TRAMP_F_SKIP_FRAME))
1959                 return -EINVAL;
1960
1961         if (flags & BPF_TRAMP_F_CALL_ORIG)
1962                 stack_size += 8; /* room for return value of orig_call */
1963
1964         if (flags & BPF_TRAMP_F_IP_ARG)
1965                 stack_size += 8; /* room for IP address argument */
1966
1967         if (flags & BPF_TRAMP_F_SKIP_FRAME)
1968                 /* skip patched call instruction and point orig_call to actual
1969                  * body of the kernel function.
1970                  */
1971                 orig_call += X86_PATCH_SIZE;
1972
1973         prog = image;
1974
1975         EMIT1(0x55);             /* push rbp */
1976         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
1977         EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
1978         EMIT1(0x53);             /* push rbx */
1979
1980         if (flags & BPF_TRAMP_F_IP_ARG) {
1981                 /* Store IP address of the traced function:
1982                  * mov rax, QWORD PTR [rbp + 8]
1983                  * sub rax, X86_PATCH_SIZE
1984                  * mov QWORD PTR [rbp - stack_size], rax
1985                  */
1986                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
1987                 EMIT4(0x48, 0x83, 0xe8, X86_PATCH_SIZE);
1988                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -stack_size);
1989
1990                 /* Continue with stack_size for regs storage, stack will
1991                  * be correctly restored with 'leave' instruction.
1992                  */
1993                 stack_size -= 8;
1994         }
1995
1996         save_regs(m, &prog, nr_args, stack_size);
1997
1998         if (flags & BPF_TRAMP_F_CALL_ORIG) {
1999                 /* arg1: mov rdi, im */
2000                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2001                 if (emit_call(&prog, __bpf_tramp_enter, prog)) {
2002                         ret = -EINVAL;
2003                         goto cleanup;
2004                 }
2005         }
2006
2007         if (fentry->nr_progs)
2008                 if (invoke_bpf(m, &prog, fentry, stack_size))
2009                         return -EINVAL;
2010
2011         if (fmod_ret->nr_progs) {
2012                 branches = kcalloc(fmod_ret->nr_progs, sizeof(u8 *),
2013                                    GFP_KERNEL);
2014                 if (!branches)
2015                         return -ENOMEM;
2016
2017                 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, stack_size,
2018                                        branches)) {
2019                         ret = -EINVAL;
2020                         goto cleanup;
2021                 }
2022         }
2023
2024         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2025                 restore_regs(m, &prog, nr_args, stack_size);
2026
2027                 /* call original function */
2028                 if (emit_call(&prog, orig_call, prog)) {
2029                         ret = -EINVAL;
2030                         goto cleanup;
2031                 }
2032                 /* remember return value in a stack for bpf prog to access */
2033                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2034                 im->ip_after_call = prog;
2035                 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2036                 prog += X86_PATCH_SIZE;
2037         }
2038
2039         if (fmod_ret->nr_progs) {
2040                 /* From Intel 64 and IA-32 Architectures Optimization
2041                  * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2042                  * Coding Rule 11: All branch targets should be 16-byte
2043                  * aligned.
2044                  */
2045                 emit_align(&prog, 16);
2046                 /* Update the branches saved in invoke_bpf_mod_ret with the
2047                  * aligned address of do_fexit.
2048                  */
2049                 for (i = 0; i < fmod_ret->nr_progs; i++)
2050                         emit_cond_near_jump(&branches[i], prog, branches[i],
2051                                             X86_JNE);
2052         }
2053
2054         if (fexit->nr_progs)
2055                 if (invoke_bpf(m, &prog, fexit, stack_size)) {
2056                         ret = -EINVAL;
2057                         goto cleanup;
2058                 }
2059
2060         if (flags & BPF_TRAMP_F_RESTORE_REGS)
2061                 restore_regs(m, &prog, nr_args, stack_size);
2062
2063         /* This needs to be done regardless. If there were fmod_ret programs,
2064          * the return value is only updated on the stack and still needs to be
2065          * restored to R0.
2066          */
2067         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2068                 im->ip_epilogue = prog;
2069                 /* arg1: mov rdi, im */
2070                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2071                 if (emit_call(&prog, __bpf_tramp_exit, prog)) {
2072                         ret = -EINVAL;
2073                         goto cleanup;
2074                 }
2075                 /* restore original return value back into RAX */
2076                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2077         }
2078
2079         EMIT1(0x5B); /* pop rbx */
2080         EMIT1(0xC9); /* leave */
2081         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2082                 /* skip our return address and return to parent */
2083                 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2084         EMIT1(0xC3); /* ret */
2085         /* Make sure the trampoline generation logic doesn't overflow */
2086         if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2087                 ret = -EFAULT;
2088                 goto cleanup;
2089         }
2090         ret = prog - (u8 *)image;
2091
2092 cleanup:
2093         kfree(branches);
2094         return ret;
2095 }
2096
2097 static int emit_fallback_jump(u8 **pprog)
2098 {
2099         u8 *prog = *pprog;
2100         int err = 0;
2101
2102 #ifdef CONFIG_RETPOLINE
2103         /* Note that this assumes the the compiler uses external
2104          * thunks for indirect calls. Both clang and GCC use the same
2105          * naming convention for external thunks.
2106          */
2107         err = emit_jump(&prog, __x86_indirect_thunk_rdx, prog);
2108 #else
2109         EMIT2(0xFF, 0xE2);      /* jmp rdx */
2110 #endif
2111         *pprog = prog;
2112         return err;
2113 }
2114
2115 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs)
2116 {
2117         u8 *jg_reloc, *prog = *pprog;
2118         int pivot, err, jg_bytes = 1;
2119         s64 jg_offset;
2120
2121         if (a == b) {
2122                 /* Leaf node of recursion, i.e. not a range of indices
2123                  * anymore.
2124                  */
2125                 EMIT1(add_1mod(0x48, BPF_REG_3));       /* cmp rdx,func */
2126                 if (!is_simm32(progs[a]))
2127                         return -1;
2128                 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2129                             progs[a]);
2130                 err = emit_cond_near_jump(&prog,        /* je func */
2131                                           (void *)progs[a], prog,
2132                                           X86_JE);
2133                 if (err)
2134                         return err;
2135
2136                 err = emit_fallback_jump(&prog);        /* jmp thunk/indirect */
2137                 if (err)
2138                         return err;
2139
2140                 *pprog = prog;
2141                 return 0;
2142         }
2143
2144         /* Not a leaf node, so we pivot, and recursively descend into
2145          * the lower and upper ranges.
2146          */
2147         pivot = (b - a) / 2;
2148         EMIT1(add_1mod(0x48, BPF_REG_3));               /* cmp rdx,func */
2149         if (!is_simm32(progs[a + pivot]))
2150                 return -1;
2151         EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2152
2153         if (pivot > 2) {                                /* jg upper_part */
2154                 /* Require near jump. */
2155                 jg_bytes = 4;
2156                 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2157         } else {
2158                 EMIT2(X86_JG, 0);
2159         }
2160         jg_reloc = prog;
2161
2162         err = emit_bpf_dispatcher(&prog, a, a + pivot,  /* emit lower_part */
2163                                   progs);
2164         if (err)
2165                 return err;
2166
2167         /* From Intel 64 and IA-32 Architectures Optimization
2168          * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2169          * Coding Rule 11: All branch targets should be 16-byte
2170          * aligned.
2171          */
2172         emit_align(&prog, 16);
2173         jg_offset = prog - jg_reloc;
2174         emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2175
2176         err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2177                                   b, progs);
2178         if (err)
2179                 return err;
2180
2181         *pprog = prog;
2182         return 0;
2183 }
2184
2185 static int cmp_ips(const void *a, const void *b)
2186 {
2187         const s64 *ipa = a;
2188         const s64 *ipb = b;
2189
2190         if (*ipa > *ipb)
2191                 return 1;
2192         if (*ipa < *ipb)
2193                 return -1;
2194         return 0;
2195 }
2196
2197 int arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs)
2198 {
2199         u8 *prog = image;
2200
2201         sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2202         return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs);
2203 }
2204
2205 struct x64_jit_data {
2206         struct bpf_binary_header *header;
2207         int *addrs;
2208         u8 *image;
2209         int proglen;
2210         struct jit_context ctx;
2211 };
2212
2213 #define MAX_PASSES 20
2214 #define PADDING_PASSES (MAX_PASSES - 5)
2215
2216 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2217 {
2218         struct bpf_binary_header *header = NULL;
2219         struct bpf_prog *tmp, *orig_prog = prog;
2220         struct x64_jit_data *jit_data;
2221         int proglen, oldproglen = 0;
2222         struct jit_context ctx = {};
2223         bool tmp_blinded = false;
2224         bool extra_pass = false;
2225         bool padding = false;
2226         u8 *image = NULL;
2227         int *addrs;
2228         int pass;
2229         int i;
2230
2231         if (!prog->jit_requested)
2232                 return orig_prog;
2233
2234         tmp = bpf_jit_blind_constants(prog);
2235         /*
2236          * If blinding was requested and we failed during blinding,
2237          * we must fall back to the interpreter.
2238          */
2239         if (IS_ERR(tmp))
2240                 return orig_prog;
2241         if (tmp != prog) {
2242                 tmp_blinded = true;
2243                 prog = tmp;
2244         }
2245
2246         jit_data = prog->aux->jit_data;
2247         if (!jit_data) {
2248                 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2249                 if (!jit_data) {
2250                         prog = orig_prog;
2251                         goto out;
2252                 }
2253                 prog->aux->jit_data = jit_data;
2254         }
2255         addrs = jit_data->addrs;
2256         if (addrs) {
2257                 ctx = jit_data->ctx;
2258                 oldproglen = jit_data->proglen;
2259                 image = jit_data->image;
2260                 header = jit_data->header;
2261                 extra_pass = true;
2262                 padding = true;
2263                 goto skip_init_addrs;
2264         }
2265         addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2266         if (!addrs) {
2267                 prog = orig_prog;
2268                 goto out_addrs;
2269         }
2270
2271         /*
2272          * Before first pass, make a rough estimation of addrs[]
2273          * each BPF instruction is translated to less than 64 bytes
2274          */
2275         for (proglen = 0, i = 0; i <= prog->len; i++) {
2276                 proglen += 64;
2277                 addrs[i] = proglen;
2278         }
2279         ctx.cleanup_addr = proglen;
2280 skip_init_addrs:
2281
2282         /*
2283          * JITed image shrinks with every pass and the loop iterates
2284          * until the image stops shrinking. Very large BPF programs
2285          * may converge on the last pass. In such case do one more
2286          * pass to emit the final image.
2287          */
2288         for (pass = 0; pass < MAX_PASSES || image; pass++) {
2289                 if (!padding && pass >= PADDING_PASSES)
2290                         padding = true;
2291                 proglen = do_jit(prog, addrs, image, oldproglen, &ctx, padding);
2292                 if (proglen <= 0) {
2293 out_image:
2294                         image = NULL;
2295                         if (header)
2296                                 bpf_jit_binary_free(header);
2297                         prog = orig_prog;
2298                         goto out_addrs;
2299                 }
2300                 if (image) {
2301                         if (proglen != oldproglen) {
2302                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2303                                        proglen, oldproglen);
2304                                 goto out_image;
2305                         }
2306                         break;
2307                 }
2308                 if (proglen == oldproglen) {
2309                         /*
2310                          * The number of entries in extable is the number of BPF_LDX
2311                          * insns that access kernel memory via "pointer to BTF type".
2312                          * The verifier changed their opcode from LDX|MEM|size
2313                          * to LDX|PROBE_MEM|size to make JITing easier.
2314                          */
2315                         u32 align = __alignof__(struct exception_table_entry);
2316                         u32 extable_size = prog->aux->num_exentries *
2317                                 sizeof(struct exception_table_entry);
2318
2319                         /* allocate module memory for x86 insns and extable */
2320                         header = bpf_jit_binary_alloc(roundup(proglen, align) + extable_size,
2321                                                       &image, align, jit_fill_hole);
2322                         if (!header) {
2323                                 prog = orig_prog;
2324                                 goto out_addrs;
2325                         }
2326                         prog->aux->extable = (void *) image + roundup(proglen, align);
2327                 }
2328                 oldproglen = proglen;
2329                 cond_resched();
2330         }
2331
2332         if (bpf_jit_enable > 1)
2333                 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2334
2335         if (image) {
2336                 if (!prog->is_func || extra_pass) {
2337                         bpf_tail_call_direct_fixup(prog);
2338                         bpf_jit_binary_lock_ro(header);
2339                 } else {
2340                         jit_data->addrs = addrs;
2341                         jit_data->ctx = ctx;
2342                         jit_data->proglen = proglen;
2343                         jit_data->image = image;
2344                         jit_data->header = header;
2345                 }
2346                 prog->bpf_func = (void *)image;
2347                 prog->jited = 1;
2348                 prog->jited_len = proglen;
2349         } else {
2350                 prog = orig_prog;
2351         }
2352
2353         if (!image || !prog->is_func || extra_pass) {
2354                 if (image)
2355                         bpf_prog_fill_jited_linfo(prog, addrs + 1);
2356 out_addrs:
2357                 kvfree(addrs);
2358                 kfree(jit_data);
2359                 prog->aux->jit_data = NULL;
2360         }
2361 out:
2362         if (tmp_blinded)
2363                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2364                                            tmp : orig_prog);
2365         return prog;
2366 }
2367
2368 bool bpf_jit_supports_kfunc_call(void)
2369 {
2370         return true;
2371 }