arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is always on */
  94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_INVALID,                         .always = false },
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 bool npt_enabled = true;
 117 #else
 118 bool npt_enabled;
 119 #endif
 120
 121 /*
 122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 123  * pause_filter_count: On processors that support Pause filtering(indicated
 124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 125  *      count value. On VMRUN this value is loaded into an internal counter.
 126  *      Each time a pause instruction is executed, this counter is decremented
 127  *      until it reaches zero at which time a #VMEXIT is generated if pause
 128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 129  *      Intercept Filtering for more details.
 130  *      This also indicate if ple logic enabled.
 131  *
 132  * pause_filter_thresh: In addition, some processor families support advanced
 133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 134  *      the amount of time a guest is allowed to execute in a pause loop.
 135  *      In this mode, a 16-bit pause filter threshold field is added in the
 136  *      VMCB. The threshold value is a cycle count that is used to reset the
 137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 138  *      count value from VMCB into an internal counter. Then, on each pause
 139  *      instruction the hardware checks the elapsed number of cycles since
 140  *      the most recent pause instruction against the pause filter threshold.
 141  *      If the elapsed cycle count is greater than the pause filter threshold,
 142  *      then the internal pause count is reloaded from the VMCB and execution
 143  *      continues. If the elapsed cycle count is less than the pause filter
 144  *      threshold, then the internal pause count is decremented. If the count
 145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 146  *      triggered. If advanced pause filtering is supported and pause filter
 147  *      threshold field is set to zero, the filter will operate in the simpler,
 148  *      count only mode.
 149  */
 150
 151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 152 module_param(pause_filter_thresh, ushort, 0444);
 153
 154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 155 module_param(pause_filter_count, ushort, 0444);
 156
 157 /* Default doubles per-vcpu window every exit. */
 158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 159 module_param(pause_filter_count_grow, ushort, 0444);
 160
 161 /* Default resets per-vcpu window every exit to pause_filter_count. */
 162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 163 module_param(pause_filter_count_shrink, ushort, 0444);
 164
 165 /* Default is to compute the maximum so we can never overflow. */
 166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 167 module_param(pause_filter_count_max, ushort, 0444);
 168
 169 /* allow nested paging (virtualized MMU) for all guests */
 170 static int npt = true;
 171 module_param(npt, int, S_IRUGO);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 /* enable/disable SEV-ES support */
 194 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 195 module_param(sev_es, int, 0444);
 196
 197 static bool __read_mostly dump_invalid_vmcb = 0;
 198 module_param(dump_invalid_vmcb, bool, 0644);
 199
 200 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 201
 202 static void svm_complete_interrupts(struct vcpu_svm *svm);
 203
 204 static unsigned long iopm_base;
 205
 206 struct kvm_ldttss_desc {
 207         u16 limit0;
 208         u16 base0;
 209         unsigned base1:8, type:5, dpl:2, p:1;
 210         unsigned limit1:4, zero0:3, g:1, base2:8;
 211         u32 base3;
 212         u32 zero1;
 213 } __attribute__((packed));
 214
 215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 216
 217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 218
 219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 220 #define MSRS_RANGE_SIZE 2048
 221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 222
 223 u32 svm_msrpm_offset(u32 msr)
 224 {
 225         u32 offset;
 226         int i;
 227
 228         for (i = 0; i < NUM_MSR_MAPS; i++) {
 229                 if (msr < msrpm_ranges[i] ||
 230                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 231                         continue;
 232
 233                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 234                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 235
 236                 /* Now we have the u8 offset - but need the u32 offset */
 237                 return offset / 4;
 238         }
 239
 240         /* MSR not in any range */
 241         return MSR_INVALID;
 242 }
 243
 244 #define MAX_INST_SIZE 15
 245
 246 static inline void clgi(void)
 247 {
 248         asm volatile (__ex("clgi"));
 249 }
 250
 251 static inline void stgi(void)
 252 {
 253         asm volatile (__ex("stgi"));
 254 }
 255
 256 static inline void invlpga(unsigned long addr, u32 asid)
 257 {
 258         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 259 }
 260
 261 static int get_max_npt_level(void)
 262 {
 263 #ifdef CONFIG_X86_64
 264         return PT64_ROOT_4LEVEL;
 265 #else
 266         return PT32E_ROOT_LEVEL;
 267 #endif
 268 }
 269
 270 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273         u64 old_efer = vcpu->arch.efer;
 274         vcpu->arch.efer = efer;
 275
 276         if (!npt_enabled) {
 277                 /* Shadow paging assumes NX to be available.  */
 278                 efer |= EFER_NX;
 279
 280                 if (!(efer & EFER_LMA))
 281                         efer &= ~EFER_LME;
 282         }
 283
 284         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 285                 if (!(efer & EFER_SVME)) {
 286                         svm_leave_nested(svm);
 287                         svm_set_gif(svm, true);
 288
 289                         /*
 290                          * Free the nested guest state, unless we are in SMM.
 291                          * In this case we will return to the nested guest
 292                          * as soon as we leave SMM.
 293                          */
 294                         if (!is_smm(&svm->vcpu))
 295                                 svm_free_nested(svm);
 296
 297                 } else {
 298                         int ret = svm_allocate_nested(svm);
 299
 300                         if (ret) {
 301                                 vcpu->arch.efer = old_efer;
 302                                 return ret;
 303                         }
 304                 }
 305         }
 306
 307         svm->vmcb->save.efer = efer | EFER_SVME;
 308         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 309         return 0;
 310 }
 311
 312 static int is_external_interrupt(u32 info)
 313 {
 314         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 315         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 316 }
 317
 318 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 319 {
 320         struct vcpu_svm *svm = to_svm(vcpu);
 321         u32 ret = 0;
 322
 323         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 324                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 325         return ret;
 326 }
 327
 328 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 329 {
 330         struct vcpu_svm *svm = to_svm(vcpu);
 331
 332         if (mask == 0)
 333                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 334         else
 335                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 336
 337 }
 338
 339 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 340 {
 341         struct vcpu_svm *svm = to_svm(vcpu);
 342
 343         /*
 344          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 345          * the type of exit and the #VC handler in the guest.
 346          */
 347         if (sev_es_guest(vcpu->kvm))
 348                 goto done;
 349
 350         if (nrips && svm->vmcb->control.next_rip != 0) {
 351                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 352                 svm->next_rip = svm->vmcb->control.next_rip;
 353         }
 354
 355         if (!svm->next_rip) {
 356                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 357                         return 0;
 358         } else {
 359                 kvm_rip_write(vcpu, svm->next_rip);
 360         }
 361
 362 done:
 363         svm_set_interrupt_shadow(vcpu, 0);
 364
 365         return 1;
 366 }
 367
 368 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 369 {
 370         struct vcpu_svm *svm = to_svm(vcpu);
 371         unsigned nr = vcpu->arch.exception.nr;
 372         bool has_error_code = vcpu->arch.exception.has_error_code;
 373         u32 error_code = vcpu->arch.exception.error_code;
 374
 375         kvm_deliver_exception_payload(&svm->vcpu);
 376
 377         if (nr == BP_VECTOR && !nrips) {
 378                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 379
 380                 /*
 381                  * For guest debugging where we have to reinject #BP if some
 382                  * INT3 is guest-owned:
 383                  * Emulate nRIP by moving RIP forward. Will fail if injection
 384                  * raises a fault that is not intercepted. Still better than
 385                  * failing in all cases.
 386                  */
 387                 (void)skip_emulated_instruction(&svm->vcpu);
 388                 rip = kvm_rip_read(&svm->vcpu);
 389                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 390                 svm->int3_injected = rip - old_rip;
 391         }
 392
 393         svm->vmcb->control.event_inj = nr
 394                 | SVM_EVTINJ_VALID
 395                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 396                 | SVM_EVTINJ_TYPE_EXEPT;
 397         svm->vmcb->control.event_inj_err = error_code;
 398 }
 399
 400 static void svm_init_erratum_383(void)
 401 {
 402         u32 low, high;
 403         int err;
 404         u64 val;
 405
 406         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 407                 return;
 408
 409         /* Use _safe variants to not break nested virtualization */
 410         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 411         if (err)
 412                 return;
 413
 414         val |= (1ULL << 47);
 415
 416         low  = lower_32_bits(val);
 417         high = upper_32_bits(val);
 418
 419         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 420
 421         erratum_383_found = true;
 422 }
 423
 424 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 425 {
 426         /*
 427          * Guests should see errata 400 and 415 as fixed (assuming that
 428          * HLT and IO instructions are intercepted).
 429          */
 430         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 431         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 432
 433         /*
 434          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 435          * all osvw.status bits inside that length, including bit 0 (which is
 436          * reserved for erratum 298), are valid. However, if host processor's
 437          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 438          * be conservative here and therefore we tell the guest that erratum 298
 439          * is present (because we really don't know).
 440          */
 441         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 442                 vcpu->arch.osvw.status |= 1;
 443 }
 444
 445 static int has_svm(void)
 446 {
 447         const char *msg;
 448
 449         if (!cpu_has_svm(&msg)) {
 450                 printk(KERN_INFO "has_svm: %s\n", msg);
 451                 return 0;
 452         }
 453
 454         return 1;
 455 }
 456
 457 static void svm_hardware_disable(void)
 458 {
 459         /* Make sure we clean up behind us */
 460         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 461                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 462
 463         cpu_svm_disable();
 464
 465         amd_pmu_disable_virt();
 466 }
 467
 468 static int svm_hardware_enable(void)
 469 {
 470
 471         struct svm_cpu_data *sd;
 472         uint64_t efer;
 473         struct desc_struct *gdt;
 474         int me = raw_smp_processor_id();
 475
 476         rdmsrl(MSR_EFER, efer);
 477         if (efer & EFER_SVME)
 478                 return -EBUSY;
 479
 480         if (!has_svm()) {
 481                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 482                 return -EINVAL;
 483         }
 484         sd = per_cpu(svm_data, me);
 485         if (!sd) {
 486                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 487                 return -EINVAL;
 488         }
 489
 490         sd->asid_generation = 1;
 491         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 492         sd->next_asid = sd->max_asid + 1;
 493         sd->min_asid = max_sev_asid + 1;
 494
 495         gdt = get_current_gdt_rw();
 496         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 497
 498         wrmsrl(MSR_EFER, efer | EFER_SVME);
 499
 500         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 501
 502         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 503                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 504                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 505         }
 506
 507
 508         /*
 509          * Get OSVW bits.
 510          *
 511          * Note that it is possible to have a system with mixed processor
 512          * revisions and therefore different OSVW bits. If bits are not the same
 513          * on different processors then choose the worst case (i.e. if erratum
 514          * is present on one processor and not on another then assume that the
 515          * erratum is present everywhere).
 516          */
 517         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 518                 uint64_t len, status = 0;
 519                 int err;
 520
 521                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 522                 if (!err)
 523                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 524                                                       &err);
 525
 526                 if (err)
 527                         osvw_status = osvw_len = 0;
 528                 else {
 529                         if (len < osvw_len)
 530                                 osvw_len = len;
 531                         osvw_status |= status;
 532                         osvw_status &= (1ULL << osvw_len) - 1;
 533                 }
 534         } else
 535                 osvw_status = osvw_len = 0;
 536
 537         svm_init_erratum_383();
 538
 539         amd_pmu_enable_virt();
 540
 541         return 0;
 542 }
 543
 544 static void svm_cpu_uninit(int cpu)
 545 {
 546         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 547
 548         if (!sd)
 549                 return;
 550
 551         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 552         kfree(sd->sev_vmcbs);
 553         __free_page(sd->save_area);
 554         kfree(sd);
 555 }
 556
 557 static int svm_cpu_init(int cpu)
 558 {
 559         struct svm_cpu_data *sd;
 560
 561         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 562         if (!sd)
 563                 return -ENOMEM;
 564         sd->cpu = cpu;
 565         sd->save_area = alloc_page(GFP_KERNEL);
 566         if (!sd->save_area)
 567                 goto free_cpu_data;
 568
 569         if (svm_sev_enabled()) {
 570                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 571                                               sizeof(void *),
 572                                               GFP_KERNEL);
 573                 if (!sd->sev_vmcbs)
 574                         goto free_save_area;
 575         }
 576
 577         per_cpu(svm_data, cpu) = sd;
 578
 579         return 0;
 580
 581 free_save_area:
 582         __free_page(sd->save_area);
 583 free_cpu_data:
 584         kfree(sd);
 585         return -ENOMEM;
 586
 587 }
 588
 589 static int direct_access_msr_slot(u32 msr)
 590 {
 591         u32 i;
 592
 593         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 594                 if (direct_access_msrs[i].index == msr)
 595                         return i;
 596
 597         return -ENOENT;
 598 }
 599
 600 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 601                                      int write)
 602 {
 603         struct vcpu_svm *svm = to_svm(vcpu);
 604         int slot = direct_access_msr_slot(msr);
 605
 606         if (slot == -ENOENT)
 607                 return;
 608
 609         /* Set the shadow bitmaps to the desired intercept states */
 610         if (read)
 611                 set_bit(slot, svm->shadow_msr_intercept.read);
 612         else
 613                 clear_bit(slot, svm->shadow_msr_intercept.read);
 614
 615         if (write)
 616                 set_bit(slot, svm->shadow_msr_intercept.write);
 617         else
 618                 clear_bit(slot, svm->shadow_msr_intercept.write);
 619 }
 620
 621 static bool valid_msr_intercept(u32 index)
 622 {
 623         return direct_access_msr_slot(index) != -ENOENT;
 624 }
 625
 626 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 627 {
 628         u8 bit_write;
 629         unsigned long tmp;
 630         u32 offset;
 631         u32 *msrpm;
 632
 633         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 634                                       to_svm(vcpu)->msrpm;
 635
 636         offset    = svm_msrpm_offset(msr);
 637         bit_write = 2 * (msr & 0x0f) + 1;
 638         tmp       = msrpm[offset];
 639
 640         BUG_ON(offset == MSR_INVALID);
 641
 642         return !!test_bit(bit_write,  &tmp);
 643 }
 644
 645 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 646                                         u32 msr, int read, int write)
 647 {
 648         u8 bit_read, bit_write;
 649         unsigned long tmp;
 650         u32 offset;
 651
 652         /*
 653          * If this warning triggers extend the direct_access_msrs list at the
 654          * beginning of the file
 655          */
 656         WARN_ON(!valid_msr_intercept(msr));
 657
 658         /* Enforce non allowed MSRs to trap */
 659         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 660                 read = 0;
 661
 662         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 663                 write = 0;
 664
 665         offset    = svm_msrpm_offset(msr);
 666         bit_read  = 2 * (msr & 0x0f);
 667         bit_write = 2 * (msr & 0x0f) + 1;
 668         tmp       = msrpm[offset];
 669
 670         BUG_ON(offset == MSR_INVALID);
 671
 672         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 673         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 674
 675         msrpm[offset] = tmp;
 676 }
 677
 678 static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 679                                  int read, int write)
 680 {
 681         set_shadow_msr_intercept(vcpu, msr, read, write);
 682         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 683 }
 684
 685 u32 *svm_vcpu_alloc_msrpm(void)
 686 {
 687         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
 688         u32 *msrpm;
 689
 690         if (!pages)
 691                 return NULL;
 692
 693         msrpm = page_address(pages);
 694         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 695
 696         return msrpm;
 697 }
 698
 699 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 700 {
 701         int i;
 702
 703         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 704                 if (!direct_access_msrs[i].always)
 705                         continue;
 706                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 707         }
 708 }
 709
 710
 711 void svm_vcpu_free_msrpm(u32 *msrpm)
 712 {
 713         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
 714 }
 715
 716 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 717 {
 718         struct vcpu_svm *svm = to_svm(vcpu);
 719         u32 i;
 720
 721         /*
 722          * Set intercept permissions for all direct access MSRs again. They
 723          * will automatically get filtered through the MSR filter, so we are
 724          * back in sync after this.
 725          */
 726         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 727                 u32 msr = direct_access_msrs[i].index;
 728                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 729                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 730
 731                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 732         }
 733 }
 734
 735 static void add_msr_offset(u32 offset)
 736 {
 737         int i;
 738
 739         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 740
 741                 /* Offset already in list? */
 742                 if (msrpm_offsets[i] == offset)
 743                         return;
 744
 745                 /* Slot used by another offset? */
 746                 if (msrpm_offsets[i] != MSR_INVALID)
 747                         continue;
 748
 749                 /* Add offset to list */
 750                 msrpm_offsets[i] = offset;
 751
 752                 return;
 753         }
 754
 755         /*
 756          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 757          * increase MSRPM_OFFSETS in this case.
 758          */
 759         BUG();
 760 }
 761
 762 static void init_msrpm_offsets(void)
 763 {
 764         int i;
 765
 766         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 767
 768         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 769                 u32 offset;
 770
 771                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 772                 BUG_ON(offset == MSR_INVALID);
 773
 774                 add_msr_offset(offset);
 775         }
 776 }
 777
 778 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 779 {
 780         struct vcpu_svm *svm = to_svm(vcpu);
 781
 782         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 783         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 784         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 785         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 786         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 787 }
 788
 789 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 790 {
 791         struct vcpu_svm *svm = to_svm(vcpu);
 792
 793         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 794         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 795         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 796         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 797         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 798 }
 799
 800 void disable_nmi_singlestep(struct vcpu_svm *svm)
 801 {
 802         svm->nmi_singlestep = false;
 803
 804         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 805                 /* Clear our flags if they were not set by the guest */
 806                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 807                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 808                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 809                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 810         }
 811 }
 812
 813 static void grow_ple_window(struct kvm_vcpu *vcpu)
 814 {
 815         struct vcpu_svm *svm = to_svm(vcpu);
 816         struct vmcb_control_area *control = &svm->vmcb->control;
 817         int old = control->pause_filter_count;
 818
 819         control->pause_filter_count = __grow_ple_window(old,
 820                                                         pause_filter_count,
 821                                                         pause_filter_count_grow,
 822                                                         pause_filter_count_max);
 823
 824         if (control->pause_filter_count != old) {
 825                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 826                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 827                                             control->pause_filter_count, old);
 828         }
 829 }
 830
 831 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 832 {
 833         struct vcpu_svm *svm = to_svm(vcpu);
 834         struct vmcb_control_area *control = &svm->vmcb->control;
 835         int old = control->pause_filter_count;
 836
 837         control->pause_filter_count =
 838                                 __shrink_ple_window(old,
 839                                                     pause_filter_count,
 840                                                     pause_filter_count_shrink,
 841                                                     pause_filter_count);
 842         if (control->pause_filter_count != old) {
 843                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 844                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 845                                             control->pause_filter_count, old);
 846         }
 847 }
 848
 849 /*
 850  * The default MMIO mask is a single bit (excluding the present bit),
 851  * which could conflict with the memory encryption bit. Check for
 852  * memory encryption support and override the default MMIO mask if
 853  * memory encryption is enabled.
 854  */
 855 static __init void svm_adjust_mmio_mask(void)
 856 {
 857         unsigned int enc_bit, mask_bit;
 858         u64 msr, mask;
 859
 860         /* If there is no memory encryption support, use existing mask */
 861         if (cpuid_eax(0x80000000) < 0x8000001f)
 862                 return;
 863
 864         /* If memory encryption is not enabled, use existing mask */
 865         rdmsrl(MSR_K8_SYSCFG, msr);
 866         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 867                 return;
 868
 869         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 870         mask_bit = boot_cpu_data.x86_phys_bits;
 871
 872         /* Increment the mask bit if it is the same as the encryption bit */
 873         if (enc_bit == mask_bit)
 874                 mask_bit++;
 875
 876         /*
 877          * If the mask bit location is below 52, then some bits above the
 878          * physical addressing limit will always be reserved, so use the
 879          * rsvd_bits() function to generate the mask. This mask, along with
 880          * the present bit, will be used to generate a page fault with
 881          * PFER.RSV = 1.
 882          *
 883          * If the mask bit location is 52 (or above), then clear the mask.
 884          */
 885         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 886
 887         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 888 }
 889
 890 static void svm_hardware_teardown(void)
 891 {
 892         int cpu;
 893
 894         if (svm_sev_enabled())
 895                 sev_hardware_teardown();
 896
 897         for_each_possible_cpu(cpu)
 898                 svm_cpu_uninit(cpu);
 899
 900         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 901         iopm_base = 0;
 902 }
 903
 904 static __init void svm_set_cpu_caps(void)
 905 {
 906         kvm_set_cpu_caps();
 907
 908         supported_xss = 0;
 909
 910         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 911         if (nested) {
 912                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 913
 914                 if (nrips)
 915                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 916
 917                 if (npt_enabled)
 918                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 919         }
 920
 921         /* CPUID 0x80000008 */
 922         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 923             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 924                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 925
 926         /* Enable INVPCID feature */
 927         kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
 928 }
 929
 930 static __init int svm_hardware_setup(void)
 931 {
 932         int cpu;
 933         struct page *iopm_pages;
 934         void *iopm_va;
 935         int r;
 936
 937         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 938
 939         if (!iopm_pages)
 940                 return -ENOMEM;
 941
 942         iopm_va = page_address(iopm_pages);
 943         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 944         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 945
 946         init_msrpm_offsets();
 947
 948         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 949
 950         if (boot_cpu_has(X86_FEATURE_NX))
 951                 kvm_enable_efer_bits(EFER_NX);
 952
 953         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 954                 kvm_enable_efer_bits(EFER_FFXSR);
 955
 956         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 957                 kvm_has_tsc_control = true;
 958                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 959                 kvm_tsc_scaling_ratio_frac_bits = 32;
 960         }
 961
 962         /* Check for pause filtering support */
 963         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 964                 pause_filter_count = 0;
 965                 pause_filter_thresh = 0;
 966         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 967                 pause_filter_thresh = 0;
 968         }
 969
 970         if (nested) {
 971                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 972                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 973         }
 974
 975         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 976                 sev_hardware_setup();
 977         } else {
 978                 sev = false;
 979                 sev_es = false;
 980         }
 981
 982         svm_adjust_mmio_mask();
 983
 984         for_each_possible_cpu(cpu) {
 985                 r = svm_cpu_init(cpu);
 986                 if (r)
 987                         goto err;
 988         }
 989
 990         if (!boot_cpu_has(X86_FEATURE_NPT))
 991                 npt_enabled = false;
 992
 993         if (npt_enabled && !npt)
 994                 npt_enabled = false;
 995
 996         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 997         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 998
 999         if (nrips) {
1000                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1001                         nrips = false;
1002         }
1003
1004         if (avic) {
1005                 if (!npt_enabled ||
1006                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1007                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1008                         avic = false;
1009                 } else {
1010                         pr_info("AVIC enabled\n");
1011
1012                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1013                 }
1014         }
1015
1016         if (vls) {
1017                 if (!npt_enabled ||
1018                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1019                     !IS_ENABLED(CONFIG_X86_64)) {
1020                         vls = false;
1021                 } else {
1022                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1023                 }
1024         }
1025
1026         if (vgif) {
1027                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1028                         vgif = false;
1029                 else
1030                         pr_info("Virtual GIF supported\n");
1031         }
1032
1033         svm_set_cpu_caps();
1034
1035         /*
1036          * It seems that on AMD processors PTE's accessed bit is
1037          * being set by the CPU hardware before the NPF vmexit.
1038          * This is not expected behaviour and our tests fail because
1039          * of it.
1040          * A workaround here is to disable support for
1041          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1042          * In this case userspace can know if there is support using
1043          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1044          * it
1045          * If future AMD CPU models change the behaviour described above,
1046          * this variable can be changed accordingly
1047          */
1048         allow_smaller_maxphyaddr = !npt_enabled;
1049
1050         return 0;
1051
1052 err:
1053         svm_hardware_teardown();
1054         return r;
1055 }
1056
1057 static void init_seg(struct vmcb_seg *seg)
1058 {
1059         seg->selector = 0;
1060         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1061                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1062         seg->limit = 0xffff;
1063         seg->base = 0;
1064 }
1065
1066 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1067 {
1068         seg->selector = 0;
1069         seg->attrib = SVM_SELECTOR_P_MASK | type;
1070         seg->limit = 0xffff;
1071         seg->base = 0;
1072 }
1073
1074 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1075 {
1076         struct vcpu_svm *svm = to_svm(vcpu);
1077         u64 g_tsc_offset = 0;
1078
1079         if (is_guest_mode(vcpu)) {
1080                 /* Write L1's TSC offset.  */
1081                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1082                                svm->nested.hsave->control.tsc_offset;
1083                 svm->nested.hsave->control.tsc_offset = offset;
1084         }
1085
1086         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1087                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1088                                    offset);
1089
1090         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1091
1092         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1093         return svm->vmcb->control.tsc_offset;
1094 }
1095
1096 static void svm_check_invpcid(struct vcpu_svm *svm)
1097 {
1098         /*
1099          * Intercept INVPCID instruction only if shadow page table is
1100          * enabled. Interception is not required with nested page table
1101          * enabled.
1102          */
1103         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1104                 if (!npt_enabled)
1105                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1106                 else
1107                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1108         }
1109 }
1110
1111 static void init_vmcb(struct vcpu_svm *svm)
1112 {
1113         struct vmcb_control_area *control = &svm->vmcb->control;
1114         struct vmcb_save_area *save = &svm->vmcb->save;
1115
1116         svm->vcpu.arch.hflags = 0;
1117
1118         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1119         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1120         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1121         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1122         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1123         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1124         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1125                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1126
1127         set_dr_intercepts(svm);
1128
1129         set_exception_intercept(svm, PF_VECTOR);
1130         set_exception_intercept(svm, UD_VECTOR);
1131         set_exception_intercept(svm, MC_VECTOR);
1132         set_exception_intercept(svm, AC_VECTOR);
1133         set_exception_intercept(svm, DB_VECTOR);
1134         /*
1135          * Guest access to VMware backdoor ports could legitimately
1136          * trigger #GP because of TSS I/O permission bitmap.
1137          * We intercept those #GP and allow access to them anyway
1138          * as VMware does.
1139          */
1140         if (enable_vmware_backdoor)
1141                 set_exception_intercept(svm, GP_VECTOR);
1142
1143         svm_set_intercept(svm, INTERCEPT_INTR);
1144         svm_set_intercept(svm, INTERCEPT_NMI);
1145         svm_set_intercept(svm, INTERCEPT_SMI);
1146         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1147         svm_set_intercept(svm, INTERCEPT_RDPMC);
1148         svm_set_intercept(svm, INTERCEPT_CPUID);
1149         svm_set_intercept(svm, INTERCEPT_INVD);
1150         svm_set_intercept(svm, INTERCEPT_INVLPG);
1151         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1152         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1153         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1154         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1155         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1156         svm_set_intercept(svm, INTERCEPT_VMRUN);
1157         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1158         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1159         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1160         svm_set_intercept(svm, INTERCEPT_STGI);
1161         svm_set_intercept(svm, INTERCEPT_CLGI);
1162         svm_set_intercept(svm, INTERCEPT_SKINIT);
1163         svm_set_intercept(svm, INTERCEPT_WBINVD);
1164         svm_set_intercept(svm, INTERCEPT_XSETBV);
1165         svm_set_intercept(svm, INTERCEPT_RDPRU);
1166         svm_set_intercept(svm, INTERCEPT_RSM);
1167
1168         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1169                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1170                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1171         }
1172
1173         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1174                 svm_set_intercept(svm, INTERCEPT_HLT);
1175
1176         control->iopm_base_pa = __sme_set(iopm_base);
1177         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1178         control->int_ctl = V_INTR_MASKING_MASK;
1179
1180         init_seg(&save->es);
1181         init_seg(&save->ss);
1182         init_seg(&save->ds);
1183         init_seg(&save->fs);
1184         init_seg(&save->gs);
1185
1186         save->cs.selector = 0xf000;
1187         save->cs.base = 0xffff0000;
1188         /* Executable/Readable Code Segment */
1189         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1190                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1191         save->cs.limit = 0xffff;
1192
1193         save->gdtr.limit = 0xffff;
1194         save->idtr.limit = 0xffff;
1195
1196         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1197         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1198
1199         svm_set_efer(&svm->vcpu, 0);
1200         save->dr6 = 0xffff0ff0;
1201         kvm_set_rflags(&svm->vcpu, 2);
1202         save->rip = 0x0000fff0;
1203         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1204
1205         /*
1206          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1207          * It also updates the guest-visible cr0 value.
1208          */
1209         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1210         kvm_mmu_reset_context(&svm->vcpu);
1211
1212         save->cr4 = X86_CR4_PAE;
1213         /* rdx = ?? */
1214
1215         if (npt_enabled) {
1216                 /* Setup VMCB for Nested Paging */
1217                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1218                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1219                 clr_exception_intercept(svm, PF_VECTOR);
1220                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1221                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1222                 save->g_pat = svm->vcpu.arch.pat;
1223                 save->cr3 = 0;
1224                 save->cr4 = 0;
1225         }
1226         svm->asid_generation = 0;
1227         svm->asid = 0;
1228
1229         svm->nested.vmcb12_gpa = 0;
1230         svm->vcpu.arch.hflags = 0;
1231
1232         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1233                 control->pause_filter_count = pause_filter_count;
1234                 if (pause_filter_thresh)
1235                         control->pause_filter_thresh = pause_filter_thresh;
1236                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1237         } else {
1238                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1239         }
1240
1241         svm_check_invpcid(svm);
1242
1243         if (kvm_vcpu_apicv_active(&svm->vcpu))
1244                 avic_init_vmcb(svm);
1245
1246         /*
1247          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1248          * in VMCB and clear intercepts to avoid #VMEXIT.
1249          */
1250         if (vls) {
1251                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1252                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1253                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1254         }
1255
1256         if (vgif) {
1257                 svm_clr_intercept(svm, INTERCEPT_STGI);
1258                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1259                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1260         }
1261
1262         if (sev_guest(svm->vcpu.kvm)) {
1263                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1264                 clr_exception_intercept(svm, UD_VECTOR);
1265         }
1266
1267         vmcb_mark_all_dirty(svm->vmcb);
1268
1269         enable_gif(svm);
1270
1271 }
1272
1273 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1274 {
1275         struct vcpu_svm *svm = to_svm(vcpu);
1276         u32 dummy;
1277         u32 eax = 1;
1278
1279         svm->spec_ctrl = 0;
1280         svm->virt_spec_ctrl = 0;
1281
1282         if (!init_event) {
1283                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1284                                            MSR_IA32_APICBASE_ENABLE;
1285                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1286                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1287         }
1288         init_vmcb(svm);
1289
1290         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1291         kvm_rdx_write(vcpu, eax);
1292
1293         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1294                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1295 }
1296
1297 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1298 {
1299         struct vcpu_svm *svm;
1300         struct page *vmcb_page;
1301         struct page *vmsa_page = NULL;
1302         int err;
1303
1304         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1305         svm = to_svm(vcpu);
1306
1307         err = -ENOMEM;
1308         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1309         if (!vmcb_page)
1310                 goto out;
1311
1312         if (sev_es_guest(svm->vcpu.kvm)) {
1313                 /*
1314                  * SEV-ES guests require a separate VMSA page used to contain
1315                  * the encrypted register state of the guest.
1316                  */
1317                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1318                 if (!vmsa_page)
1319                         goto error_free_vmcb_page;
1320         }
1321
1322         err = avic_init_vcpu(svm);
1323         if (err)
1324                 goto error_free_vmsa_page;
1325
1326         /* We initialize this flag to true to make sure that the is_running
1327          * bit would be set the first time the vcpu is loaded.
1328          */
1329         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1330                 svm->avic_is_running = true;
1331
1332         svm->msrpm = svm_vcpu_alloc_msrpm();
1333         if (!svm->msrpm)
1334                 goto error_free_vmsa_page;
1335
1336         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1337
1338         svm->vmcb = page_address(vmcb_page);
1339         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1340
1341         if (vmsa_page)
1342                 svm->vmsa = page_address(vmsa_page);
1343
1344         svm->asid_generation = 0;
1345         init_vmcb(svm);
1346
1347         svm_init_osvw(vcpu);
1348         vcpu->arch.microcode_version = 0x01000065;
1349
1350         return 0;
1351
1352 error_free_vmsa_page:
1353         if (vmsa_page)
1354                 __free_page(vmsa_page);
1355 error_free_vmcb_page:
1356         __free_page(vmcb_page);
1357 out:
1358         return err;
1359 }
1360
1361 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1362 {
1363         int i;
1364
1365         for_each_online_cpu(i)
1366                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1367 }
1368
1369 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1370 {
1371         struct vcpu_svm *svm = to_svm(vcpu);
1372
1373         /*
1374          * The vmcb page can be recycled, causing a false negative in
1375          * svm_vcpu_load(). So, ensure that no logical CPU has this
1376          * vmcb page recorded as its current vmcb.
1377          */
1378         svm_clear_current_vmcb(svm->vmcb);
1379
1380         svm_free_nested(svm);
1381
1382         sev_free_vcpu(vcpu);
1383
1384         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1385         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1386 }
1387
1388 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1389 {
1390         struct vcpu_svm *svm = to_svm(vcpu);
1391         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1392         int i;
1393
1394         if (unlikely(cpu != vcpu->cpu)) {
1395                 svm->asid_generation = 0;
1396                 vmcb_mark_all_dirty(svm->vmcb);
1397         }
1398
1399 #ifdef CONFIG_X86_64
1400         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1401 #endif
1402         savesegment(fs, svm->host.fs);
1403         savesegment(gs, svm->host.gs);
1404         svm->host.ldt = kvm_read_ldt();
1405
1406         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1407                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1408
1409         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1410                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1411                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1412                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1413                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1414                 }
1415         }
1416         /* This assumes that the kernel never uses MSR_TSC_AUX */
1417         if (static_cpu_has(X86_FEATURE_RDTSCP))
1418                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1419
1420         if (sd->current_vmcb != svm->vmcb) {
1421                 sd->current_vmcb = svm->vmcb;
1422                 indirect_branch_prediction_barrier();
1423         }
1424         avic_vcpu_load(vcpu, cpu);
1425 }
1426
1427 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1428 {
1429         struct vcpu_svm *svm = to_svm(vcpu);
1430         int i;
1431
1432         avic_vcpu_put(vcpu);
1433
1434         ++vcpu->stat.host_state_reload;
1435         kvm_load_ldt(svm->host.ldt);
1436 #ifdef CONFIG_X86_64
1437         loadsegment(fs, svm->host.fs);
1438         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1439         load_gs_index(svm->host.gs);
1440 #else
1441 #ifdef CONFIG_X86_32_LAZY_GS
1442         loadsegment(gs, svm->host.gs);
1443 #endif
1444 #endif
1445         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1446                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1447 }
1448
1449 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1450 {
1451         struct vcpu_svm *svm = to_svm(vcpu);
1452         unsigned long rflags = svm->vmcb->save.rflags;
1453
1454         if (svm->nmi_singlestep) {
1455                 /* Hide our flags if they were not set by the guest */
1456                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1457                         rflags &= ~X86_EFLAGS_TF;
1458                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1459                         rflags &= ~X86_EFLAGS_RF;
1460         }
1461         return rflags;
1462 }
1463
1464 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1465 {
1466         if (to_svm(vcpu)->nmi_singlestep)
1467                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1468
1469        /*
1470         * Any change of EFLAGS.VM is accompanied by a reload of SS
1471         * (caused by either a task switch or an inter-privilege IRET),
1472         * so we do not need to update the CPL here.
1473         */
1474         to_svm(vcpu)->vmcb->save.rflags = rflags;
1475 }
1476
1477 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1478 {
1479         switch (reg) {
1480         case VCPU_EXREG_PDPTR:
1481                 BUG_ON(!npt_enabled);
1482                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1483                 break;
1484         default:
1485                 WARN_ON_ONCE(1);
1486         }
1487 }
1488
1489 static void svm_set_vintr(struct vcpu_svm *svm)
1490 {
1491         struct vmcb_control_area *control;
1492
1493         /* The following fields are ignored when AVIC is enabled */
1494         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1495         svm_set_intercept(svm, INTERCEPT_VINTR);
1496
1497         /*
1498          * This is just a dummy VINTR to actually cause a vmexit to happen.
1499          * Actual injection of virtual interrupts happens through EVENTINJ.
1500          */
1501         control = &svm->vmcb->control;
1502         control->int_vector = 0x0;
1503         control->int_ctl &= ~V_INTR_PRIO_MASK;
1504         control->int_ctl |= V_IRQ_MASK |
1505                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1506         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1507 }
1508
1509 static void svm_clear_vintr(struct vcpu_svm *svm)
1510 {
1511         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1512         svm_clr_intercept(svm, INTERCEPT_VINTR);
1513
1514         /* Drop int_ctl fields related to VINTR injection.  */
1515         svm->vmcb->control.int_ctl &= mask;
1516         if (is_guest_mode(&svm->vcpu)) {
1517                 svm->nested.hsave->control.int_ctl &= mask;
1518
1519                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1520                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1521                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1522         }
1523
1524         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1525 }
1526
1527 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1528 {
1529         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1530
1531         switch (seg) {
1532         case VCPU_SREG_CS: return &save->cs;
1533         case VCPU_SREG_DS: return &save->ds;
1534         case VCPU_SREG_ES: return &save->es;
1535         case VCPU_SREG_FS: return &save->fs;
1536         case VCPU_SREG_GS: return &save->gs;
1537         case VCPU_SREG_SS: return &save->ss;
1538         case VCPU_SREG_TR: return &save->tr;
1539         case VCPU_SREG_LDTR: return &save->ldtr;
1540         }
1541         BUG();
1542         return NULL;
1543 }
1544
1545 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1546 {
1547         struct vmcb_seg *s = svm_seg(vcpu, seg);
1548
1549         return s->base;
1550 }
1551
1552 static void svm_get_segment(struct kvm_vcpu *vcpu,
1553                             struct kvm_segment *var, int seg)
1554 {
1555         struct vmcb_seg *s = svm_seg(vcpu, seg);
1556
1557         var->base = s->base;
1558         var->limit = s->limit;
1559         var->selector = s->selector;
1560         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1561         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1562         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1563         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1564         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1565         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1566         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1567
1568         /*
1569          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1570          * However, the SVM spec states that the G bit is not observed by the
1571          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1572          * So let's synthesize a legal G bit for all segments, this helps
1573          * running KVM nested. It also helps cross-vendor migration, because
1574          * Intel's vmentry has a check on the 'G' bit.
1575          */
1576         var->g = s->limit > 0xfffff;
1577
1578         /*
1579          * AMD's VMCB does not have an explicit unusable field, so emulate it
1580          * for cross vendor migration purposes by "not present"
1581          */
1582         var->unusable = !var->present;
1583
1584         switch (seg) {
1585         case VCPU_SREG_TR:
1586                 /*
1587                  * Work around a bug where the busy flag in the tr selector
1588                  * isn't exposed
1589                  */
1590                 var->type |= 0x2;
1591                 break;
1592         case VCPU_SREG_DS:
1593         case VCPU_SREG_ES:
1594         case VCPU_SREG_FS:
1595         case VCPU_SREG_GS:
1596                 /*
1597                  * The accessed bit must always be set in the segment
1598                  * descriptor cache, although it can be cleared in the
1599                  * descriptor, the cached bit always remains at 1. Since
1600                  * Intel has a check on this, set it here to support
1601                  * cross-vendor migration.
1602                  */
1603                 if (!var->unusable)
1604                         var->type |= 0x1;
1605                 break;
1606         case VCPU_SREG_SS:
1607                 /*
1608                  * On AMD CPUs sometimes the DB bit in the segment
1609                  * descriptor is left as 1, although the whole segment has
1610                  * been made unusable. Clear it here to pass an Intel VMX
1611                  * entry check when cross vendor migrating.
1612                  */
1613                 if (var->unusable)
1614                         var->db = 0;
1615                 /* This is symmetric with svm_set_segment() */
1616                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1617                 break;
1618         }
1619 }
1620
1621 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1622 {
1623         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1624
1625         return save->cpl;
1626 }
1627
1628 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1629 {
1630         struct vcpu_svm *svm = to_svm(vcpu);
1631
1632         dt->size = svm->vmcb->save.idtr.limit;
1633         dt->address = svm->vmcb->save.idtr.base;
1634 }
1635
1636 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1637 {
1638         struct vcpu_svm *svm = to_svm(vcpu);
1639
1640         svm->vmcb->save.idtr.limit = dt->size;
1641         svm->vmcb->save.idtr.base = dt->address ;
1642         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1643 }
1644
1645 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1646 {
1647         struct vcpu_svm *svm = to_svm(vcpu);
1648
1649         dt->size = svm->vmcb->save.gdtr.limit;
1650         dt->address = svm->vmcb->save.gdtr.base;
1651 }
1652
1653 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1654 {
1655         struct vcpu_svm *svm = to_svm(vcpu);
1656
1657         svm->vmcb->save.gdtr.limit = dt->size;
1658         svm->vmcb->save.gdtr.base = dt->address ;
1659         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1660 }
1661
1662 static void update_cr0_intercept(struct vcpu_svm *svm)
1663 {
1664         ulong gcr0;
1665         u64 *hcr0;
1666
1667         /*
1668          * SEV-ES guests must always keep the CR intercepts cleared. CR
1669          * tracking is done using the CR write traps.
1670          */
1671         if (sev_es_guest(svm->vcpu.kvm))
1672                 return;
1673
1674         gcr0 = svm->vcpu.arch.cr0;
1675         hcr0 = &svm->vmcb->save.cr0;
1676         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1677                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1678
1679         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1680
1681         if (gcr0 == *hcr0) {
1682                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1683                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1684         } else {
1685                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1686                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1687         }
1688 }
1689
1690 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1691 {
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693
1694 #ifdef CONFIG_X86_64
1695         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1696                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1697                         vcpu->arch.efer |= EFER_LMA;
1698                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1699                 }
1700
1701                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1702                         vcpu->arch.efer &= ~EFER_LMA;
1703                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1704                 }
1705         }
1706 #endif
1707         vcpu->arch.cr0 = cr0;
1708
1709         if (!npt_enabled)
1710                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1711
1712         /*
1713          * re-enable caching here because the QEMU bios
1714          * does not do it - this results in some delay at
1715          * reboot
1716          */
1717         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1718                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1719         svm->vmcb->save.cr0 = cr0;
1720         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1721         update_cr0_intercept(svm);
1722 }
1723
1724 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1725 {
1726         return true;
1727 }
1728
1729 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1730 {
1731         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1732         unsigned long old_cr4 = vcpu->arch.cr4;
1733
1734         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1735                 svm_flush_tlb(vcpu);
1736
1737         vcpu->arch.cr4 = cr4;
1738         if (!npt_enabled)
1739                 cr4 |= X86_CR4_PAE;
1740         cr4 |= host_cr4_mce;
1741         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1742         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1743
1744         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1745                 kvm_update_cpuid_runtime(vcpu);
1746 }
1747
1748 static void svm_set_segment(struct kvm_vcpu *vcpu,
1749                             struct kvm_segment *var, int seg)
1750 {
1751         struct vcpu_svm *svm = to_svm(vcpu);
1752         struct vmcb_seg *s = svm_seg(vcpu, seg);
1753
1754         s->base = var->base;
1755         s->limit = var->limit;
1756         s->selector = var->selector;
1757         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1758         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1759         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1760         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1761         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1762         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1763         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1764         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1765
1766         /*
1767          * This is always accurate, except if SYSRET returned to a segment
1768          * with SS.DPL != 3.  Intel does not have this quirk, and always
1769          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1770          * would entail passing the CPL to userspace and back.
1771          */
1772         if (seg == VCPU_SREG_SS)
1773                 /* This is symmetric with svm_get_segment() */
1774                 svm->vmcb->save.cpl = (var->dpl & 3);
1775
1776         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1777 }
1778
1779 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1780 {
1781         struct vcpu_svm *svm = to_svm(vcpu);
1782
1783         clr_exception_intercept(svm, BP_VECTOR);
1784
1785         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1786                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1787                         set_exception_intercept(svm, BP_VECTOR);
1788         }
1789 }
1790
1791 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1792 {
1793         if (sd->next_asid > sd->max_asid) {
1794                 ++sd->asid_generation;
1795                 sd->next_asid = sd->min_asid;
1796                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1797                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1798         }
1799
1800         svm->asid_generation = sd->asid_generation;
1801         svm->asid = sd->next_asid++;
1802 }
1803
1804 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1805 {
1806         struct vmcb *vmcb = svm->vmcb;
1807
1808         if (unlikely(value != vmcb->save.dr6)) {
1809                 vmcb->save.dr6 = value;
1810                 vmcb_mark_dirty(vmcb, VMCB_DR);
1811         }
1812 }
1813
1814 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1815 {
1816         struct vcpu_svm *svm = to_svm(vcpu);
1817
1818         get_debugreg(vcpu->arch.db[0], 0);
1819         get_debugreg(vcpu->arch.db[1], 1);
1820         get_debugreg(vcpu->arch.db[2], 2);
1821         get_debugreg(vcpu->arch.db[3], 3);
1822         /*
1823          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1824          * because db_interception might need it.  We can do it before vmentry.
1825          */
1826         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1827         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1828         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1829         set_dr_intercepts(svm);
1830 }
1831
1832 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1833 {
1834         struct vcpu_svm *svm = to_svm(vcpu);
1835
1836         svm->vmcb->save.dr7 = value;
1837         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1838 }
1839
1840 static int pf_interception(struct vcpu_svm *svm)
1841 {
1842         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1843         u64 error_code = svm->vmcb->control.exit_info_1;
1844
1845         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1846                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1847                         svm->vmcb->control.insn_bytes : NULL,
1848                         svm->vmcb->control.insn_len);
1849 }
1850
1851 static int npf_interception(struct vcpu_svm *svm)
1852 {
1853         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1854         u64 error_code = svm->vmcb->control.exit_info_1;
1855
1856         trace_kvm_page_fault(fault_address, error_code);
1857         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1858                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1859                         svm->vmcb->control.insn_bytes : NULL,
1860                         svm->vmcb->control.insn_len);
1861 }
1862
1863 static int db_interception(struct vcpu_svm *svm)
1864 {
1865         struct kvm_run *kvm_run = svm->vcpu.run;
1866         struct kvm_vcpu *vcpu = &svm->vcpu;
1867
1868         if (!(svm->vcpu.guest_debug &
1869               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1870                 !svm->nmi_singlestep) {
1871                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1872                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1873                 return 1;
1874         }
1875
1876         if (svm->nmi_singlestep) {
1877                 disable_nmi_singlestep(svm);
1878                 /* Make sure we check for pending NMIs upon entry */
1879                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1880         }
1881
1882         if (svm->vcpu.guest_debug &
1883             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1884                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1885                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1886                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1887                 kvm_run->debug.arch.pc =
1888                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1889                 kvm_run->debug.arch.exception = DB_VECTOR;
1890                 return 0;
1891         }
1892
1893         return 1;
1894 }
1895
1896 static int bp_interception(struct vcpu_svm *svm)
1897 {
1898         struct kvm_run *kvm_run = svm->vcpu.run;
1899
1900         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1901         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1902         kvm_run->debug.arch.exception = BP_VECTOR;
1903         return 0;
1904 }
1905
1906 static int ud_interception(struct vcpu_svm *svm)
1907 {
1908         return handle_ud(&svm->vcpu);
1909 }
1910
1911 static int ac_interception(struct vcpu_svm *svm)
1912 {
1913         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1914         return 1;
1915 }
1916
1917 static int gp_interception(struct vcpu_svm *svm)
1918 {
1919         struct kvm_vcpu *vcpu = &svm->vcpu;
1920         u32 error_code = svm->vmcb->control.exit_info_1;
1921
1922         WARN_ON_ONCE(!enable_vmware_backdoor);
1923
1924         /*
1925          * VMware backdoor emulation on #GP interception only handles IN{S},
1926          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1927          */
1928         if (error_code) {
1929                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1930                 return 1;
1931         }
1932         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1933 }
1934
1935 static bool is_erratum_383(void)
1936 {
1937         int err, i;
1938         u64 value;
1939
1940         if (!erratum_383_found)
1941                 return false;
1942
1943         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1944         if (err)
1945                 return false;
1946
1947         /* Bit 62 may or may not be set for this mce */
1948         value &= ~(1ULL << 62);
1949
1950         if (value != 0xb600000000010015ULL)
1951                 return false;
1952
1953         /* Clear MCi_STATUS registers */
1954         for (i = 0; i < 6; ++i)
1955                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1956
1957         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1958         if (!err) {
1959                 u32 low, high;
1960
1961                 value &= ~(1ULL << 2);
1962                 low    = lower_32_bits(value);
1963                 high   = upper_32_bits(value);
1964
1965                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1966         }
1967
1968         /* Flush tlb to evict multi-match entries */
1969         __flush_tlb_all();
1970
1971         return true;
1972 }
1973
1974 static void svm_handle_mce(struct vcpu_svm *svm)
1975 {
1976         if (is_erratum_383()) {
1977                 /*
1978                  * Erratum 383 triggered. Guest state is corrupt so kill the
1979                  * guest.
1980                  */
1981                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1982
1983                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1984
1985                 return;
1986         }
1987
1988         /*
1989          * On an #MC intercept the MCE handler is not called automatically in
1990          * the host. So do it by hand here.
1991          */
1992         kvm_machine_check();
1993 }
1994
1995 static int mc_interception(struct vcpu_svm *svm)
1996 {
1997         return 1;
1998 }
1999
2000 static int shutdown_interception(struct vcpu_svm *svm)
2001 {
2002         struct kvm_run *kvm_run = svm->vcpu.run;
2003
2004         /*
2005          * VMCB is undefined after a SHUTDOWN intercept
2006          * so reinitialize it.
2007          */
2008         clear_page(svm->vmcb);
2009         init_vmcb(svm);
2010
2011         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2012         return 0;
2013 }
2014
2015 static int io_interception(struct vcpu_svm *svm)
2016 {
2017         struct kvm_vcpu *vcpu = &svm->vcpu;
2018         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2019         int size, in, string;
2020         unsigned port;
2021
2022         ++svm->vcpu.stat.io_exits;
2023         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2024         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2025         if (string)
2026                 return kvm_emulate_instruction(vcpu, 0);
2027
2028         port = io_info >> 16;
2029         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2030         svm->next_rip = svm->vmcb->control.exit_info_2;
2031
2032         return kvm_fast_pio(&svm->vcpu, size, port, in);
2033 }
2034
2035 static int nmi_interception(struct vcpu_svm *svm)
2036 {
2037         return 1;
2038 }
2039
2040 static int intr_interception(struct vcpu_svm *svm)
2041 {
2042         ++svm->vcpu.stat.irq_exits;
2043         return 1;
2044 }
2045
2046 static int nop_on_interception(struct vcpu_svm *svm)
2047 {
2048         return 1;
2049 }
2050
2051 static int halt_interception(struct vcpu_svm *svm)
2052 {
2053         return kvm_emulate_halt(&svm->vcpu);
2054 }
2055
2056 static int vmmcall_interception(struct vcpu_svm *svm)
2057 {
2058         return kvm_emulate_hypercall(&svm->vcpu);
2059 }
2060
2061 static int vmload_interception(struct vcpu_svm *svm)
2062 {
2063         struct vmcb *nested_vmcb;
2064         struct kvm_host_map map;
2065         int ret;
2066
2067         if (nested_svm_check_permissions(svm))
2068                 return 1;
2069
2070         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2071         if (ret) {
2072                 if (ret == -EINVAL)
2073                         kvm_inject_gp(&svm->vcpu, 0);
2074                 return 1;
2075         }
2076
2077         nested_vmcb = map.hva;
2078
2079         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2080
2081         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2082         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2083
2084         return ret;
2085 }
2086
2087 static int vmsave_interception(struct vcpu_svm *svm)
2088 {
2089         struct vmcb *nested_vmcb;
2090         struct kvm_host_map map;
2091         int ret;
2092
2093         if (nested_svm_check_permissions(svm))
2094                 return 1;
2095
2096         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2097         if (ret) {
2098                 if (ret == -EINVAL)
2099                         kvm_inject_gp(&svm->vcpu, 0);
2100                 return 1;
2101         }
2102
2103         nested_vmcb = map.hva;
2104
2105         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2106
2107         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2108         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2109
2110         return ret;
2111 }
2112
2113 static int vmrun_interception(struct vcpu_svm *svm)
2114 {
2115         if (nested_svm_check_permissions(svm))
2116                 return 1;
2117
2118         return nested_svm_vmrun(svm);
2119 }
2120
2121 void svm_set_gif(struct vcpu_svm *svm, bool value)
2122 {
2123         if (value) {
2124                 /*
2125                  * If VGIF is enabled, the STGI intercept is only added to
2126                  * detect the opening of the SMI/NMI window; remove it now.
2127                  * Likewise, clear the VINTR intercept, we will set it
2128                  * again while processing KVM_REQ_EVENT if needed.
2129                  */
2130                 if (vgif_enabled(svm))
2131                         svm_clr_intercept(svm, INTERCEPT_STGI);
2132                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2133                         svm_clear_vintr(svm);
2134
2135                 enable_gif(svm);
2136                 if (svm->vcpu.arch.smi_pending ||
2137                     svm->vcpu.arch.nmi_pending ||
2138                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2139                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2140         } else {
2141                 disable_gif(svm);
2142
2143                 /*
2144                  * After a CLGI no interrupts should come.  But if vGIF is
2145                  * in use, we still rely on the VINTR intercept (rather than
2146                  * STGI) to detect an open interrupt window.
2147                 */
2148                 if (!vgif_enabled(svm))
2149                         svm_clear_vintr(svm);
2150         }
2151 }
2152
2153 static int stgi_interception(struct vcpu_svm *svm)
2154 {
2155         int ret;
2156
2157         if (nested_svm_check_permissions(svm))
2158                 return 1;
2159
2160         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2161         svm_set_gif(svm, true);
2162         return ret;
2163 }
2164
2165 static int clgi_interception(struct vcpu_svm *svm)
2166 {
2167         int ret;
2168
2169         if (nested_svm_check_permissions(svm))
2170                 return 1;
2171
2172         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2173         svm_set_gif(svm, false);
2174         return ret;
2175 }
2176
2177 static int invlpga_interception(struct vcpu_svm *svm)
2178 {
2179         struct kvm_vcpu *vcpu = &svm->vcpu;
2180
2181         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2182                           kvm_rax_read(&svm->vcpu));
2183
2184         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2185         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2186
2187         return kvm_skip_emulated_instruction(&svm->vcpu);
2188 }
2189
2190 static int skinit_interception(struct vcpu_svm *svm)
2191 {
2192         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2193
2194         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2195         return 1;
2196 }
2197
2198 static int wbinvd_interception(struct vcpu_svm *svm)
2199 {
2200         return kvm_emulate_wbinvd(&svm->vcpu);
2201 }
2202
2203 static int xsetbv_interception(struct vcpu_svm *svm)
2204 {
2205         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2206         u32 index = kvm_rcx_read(&svm->vcpu);
2207
2208         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2209                 return kvm_skip_emulated_instruction(&svm->vcpu);
2210         }
2211
2212         return 1;
2213 }
2214
2215 static int rdpru_interception(struct vcpu_svm *svm)
2216 {
2217         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2218         return 1;
2219 }
2220
2221 static int task_switch_interception(struct vcpu_svm *svm)
2222 {
2223         u16 tss_selector;
2224         int reason;
2225         int int_type = svm->vmcb->control.exit_int_info &
2226                 SVM_EXITINTINFO_TYPE_MASK;
2227         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2228         uint32_t type =
2229                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2230         uint32_t idt_v =
2231                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2232         bool has_error_code = false;
2233         u32 error_code = 0;
2234
2235         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2236
2237         if (svm->vmcb->control.exit_info_2 &
2238             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2239                 reason = TASK_SWITCH_IRET;
2240         else if (svm->vmcb->control.exit_info_2 &
2241                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2242                 reason = TASK_SWITCH_JMP;
2243         else if (idt_v)
2244                 reason = TASK_SWITCH_GATE;
2245         else
2246                 reason = TASK_SWITCH_CALL;
2247
2248         if (reason == TASK_SWITCH_GATE) {
2249                 switch (type) {
2250                 case SVM_EXITINTINFO_TYPE_NMI:
2251                         svm->vcpu.arch.nmi_injected = false;
2252                         break;
2253                 case SVM_EXITINTINFO_TYPE_EXEPT:
2254                         if (svm->vmcb->control.exit_info_2 &
2255                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2256                                 has_error_code = true;
2257                                 error_code =
2258                                         (u32)svm->vmcb->control.exit_info_2;
2259                         }
2260                         kvm_clear_exception_queue(&svm->vcpu);
2261                         break;
2262                 case SVM_EXITINTINFO_TYPE_INTR:
2263                         kvm_clear_interrupt_queue(&svm->vcpu);
2264                         break;
2265                 default:
2266                         break;
2267                 }
2268         }
2269
2270         if (reason != TASK_SWITCH_GATE ||
2271             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2272             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2273              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2274                 if (!skip_emulated_instruction(&svm->vcpu))
2275                         return 0;
2276         }
2277
2278         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2279                 int_vec = -1;
2280
2281         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2282                                has_error_code, error_code);
2283 }
2284
2285 static int cpuid_interception(struct vcpu_svm *svm)
2286 {
2287         return kvm_emulate_cpuid(&svm->vcpu);
2288 }
2289
2290 static int iret_interception(struct vcpu_svm *svm)
2291 {
2292         ++svm->vcpu.stat.nmi_window_exits;
2293         svm_clr_intercept(svm, INTERCEPT_IRET);
2294         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2295         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2296         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2297         return 1;
2298 }
2299
2300 static int invd_interception(struct vcpu_svm *svm)
2301 {
2302         /* Treat an INVD instruction as a NOP and just skip it. */
2303         return kvm_skip_emulated_instruction(&svm->vcpu);
2304 }
2305
2306 static int invlpg_interception(struct vcpu_svm *svm)
2307 {
2308         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2309                 return kvm_emulate_instruction(&svm->vcpu, 0);
2310
2311         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2312         return kvm_skip_emulated_instruction(&svm->vcpu);
2313 }
2314
2315 static int emulate_on_interception(struct vcpu_svm *svm)
2316 {
2317         return kvm_emulate_instruction(&svm->vcpu, 0);
2318 }
2319
2320 static int rsm_interception(struct vcpu_svm *svm)
2321 {
2322         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2323 }
2324
2325 static int rdpmc_interception(struct vcpu_svm *svm)
2326 {
2327         int err;
2328
2329         if (!nrips)
2330                 return emulate_on_interception(svm);
2331
2332         err = kvm_rdpmc(&svm->vcpu);
2333         return kvm_complete_insn_gp(&svm->vcpu, err);
2334 }
2335
2336 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2337                                             unsigned long val)
2338 {
2339         unsigned long cr0 = svm->vcpu.arch.cr0;
2340         bool ret = false;
2341
2342         if (!is_guest_mode(&svm->vcpu) ||
2343             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2344                 return false;
2345
2346         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2347         val &= ~SVM_CR0_SELECTIVE_MASK;
2348
2349         if (cr0 ^ val) {
2350                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2351                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2352         }
2353
2354         return ret;
2355 }
2356
2357 #define CR_VALID (1ULL << 63)
2358
2359 static int cr_interception(struct vcpu_svm *svm)
2360 {
2361         int reg, cr;
2362         unsigned long val;
2363         int err;
2364
2365         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2366                 return emulate_on_interception(svm);
2367
2368         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2369                 return emulate_on_interception(svm);
2370
2371         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2372         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2373                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2374         else
2375                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2376
2377         err = 0;
2378         if (cr >= 16) { /* mov to cr */
2379                 cr -= 16;
2380                 val = kvm_register_read(&svm->vcpu, reg);
2381                 trace_kvm_cr_write(cr, val);
2382                 switch (cr) {
2383                 case 0:
2384                         if (!check_selective_cr0_intercepted(svm, val))
2385                                 err = kvm_set_cr0(&svm->vcpu, val);
2386                         else
2387                                 return 1;
2388
2389                         break;
2390                 case 3:
2391                         err = kvm_set_cr3(&svm->vcpu, val);
2392                         break;
2393                 case 4:
2394                         err = kvm_set_cr4(&svm->vcpu, val);
2395                         break;
2396                 case 8:
2397                         err = kvm_set_cr8(&svm->vcpu, val);
2398                         break;
2399                 default:
2400                         WARN(1, "unhandled write to CR%d", cr);
2401                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2402                         return 1;
2403                 }
2404         } else { /* mov from cr */
2405                 switch (cr) {
2406                 case 0:
2407                         val = kvm_read_cr0(&svm->vcpu);
2408                         break;
2409                 case 2:
2410                         val = svm->vcpu.arch.cr2;
2411                         break;
2412                 case 3:
2413                         val = kvm_read_cr3(&svm->vcpu);
2414                         break;
2415                 case 4:
2416                         val = kvm_read_cr4(&svm->vcpu);
2417                         break;
2418                 case 8:
2419                         val = kvm_get_cr8(&svm->vcpu);
2420                         break;
2421                 default:
2422                         WARN(1, "unhandled read from CR%d", cr);
2423                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2424                         return 1;
2425                 }
2426                 kvm_register_write(&svm->vcpu, reg, val);
2427                 trace_kvm_cr_read(cr, val);
2428         }
2429         return kvm_complete_insn_gp(&svm->vcpu, err);
2430 }
2431
2432 static int dr_interception(struct vcpu_svm *svm)
2433 {
2434         int reg, dr;
2435         unsigned long val;
2436
2437         if (svm->vcpu.guest_debug == 0) {
2438                 /*
2439                  * No more DR vmexits; force a reload of the debug registers
2440                  * and reenter on this instruction.  The next vmexit will
2441                  * retrieve the full state of the debug registers.
2442                  */
2443                 clr_dr_intercepts(svm);
2444                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2445                 return 1;
2446         }
2447
2448         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2449                 return emulate_on_interception(svm);
2450
2451         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2452         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2453
2454         if (dr >= 16) { /* mov to DRn */
2455                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2456                         return 1;
2457                 val = kvm_register_read(&svm->vcpu, reg);
2458                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2459         } else {
2460                 if (!kvm_require_dr(&svm->vcpu, dr))
2461                         return 1;
2462                 kvm_get_dr(&svm->vcpu, dr, &val);
2463                 kvm_register_write(&svm->vcpu, reg, val);
2464         }
2465
2466         return kvm_skip_emulated_instruction(&svm->vcpu);
2467 }
2468
2469 static int cr8_write_interception(struct vcpu_svm *svm)
2470 {
2471         struct kvm_run *kvm_run = svm->vcpu.run;
2472         int r;
2473
2474         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2475         /* instruction emulation calls kvm_set_cr8() */
2476         r = cr_interception(svm);
2477         if (lapic_in_kernel(&svm->vcpu))
2478                 return r;
2479         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2480                 return r;
2481         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2482         return 0;
2483 }
2484
2485 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2486 {
2487         msr->data = 0;
2488
2489         switch (msr->index) {
2490         case MSR_F10H_DECFG:
2491                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2492                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2493                 break;
2494         case MSR_IA32_PERF_CAPABILITIES:
2495                 return 0;
2496         default:
2497                 return KVM_MSR_RET_INVALID;
2498         }
2499
2500         return 0;
2501 }
2502
2503 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2504 {
2505         struct vcpu_svm *svm = to_svm(vcpu);
2506
2507         switch (msr_info->index) {
2508         case MSR_STAR:
2509                 msr_info->data = svm->vmcb->save.star;
2510                 break;
2511 #ifdef CONFIG_X86_64
2512         case MSR_LSTAR:
2513                 msr_info->data = svm->vmcb->save.lstar;
2514                 break;
2515         case MSR_CSTAR:
2516                 msr_info->data = svm->vmcb->save.cstar;
2517                 break;
2518         case MSR_KERNEL_GS_BASE:
2519                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2520                 break;
2521         case MSR_SYSCALL_MASK:
2522                 msr_info->data = svm->vmcb->save.sfmask;
2523                 break;
2524 #endif
2525         case MSR_IA32_SYSENTER_CS:
2526                 msr_info->data = svm->vmcb->save.sysenter_cs;
2527                 break;
2528         case MSR_IA32_SYSENTER_EIP:
2529                 msr_info->data = svm->sysenter_eip;
2530                 break;
2531         case MSR_IA32_SYSENTER_ESP:
2532                 msr_info->data = svm->sysenter_esp;
2533                 break;
2534         case MSR_TSC_AUX:
2535                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2536                         return 1;
2537                 msr_info->data = svm->tsc_aux;
2538                 break;
2539         /*
2540          * Nobody will change the following 5 values in the VMCB so we can
2541          * safely return them on rdmsr. They will always be 0 until LBRV is
2542          * implemented.
2543          */
2544         case MSR_IA32_DEBUGCTLMSR:
2545                 msr_info->data = svm->vmcb->save.dbgctl;
2546                 break;
2547         case MSR_IA32_LASTBRANCHFROMIP:
2548                 msr_info->data = svm->vmcb->save.br_from;
2549                 break;
2550         case MSR_IA32_LASTBRANCHTOIP:
2551                 msr_info->data = svm->vmcb->save.br_to;
2552                 break;
2553         case MSR_IA32_LASTINTFROMIP:
2554                 msr_info->data = svm->vmcb->save.last_excp_from;
2555                 break;
2556         case MSR_IA32_LASTINTTOIP:
2557                 msr_info->data = svm->vmcb->save.last_excp_to;
2558                 break;
2559         case MSR_VM_HSAVE_PA:
2560                 msr_info->data = svm->nested.hsave_msr;
2561                 break;
2562         case MSR_VM_CR:
2563                 msr_info->data = svm->nested.vm_cr_msr;
2564                 break;
2565         case MSR_IA32_SPEC_CTRL:
2566                 if (!msr_info->host_initiated &&
2567                     !guest_has_spec_ctrl_msr(vcpu))
2568                         return 1;
2569
2570                 msr_info->data = svm->spec_ctrl;
2571                 break;
2572         case MSR_AMD64_VIRT_SPEC_CTRL:
2573                 if (!msr_info->host_initiated &&
2574                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2575                         return 1;
2576
2577                 msr_info->data = svm->virt_spec_ctrl;
2578                 break;
2579         case MSR_F15H_IC_CFG: {
2580
2581                 int family, model;
2582
2583                 family = guest_cpuid_family(vcpu);
2584                 model  = guest_cpuid_model(vcpu);
2585
2586                 if (family < 0 || model < 0)
2587                         return kvm_get_msr_common(vcpu, msr_info);
2588
2589                 msr_info->data = 0;
2590
2591                 if (family == 0x15 &&
2592                     (model >= 0x2 && model < 0x20))
2593                         msr_info->data = 0x1E;
2594                 }
2595                 break;
2596         case MSR_F10H_DECFG:
2597                 msr_info->data = svm->msr_decfg;
2598                 break;
2599         default:
2600                 return kvm_get_msr_common(vcpu, msr_info);
2601         }
2602         return 0;
2603 }
2604
2605 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2606 {
2607         struct vcpu_svm *svm = to_svm(vcpu);
2608         if (!sev_es_guest(svm->vcpu.kvm) || !err)
2609                 return kvm_complete_insn_gp(&svm->vcpu, err);
2610
2611         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2612         ghcb_set_sw_exit_info_2(svm->ghcb,
2613                                 X86_TRAP_GP |
2614                                 SVM_EVTINJ_TYPE_EXEPT |
2615                                 SVM_EVTINJ_VALID);
2616         return 1;
2617 }
2618
2619 static int rdmsr_interception(struct vcpu_svm *svm)
2620 {
2621         return kvm_emulate_rdmsr(&svm->vcpu);
2622 }
2623
2624 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2625 {
2626         struct vcpu_svm *svm = to_svm(vcpu);
2627         int svm_dis, chg_mask;
2628
2629         if (data & ~SVM_VM_CR_VALID_MASK)
2630                 return 1;
2631
2632         chg_mask = SVM_VM_CR_VALID_MASK;
2633
2634         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2635                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2636
2637         svm->nested.vm_cr_msr &= ~chg_mask;
2638         svm->nested.vm_cr_msr |= (data & chg_mask);
2639
2640         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2641
2642         /* check for svm_disable while efer.svme is set */
2643         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2644                 return 1;
2645
2646         return 0;
2647 }
2648
2649 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2650 {
2651         struct vcpu_svm *svm = to_svm(vcpu);
2652
2653         u32 ecx = msr->index;
2654         u64 data = msr->data;
2655         switch (ecx) {
2656         case MSR_IA32_CR_PAT:
2657                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2658                         return 1;
2659                 vcpu->arch.pat = data;
2660                 svm->vmcb->save.g_pat = data;
2661                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2662                 break;
2663         case MSR_IA32_SPEC_CTRL:
2664                 if (!msr->host_initiated &&
2665                     !guest_has_spec_ctrl_msr(vcpu))
2666                         return 1;
2667
2668                 if (kvm_spec_ctrl_test_value(data))
2669                         return 1;
2670
2671                 svm->spec_ctrl = data;
2672                 if (!data)
2673                         break;
2674
2675                 /*
2676                  * For non-nested:
2677                  * When it's written (to non-zero) for the first time, pass
2678                  * it through.
2679                  *
2680                  * For nested:
2681                  * The handling of the MSR bitmap for L2 guests is done in
2682                  * nested_svm_vmrun_msrpm.
2683                  * We update the L1 MSR bit as well since it will end up
2684                  * touching the MSR anyway now.
2685                  */
2686                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2687                 break;
2688         case MSR_IA32_PRED_CMD:
2689                 if (!msr->host_initiated &&
2690                     !guest_has_pred_cmd_msr(vcpu))
2691                         return 1;
2692
2693                 if (data & ~PRED_CMD_IBPB)
2694                         return 1;
2695                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2696                         return 1;
2697                 if (!data)
2698                         break;
2699
2700                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2701                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2702                 break;
2703         case MSR_AMD64_VIRT_SPEC_CTRL:
2704                 if (!msr->host_initiated &&
2705                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2706                         return 1;
2707
2708                 if (data & ~SPEC_CTRL_SSBD)
2709                         return 1;
2710
2711                 svm->virt_spec_ctrl = data;
2712                 break;
2713         case MSR_STAR:
2714                 svm->vmcb->save.star = data;
2715                 break;
2716 #ifdef CONFIG_X86_64
2717         case MSR_LSTAR:
2718                 svm->vmcb->save.lstar = data;
2719                 break;
2720         case MSR_CSTAR:
2721                 svm->vmcb->save.cstar = data;
2722                 break;
2723         case MSR_KERNEL_GS_BASE:
2724                 svm->vmcb->save.kernel_gs_base = data;
2725                 break;
2726         case MSR_SYSCALL_MASK:
2727                 svm->vmcb->save.sfmask = data;
2728                 break;
2729 #endif
2730         case MSR_IA32_SYSENTER_CS:
2731                 svm->vmcb->save.sysenter_cs = data;
2732                 break;
2733         case MSR_IA32_SYSENTER_EIP:
2734                 svm->sysenter_eip = data;
2735                 svm->vmcb->save.sysenter_eip = data;
2736                 break;
2737         case MSR_IA32_SYSENTER_ESP:
2738                 svm->sysenter_esp = data;
2739                 svm->vmcb->save.sysenter_esp = data;
2740                 break;
2741         case MSR_TSC_AUX:
2742                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2743                         return 1;
2744
2745                 /*
2746                  * This is rare, so we update the MSR here instead of using
2747                  * direct_access_msrs.  Doing that would require a rdmsr in
2748                  * svm_vcpu_put.
2749                  */
2750                 svm->tsc_aux = data;
2751                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2752                 break;
2753         case MSR_IA32_DEBUGCTLMSR:
2754                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2755                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2756                                     __func__, data);
2757                         break;
2758                 }
2759                 if (data & DEBUGCTL_RESERVED_BITS)
2760                         return 1;
2761
2762                 svm->vmcb->save.dbgctl = data;
2763                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2764                 if (data & (1ULL<<0))
2765                         svm_enable_lbrv(vcpu);
2766                 else
2767                         svm_disable_lbrv(vcpu);
2768                 break;
2769         case MSR_VM_HSAVE_PA:
2770                 svm->nested.hsave_msr = data;
2771                 break;
2772         case MSR_VM_CR:
2773                 return svm_set_vm_cr(vcpu, data);
2774         case MSR_VM_IGNNE:
2775                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2776                 break;
2777         case MSR_F10H_DECFG: {
2778                 struct kvm_msr_entry msr_entry;
2779
2780                 msr_entry.index = msr->index;
2781                 if (svm_get_msr_feature(&msr_entry))
2782                         return 1;
2783
2784                 /* Check the supported bits */
2785                 if (data & ~msr_entry.data)
2786                         return 1;
2787
2788                 /* Don't allow the guest to change a bit, #GP */
2789                 if (!msr->host_initiated && (data ^ msr_entry.data))
2790                         return 1;
2791
2792                 svm->msr_decfg = data;
2793                 break;
2794         }
2795         case MSR_IA32_APICBASE:
2796                 if (kvm_vcpu_apicv_active(vcpu))
2797                         avic_update_vapic_bar(to_svm(vcpu), data);
2798                 fallthrough;
2799         default:
2800                 return kvm_set_msr_common(vcpu, msr);
2801         }
2802         return 0;
2803 }
2804
2805 static int wrmsr_interception(struct vcpu_svm *svm)
2806 {
2807         return kvm_emulate_wrmsr(&svm->vcpu);
2808 }
2809
2810 static int msr_interception(struct vcpu_svm *svm)
2811 {
2812         if (svm->vmcb->control.exit_info_1)
2813                 return wrmsr_interception(svm);
2814         else
2815                 return rdmsr_interception(svm);
2816 }
2817
2818 static int interrupt_window_interception(struct vcpu_svm *svm)
2819 {
2820         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2821         svm_clear_vintr(svm);
2822
2823         /*
2824          * For AVIC, the only reason to end up here is ExtINTs.
2825          * In this case AVIC was temporarily disabled for
2826          * requesting the IRQ window and we have to re-enable it.
2827          */
2828         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2829
2830         ++svm->vcpu.stat.irq_window_exits;
2831         return 1;
2832 }
2833
2834 static int pause_interception(struct vcpu_svm *svm)
2835 {
2836         struct kvm_vcpu *vcpu = &svm->vcpu;
2837         bool in_kernel;
2838
2839         /*
2840          * CPL is not made available for an SEV-ES guest, therefore
2841          * vcpu->arch.preempted_in_kernel can never be true.  Just
2842          * set in_kernel to false as well.
2843          */
2844         in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
2845
2846         if (!kvm_pause_in_guest(vcpu->kvm))
2847                 grow_ple_window(vcpu);
2848
2849         kvm_vcpu_on_spin(vcpu, in_kernel);
2850         return 1;
2851 }
2852
2853 static int nop_interception(struct vcpu_svm *svm)
2854 {
2855         return kvm_skip_emulated_instruction(&(svm->vcpu));
2856 }
2857
2858 static int monitor_interception(struct vcpu_svm *svm)
2859 {
2860         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2861         return nop_interception(svm);
2862 }
2863
2864 static int mwait_interception(struct vcpu_svm *svm)
2865 {
2866         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2867         return nop_interception(svm);
2868 }
2869
2870 static int invpcid_interception(struct vcpu_svm *svm)
2871 {
2872         struct kvm_vcpu *vcpu = &svm->vcpu;
2873         unsigned long type;
2874         gva_t gva;
2875
2876         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2877                 kvm_queue_exception(vcpu, UD_VECTOR);
2878                 return 1;
2879         }
2880
2881         /*
2882          * For an INVPCID intercept:
2883          * EXITINFO1 provides the linear address of the memory operand.
2884          * EXITINFO2 provides the contents of the register operand.
2885          */
2886         type = svm->vmcb->control.exit_info_2;
2887         gva = svm->vmcb->control.exit_info_1;
2888
2889         if (type > 3) {
2890                 kvm_inject_gp(vcpu, 0);
2891                 return 1;
2892         }
2893
2894         return kvm_handle_invpcid(vcpu, type, gva);
2895 }
2896
2897 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2898         [SVM_EXIT_READ_CR0]                     = cr_interception,
2899         [SVM_EXIT_READ_CR3]                     = cr_interception,
2900         [SVM_EXIT_READ_CR4]                     = cr_interception,
2901         [SVM_EXIT_READ_CR8]                     = cr_interception,
2902         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2903         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2904         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2905         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2906         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2907         [SVM_EXIT_READ_DR0]                     = dr_interception,
2908         [SVM_EXIT_READ_DR1]                     = dr_interception,
2909         [SVM_EXIT_READ_DR2]                     = dr_interception,
2910         [SVM_EXIT_READ_DR3]                     = dr_interception,
2911         [SVM_EXIT_READ_DR4]                     = dr_interception,
2912         [SVM_EXIT_READ_DR5]                     = dr_interception,
2913         [SVM_EXIT_READ_DR6]                     = dr_interception,
2914         [SVM_EXIT_READ_DR7]                     = dr_interception,
2915         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2916         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2917         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2918         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2919         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2920         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2921         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2922         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2923         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2924         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2925         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2926         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2927         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2928         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2929         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2930         [SVM_EXIT_INTR]                         = intr_interception,
2931         [SVM_EXIT_NMI]                          = nmi_interception,
2932         [SVM_EXIT_SMI]                          = nop_on_interception,
2933         [SVM_EXIT_INIT]                         = nop_on_interception,
2934         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2935         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
2936         [SVM_EXIT_CPUID]                        = cpuid_interception,
2937         [SVM_EXIT_IRET]                         = iret_interception,
2938         [SVM_EXIT_INVD]                         = invd_interception,
2939         [SVM_EXIT_PAUSE]                        = pause_interception,
2940         [SVM_EXIT_HLT]                          = halt_interception,
2941         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2942         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2943         [SVM_EXIT_IOIO]                         = io_interception,
2944         [SVM_EXIT_MSR]                          = msr_interception,
2945         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2946         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2947         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2948         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2949         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2950         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2951         [SVM_EXIT_STGI]                         = stgi_interception,
2952         [SVM_EXIT_CLGI]                         = clgi_interception,
2953         [SVM_EXIT_SKINIT]                       = skinit_interception,
2954         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
2955         [SVM_EXIT_MONITOR]                      = monitor_interception,
2956         [SVM_EXIT_MWAIT]                        = mwait_interception,
2957         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2958         [SVM_EXIT_RDPRU]                        = rdpru_interception,
2959         [SVM_EXIT_INVPCID]                      = invpcid_interception,
2960         [SVM_EXIT_NPF]                          = npf_interception,
2961         [SVM_EXIT_RSM]                          = rsm_interception,
2962         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
2963         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
2964 };
2965
2966 static void dump_vmcb(struct kvm_vcpu *vcpu)
2967 {
2968         struct vcpu_svm *svm = to_svm(vcpu);
2969         struct vmcb_control_area *control = &svm->vmcb->control;
2970         struct vmcb_save_area *save = &svm->vmcb->save;
2971
2972         if (!dump_invalid_vmcb) {
2973                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2974                 return;
2975         }
2976
2977         pr_err("VMCB Control Area:\n");
2978         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2979         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
2980         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2981         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
2982         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
2983         pr_err("%-20s%08x %08x\n", "intercepts:",
2984               control->intercepts[INTERCEPT_WORD3],
2985                control->intercepts[INTERCEPT_WORD4]);
2986         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2987         pr_err("%-20s%d\n", "pause filter threshold:",
2988                control->pause_filter_thresh);
2989         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2990         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2991         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2992         pr_err("%-20s%d\n", "asid:", control->asid);
2993         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2994         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2995         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2996         pr_err("%-20s%08x\n", "int_state:", control->int_state);
2997         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2998         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2999         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3000         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3001         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3002         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3003         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3004         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3005         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3006         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3007         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3008         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3009         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3010         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3011         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3012         pr_err("VMCB State Save Area:\n");
3013         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3014                "es:",
3015                save->es.selector, save->es.attrib,
3016                save->es.limit, save->es.base);
3017         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3018                "cs:",
3019                save->cs.selector, save->cs.attrib,
3020                save->cs.limit, save->cs.base);
3021         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3022                "ss:",
3023                save->ss.selector, save->ss.attrib,
3024                save->ss.limit, save->ss.base);
3025         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3026                "ds:",
3027                save->ds.selector, save->ds.attrib,
3028                save->ds.limit, save->ds.base);
3029         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3030                "fs:",
3031                save->fs.selector, save->fs.attrib,
3032                save->fs.limit, save->fs.base);
3033         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3034                "gs:",
3035                save->gs.selector, save->gs.attrib,
3036                save->gs.limit, save->gs.base);
3037         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3038                "gdtr:",
3039                save->gdtr.selector, save->gdtr.attrib,
3040                save->gdtr.limit, save->gdtr.base);
3041         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3042                "ldtr:",
3043                save->ldtr.selector, save->ldtr.attrib,
3044                save->ldtr.limit, save->ldtr.base);
3045         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3046                "idtr:",
3047                save->idtr.selector, save->idtr.attrib,
3048                save->idtr.limit, save->idtr.base);
3049         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3050                "tr:",
3051                save->tr.selector, save->tr.attrib,
3052                save->tr.limit, save->tr.base);
3053         pr_err("cpl:            %d                efer:         %016llx\n",
3054                 save->cpl, save->efer);
3055         pr_err("%-15s %016llx %-13s %016llx\n",
3056                "cr0:", save->cr0, "cr2:", save->cr2);
3057         pr_err("%-15s %016llx %-13s %016llx\n",
3058                "cr3:", save->cr3, "cr4:", save->cr4);
3059         pr_err("%-15s %016llx %-13s %016llx\n",
3060                "dr6:", save->dr6, "dr7:", save->dr7);
3061         pr_err("%-15s %016llx %-13s %016llx\n",
3062                "rip:", save->rip, "rflags:", save->rflags);
3063         pr_err("%-15s %016llx %-13s %016llx\n",
3064                "rsp:", save->rsp, "rax:", save->rax);
3065         pr_err("%-15s %016llx %-13s %016llx\n",
3066                "star:", save->star, "lstar:", save->lstar);
3067         pr_err("%-15s %016llx %-13s %016llx\n",
3068                "cstar:", save->cstar, "sfmask:", save->sfmask);
3069         pr_err("%-15s %016llx %-13s %016llx\n",
3070                "kernel_gs_base:", save->kernel_gs_base,
3071                "sysenter_cs:", save->sysenter_cs);
3072         pr_err("%-15s %016llx %-13s %016llx\n",
3073                "sysenter_esp:", save->sysenter_esp,
3074                "sysenter_eip:", save->sysenter_eip);
3075         pr_err("%-15s %016llx %-13s %016llx\n",
3076                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3077         pr_err("%-15s %016llx %-13s %016llx\n",
3078                "br_from:", save->br_from, "br_to:", save->br_to);
3079         pr_err("%-15s %016llx %-13s %016llx\n",
3080                "excp_from:", save->last_excp_from,
3081                "excp_to:", save->last_excp_to);
3082 }
3083
3084 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3085                               u32 *intr_info, u32 *error_code)
3086 {
3087         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3088
3089         *info1 = control->exit_info_1;
3090         *info2 = control->exit_info_2;
3091         *intr_info = control->exit_int_info;
3092         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3093             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3094                 *error_code = control->exit_int_info_err;
3095         else
3096                 *error_code = 0;
3097 }
3098
3099 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3100 {
3101         struct vcpu_svm *svm = to_svm(vcpu);
3102         struct kvm_run *kvm_run = vcpu->run;
3103         u32 exit_code = svm->vmcb->control.exit_code;
3104
3105         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3106
3107         /* SEV-ES guests must use the CR write traps to track CR registers. */
3108         if (!sev_es_guest(vcpu->kvm)) {
3109                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3110                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3111                 if (npt_enabled)
3112                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3113         }
3114
3115         if (is_guest_mode(vcpu)) {
3116                 int vmexit;
3117
3118                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3119
3120                 vmexit = nested_svm_exit_special(svm);
3121
3122                 if (vmexit == NESTED_EXIT_CONTINUE)
3123                         vmexit = nested_svm_exit_handled(svm);
3124
3125                 if (vmexit == NESTED_EXIT_DONE)
3126                         return 1;
3127         }
3128
3129         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3130                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3131                 kvm_run->fail_entry.hardware_entry_failure_reason
3132                         = svm->vmcb->control.exit_code;
3133                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3134                 dump_vmcb(vcpu);
3135                 return 0;
3136         }
3137
3138         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3139             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3140             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3141             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3142                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3143                        "exit_code 0x%x\n",
3144                        __func__, svm->vmcb->control.exit_int_info,
3145                        exit_code);
3146
3147         if (exit_fastpath != EXIT_FASTPATH_NONE)
3148                 return 1;
3149
3150         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3151             || !svm_exit_handlers[exit_code]) {
3152                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
3153                 dump_vmcb(vcpu);
3154                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3155                 vcpu->run->internal.suberror =
3156                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3157                 vcpu->run->internal.ndata = 2;
3158                 vcpu->run->internal.data[0] = exit_code;
3159                 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3160                 return 0;
3161         }
3162
3163 #ifdef CONFIG_RETPOLINE
3164         if (exit_code == SVM_EXIT_MSR)
3165                 return msr_interception(svm);
3166         else if (exit_code == SVM_EXIT_VINTR)
3167                 return interrupt_window_interception(svm);
3168         else if (exit_code == SVM_EXIT_INTR)
3169                 return intr_interception(svm);
3170         else if (exit_code == SVM_EXIT_HLT)
3171                 return halt_interception(svm);
3172         else if (exit_code == SVM_EXIT_NPF)
3173                 return npf_interception(svm);
3174 #endif
3175         return svm_exit_handlers[exit_code](svm);
3176 }
3177
3178 static void reload_tss(struct kvm_vcpu *vcpu)
3179 {
3180         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3181
3182         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3183         load_TR_desc();
3184 }
3185
3186 static void pre_svm_run(struct vcpu_svm *svm)
3187 {
3188         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3189
3190         if (sev_guest(svm->vcpu.kvm))
3191                 return pre_sev_run(svm, svm->vcpu.cpu);
3192
3193         /* FIXME: handle wraparound of asid_generation */
3194         if (svm->asid_generation != sd->asid_generation)
3195                 new_asid(svm, sd);
3196 }
3197
3198 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3199 {
3200         struct vcpu_svm *svm = to_svm(vcpu);
3201
3202         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3203         vcpu->arch.hflags |= HF_NMI_MASK;
3204         svm_set_intercept(svm, INTERCEPT_IRET);
3205         ++vcpu->stat.nmi_injections;
3206 }
3207
3208 static void svm_set_irq(struct kvm_vcpu *vcpu)
3209 {
3210         struct vcpu_svm *svm = to_svm(vcpu);
3211
3212         BUG_ON(!(gif_set(svm)));
3213
3214         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3215         ++vcpu->stat.irq_injections;
3216
3217         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3218                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3219 }
3220
3221 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3222 {
3223         struct vcpu_svm *svm = to_svm(vcpu);
3224
3225         /*
3226          * SEV-ES guests must always keep the CR intercepts cleared. CR
3227          * tracking is done using the CR write traps.
3228          */
3229         if (sev_es_guest(vcpu->kvm))
3230                 return;
3231
3232         if (nested_svm_virtualize_tpr(vcpu))
3233                 return;
3234
3235         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3236
3237         if (irr == -1)
3238                 return;
3239
3240         if (tpr >= irr)
3241                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3242 }
3243
3244 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3245 {
3246         struct vcpu_svm *svm = to_svm(vcpu);
3247         struct vmcb *vmcb = svm->vmcb;
3248         bool ret;
3249
3250         if (!gif_set(svm))
3251                 return true;
3252
3253         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3254                 return false;
3255
3256         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3257               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3258
3259         return ret;
3260 }
3261
3262 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3263 {
3264         struct vcpu_svm *svm = to_svm(vcpu);
3265         if (svm->nested.nested_run_pending)
3266                 return -EBUSY;
3267
3268         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3269         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3270                 return -EBUSY;
3271
3272         return !svm_nmi_blocked(vcpu);
3273 }
3274
3275 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3276 {
3277         struct vcpu_svm *svm = to_svm(vcpu);
3278
3279         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3280 }
3281
3282 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3283 {
3284         struct vcpu_svm *svm = to_svm(vcpu);
3285
3286         if (masked) {
3287                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3288                 svm_set_intercept(svm, INTERCEPT_IRET);
3289         } else {
3290                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3291                 svm_clr_intercept(svm, INTERCEPT_IRET);
3292         }
3293 }
3294
3295 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3296 {
3297         struct vcpu_svm *svm = to_svm(vcpu);
3298         struct vmcb *vmcb = svm->vmcb;
3299
3300         if (!gif_set(svm))
3301                 return true;
3302
3303         if (sev_es_guest(svm->vcpu.kvm)) {
3304                 /*
3305                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3306                  * bit to determine the state of the IF flag.
3307                  */
3308                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3309                         return true;
3310         } else if (is_guest_mode(vcpu)) {
3311                 /* As long as interrupts are being delivered...  */
3312                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3313                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3314                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3315                         return true;
3316
3317                 /* ... vmexits aren't blocked by the interrupt shadow  */
3318                 if (nested_exit_on_intr(svm))
3319                         return false;
3320         } else {
3321                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3322                         return true;
3323         }
3324
3325         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3326 }
3327
3328 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3329 {
3330         struct vcpu_svm *svm = to_svm(vcpu);
3331         if (svm->nested.nested_run_pending)
3332                 return -EBUSY;
3333
3334         /*
3335          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3336          * e.g. if the IRQ arrived asynchronously after checking nested events.
3337          */
3338         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3339                 return -EBUSY;
3340
3341         return !svm_interrupt_blocked(vcpu);
3342 }
3343
3344 static void enable_irq_window(struct kvm_vcpu *vcpu)
3345 {
3346         struct vcpu_svm *svm = to_svm(vcpu);
3347
3348         /*
3349          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3350          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3351          * get that intercept, this function will be called again though and
3352          * we'll get the vintr intercept. However, if the vGIF feature is
3353          * enabled, the STGI interception will not occur. Enable the irq
3354          * window under the assumption that the hardware will set the GIF.
3355          */
3356         if (vgif_enabled(svm) || gif_set(svm)) {
3357                 /*
3358                  * IRQ window is not needed when AVIC is enabled,
3359                  * unless we have pending ExtINT since it cannot be injected
3360                  * via AVIC. In such case, we need to temporarily disable AVIC,
3361                  * and fallback to injecting IRQ via V_IRQ.
3362                  */
3363                 svm_toggle_avic_for_irq_window(vcpu, false);
3364                 svm_set_vintr(svm);
3365         }
3366 }
3367
3368 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3369 {
3370         struct vcpu_svm *svm = to_svm(vcpu);
3371
3372         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3373             == HF_NMI_MASK)
3374                 return; /* IRET will cause a vm exit */
3375
3376         if (!gif_set(svm)) {
3377                 if (vgif_enabled(svm))
3378                         svm_set_intercept(svm, INTERCEPT_STGI);
3379                 return; /* STGI will cause a vm exit */
3380         }
3381
3382         /*
3383          * Something prevents NMI from been injected. Single step over possible
3384          * problem (IRET or exception injection or interrupt shadow)
3385          */
3386         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3387         svm->nmi_singlestep = true;
3388         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3389 }
3390
3391 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3392 {
3393         return 0;
3394 }
3395
3396 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3397 {
3398         return 0;
3399 }
3400
3401 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3402 {
3403         struct vcpu_svm *svm = to_svm(vcpu);
3404
3405         /*
3406          * Flush only the current ASID even if the TLB flush was invoked via
3407          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3408          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3409          * unconditionally does a TLB flush on both nested VM-Enter and nested
3410          * VM-Exit (via kvm_mmu_reset_context()).
3411          */
3412         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3413                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3414         else
3415                 svm->asid_generation--;
3416 }
3417
3418 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3419 {
3420         struct vcpu_svm *svm = to_svm(vcpu);
3421
3422         invlpga(gva, svm->vmcb->control.asid);
3423 }
3424
3425 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3426 {
3427 }
3428
3429 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3430 {
3431         struct vcpu_svm *svm = to_svm(vcpu);
3432
3433         if (nested_svm_virtualize_tpr(vcpu))
3434                 return;
3435
3436         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3437                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3438                 kvm_set_cr8(vcpu, cr8);
3439         }
3440 }
3441
3442 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3443 {
3444         struct vcpu_svm *svm = to_svm(vcpu);
3445         u64 cr8;
3446
3447         if (nested_svm_virtualize_tpr(vcpu) ||
3448             kvm_vcpu_apicv_active(vcpu))
3449                 return;
3450
3451         cr8 = kvm_get_cr8(vcpu);
3452         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3453         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3454 }
3455
3456 static void svm_complete_interrupts(struct vcpu_svm *svm)
3457 {
3458         u8 vector;
3459         int type;
3460         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3461         unsigned int3_injected = svm->int3_injected;
3462
3463         svm->int3_injected = 0;
3464
3465         /*
3466          * If we've made progress since setting HF_IRET_MASK, we've
3467          * executed an IRET and can allow NMI injection.
3468          */
3469         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3470             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3471                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3472                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3473         }
3474
3475         svm->vcpu.arch.nmi_injected = false;
3476         kvm_clear_exception_queue(&svm->vcpu);
3477         kvm_clear_interrupt_queue(&svm->vcpu);
3478
3479         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3480                 return;
3481
3482         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3483
3484         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3485         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3486
3487         switch (type) {
3488         case SVM_EXITINTINFO_TYPE_NMI:
3489                 svm->vcpu.arch.nmi_injected = true;
3490                 break;
3491         case SVM_EXITINTINFO_TYPE_EXEPT:
3492                 /*
3493                  * Never re-inject a #VC exception.
3494                  */
3495                 if (vector == X86_TRAP_VC)
3496                         break;
3497
3498                 /*
3499                  * In case of software exceptions, do not reinject the vector,
3500                  * but re-execute the instruction instead. Rewind RIP first
3501                  * if we emulated INT3 before.
3502                  */
3503                 if (kvm_exception_is_soft(vector)) {
3504                         if (vector == BP_VECTOR && int3_injected &&
3505                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3506                                 kvm_rip_write(&svm->vcpu,
3507                                               kvm_rip_read(&svm->vcpu) -
3508                                               int3_injected);
3509                         break;
3510                 }
3511                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3512                         u32 err = svm->vmcb->control.exit_int_info_err;
3513                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3514
3515                 } else
3516                         kvm_requeue_exception(&svm->vcpu, vector);
3517                 break;
3518         case SVM_EXITINTINFO_TYPE_INTR:
3519                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3520                 break;
3521         default:
3522                 break;
3523         }
3524 }
3525
3526 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3527 {
3528         struct vcpu_svm *svm = to_svm(vcpu);
3529         struct vmcb_control_area *control = &svm->vmcb->control;
3530
3531         control->exit_int_info = control->event_inj;
3532         control->exit_int_info_err = control->event_inj_err;
3533         control->event_inj = 0;
3534         svm_complete_interrupts(svm);
3535 }
3536
3537 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3538 {
3539         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3540             to_svm(vcpu)->vmcb->control.exit_info_1)
3541                 return handle_fastpath_set_msr_irqoff(vcpu);
3542
3543         return EXIT_FASTPATH_NONE;
3544 }
3545
3546 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3547
3548 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3549                                         struct vcpu_svm *svm)
3550 {
3551         /*
3552          * VMENTER enables interrupts (host state), but the kernel state is
3553          * interrupts disabled when this is invoked. Also tell RCU about
3554          * it. This is the same logic as for exit_to_user_mode().
3555          *
3556          * This ensures that e.g. latency analysis on the host observes
3557          * guest mode as interrupt enabled.
3558          *
3559          * guest_enter_irqoff() informs context tracking about the
3560          * transition to guest mode and if enabled adjusts RCU state
3561          * accordingly.
3562          */
3563         instrumentation_begin();
3564         trace_hardirqs_on_prepare();
3565         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3566         instrumentation_end();
3567
3568         guest_enter_irqoff();
3569         lockdep_hardirqs_on(CALLER_ADDR0);
3570
3571         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3572
3573 #ifdef CONFIG_X86_64
3574         native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3575 #else
3576         loadsegment(fs, svm->host.fs);
3577 #ifndef CONFIG_X86_32_LAZY_GS
3578         loadsegment(gs, svm->host.gs);
3579 #endif
3580 #endif
3581
3582         /*
3583          * VMEXIT disables interrupts (host state), but tracing and lockdep
3584          * have them in state 'on' as recorded before entering guest mode.
3585          * Same as enter_from_user_mode().
3586          *
3587          * guest_exit_irqoff() restores host context and reinstates RCU if
3588          * enabled and required.
3589          *
3590          * This needs to be done before the below as native_read_msr()
3591          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3592          * into world and some more.
3593          */
3594         lockdep_hardirqs_off(CALLER_ADDR0);
3595         guest_exit_irqoff();
3596
3597         instrumentation_begin();
3598         trace_hardirqs_off_finish();
3599         instrumentation_end();
3600 }
3601
3602 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3603 {
3604         struct vcpu_svm *svm = to_svm(vcpu);
3605
3606         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3607         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3608         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3609
3610         /*
3611          * Disable singlestep if we're injecting an interrupt/exception.
3612          * We don't want our modified rflags to be pushed on the stack where
3613          * we might not be able to easily reset them if we disabled NMI
3614          * singlestep later.
3615          */
3616         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3617                 /*
3618                  * Event injection happens before external interrupts cause a
3619                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3620                  * is enough to force an immediate vmexit.
3621                  */
3622                 disable_nmi_singlestep(svm);
3623                 smp_send_reschedule(vcpu->cpu);
3624         }
3625
3626         pre_svm_run(svm);
3627
3628         sync_lapic_to_cr8(vcpu);
3629
3630         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3631                 svm->vmcb->control.asid = svm->asid;
3632                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3633         }
3634         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3635
3636         /*
3637          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3638          * of a #DB.
3639          */
3640         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3641                 svm_set_dr6(svm, vcpu->arch.dr6);
3642         else
3643                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3644
3645         clgi();
3646         kvm_load_guest_xsave_state(vcpu);
3647
3648         kvm_wait_lapic_expire(vcpu);
3649
3650         /*
3651          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3652          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3653          * is no need to worry about the conditional branch over the wrmsr
3654          * being speculatively taken.
3655          */
3656         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3657
3658         svm_vcpu_enter_exit(vcpu, svm);
3659
3660         /*
3661          * We do not use IBRS in the kernel. If this vCPU has used the
3662          * SPEC_CTRL MSR it may have left it on; save the value and
3663          * turn it off. This is much more efficient than blindly adding
3664          * it to the atomic save/restore list. Especially as the former
3665          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3666          *
3667          * For non-nested case:
3668          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3669          * save it.
3670          *
3671          * For nested case:
3672          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3673          * save it.
3674          */
3675         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3676                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3677
3678         reload_tss(vcpu);
3679
3680         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3681
3682         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3683         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3684         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3685         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3686
3687         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3688                 kvm_before_interrupt(&svm->vcpu);
3689
3690         kvm_load_host_xsave_state(vcpu);
3691         stgi();
3692
3693         /* Any pending NMI will happen here */
3694
3695         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3696                 kvm_after_interrupt(&svm->vcpu);
3697
3698         sync_cr8_to_lapic(vcpu);
3699
3700         svm->next_rip = 0;
3701         if (is_guest_mode(&svm->vcpu)) {
3702                 sync_nested_vmcb_control(svm);
3703                 svm->nested.nested_run_pending = 0;
3704         }
3705
3706         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3707         vmcb_mark_all_clean(svm->vmcb);
3708
3709         /* if exit due to PF check for async PF */
3710         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3711                 svm->vcpu.arch.apf.host_apf_flags =
3712                         kvm_read_and_reset_apf_flags();
3713
3714         if (npt_enabled) {
3715                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3716                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3717         }
3718
3719         /*
3720          * We need to handle MC intercepts here before the vcpu has a chance to
3721          * change the physical cpu
3722          */
3723         if (unlikely(svm->vmcb->control.exit_code ==
3724                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3725                 svm_handle_mce(svm);
3726
3727         svm_complete_interrupts(svm);
3728
3729         if (is_guest_mode(vcpu))
3730                 return EXIT_FASTPATH_NONE;
3731
3732         return svm_exit_handlers_fastpath(vcpu);
3733 }
3734
3735 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3736                              int root_level)
3737 {
3738         struct vcpu_svm *svm = to_svm(vcpu);
3739         unsigned long cr3;
3740
3741         cr3 = __sme_set(root);
3742         if (npt_enabled) {
3743                 svm->vmcb->control.nested_cr3 = cr3;
3744                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3745
3746                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3747                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3748                         return;
3749                 cr3 = vcpu->arch.cr3;
3750         }
3751
3752         svm->vmcb->save.cr3 = cr3;
3753         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3754 }
3755
3756 static int is_disabled(void)
3757 {
3758         u64 vm_cr;
3759
3760         rdmsrl(MSR_VM_CR, vm_cr);
3761         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3762                 return 1;
3763
3764         return 0;
3765 }
3766
3767 static void
3768 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3769 {
3770         /*
3771          * Patch in the VMMCALL instruction:
3772          */
3773         hypercall[0] = 0x0f;
3774         hypercall[1] = 0x01;
3775         hypercall[2] = 0xd9;
3776 }
3777
3778 static int __init svm_check_processor_compat(void)
3779 {
3780         return 0;
3781 }
3782
3783 static bool svm_cpu_has_accelerated_tpr(void)
3784 {
3785         return false;
3786 }
3787
3788 static bool svm_has_emulated_msr(u32 index)
3789 {
3790         switch (index) {
3791         case MSR_IA32_MCG_EXT_CTL:
3792         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3793                 return false;
3794         default:
3795                 break;
3796         }
3797
3798         return true;
3799 }
3800
3801 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3802 {
3803         return 0;
3804 }
3805
3806 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3807 {
3808         struct vcpu_svm *svm = to_svm(vcpu);
3809         struct kvm_cpuid_entry2 *best;
3810
3811         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3812                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3813                                     boot_cpu_has(X86_FEATURE_XSAVES);
3814
3815         /* Update nrips enabled cache */
3816         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3817                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3818
3819         /* Check again if INVPCID interception if required */
3820         svm_check_invpcid(svm);
3821
3822         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
3823         if (sev_guest(vcpu->kvm)) {
3824                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3825                 if (best)
3826                         vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3827         }
3828
3829         if (!kvm_vcpu_apicv_active(vcpu))
3830                 return;
3831
3832         /*
3833          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3834          * is exposed to the guest, disable AVIC.
3835          */
3836         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3837                 kvm_request_apicv_update(vcpu->kvm, false,
3838                                          APICV_INHIBIT_REASON_X2APIC);
3839
3840         /*
3841          * Currently, AVIC does not work with nested virtualization.
3842          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3843          */
3844         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3845                 kvm_request_apicv_update(vcpu->kvm, false,
3846                                          APICV_INHIBIT_REASON_NESTED);
3847 }
3848
3849 static bool svm_has_wbinvd_exit(void)
3850 {
3851         return true;
3852 }
3853
3854 #define PRE_EX(exit)  { .exit_code = (exit), \
3855                         .stage = X86_ICPT_PRE_EXCEPT, }
3856 #define POST_EX(exit) { .exit_code = (exit), \
3857                         .stage = X86_ICPT_POST_EXCEPT, }
3858 #define POST_MEM(exit) { .exit_code = (exit), \
3859                         .stage = X86_ICPT_POST_MEMACCESS, }
3860
3861 static const struct __x86_intercept {
3862         u32 exit_code;
3863         enum x86_intercept_stage stage;
3864 } x86_intercept_map[] = {
3865         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3866         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3867         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3868         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3869         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3870         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3871         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3872         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3873         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3874         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3875         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3876         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3877         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3878         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3879         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3880         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3881         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3882         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3883         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3884         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3885         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3886         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3887         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3888         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3889         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3890         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3891         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3892         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3893         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3894         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3895         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3896         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3897         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3898         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3899         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3900         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3901         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3902         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3903         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3904         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
3905         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
3906         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
3907         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
3908         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
3909         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
3910         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
3911         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
3912 };
3913
3914 #undef PRE_EX
3915 #undef POST_EX
3916 #undef POST_MEM
3917
3918 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3919                                struct x86_instruction_info *info,
3920                                enum x86_intercept_stage stage,
3921                                struct x86_exception *exception)
3922 {
3923         struct vcpu_svm *svm = to_svm(vcpu);
3924         int vmexit, ret = X86EMUL_CONTINUE;
3925         struct __x86_intercept icpt_info;
3926         struct vmcb *vmcb = svm->vmcb;
3927
3928         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3929                 goto out;
3930
3931         icpt_info = x86_intercept_map[info->intercept];
3932
3933         if (stage != icpt_info.stage)
3934                 goto out;
3935
3936         switch (icpt_info.exit_code) {
3937         case SVM_EXIT_READ_CR0:
3938                 if (info->intercept == x86_intercept_cr_read)
3939                         icpt_info.exit_code += info->modrm_reg;
3940                 break;
3941         case SVM_EXIT_WRITE_CR0: {
3942                 unsigned long cr0, val;
3943
3944                 if (info->intercept == x86_intercept_cr_write)
3945                         icpt_info.exit_code += info->modrm_reg;
3946
3947                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3948                     info->intercept == x86_intercept_clts)
3949                         break;
3950
3951                 if (!(vmcb_is_intercept(&svm->nested.ctl,
3952                                         INTERCEPT_SELECTIVE_CR0)))
3953                         break;
3954
3955                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3956                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
3957
3958                 if (info->intercept == x86_intercept_lmsw) {
3959                         cr0 &= 0xfUL;
3960                         val &= 0xfUL;
3961                         /* lmsw can't clear PE - catch this here */
3962                         if (cr0 & X86_CR0_PE)
3963                                 val |= X86_CR0_PE;
3964                 }
3965
3966                 if (cr0 ^ val)
3967                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3968
3969                 break;
3970         }
3971         case SVM_EXIT_READ_DR0:
3972         case SVM_EXIT_WRITE_DR0:
3973                 icpt_info.exit_code += info->modrm_reg;
3974                 break;
3975         case SVM_EXIT_MSR:
3976                 if (info->intercept == x86_intercept_wrmsr)
3977                         vmcb->control.exit_info_1 = 1;
3978                 else
3979                         vmcb->control.exit_info_1 = 0;
3980                 break;
3981         case SVM_EXIT_PAUSE:
3982                 /*
3983                  * We get this for NOP only, but pause
3984                  * is rep not, check this here
3985                  */
3986                 if (info->rep_prefix != REPE_PREFIX)
3987                         goto out;
3988                 break;
3989         case SVM_EXIT_IOIO: {
3990                 u64 exit_info;
3991                 u32 bytes;
3992
3993                 if (info->intercept == x86_intercept_in ||
3994                     info->intercept == x86_intercept_ins) {
3995                         exit_info = ((info->src_val & 0xffff) << 16) |
3996                                 SVM_IOIO_TYPE_MASK;
3997                         bytes = info->dst_bytes;
3998                 } else {
3999                         exit_info = (info->dst_val & 0xffff) << 16;
4000                         bytes = info->src_bytes;
4001                 }
4002
4003                 if (info->intercept == x86_intercept_outs ||
4004                     info->intercept == x86_intercept_ins)
4005                         exit_info |= SVM_IOIO_STR_MASK;
4006
4007                 if (info->rep_prefix)
4008                         exit_info |= SVM_IOIO_REP_MASK;
4009
4010                 bytes = min(bytes, 4u);
4011
4012                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4013
4014                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4015
4016                 vmcb->control.exit_info_1 = exit_info;
4017                 vmcb->control.exit_info_2 = info->next_rip;
4018
4019                 break;
4020         }
4021         default:
4022                 break;
4023         }
4024
4025         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4026         if (static_cpu_has(X86_FEATURE_NRIPS))
4027                 vmcb->control.next_rip  = info->next_rip;
4028         vmcb->control.exit_code = icpt_info.exit_code;
4029         vmexit = nested_svm_exit_handled(svm);
4030
4031         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4032                                            : X86EMUL_CONTINUE;
4033
4034 out:
4035         return ret;
4036 }
4037
4038 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4039 {
4040 }
4041
4042 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4043 {
4044         if (!kvm_pause_in_guest(vcpu->kvm))
4045                 shrink_ple_window(vcpu);
4046 }
4047
4048 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4049 {
4050         /* [63:9] are reserved. */
4051         vcpu->arch.mcg_cap &= 0x1ff;
4052 }
4053
4054 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4055 {
4056         struct vcpu_svm *svm = to_svm(vcpu);
4057
4058         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4059         if (!gif_set(svm))
4060                 return true;
4061
4062         return is_smm(vcpu);
4063 }
4064
4065 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4066 {
4067         struct vcpu_svm *svm = to_svm(vcpu);
4068         if (svm->nested.nested_run_pending)
4069                 return -EBUSY;
4070
4071         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4072         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4073                 return -EBUSY;
4074
4075         return !svm_smi_blocked(vcpu);
4076 }
4077
4078 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4079 {
4080         struct vcpu_svm *svm = to_svm(vcpu);
4081         int ret;
4082
4083         if (is_guest_mode(vcpu)) {
4084                 /* FED8h - SVM Guest */
4085                 put_smstate(u64, smstate, 0x7ed8, 1);
4086                 /* FEE0h - SVM Guest VMCB Physical Address */
4087                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4088
4089                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4090                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4091                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4092
4093                 ret = nested_svm_vmexit(svm);
4094                 if (ret)
4095                         return ret;
4096         }
4097         return 0;
4098 }
4099
4100 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4101 {
4102         struct vcpu_svm *svm = to_svm(vcpu);
4103         struct kvm_host_map map;
4104         int ret = 0;
4105
4106         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4107                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4108                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4109                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4110
4111                 if (guest) {
4112                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4113                                 return 1;
4114
4115                         if (!(saved_efer & EFER_SVME))
4116                                 return 1;
4117
4118                         if (kvm_vcpu_map(&svm->vcpu,
4119                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4120                                 return 1;
4121
4122                         if (svm_allocate_nested(svm))
4123                                 return 1;
4124
4125                         ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4126                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
4127                 }
4128         }
4129
4130         return ret;
4131 }
4132
4133 static void enable_smi_window(struct kvm_vcpu *vcpu)
4134 {
4135         struct vcpu_svm *svm = to_svm(vcpu);
4136
4137         if (!gif_set(svm)) {
4138                 if (vgif_enabled(svm))
4139                         svm_set_intercept(svm, INTERCEPT_STGI);
4140                 /* STGI will cause a vm exit */
4141         } else {
4142                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4143         }
4144 }
4145
4146 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4147 {
4148         bool smep, smap, is_user;
4149         unsigned long cr4;
4150
4151         /*
4152          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4153          *
4154          * Errata:
4155          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4156          * possible that CPU microcode implementing DecodeAssist will fail
4157          * to read bytes of instruction which caused #NPF. In this case,
4158          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4159          * return 0 instead of the correct guest instruction bytes.
4160          *
4161          * This happens because CPU microcode reading instruction bytes
4162          * uses a special opcode which attempts to read data using CPL=0
4163          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4164          * fault, it gives up and returns no instruction bytes.
4165          *
4166          * Detection:
4167          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4168          * returned 0 in GuestIntrBytes field of the VMCB.
4169          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4170          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4171          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4172          * a SMEP fault instead of #NPF).
4173          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4174          * As most guests enable SMAP if they have also enabled SMEP, use above
4175          * logic in order to attempt minimize false-positive of detecting errata
4176          * while still preserving all cases semantic correctness.
4177          *
4178          * Workaround:
4179          * To determine what instruction the guest was executing, the hypervisor
4180          * will have to decode the instruction at the instruction pointer.
4181          *
4182          * In non SEV guest, hypervisor will be able to read the guest
4183          * memory to decode the instruction pointer when insn_len is zero
4184          * so we return true to indicate that decoding is possible.
4185          *
4186          * But in the SEV guest, the guest memory is encrypted with the
4187          * guest specific key and hypervisor will not be able to decode the
4188          * instruction pointer so we will not able to workaround it. Lets
4189          * print the error and request to kill the guest.
4190          */
4191         if (likely(!insn || insn_len))
4192                 return true;
4193
4194         /*
4195          * If RIP is invalid, go ahead with emulation which will cause an
4196          * internal error exit.
4197          */
4198         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4199                 return true;
4200
4201         cr4 = kvm_read_cr4(vcpu);
4202         smep = cr4 & X86_CR4_SMEP;
4203         smap = cr4 & X86_CR4_SMAP;
4204         is_user = svm_get_cpl(vcpu) == 3;
4205         if (smap && (!smep || is_user)) {
4206                 if (!sev_guest(vcpu->kvm))
4207                         return true;
4208
4209                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4210                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4211         }
4212
4213         return false;
4214 }
4215
4216 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4217 {
4218         struct vcpu_svm *svm = to_svm(vcpu);
4219
4220         /*
4221          * TODO: Last condition latch INIT signals on vCPU when
4222          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4223          * To properly emulate the INIT intercept,
4224          * svm_check_nested_events() should call nested_svm_vmexit()
4225          * if an INIT signal is pending.
4226          */
4227         return !gif_set(svm) ||
4228                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4229 }
4230
4231 static void svm_vm_destroy(struct kvm *kvm)
4232 {
4233         avic_vm_destroy(kvm);
4234         sev_vm_destroy(kvm);
4235 }
4236
4237 static int svm_vm_init(struct kvm *kvm)
4238 {
4239         if (!pause_filter_count || !pause_filter_thresh)
4240                 kvm->arch.pause_in_guest = true;
4241
4242         if (avic) {
4243                 int ret = avic_vm_init(kvm);
4244                 if (ret)
4245                         return ret;
4246         }
4247
4248         kvm_apicv_init(kvm, avic);
4249         return 0;
4250 }
4251
4252 static struct kvm_x86_ops svm_x86_ops __initdata = {
4253         .hardware_unsetup = svm_hardware_teardown,
4254         .hardware_enable = svm_hardware_enable,
4255         .hardware_disable = svm_hardware_disable,
4256         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4257         .has_emulated_msr = svm_has_emulated_msr,
4258
4259         .vcpu_create = svm_create_vcpu,
4260         .vcpu_free = svm_free_vcpu,
4261         .vcpu_reset = svm_vcpu_reset,
4262
4263         .vm_size = sizeof(struct kvm_svm),
4264         .vm_init = svm_vm_init,
4265         .vm_destroy = svm_vm_destroy,
4266
4267         .prepare_guest_switch = svm_prepare_guest_switch,
4268         .vcpu_load = svm_vcpu_load,
4269         .vcpu_put = svm_vcpu_put,
4270         .vcpu_blocking = svm_vcpu_blocking,
4271         .vcpu_unblocking = svm_vcpu_unblocking,
4272
4273         .update_exception_bitmap = update_exception_bitmap,
4274         .get_msr_feature = svm_get_msr_feature,
4275         .get_msr = svm_get_msr,
4276         .set_msr = svm_set_msr,
4277         .get_segment_base = svm_get_segment_base,
4278         .get_segment = svm_get_segment,
4279         .set_segment = svm_set_segment,
4280         .get_cpl = svm_get_cpl,
4281         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4282         .set_cr0 = svm_set_cr0,
4283         .is_valid_cr4 = svm_is_valid_cr4,
4284         .set_cr4 = svm_set_cr4,
4285         .set_efer = svm_set_efer,
4286         .get_idt = svm_get_idt,
4287         .set_idt = svm_set_idt,
4288         .get_gdt = svm_get_gdt,
4289         .set_gdt = svm_set_gdt,
4290         .set_dr7 = svm_set_dr7,
4291         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4292         .cache_reg = svm_cache_reg,
4293         .get_rflags = svm_get_rflags,
4294         .set_rflags = svm_set_rflags,
4295
4296         .tlb_flush_all = svm_flush_tlb,
4297         .tlb_flush_current = svm_flush_tlb,
4298         .tlb_flush_gva = svm_flush_tlb_gva,
4299         .tlb_flush_guest = svm_flush_tlb,
4300
4301         .run = svm_vcpu_run,
4302         .handle_exit = handle_exit,
4303         .skip_emulated_instruction = skip_emulated_instruction,
4304         .update_emulated_instruction = NULL,
4305         .set_interrupt_shadow = svm_set_interrupt_shadow,
4306         .get_interrupt_shadow = svm_get_interrupt_shadow,
4307         .patch_hypercall = svm_patch_hypercall,
4308         .set_irq = svm_set_irq,
4309         .set_nmi = svm_inject_nmi,
4310         .queue_exception = svm_queue_exception,
4311         .cancel_injection = svm_cancel_injection,
4312         .interrupt_allowed = svm_interrupt_allowed,
4313         .nmi_allowed = svm_nmi_allowed,
4314         .get_nmi_mask = svm_get_nmi_mask,
4315         .set_nmi_mask = svm_set_nmi_mask,
4316         .enable_nmi_window = enable_nmi_window,
4317         .enable_irq_window = enable_irq_window,
4318         .update_cr8_intercept = update_cr8_intercept,
4319         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4320         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4321         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4322         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4323         .load_eoi_exitmap = svm_load_eoi_exitmap,
4324         .hwapic_irr_update = svm_hwapic_irr_update,
4325         .hwapic_isr_update = svm_hwapic_isr_update,
4326         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4327         .apicv_post_state_restore = avic_post_state_restore,
4328
4329         .set_tss_addr = svm_set_tss_addr,
4330         .set_identity_map_addr = svm_set_identity_map_addr,
4331         .get_mt_mask = svm_get_mt_mask,
4332
4333         .get_exit_info = svm_get_exit_info,
4334
4335         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4336
4337         .has_wbinvd_exit = svm_has_wbinvd_exit,
4338
4339         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4340
4341         .load_mmu_pgd = svm_load_mmu_pgd,
4342
4343         .check_intercept = svm_check_intercept,
4344         .handle_exit_irqoff = svm_handle_exit_irqoff,
4345
4346         .request_immediate_exit = __kvm_request_immediate_exit,
4347
4348         .sched_in = svm_sched_in,
4349
4350         .pmu_ops = &amd_pmu_ops,
4351         .nested_ops = &svm_nested_ops,
4352
4353         .deliver_posted_interrupt = svm_deliver_avic_intr,
4354         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4355         .update_pi_irte = svm_update_pi_irte,
4356         .setup_mce = svm_setup_mce,
4357
4358         .smi_allowed = svm_smi_allowed,
4359         .pre_enter_smm = svm_pre_enter_smm,
4360         .pre_leave_smm = svm_pre_leave_smm,
4361         .enable_smi_window = enable_smi_window,
4362
4363         .mem_enc_op = svm_mem_enc_op,
4364         .mem_enc_reg_region = svm_register_enc_region,
4365         .mem_enc_unreg_region = svm_unregister_enc_region,
4366
4367         .can_emulate_instruction = svm_can_emulate_instruction,
4368
4369         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4370
4371         .msr_filter_changed = svm_msr_filter_changed,
4372         .complete_emulated_msr = svm_complete_emulated_msr,
4373 };
4374
4375 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4376         .cpu_has_kvm_support = has_svm,
4377         .disabled_by_bios = is_disabled,
4378         .hardware_setup = svm_hardware_setup,
4379         .check_processor_compatibility = svm_check_processor_compat,
4380
4381         .runtime_ops = &svm_x86_ops,
4382 };
4383
4384 static int __init svm_init(void)
4385 {
4386         __unused_size_checks();
4387
4388         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4389                         __alignof__(struct vcpu_svm), THIS_MODULE);
4390 }
4391
4392 static void __exit svm_exit(void)
4393 {
4394         kvm_exit();
4395 }
4396
4397 module_init(svm_init)
4398 module_exit(svm_exit)