1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
40 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
51 static const struct x86_cpu_id svm_cpu_id[] = {
52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
64 #define SVM_FEATURE_LBRV (1 << 1)
65 #define SVM_FEATURE_SVML (1 << 2)
66 #define SVM_FEATURE_TSC_RATE (1 << 4)
67 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
69 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
70 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78 static bool erratum_383_found __read_mostly;
80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
86 static uint64_t osvw_len = 4, osvw_status;
88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
91 static const struct svm_direct_access_msrs {
92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
95 { .index = MSR_STAR, .always = true },
96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
106 { .index = MSR_IA32_PRED_CMD, .always = false },
107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 bool npt_enabled = true;
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152 module_param(pause_filter_thresh, ushort, 0444);
154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155 module_param(pause_filter_count, ushort, 0444);
157 /* Default doubles per-vcpu window every exit. */
158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159 module_param(pause_filter_count_grow, ushort, 0444);
161 /* Default resets per-vcpu window every exit to pause_filter_count. */
162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163 module_param(pause_filter_count_shrink, ushort, 0444);
165 /* Default is to compute the maximum so we can never overflow. */
166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167 module_param(pause_filter_count_max, ushort, 0444);
169 /* allow nested paging (virtualized MMU) for all guests */
170 static int npt = true;
171 module_param(npt, int, S_IRUGO);
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
189 /* enable/disable SEV support */
190 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191 module_param(sev, int, 0444);
193 /* enable/disable SEV-ES support */
194 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
195 module_param(sev_es, int, 0444);
197 static bool __read_mostly dump_invalid_vmcb = 0;
198 module_param(dump_invalid_vmcb, bool, 0644);
200 static u8 rsm_ins_bytes[] = "\x0f\xaa";
202 static void svm_complete_interrupts(struct vcpu_svm *svm);
204 static unsigned long iopm_base;
206 struct kvm_ldttss_desc {
209 unsigned base1:8, type:5, dpl:2, p:1;
210 unsigned limit1:4, zero0:3, g:1, base2:8;
213 } __attribute__((packed));
215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
220 #define MSRS_RANGE_SIZE 2048
221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
223 u32 svm_msrpm_offset(u32 msr)
228 for (i = 0; i < NUM_MSR_MAPS; i++) {
229 if (msr < msrpm_ranges[i] ||
230 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
233 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
234 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
236 /* Now we have the u8 offset - but need the u32 offset */
240 /* MSR not in any range */
244 #define MAX_INST_SIZE 15
246 static inline void clgi(void)
248 asm volatile (__ex("clgi"));
251 static inline void stgi(void)
253 asm volatile (__ex("stgi"));
256 static inline void invlpga(unsigned long addr, u32 asid)
258 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
261 static int get_max_npt_level(void)
264 return PT64_ROOT_4LEVEL;
266 return PT32E_ROOT_LEVEL;
270 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
272 struct vcpu_svm *svm = to_svm(vcpu);
273 u64 old_efer = vcpu->arch.efer;
274 vcpu->arch.efer = efer;
277 /* Shadow paging assumes NX to be available. */
280 if (!(efer & EFER_LMA))
284 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
285 if (!(efer & EFER_SVME)) {
286 svm_leave_nested(svm);
287 svm_set_gif(svm, true);
290 * Free the nested guest state, unless we are in SMM.
291 * In this case we will return to the nested guest
292 * as soon as we leave SMM.
294 if (!is_smm(&svm->vcpu))
295 svm_free_nested(svm);
298 int ret = svm_allocate_nested(svm);
301 vcpu->arch.efer = old_efer;
307 svm->vmcb->save.efer = efer | EFER_SVME;
308 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
312 static int is_external_interrupt(u32 info)
314 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
315 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
318 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
320 struct vcpu_svm *svm = to_svm(vcpu);
323 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
324 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
328 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
330 struct vcpu_svm *svm = to_svm(vcpu);
333 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
335 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
339 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
341 struct vcpu_svm *svm = to_svm(vcpu);
344 * SEV-ES does not expose the next RIP. The RIP update is controlled by
345 * the type of exit and the #VC handler in the guest.
347 if (sev_es_guest(vcpu->kvm))
350 if (nrips && svm->vmcb->control.next_rip != 0) {
351 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
352 svm->next_rip = svm->vmcb->control.next_rip;
355 if (!svm->next_rip) {
356 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
359 kvm_rip_write(vcpu, svm->next_rip);
363 svm_set_interrupt_shadow(vcpu, 0);
368 static void svm_queue_exception(struct kvm_vcpu *vcpu)
370 struct vcpu_svm *svm = to_svm(vcpu);
371 unsigned nr = vcpu->arch.exception.nr;
372 bool has_error_code = vcpu->arch.exception.has_error_code;
373 u32 error_code = vcpu->arch.exception.error_code;
375 kvm_deliver_exception_payload(&svm->vcpu);
377 if (nr == BP_VECTOR && !nrips) {
378 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
381 * For guest debugging where we have to reinject #BP if some
382 * INT3 is guest-owned:
383 * Emulate nRIP by moving RIP forward. Will fail if injection
384 * raises a fault that is not intercepted. Still better than
385 * failing in all cases.
387 (void)skip_emulated_instruction(&svm->vcpu);
388 rip = kvm_rip_read(&svm->vcpu);
389 svm->int3_rip = rip + svm->vmcb->save.cs.base;
390 svm->int3_injected = rip - old_rip;
393 svm->vmcb->control.event_inj = nr
395 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
396 | SVM_EVTINJ_TYPE_EXEPT;
397 svm->vmcb->control.event_inj_err = error_code;
400 static void svm_init_erratum_383(void)
406 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
409 /* Use _safe variants to not break nested virtualization */
410 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
416 low = lower_32_bits(val);
417 high = upper_32_bits(val);
419 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
421 erratum_383_found = true;
424 static void svm_init_osvw(struct kvm_vcpu *vcpu)
427 * Guests should see errata 400 and 415 as fixed (assuming that
428 * HLT and IO instructions are intercepted).
430 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
431 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
434 * By increasing VCPU's osvw.length to 3 we are telling the guest that
435 * all osvw.status bits inside that length, including bit 0 (which is
436 * reserved for erratum 298), are valid. However, if host processor's
437 * osvw_len is 0 then osvw_status[0] carries no information. We need to
438 * be conservative here and therefore we tell the guest that erratum 298
439 * is present (because we really don't know).
441 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
442 vcpu->arch.osvw.status |= 1;
445 static int has_svm(void)
449 if (!cpu_has_svm(&msg)) {
450 printk(KERN_INFO "has_svm: %s\n", msg);
457 static void svm_hardware_disable(void)
459 /* Make sure we clean up behind us */
460 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
461 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
465 amd_pmu_disable_virt();
468 static int svm_hardware_enable(void)
471 struct svm_cpu_data *sd;
473 struct desc_struct *gdt;
474 int me = raw_smp_processor_id();
476 rdmsrl(MSR_EFER, efer);
477 if (efer & EFER_SVME)
481 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
484 sd = per_cpu(svm_data, me);
486 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
490 sd->asid_generation = 1;
491 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
492 sd->next_asid = sd->max_asid + 1;
493 sd->min_asid = max_sev_asid + 1;
495 gdt = get_current_gdt_rw();
496 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
498 wrmsrl(MSR_EFER, efer | EFER_SVME);
500 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
502 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
503 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
504 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
511 * Note that it is possible to have a system with mixed processor
512 * revisions and therefore different OSVW bits. If bits are not the same
513 * on different processors then choose the worst case (i.e. if erratum
514 * is present on one processor and not on another then assume that the
515 * erratum is present everywhere).
517 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
518 uint64_t len, status = 0;
521 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
523 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
527 osvw_status = osvw_len = 0;
531 osvw_status |= status;
532 osvw_status &= (1ULL << osvw_len) - 1;
535 osvw_status = osvw_len = 0;
537 svm_init_erratum_383();
539 amd_pmu_enable_virt();
544 static void svm_cpu_uninit(int cpu)
546 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
551 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
552 kfree(sd->sev_vmcbs);
553 __free_page(sd->save_area);
557 static int svm_cpu_init(int cpu)
559 struct svm_cpu_data *sd;
561 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
565 sd->save_area = alloc_page(GFP_KERNEL);
569 if (svm_sev_enabled()) {
570 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
577 per_cpu(svm_data, cpu) = sd;
582 __free_page(sd->save_area);
589 static int direct_access_msr_slot(u32 msr)
593 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
594 if (direct_access_msrs[i].index == msr)
600 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
603 struct vcpu_svm *svm = to_svm(vcpu);
604 int slot = direct_access_msr_slot(msr);
609 /* Set the shadow bitmaps to the desired intercept states */
611 set_bit(slot, svm->shadow_msr_intercept.read);
613 clear_bit(slot, svm->shadow_msr_intercept.read);
616 set_bit(slot, svm->shadow_msr_intercept.write);
618 clear_bit(slot, svm->shadow_msr_intercept.write);
621 static bool valid_msr_intercept(u32 index)
623 return direct_access_msr_slot(index) != -ENOENT;
626 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
633 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
636 offset = svm_msrpm_offset(msr);
637 bit_write = 2 * (msr & 0x0f) + 1;
640 BUG_ON(offset == MSR_INVALID);
642 return !!test_bit(bit_write, &tmp);
645 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
646 u32 msr, int read, int write)
648 u8 bit_read, bit_write;
653 * If this warning triggers extend the direct_access_msrs list at the
654 * beginning of the file
656 WARN_ON(!valid_msr_intercept(msr));
658 /* Enforce non allowed MSRs to trap */
659 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
662 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
665 offset = svm_msrpm_offset(msr);
666 bit_read = 2 * (msr & 0x0f);
667 bit_write = 2 * (msr & 0x0f) + 1;
670 BUG_ON(offset == MSR_INVALID);
672 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
673 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
678 static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
681 set_shadow_msr_intercept(vcpu, msr, read, write);
682 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
685 u32 *svm_vcpu_alloc_msrpm(void)
687 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
693 msrpm = page_address(pages);
694 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
699 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
703 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
704 if (!direct_access_msrs[i].always)
706 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
711 void svm_vcpu_free_msrpm(u32 *msrpm)
713 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
716 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
718 struct vcpu_svm *svm = to_svm(vcpu);
722 * Set intercept permissions for all direct access MSRs again. They
723 * will automatically get filtered through the MSR filter, so we are
724 * back in sync after this.
726 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
727 u32 msr = direct_access_msrs[i].index;
728 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
729 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
731 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
735 static void add_msr_offset(u32 offset)
739 for (i = 0; i < MSRPM_OFFSETS; ++i) {
741 /* Offset already in list? */
742 if (msrpm_offsets[i] == offset)
745 /* Slot used by another offset? */
746 if (msrpm_offsets[i] != MSR_INVALID)
749 /* Add offset to list */
750 msrpm_offsets[i] = offset;
756 * If this BUG triggers the msrpm_offsets table has an overflow. Just
757 * increase MSRPM_OFFSETS in this case.
762 static void init_msrpm_offsets(void)
766 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
768 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
771 offset = svm_msrpm_offset(direct_access_msrs[i].index);
772 BUG_ON(offset == MSR_INVALID);
774 add_msr_offset(offset);
778 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
780 struct vcpu_svm *svm = to_svm(vcpu);
782 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
783 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
784 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
785 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
786 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
789 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
791 struct vcpu_svm *svm = to_svm(vcpu);
793 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
794 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
795 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
796 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
797 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
800 void disable_nmi_singlestep(struct vcpu_svm *svm)
802 svm->nmi_singlestep = false;
804 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
805 /* Clear our flags if they were not set by the guest */
806 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
807 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
808 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
809 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
813 static void grow_ple_window(struct kvm_vcpu *vcpu)
815 struct vcpu_svm *svm = to_svm(vcpu);
816 struct vmcb_control_area *control = &svm->vmcb->control;
817 int old = control->pause_filter_count;
819 control->pause_filter_count = __grow_ple_window(old,
821 pause_filter_count_grow,
822 pause_filter_count_max);
824 if (control->pause_filter_count != old) {
825 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
826 trace_kvm_ple_window_update(vcpu->vcpu_id,
827 control->pause_filter_count, old);
831 static void shrink_ple_window(struct kvm_vcpu *vcpu)
833 struct vcpu_svm *svm = to_svm(vcpu);
834 struct vmcb_control_area *control = &svm->vmcb->control;
835 int old = control->pause_filter_count;
837 control->pause_filter_count =
838 __shrink_ple_window(old,
840 pause_filter_count_shrink,
842 if (control->pause_filter_count != old) {
843 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
844 trace_kvm_ple_window_update(vcpu->vcpu_id,
845 control->pause_filter_count, old);
850 * The default MMIO mask is a single bit (excluding the present bit),
851 * which could conflict with the memory encryption bit. Check for
852 * memory encryption support and override the default MMIO mask if
853 * memory encryption is enabled.
855 static __init void svm_adjust_mmio_mask(void)
857 unsigned int enc_bit, mask_bit;
860 /* If there is no memory encryption support, use existing mask */
861 if (cpuid_eax(0x80000000) < 0x8000001f)
864 /* If memory encryption is not enabled, use existing mask */
865 rdmsrl(MSR_K8_SYSCFG, msr);
866 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
869 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
870 mask_bit = boot_cpu_data.x86_phys_bits;
872 /* Increment the mask bit if it is the same as the encryption bit */
873 if (enc_bit == mask_bit)
877 * If the mask bit location is below 52, then some bits above the
878 * physical addressing limit will always be reserved, so use the
879 * rsvd_bits() function to generate the mask. This mask, along with
880 * the present bit, will be used to generate a page fault with
883 * If the mask bit location is 52 (or above), then clear the mask.
885 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
887 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
890 static void svm_hardware_teardown(void)
894 if (svm_sev_enabled())
895 sev_hardware_teardown();
897 for_each_possible_cpu(cpu)
900 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
904 static __init void svm_set_cpu_caps(void)
910 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
912 kvm_cpu_cap_set(X86_FEATURE_SVM);
915 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
918 kvm_cpu_cap_set(X86_FEATURE_NPT);
921 /* CPUID 0x80000008 */
922 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
923 boot_cpu_has(X86_FEATURE_AMD_SSBD))
924 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
926 /* Enable INVPCID feature */
927 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
930 static __init int svm_hardware_setup(void)
933 struct page *iopm_pages;
937 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
942 iopm_va = page_address(iopm_pages);
943 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
944 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
946 init_msrpm_offsets();
948 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
950 if (boot_cpu_has(X86_FEATURE_NX))
951 kvm_enable_efer_bits(EFER_NX);
953 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
954 kvm_enable_efer_bits(EFER_FFXSR);
956 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
957 kvm_has_tsc_control = true;
958 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
959 kvm_tsc_scaling_ratio_frac_bits = 32;
962 /* Check for pause filtering support */
963 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
964 pause_filter_count = 0;
965 pause_filter_thresh = 0;
966 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
967 pause_filter_thresh = 0;
971 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
972 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
975 if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
976 sev_hardware_setup();
982 svm_adjust_mmio_mask();
984 for_each_possible_cpu(cpu) {
985 r = svm_cpu_init(cpu);
990 if (!boot_cpu_has(X86_FEATURE_NPT))
993 if (npt_enabled && !npt)
996 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
997 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1000 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1006 !boot_cpu_has(X86_FEATURE_AVIC) ||
1007 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1010 pr_info("AVIC enabled\n");
1012 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1018 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1019 !IS_ENABLED(CONFIG_X86_64)) {
1022 pr_info("Virtual VMLOAD VMSAVE supported\n");
1027 if (!boot_cpu_has(X86_FEATURE_VGIF))
1030 pr_info("Virtual GIF supported\n");
1036 * It seems that on AMD processors PTE's accessed bit is
1037 * being set by the CPU hardware before the NPF vmexit.
1038 * This is not expected behaviour and our tests fail because
1040 * A workaround here is to disable support for
1041 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1042 * In this case userspace can know if there is support using
1043 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1045 * If future AMD CPU models change the behaviour described above,
1046 * this variable can be changed accordingly
1048 allow_smaller_maxphyaddr = !npt_enabled;
1053 svm_hardware_teardown();
1057 static void init_seg(struct vmcb_seg *seg)
1060 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1061 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1062 seg->limit = 0xffff;
1066 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1069 seg->attrib = SVM_SELECTOR_P_MASK | type;
1070 seg->limit = 0xffff;
1074 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1076 struct vcpu_svm *svm = to_svm(vcpu);
1077 u64 g_tsc_offset = 0;
1079 if (is_guest_mode(vcpu)) {
1080 /* Write L1's TSC offset. */
1081 g_tsc_offset = svm->vmcb->control.tsc_offset -
1082 svm->nested.hsave->control.tsc_offset;
1083 svm->nested.hsave->control.tsc_offset = offset;
1086 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1087 svm->vmcb->control.tsc_offset - g_tsc_offset,
1090 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1092 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1093 return svm->vmcb->control.tsc_offset;
1096 static void svm_check_invpcid(struct vcpu_svm *svm)
1099 * Intercept INVPCID instruction only if shadow page table is
1100 * enabled. Interception is not required with nested page table
1103 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1105 svm_set_intercept(svm, INTERCEPT_INVPCID);
1107 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1111 static void init_vmcb(struct vcpu_svm *svm)
1113 struct vmcb_control_area *control = &svm->vmcb->control;
1114 struct vmcb_save_area *save = &svm->vmcb->save;
1116 svm->vcpu.arch.hflags = 0;
1118 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1119 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1120 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1121 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1122 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1123 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1124 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1125 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1127 set_dr_intercepts(svm);
1129 set_exception_intercept(svm, PF_VECTOR);
1130 set_exception_intercept(svm, UD_VECTOR);
1131 set_exception_intercept(svm, MC_VECTOR);
1132 set_exception_intercept(svm, AC_VECTOR);
1133 set_exception_intercept(svm, DB_VECTOR);
1135 * Guest access to VMware backdoor ports could legitimately
1136 * trigger #GP because of TSS I/O permission bitmap.
1137 * We intercept those #GP and allow access to them anyway
1140 if (enable_vmware_backdoor)
1141 set_exception_intercept(svm, GP_VECTOR);
1143 svm_set_intercept(svm, INTERCEPT_INTR);
1144 svm_set_intercept(svm, INTERCEPT_NMI);
1145 svm_set_intercept(svm, INTERCEPT_SMI);
1146 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1147 svm_set_intercept(svm, INTERCEPT_RDPMC);
1148 svm_set_intercept(svm, INTERCEPT_CPUID);
1149 svm_set_intercept(svm, INTERCEPT_INVD);
1150 svm_set_intercept(svm, INTERCEPT_INVLPG);
1151 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1152 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1153 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1154 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1155 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1156 svm_set_intercept(svm, INTERCEPT_VMRUN);
1157 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1158 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1159 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1160 svm_set_intercept(svm, INTERCEPT_STGI);
1161 svm_set_intercept(svm, INTERCEPT_CLGI);
1162 svm_set_intercept(svm, INTERCEPT_SKINIT);
1163 svm_set_intercept(svm, INTERCEPT_WBINVD);
1164 svm_set_intercept(svm, INTERCEPT_XSETBV);
1165 svm_set_intercept(svm, INTERCEPT_RDPRU);
1166 svm_set_intercept(svm, INTERCEPT_RSM);
1168 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1169 svm_set_intercept(svm, INTERCEPT_MONITOR);
1170 svm_set_intercept(svm, INTERCEPT_MWAIT);
1173 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1174 svm_set_intercept(svm, INTERCEPT_HLT);
1176 control->iopm_base_pa = __sme_set(iopm_base);
1177 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1178 control->int_ctl = V_INTR_MASKING_MASK;
1180 init_seg(&save->es);
1181 init_seg(&save->ss);
1182 init_seg(&save->ds);
1183 init_seg(&save->fs);
1184 init_seg(&save->gs);
1186 save->cs.selector = 0xf000;
1187 save->cs.base = 0xffff0000;
1188 /* Executable/Readable Code Segment */
1189 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1190 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1191 save->cs.limit = 0xffff;
1193 save->gdtr.limit = 0xffff;
1194 save->idtr.limit = 0xffff;
1196 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1197 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1199 svm_set_efer(&svm->vcpu, 0);
1200 save->dr6 = 0xffff0ff0;
1201 kvm_set_rflags(&svm->vcpu, 2);
1202 save->rip = 0x0000fff0;
1203 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1206 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1207 * It also updates the guest-visible cr0 value.
1209 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1210 kvm_mmu_reset_context(&svm->vcpu);
1212 save->cr4 = X86_CR4_PAE;
1216 /* Setup VMCB for Nested Paging */
1217 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1218 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1219 clr_exception_intercept(svm, PF_VECTOR);
1220 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1221 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1222 save->g_pat = svm->vcpu.arch.pat;
1226 svm->asid_generation = 0;
1229 svm->nested.vmcb12_gpa = 0;
1230 svm->vcpu.arch.hflags = 0;
1232 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1233 control->pause_filter_count = pause_filter_count;
1234 if (pause_filter_thresh)
1235 control->pause_filter_thresh = pause_filter_thresh;
1236 svm_set_intercept(svm, INTERCEPT_PAUSE);
1238 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1241 svm_check_invpcid(svm);
1243 if (kvm_vcpu_apicv_active(&svm->vcpu))
1244 avic_init_vmcb(svm);
1247 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1248 * in VMCB and clear intercepts to avoid #VMEXIT.
1251 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1252 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1253 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1257 svm_clr_intercept(svm, INTERCEPT_STGI);
1258 svm_clr_intercept(svm, INTERCEPT_CLGI);
1259 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1262 if (sev_guest(svm->vcpu.kvm)) {
1263 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1264 clr_exception_intercept(svm, UD_VECTOR);
1267 vmcb_mark_all_dirty(svm->vmcb);
1273 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1275 struct vcpu_svm *svm = to_svm(vcpu);
1280 svm->virt_spec_ctrl = 0;
1283 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1284 MSR_IA32_APICBASE_ENABLE;
1285 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1286 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1290 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1291 kvm_rdx_write(vcpu, eax);
1293 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1294 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1297 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1299 struct vcpu_svm *svm;
1300 struct page *vmcb_page;
1301 struct page *vmsa_page = NULL;
1304 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1308 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1312 if (sev_es_guest(svm->vcpu.kvm)) {
1314 * SEV-ES guests require a separate VMSA page used to contain
1315 * the encrypted register state of the guest.
1317 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1319 goto error_free_vmcb_page;
1322 err = avic_init_vcpu(svm);
1324 goto error_free_vmsa_page;
1326 /* We initialize this flag to true to make sure that the is_running
1327 * bit would be set the first time the vcpu is loaded.
1329 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1330 svm->avic_is_running = true;
1332 svm->msrpm = svm_vcpu_alloc_msrpm();
1334 goto error_free_vmsa_page;
1336 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1338 svm->vmcb = page_address(vmcb_page);
1339 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1342 svm->vmsa = page_address(vmsa_page);
1344 svm->asid_generation = 0;
1347 svm_init_osvw(vcpu);
1348 vcpu->arch.microcode_version = 0x01000065;
1352 error_free_vmsa_page:
1354 __free_page(vmsa_page);
1355 error_free_vmcb_page:
1356 __free_page(vmcb_page);
1361 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1365 for_each_online_cpu(i)
1366 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1369 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1371 struct vcpu_svm *svm = to_svm(vcpu);
1374 * The vmcb page can be recycled, causing a false negative in
1375 * svm_vcpu_load(). So, ensure that no logical CPU has this
1376 * vmcb page recorded as its current vmcb.
1378 svm_clear_current_vmcb(svm->vmcb);
1380 svm_free_nested(svm);
1382 sev_free_vcpu(vcpu);
1384 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1385 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1388 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1390 struct vcpu_svm *svm = to_svm(vcpu);
1391 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1394 if (unlikely(cpu != vcpu->cpu)) {
1395 svm->asid_generation = 0;
1396 vmcb_mark_all_dirty(svm->vmcb);
1399 #ifdef CONFIG_X86_64
1400 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1402 savesegment(fs, svm->host.fs);
1403 savesegment(gs, svm->host.gs);
1404 svm->host.ldt = kvm_read_ldt();
1406 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1407 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1409 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1410 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1411 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1412 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1413 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1416 /* This assumes that the kernel never uses MSR_TSC_AUX */
1417 if (static_cpu_has(X86_FEATURE_RDTSCP))
1418 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1420 if (sd->current_vmcb != svm->vmcb) {
1421 sd->current_vmcb = svm->vmcb;
1422 indirect_branch_prediction_barrier();
1424 avic_vcpu_load(vcpu, cpu);
1427 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1429 struct vcpu_svm *svm = to_svm(vcpu);
1432 avic_vcpu_put(vcpu);
1434 ++vcpu->stat.host_state_reload;
1435 kvm_load_ldt(svm->host.ldt);
1436 #ifdef CONFIG_X86_64
1437 loadsegment(fs, svm->host.fs);
1438 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1439 load_gs_index(svm->host.gs);
1441 #ifdef CONFIG_X86_32_LAZY_GS
1442 loadsegment(gs, svm->host.gs);
1445 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1446 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1449 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1451 struct vcpu_svm *svm = to_svm(vcpu);
1452 unsigned long rflags = svm->vmcb->save.rflags;
1454 if (svm->nmi_singlestep) {
1455 /* Hide our flags if they were not set by the guest */
1456 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1457 rflags &= ~X86_EFLAGS_TF;
1458 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1459 rflags &= ~X86_EFLAGS_RF;
1464 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1466 if (to_svm(vcpu)->nmi_singlestep)
1467 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1470 * Any change of EFLAGS.VM is accompanied by a reload of SS
1471 * (caused by either a task switch or an inter-privilege IRET),
1472 * so we do not need to update the CPL here.
1474 to_svm(vcpu)->vmcb->save.rflags = rflags;
1477 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1480 case VCPU_EXREG_PDPTR:
1481 BUG_ON(!npt_enabled);
1482 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1489 static void svm_set_vintr(struct vcpu_svm *svm)
1491 struct vmcb_control_area *control;
1493 /* The following fields are ignored when AVIC is enabled */
1494 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1495 svm_set_intercept(svm, INTERCEPT_VINTR);
1498 * This is just a dummy VINTR to actually cause a vmexit to happen.
1499 * Actual injection of virtual interrupts happens through EVENTINJ.
1501 control = &svm->vmcb->control;
1502 control->int_vector = 0x0;
1503 control->int_ctl &= ~V_INTR_PRIO_MASK;
1504 control->int_ctl |= V_IRQ_MASK |
1505 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1506 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1509 static void svm_clear_vintr(struct vcpu_svm *svm)
1511 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1512 svm_clr_intercept(svm, INTERCEPT_VINTR);
1514 /* Drop int_ctl fields related to VINTR injection. */
1515 svm->vmcb->control.int_ctl &= mask;
1516 if (is_guest_mode(&svm->vcpu)) {
1517 svm->nested.hsave->control.int_ctl &= mask;
1519 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1520 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1521 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1524 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1527 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1529 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1532 case VCPU_SREG_CS: return &save->cs;
1533 case VCPU_SREG_DS: return &save->ds;
1534 case VCPU_SREG_ES: return &save->es;
1535 case VCPU_SREG_FS: return &save->fs;
1536 case VCPU_SREG_GS: return &save->gs;
1537 case VCPU_SREG_SS: return &save->ss;
1538 case VCPU_SREG_TR: return &save->tr;
1539 case VCPU_SREG_LDTR: return &save->ldtr;
1545 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1547 struct vmcb_seg *s = svm_seg(vcpu, seg);
1552 static void svm_get_segment(struct kvm_vcpu *vcpu,
1553 struct kvm_segment *var, int seg)
1555 struct vmcb_seg *s = svm_seg(vcpu, seg);
1557 var->base = s->base;
1558 var->limit = s->limit;
1559 var->selector = s->selector;
1560 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1561 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1562 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1563 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1564 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1565 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1566 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1569 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1570 * However, the SVM spec states that the G bit is not observed by the
1571 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1572 * So let's synthesize a legal G bit for all segments, this helps
1573 * running KVM nested. It also helps cross-vendor migration, because
1574 * Intel's vmentry has a check on the 'G' bit.
1576 var->g = s->limit > 0xfffff;
1579 * AMD's VMCB does not have an explicit unusable field, so emulate it
1580 * for cross vendor migration purposes by "not present"
1582 var->unusable = !var->present;
1587 * Work around a bug where the busy flag in the tr selector
1597 * The accessed bit must always be set in the segment
1598 * descriptor cache, although it can be cleared in the
1599 * descriptor, the cached bit always remains at 1. Since
1600 * Intel has a check on this, set it here to support
1601 * cross-vendor migration.
1608 * On AMD CPUs sometimes the DB bit in the segment
1609 * descriptor is left as 1, although the whole segment has
1610 * been made unusable. Clear it here to pass an Intel VMX
1611 * entry check when cross vendor migrating.
1615 /* This is symmetric with svm_set_segment() */
1616 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1621 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1623 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1628 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1630 struct vcpu_svm *svm = to_svm(vcpu);
1632 dt->size = svm->vmcb->save.idtr.limit;
1633 dt->address = svm->vmcb->save.idtr.base;
1636 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1638 struct vcpu_svm *svm = to_svm(vcpu);
1640 svm->vmcb->save.idtr.limit = dt->size;
1641 svm->vmcb->save.idtr.base = dt->address ;
1642 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1645 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1647 struct vcpu_svm *svm = to_svm(vcpu);
1649 dt->size = svm->vmcb->save.gdtr.limit;
1650 dt->address = svm->vmcb->save.gdtr.base;
1653 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1655 struct vcpu_svm *svm = to_svm(vcpu);
1657 svm->vmcb->save.gdtr.limit = dt->size;
1658 svm->vmcb->save.gdtr.base = dt->address ;
1659 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1662 static void update_cr0_intercept(struct vcpu_svm *svm)
1668 * SEV-ES guests must always keep the CR intercepts cleared. CR
1669 * tracking is done using the CR write traps.
1671 if (sev_es_guest(svm->vcpu.kvm))
1674 gcr0 = svm->vcpu.arch.cr0;
1675 hcr0 = &svm->vmcb->save.cr0;
1676 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1677 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1679 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1681 if (gcr0 == *hcr0) {
1682 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1683 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1685 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1686 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1690 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1692 struct vcpu_svm *svm = to_svm(vcpu);
1694 #ifdef CONFIG_X86_64
1695 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1696 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1697 vcpu->arch.efer |= EFER_LMA;
1698 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1701 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1702 vcpu->arch.efer &= ~EFER_LMA;
1703 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1707 vcpu->arch.cr0 = cr0;
1710 cr0 |= X86_CR0_PG | X86_CR0_WP;
1713 * re-enable caching here because the QEMU bios
1714 * does not do it - this results in some delay at
1717 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1718 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1719 svm->vmcb->save.cr0 = cr0;
1720 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1721 update_cr0_intercept(svm);
1724 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1729 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1731 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1732 unsigned long old_cr4 = vcpu->arch.cr4;
1734 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1735 svm_flush_tlb(vcpu);
1737 vcpu->arch.cr4 = cr4;
1740 cr4 |= host_cr4_mce;
1741 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1742 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1744 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1745 kvm_update_cpuid_runtime(vcpu);
1748 static void svm_set_segment(struct kvm_vcpu *vcpu,
1749 struct kvm_segment *var, int seg)
1751 struct vcpu_svm *svm = to_svm(vcpu);
1752 struct vmcb_seg *s = svm_seg(vcpu, seg);
1754 s->base = var->base;
1755 s->limit = var->limit;
1756 s->selector = var->selector;
1757 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1758 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1759 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1760 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1761 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1762 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1763 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1764 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1767 * This is always accurate, except if SYSRET returned to a segment
1768 * with SS.DPL != 3. Intel does not have this quirk, and always
1769 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1770 * would entail passing the CPL to userspace and back.
1772 if (seg == VCPU_SREG_SS)
1773 /* This is symmetric with svm_get_segment() */
1774 svm->vmcb->save.cpl = (var->dpl & 3);
1776 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1779 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1781 struct vcpu_svm *svm = to_svm(vcpu);
1783 clr_exception_intercept(svm, BP_VECTOR);
1785 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1786 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1787 set_exception_intercept(svm, BP_VECTOR);
1791 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1793 if (sd->next_asid > sd->max_asid) {
1794 ++sd->asid_generation;
1795 sd->next_asid = sd->min_asid;
1796 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1797 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1800 svm->asid_generation = sd->asid_generation;
1801 svm->asid = sd->next_asid++;
1804 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1806 struct vmcb *vmcb = svm->vmcb;
1808 if (svm->vcpu.arch.guest_state_protected)
1811 if (unlikely(value != vmcb->save.dr6)) {
1812 vmcb->save.dr6 = value;
1813 vmcb_mark_dirty(vmcb, VMCB_DR);
1817 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1819 struct vcpu_svm *svm = to_svm(vcpu);
1821 if (vcpu->arch.guest_state_protected)
1824 get_debugreg(vcpu->arch.db[0], 0);
1825 get_debugreg(vcpu->arch.db[1], 1);
1826 get_debugreg(vcpu->arch.db[2], 2);
1827 get_debugreg(vcpu->arch.db[3], 3);
1829 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1830 * because db_interception might need it. We can do it before vmentry.
1832 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1833 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1835 set_dr_intercepts(svm);
1838 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1840 struct vcpu_svm *svm = to_svm(vcpu);
1842 if (vcpu->arch.guest_state_protected)
1845 svm->vmcb->save.dr7 = value;
1846 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1849 static int pf_interception(struct vcpu_svm *svm)
1851 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1852 u64 error_code = svm->vmcb->control.exit_info_1;
1854 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1855 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1856 svm->vmcb->control.insn_bytes : NULL,
1857 svm->vmcb->control.insn_len);
1860 static int npf_interception(struct vcpu_svm *svm)
1862 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1863 u64 error_code = svm->vmcb->control.exit_info_1;
1865 trace_kvm_page_fault(fault_address, error_code);
1866 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1867 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1868 svm->vmcb->control.insn_bytes : NULL,
1869 svm->vmcb->control.insn_len);
1872 static int db_interception(struct vcpu_svm *svm)
1874 struct kvm_run *kvm_run = svm->vcpu.run;
1875 struct kvm_vcpu *vcpu = &svm->vcpu;
1877 if (!(svm->vcpu.guest_debug &
1878 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1879 !svm->nmi_singlestep) {
1880 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1881 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1885 if (svm->nmi_singlestep) {
1886 disable_nmi_singlestep(svm);
1887 /* Make sure we check for pending NMIs upon entry */
1888 kvm_make_request(KVM_REQ_EVENT, vcpu);
1891 if (svm->vcpu.guest_debug &
1892 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1893 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1894 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1895 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1896 kvm_run->debug.arch.pc =
1897 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1898 kvm_run->debug.arch.exception = DB_VECTOR;
1905 static int bp_interception(struct vcpu_svm *svm)
1907 struct kvm_run *kvm_run = svm->vcpu.run;
1909 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1910 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1911 kvm_run->debug.arch.exception = BP_VECTOR;
1915 static int ud_interception(struct vcpu_svm *svm)
1917 return handle_ud(&svm->vcpu);
1920 static int ac_interception(struct vcpu_svm *svm)
1922 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1926 static int gp_interception(struct vcpu_svm *svm)
1928 struct kvm_vcpu *vcpu = &svm->vcpu;
1929 u32 error_code = svm->vmcb->control.exit_info_1;
1931 WARN_ON_ONCE(!enable_vmware_backdoor);
1934 * VMware backdoor emulation on #GP interception only handles IN{S},
1935 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1938 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1941 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1944 static bool is_erratum_383(void)
1949 if (!erratum_383_found)
1952 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1956 /* Bit 62 may or may not be set for this mce */
1957 value &= ~(1ULL << 62);
1959 if (value != 0xb600000000010015ULL)
1962 /* Clear MCi_STATUS registers */
1963 for (i = 0; i < 6; ++i)
1964 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1966 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1970 value &= ~(1ULL << 2);
1971 low = lower_32_bits(value);
1972 high = upper_32_bits(value);
1974 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1977 /* Flush tlb to evict multi-match entries */
1983 static void svm_handle_mce(struct vcpu_svm *svm)
1985 if (is_erratum_383()) {
1987 * Erratum 383 triggered. Guest state is corrupt so kill the
1990 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1992 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1998 * On an #MC intercept the MCE handler is not called automatically in
1999 * the host. So do it by hand here.
2001 kvm_machine_check();
2004 static int mc_interception(struct vcpu_svm *svm)
2009 static int shutdown_interception(struct vcpu_svm *svm)
2011 struct kvm_run *kvm_run = svm->vcpu.run;
2014 * VMCB is undefined after a SHUTDOWN intercept
2015 * so reinitialize it.
2017 clear_page(svm->vmcb);
2020 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2024 static int io_interception(struct vcpu_svm *svm)
2026 struct kvm_vcpu *vcpu = &svm->vcpu;
2027 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2028 int size, in, string;
2031 ++svm->vcpu.stat.io_exits;
2032 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2033 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2035 return kvm_emulate_instruction(vcpu, 0);
2037 port = io_info >> 16;
2038 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2039 svm->next_rip = svm->vmcb->control.exit_info_2;
2041 return kvm_fast_pio(&svm->vcpu, size, port, in);
2044 static int nmi_interception(struct vcpu_svm *svm)
2049 static int intr_interception(struct vcpu_svm *svm)
2051 ++svm->vcpu.stat.irq_exits;
2055 static int nop_on_interception(struct vcpu_svm *svm)
2060 static int halt_interception(struct vcpu_svm *svm)
2062 return kvm_emulate_halt(&svm->vcpu);
2065 static int vmmcall_interception(struct vcpu_svm *svm)
2067 return kvm_emulate_hypercall(&svm->vcpu);
2070 static int vmload_interception(struct vcpu_svm *svm)
2072 struct vmcb *nested_vmcb;
2073 struct kvm_host_map map;
2076 if (nested_svm_check_permissions(svm))
2079 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2082 kvm_inject_gp(&svm->vcpu, 0);
2086 nested_vmcb = map.hva;
2088 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2090 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2091 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2096 static int vmsave_interception(struct vcpu_svm *svm)
2098 struct vmcb *nested_vmcb;
2099 struct kvm_host_map map;
2102 if (nested_svm_check_permissions(svm))
2105 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2108 kvm_inject_gp(&svm->vcpu, 0);
2112 nested_vmcb = map.hva;
2114 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2116 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2117 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2122 static int vmrun_interception(struct vcpu_svm *svm)
2124 if (nested_svm_check_permissions(svm))
2127 return nested_svm_vmrun(svm);
2130 void svm_set_gif(struct vcpu_svm *svm, bool value)
2134 * If VGIF is enabled, the STGI intercept is only added to
2135 * detect the opening of the SMI/NMI window; remove it now.
2136 * Likewise, clear the VINTR intercept, we will set it
2137 * again while processing KVM_REQ_EVENT if needed.
2139 if (vgif_enabled(svm))
2140 svm_clr_intercept(svm, INTERCEPT_STGI);
2141 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2142 svm_clear_vintr(svm);
2145 if (svm->vcpu.arch.smi_pending ||
2146 svm->vcpu.arch.nmi_pending ||
2147 kvm_cpu_has_injectable_intr(&svm->vcpu))
2148 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2153 * After a CLGI no interrupts should come. But if vGIF is
2154 * in use, we still rely on the VINTR intercept (rather than
2155 * STGI) to detect an open interrupt window.
2157 if (!vgif_enabled(svm))
2158 svm_clear_vintr(svm);
2162 static int stgi_interception(struct vcpu_svm *svm)
2166 if (nested_svm_check_permissions(svm))
2169 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2170 svm_set_gif(svm, true);
2174 static int clgi_interception(struct vcpu_svm *svm)
2178 if (nested_svm_check_permissions(svm))
2181 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2182 svm_set_gif(svm, false);
2186 static int invlpga_interception(struct vcpu_svm *svm)
2188 struct kvm_vcpu *vcpu = &svm->vcpu;
2190 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2191 kvm_rax_read(&svm->vcpu));
2193 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2194 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2196 return kvm_skip_emulated_instruction(&svm->vcpu);
2199 static int skinit_interception(struct vcpu_svm *svm)
2201 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2203 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2207 static int wbinvd_interception(struct vcpu_svm *svm)
2209 return kvm_emulate_wbinvd(&svm->vcpu);
2212 static int xsetbv_interception(struct vcpu_svm *svm)
2214 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2215 u32 index = kvm_rcx_read(&svm->vcpu);
2217 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2218 return kvm_skip_emulated_instruction(&svm->vcpu);
2224 static int rdpru_interception(struct vcpu_svm *svm)
2226 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2230 static int task_switch_interception(struct vcpu_svm *svm)
2234 int int_type = svm->vmcb->control.exit_int_info &
2235 SVM_EXITINTINFO_TYPE_MASK;
2236 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2238 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2240 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2241 bool has_error_code = false;
2244 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2246 if (svm->vmcb->control.exit_info_2 &
2247 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2248 reason = TASK_SWITCH_IRET;
2249 else if (svm->vmcb->control.exit_info_2 &
2250 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2251 reason = TASK_SWITCH_JMP;
2253 reason = TASK_SWITCH_GATE;
2255 reason = TASK_SWITCH_CALL;
2257 if (reason == TASK_SWITCH_GATE) {
2259 case SVM_EXITINTINFO_TYPE_NMI:
2260 svm->vcpu.arch.nmi_injected = false;
2262 case SVM_EXITINTINFO_TYPE_EXEPT:
2263 if (svm->vmcb->control.exit_info_2 &
2264 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2265 has_error_code = true;
2267 (u32)svm->vmcb->control.exit_info_2;
2269 kvm_clear_exception_queue(&svm->vcpu);
2271 case SVM_EXITINTINFO_TYPE_INTR:
2272 kvm_clear_interrupt_queue(&svm->vcpu);
2279 if (reason != TASK_SWITCH_GATE ||
2280 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2281 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2282 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2283 if (!skip_emulated_instruction(&svm->vcpu))
2287 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2290 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2291 has_error_code, error_code);
2294 static int cpuid_interception(struct vcpu_svm *svm)
2296 return kvm_emulate_cpuid(&svm->vcpu);
2299 static int iret_interception(struct vcpu_svm *svm)
2301 ++svm->vcpu.stat.nmi_window_exits;
2302 svm_clr_intercept(svm, INTERCEPT_IRET);
2303 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2304 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2305 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2309 static int invd_interception(struct vcpu_svm *svm)
2311 /* Treat an INVD instruction as a NOP and just skip it. */
2312 return kvm_skip_emulated_instruction(&svm->vcpu);
2315 static int invlpg_interception(struct vcpu_svm *svm)
2317 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2318 return kvm_emulate_instruction(&svm->vcpu, 0);
2320 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2321 return kvm_skip_emulated_instruction(&svm->vcpu);
2324 static int emulate_on_interception(struct vcpu_svm *svm)
2326 return kvm_emulate_instruction(&svm->vcpu, 0);
2329 static int rsm_interception(struct vcpu_svm *svm)
2331 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2334 static int rdpmc_interception(struct vcpu_svm *svm)
2339 return emulate_on_interception(svm);
2341 err = kvm_rdpmc(&svm->vcpu);
2342 return kvm_complete_insn_gp(&svm->vcpu, err);
2345 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2348 unsigned long cr0 = svm->vcpu.arch.cr0;
2351 if (!is_guest_mode(&svm->vcpu) ||
2352 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2355 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2356 val &= ~SVM_CR0_SELECTIVE_MASK;
2359 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2360 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2366 #define CR_VALID (1ULL << 63)
2368 static int cr_interception(struct vcpu_svm *svm)
2374 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2375 return emulate_on_interception(svm);
2377 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2378 return emulate_on_interception(svm);
2380 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2381 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2382 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2384 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2387 if (cr >= 16) { /* mov to cr */
2389 val = kvm_register_read(&svm->vcpu, reg);
2390 trace_kvm_cr_write(cr, val);
2393 if (!check_selective_cr0_intercepted(svm, val))
2394 err = kvm_set_cr0(&svm->vcpu, val);
2400 err = kvm_set_cr3(&svm->vcpu, val);
2403 err = kvm_set_cr4(&svm->vcpu, val);
2406 err = kvm_set_cr8(&svm->vcpu, val);
2409 WARN(1, "unhandled write to CR%d", cr);
2410 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2413 } else { /* mov from cr */
2416 val = kvm_read_cr0(&svm->vcpu);
2419 val = svm->vcpu.arch.cr2;
2422 val = kvm_read_cr3(&svm->vcpu);
2425 val = kvm_read_cr4(&svm->vcpu);
2428 val = kvm_get_cr8(&svm->vcpu);
2431 WARN(1, "unhandled read from CR%d", cr);
2432 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2435 kvm_register_write(&svm->vcpu, reg, val);
2436 trace_kvm_cr_read(cr, val);
2438 return kvm_complete_insn_gp(&svm->vcpu, err);
2441 static int dr_interception(struct vcpu_svm *svm)
2446 if (svm->vcpu.guest_debug == 0) {
2448 * No more DR vmexits; force a reload of the debug registers
2449 * and reenter on this instruction. The next vmexit will
2450 * retrieve the full state of the debug registers.
2452 clr_dr_intercepts(svm);
2453 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2457 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2458 return emulate_on_interception(svm);
2460 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2461 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2463 if (dr >= 16) { /* mov to DRn */
2464 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2466 val = kvm_register_read(&svm->vcpu, reg);
2467 kvm_set_dr(&svm->vcpu, dr - 16, val);
2469 if (!kvm_require_dr(&svm->vcpu, dr))
2471 kvm_get_dr(&svm->vcpu, dr, &val);
2472 kvm_register_write(&svm->vcpu, reg, val);
2475 return kvm_skip_emulated_instruction(&svm->vcpu);
2478 static int cr8_write_interception(struct vcpu_svm *svm)
2480 struct kvm_run *kvm_run = svm->vcpu.run;
2483 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2484 /* instruction emulation calls kvm_set_cr8() */
2485 r = cr_interception(svm);
2486 if (lapic_in_kernel(&svm->vcpu))
2488 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2490 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2494 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2498 switch (msr->index) {
2499 case MSR_F10H_DECFG:
2500 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2501 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2503 case MSR_IA32_PERF_CAPABILITIES:
2506 return KVM_MSR_RET_INVALID;
2512 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2514 struct vcpu_svm *svm = to_svm(vcpu);
2516 switch (msr_info->index) {
2518 msr_info->data = svm->vmcb->save.star;
2520 #ifdef CONFIG_X86_64
2522 msr_info->data = svm->vmcb->save.lstar;
2525 msr_info->data = svm->vmcb->save.cstar;
2527 case MSR_KERNEL_GS_BASE:
2528 msr_info->data = svm->vmcb->save.kernel_gs_base;
2530 case MSR_SYSCALL_MASK:
2531 msr_info->data = svm->vmcb->save.sfmask;
2534 case MSR_IA32_SYSENTER_CS:
2535 msr_info->data = svm->vmcb->save.sysenter_cs;
2537 case MSR_IA32_SYSENTER_EIP:
2538 msr_info->data = svm->sysenter_eip;
2540 case MSR_IA32_SYSENTER_ESP:
2541 msr_info->data = svm->sysenter_esp;
2544 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2546 msr_info->data = svm->tsc_aux;
2549 * Nobody will change the following 5 values in the VMCB so we can
2550 * safely return them on rdmsr. They will always be 0 until LBRV is
2553 case MSR_IA32_DEBUGCTLMSR:
2554 msr_info->data = svm->vmcb->save.dbgctl;
2556 case MSR_IA32_LASTBRANCHFROMIP:
2557 msr_info->data = svm->vmcb->save.br_from;
2559 case MSR_IA32_LASTBRANCHTOIP:
2560 msr_info->data = svm->vmcb->save.br_to;
2562 case MSR_IA32_LASTINTFROMIP:
2563 msr_info->data = svm->vmcb->save.last_excp_from;
2565 case MSR_IA32_LASTINTTOIP:
2566 msr_info->data = svm->vmcb->save.last_excp_to;
2568 case MSR_VM_HSAVE_PA:
2569 msr_info->data = svm->nested.hsave_msr;
2572 msr_info->data = svm->nested.vm_cr_msr;
2574 case MSR_IA32_SPEC_CTRL:
2575 if (!msr_info->host_initiated &&
2576 !guest_has_spec_ctrl_msr(vcpu))
2579 msr_info->data = svm->spec_ctrl;
2581 case MSR_AMD64_VIRT_SPEC_CTRL:
2582 if (!msr_info->host_initiated &&
2583 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2586 msr_info->data = svm->virt_spec_ctrl;
2588 case MSR_F15H_IC_CFG: {
2592 family = guest_cpuid_family(vcpu);
2593 model = guest_cpuid_model(vcpu);
2595 if (family < 0 || model < 0)
2596 return kvm_get_msr_common(vcpu, msr_info);
2600 if (family == 0x15 &&
2601 (model >= 0x2 && model < 0x20))
2602 msr_info->data = 0x1E;
2605 case MSR_F10H_DECFG:
2606 msr_info->data = svm->msr_decfg;
2609 return kvm_get_msr_common(vcpu, msr_info);
2614 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2616 struct vcpu_svm *svm = to_svm(vcpu);
2617 if (!sev_es_guest(svm->vcpu.kvm) || !err)
2618 return kvm_complete_insn_gp(&svm->vcpu, err);
2620 ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2621 ghcb_set_sw_exit_info_2(svm->ghcb,
2623 SVM_EVTINJ_TYPE_EXEPT |
2628 static int rdmsr_interception(struct vcpu_svm *svm)
2630 return kvm_emulate_rdmsr(&svm->vcpu);
2633 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2635 struct vcpu_svm *svm = to_svm(vcpu);
2636 int svm_dis, chg_mask;
2638 if (data & ~SVM_VM_CR_VALID_MASK)
2641 chg_mask = SVM_VM_CR_VALID_MASK;
2643 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2644 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2646 svm->nested.vm_cr_msr &= ~chg_mask;
2647 svm->nested.vm_cr_msr |= (data & chg_mask);
2649 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2651 /* check for svm_disable while efer.svme is set */
2652 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2658 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2660 struct vcpu_svm *svm = to_svm(vcpu);
2662 u32 ecx = msr->index;
2663 u64 data = msr->data;
2665 case MSR_IA32_CR_PAT:
2666 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2668 vcpu->arch.pat = data;
2669 svm->vmcb->save.g_pat = data;
2670 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2672 case MSR_IA32_SPEC_CTRL:
2673 if (!msr->host_initiated &&
2674 !guest_has_spec_ctrl_msr(vcpu))
2677 if (kvm_spec_ctrl_test_value(data))
2680 svm->spec_ctrl = data;
2686 * When it's written (to non-zero) for the first time, pass
2690 * The handling of the MSR bitmap for L2 guests is done in
2691 * nested_svm_vmrun_msrpm.
2692 * We update the L1 MSR bit as well since it will end up
2693 * touching the MSR anyway now.
2695 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2697 case MSR_IA32_PRED_CMD:
2698 if (!msr->host_initiated &&
2699 !guest_has_pred_cmd_msr(vcpu))
2702 if (data & ~PRED_CMD_IBPB)
2704 if (!boot_cpu_has(X86_FEATURE_IBPB))
2709 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2710 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2712 case MSR_AMD64_VIRT_SPEC_CTRL:
2713 if (!msr->host_initiated &&
2714 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2717 if (data & ~SPEC_CTRL_SSBD)
2720 svm->virt_spec_ctrl = data;
2723 svm->vmcb->save.star = data;
2725 #ifdef CONFIG_X86_64
2727 svm->vmcb->save.lstar = data;
2730 svm->vmcb->save.cstar = data;
2732 case MSR_KERNEL_GS_BASE:
2733 svm->vmcb->save.kernel_gs_base = data;
2735 case MSR_SYSCALL_MASK:
2736 svm->vmcb->save.sfmask = data;
2739 case MSR_IA32_SYSENTER_CS:
2740 svm->vmcb->save.sysenter_cs = data;
2742 case MSR_IA32_SYSENTER_EIP:
2743 svm->sysenter_eip = data;
2744 svm->vmcb->save.sysenter_eip = data;
2746 case MSR_IA32_SYSENTER_ESP:
2747 svm->sysenter_esp = data;
2748 svm->vmcb->save.sysenter_esp = data;
2751 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2755 * This is rare, so we update the MSR here instead of using
2756 * direct_access_msrs. Doing that would require a rdmsr in
2759 svm->tsc_aux = data;
2760 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2762 case MSR_IA32_DEBUGCTLMSR:
2763 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2764 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2768 if (data & DEBUGCTL_RESERVED_BITS)
2771 svm->vmcb->save.dbgctl = data;
2772 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2773 if (data & (1ULL<<0))
2774 svm_enable_lbrv(vcpu);
2776 svm_disable_lbrv(vcpu);
2778 case MSR_VM_HSAVE_PA:
2779 svm->nested.hsave_msr = data;
2782 return svm_set_vm_cr(vcpu, data);
2784 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2786 case MSR_F10H_DECFG: {
2787 struct kvm_msr_entry msr_entry;
2789 msr_entry.index = msr->index;
2790 if (svm_get_msr_feature(&msr_entry))
2793 /* Check the supported bits */
2794 if (data & ~msr_entry.data)
2797 /* Don't allow the guest to change a bit, #GP */
2798 if (!msr->host_initiated && (data ^ msr_entry.data))
2801 svm->msr_decfg = data;
2804 case MSR_IA32_APICBASE:
2805 if (kvm_vcpu_apicv_active(vcpu))
2806 avic_update_vapic_bar(to_svm(vcpu), data);
2809 return kvm_set_msr_common(vcpu, msr);
2814 static int wrmsr_interception(struct vcpu_svm *svm)
2816 return kvm_emulate_wrmsr(&svm->vcpu);
2819 static int msr_interception(struct vcpu_svm *svm)
2821 if (svm->vmcb->control.exit_info_1)
2822 return wrmsr_interception(svm);
2824 return rdmsr_interception(svm);
2827 static int interrupt_window_interception(struct vcpu_svm *svm)
2829 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2830 svm_clear_vintr(svm);
2833 * For AVIC, the only reason to end up here is ExtINTs.
2834 * In this case AVIC was temporarily disabled for
2835 * requesting the IRQ window and we have to re-enable it.
2837 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2839 ++svm->vcpu.stat.irq_window_exits;
2843 static int pause_interception(struct vcpu_svm *svm)
2845 struct kvm_vcpu *vcpu = &svm->vcpu;
2849 * CPL is not made available for an SEV-ES guest, therefore
2850 * vcpu->arch.preempted_in_kernel can never be true. Just
2851 * set in_kernel to false as well.
2853 in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
2855 if (!kvm_pause_in_guest(vcpu->kvm))
2856 grow_ple_window(vcpu);
2858 kvm_vcpu_on_spin(vcpu, in_kernel);
2862 static int nop_interception(struct vcpu_svm *svm)
2864 return kvm_skip_emulated_instruction(&(svm->vcpu));
2867 static int monitor_interception(struct vcpu_svm *svm)
2869 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2870 return nop_interception(svm);
2873 static int mwait_interception(struct vcpu_svm *svm)
2875 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2876 return nop_interception(svm);
2879 static int invpcid_interception(struct vcpu_svm *svm)
2881 struct kvm_vcpu *vcpu = &svm->vcpu;
2885 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2886 kvm_queue_exception(vcpu, UD_VECTOR);
2891 * For an INVPCID intercept:
2892 * EXITINFO1 provides the linear address of the memory operand.
2893 * EXITINFO2 provides the contents of the register operand.
2895 type = svm->vmcb->control.exit_info_2;
2896 gva = svm->vmcb->control.exit_info_1;
2899 kvm_inject_gp(vcpu, 0);
2903 return kvm_handle_invpcid(vcpu, type, gva);
2906 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2907 [SVM_EXIT_READ_CR0] = cr_interception,
2908 [SVM_EXIT_READ_CR3] = cr_interception,
2909 [SVM_EXIT_READ_CR4] = cr_interception,
2910 [SVM_EXIT_READ_CR8] = cr_interception,
2911 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
2912 [SVM_EXIT_WRITE_CR0] = cr_interception,
2913 [SVM_EXIT_WRITE_CR3] = cr_interception,
2914 [SVM_EXIT_WRITE_CR4] = cr_interception,
2915 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2916 [SVM_EXIT_READ_DR0] = dr_interception,
2917 [SVM_EXIT_READ_DR1] = dr_interception,
2918 [SVM_EXIT_READ_DR2] = dr_interception,
2919 [SVM_EXIT_READ_DR3] = dr_interception,
2920 [SVM_EXIT_READ_DR4] = dr_interception,
2921 [SVM_EXIT_READ_DR5] = dr_interception,
2922 [SVM_EXIT_READ_DR6] = dr_interception,
2923 [SVM_EXIT_READ_DR7] = dr_interception,
2924 [SVM_EXIT_WRITE_DR0] = dr_interception,
2925 [SVM_EXIT_WRITE_DR1] = dr_interception,
2926 [SVM_EXIT_WRITE_DR2] = dr_interception,
2927 [SVM_EXIT_WRITE_DR3] = dr_interception,
2928 [SVM_EXIT_WRITE_DR4] = dr_interception,
2929 [SVM_EXIT_WRITE_DR5] = dr_interception,
2930 [SVM_EXIT_WRITE_DR6] = dr_interception,
2931 [SVM_EXIT_WRITE_DR7] = dr_interception,
2932 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2933 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2934 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2935 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2936 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2937 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
2938 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
2939 [SVM_EXIT_INTR] = intr_interception,
2940 [SVM_EXIT_NMI] = nmi_interception,
2941 [SVM_EXIT_SMI] = nop_on_interception,
2942 [SVM_EXIT_INIT] = nop_on_interception,
2943 [SVM_EXIT_VINTR] = interrupt_window_interception,
2944 [SVM_EXIT_RDPMC] = rdpmc_interception,
2945 [SVM_EXIT_CPUID] = cpuid_interception,
2946 [SVM_EXIT_IRET] = iret_interception,
2947 [SVM_EXIT_INVD] = invd_interception,
2948 [SVM_EXIT_PAUSE] = pause_interception,
2949 [SVM_EXIT_HLT] = halt_interception,
2950 [SVM_EXIT_INVLPG] = invlpg_interception,
2951 [SVM_EXIT_INVLPGA] = invlpga_interception,
2952 [SVM_EXIT_IOIO] = io_interception,
2953 [SVM_EXIT_MSR] = msr_interception,
2954 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2955 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2956 [SVM_EXIT_VMRUN] = vmrun_interception,
2957 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2958 [SVM_EXIT_VMLOAD] = vmload_interception,
2959 [SVM_EXIT_VMSAVE] = vmsave_interception,
2960 [SVM_EXIT_STGI] = stgi_interception,
2961 [SVM_EXIT_CLGI] = clgi_interception,
2962 [SVM_EXIT_SKINIT] = skinit_interception,
2963 [SVM_EXIT_WBINVD] = wbinvd_interception,
2964 [SVM_EXIT_MONITOR] = monitor_interception,
2965 [SVM_EXIT_MWAIT] = mwait_interception,
2966 [SVM_EXIT_XSETBV] = xsetbv_interception,
2967 [SVM_EXIT_RDPRU] = rdpru_interception,
2968 [SVM_EXIT_INVPCID] = invpcid_interception,
2969 [SVM_EXIT_NPF] = npf_interception,
2970 [SVM_EXIT_RSM] = rsm_interception,
2971 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2972 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
2975 static void dump_vmcb(struct kvm_vcpu *vcpu)
2977 struct vcpu_svm *svm = to_svm(vcpu);
2978 struct vmcb_control_area *control = &svm->vmcb->control;
2979 struct vmcb_save_area *save = &svm->vmcb->save;
2981 if (!dump_invalid_vmcb) {
2982 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2986 pr_err("VMCB Control Area:\n");
2987 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2988 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
2989 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2990 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
2991 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
2992 pr_err("%-20s%08x %08x\n", "intercepts:",
2993 control->intercepts[INTERCEPT_WORD3],
2994 control->intercepts[INTERCEPT_WORD4]);
2995 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2996 pr_err("%-20s%d\n", "pause filter threshold:",
2997 control->pause_filter_thresh);
2998 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2999 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3000 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3001 pr_err("%-20s%d\n", "asid:", control->asid);
3002 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3003 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3004 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3005 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3006 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3007 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3008 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3009 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3010 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3011 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3012 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3013 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3014 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3015 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3016 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3017 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3018 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3019 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3020 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3021 pr_err("VMCB State Save Area:\n");
3022 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3024 save->es.selector, save->es.attrib,
3025 save->es.limit, save->es.base);
3026 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3028 save->cs.selector, save->cs.attrib,
3029 save->cs.limit, save->cs.base);
3030 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3032 save->ss.selector, save->ss.attrib,
3033 save->ss.limit, save->ss.base);
3034 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3036 save->ds.selector, save->ds.attrib,
3037 save->ds.limit, save->ds.base);
3038 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3040 save->fs.selector, save->fs.attrib,
3041 save->fs.limit, save->fs.base);
3042 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3044 save->gs.selector, save->gs.attrib,
3045 save->gs.limit, save->gs.base);
3046 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3048 save->gdtr.selector, save->gdtr.attrib,
3049 save->gdtr.limit, save->gdtr.base);
3050 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3052 save->ldtr.selector, save->ldtr.attrib,
3053 save->ldtr.limit, save->ldtr.base);
3054 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3056 save->idtr.selector, save->idtr.attrib,
3057 save->idtr.limit, save->idtr.base);
3058 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3060 save->tr.selector, save->tr.attrib,
3061 save->tr.limit, save->tr.base);
3062 pr_err("cpl: %d efer: %016llx\n",
3063 save->cpl, save->efer);
3064 pr_err("%-15s %016llx %-13s %016llx\n",
3065 "cr0:", save->cr0, "cr2:", save->cr2);
3066 pr_err("%-15s %016llx %-13s %016llx\n",
3067 "cr3:", save->cr3, "cr4:", save->cr4);
3068 pr_err("%-15s %016llx %-13s %016llx\n",
3069 "dr6:", save->dr6, "dr7:", save->dr7);
3070 pr_err("%-15s %016llx %-13s %016llx\n",
3071 "rip:", save->rip, "rflags:", save->rflags);
3072 pr_err("%-15s %016llx %-13s %016llx\n",
3073 "rsp:", save->rsp, "rax:", save->rax);
3074 pr_err("%-15s %016llx %-13s %016llx\n",
3075 "star:", save->star, "lstar:", save->lstar);
3076 pr_err("%-15s %016llx %-13s %016llx\n",
3077 "cstar:", save->cstar, "sfmask:", save->sfmask);
3078 pr_err("%-15s %016llx %-13s %016llx\n",
3079 "kernel_gs_base:", save->kernel_gs_base,
3080 "sysenter_cs:", save->sysenter_cs);
3081 pr_err("%-15s %016llx %-13s %016llx\n",
3082 "sysenter_esp:", save->sysenter_esp,
3083 "sysenter_eip:", save->sysenter_eip);
3084 pr_err("%-15s %016llx %-13s %016llx\n",
3085 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3086 pr_err("%-15s %016llx %-13s %016llx\n",
3087 "br_from:", save->br_from, "br_to:", save->br_to);
3088 pr_err("%-15s %016llx %-13s %016llx\n",
3089 "excp_from:", save->last_excp_from,
3090 "excp_to:", save->last_excp_to);
3093 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3094 u32 *intr_info, u32 *error_code)
3096 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3098 *info1 = control->exit_info_1;
3099 *info2 = control->exit_info_2;
3100 *intr_info = control->exit_int_info;
3101 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3102 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3103 *error_code = control->exit_int_info_err;
3108 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3110 struct vcpu_svm *svm = to_svm(vcpu);
3111 struct kvm_run *kvm_run = vcpu->run;
3112 u32 exit_code = svm->vmcb->control.exit_code;
3114 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3116 /* SEV-ES guests must use the CR write traps to track CR registers. */
3117 if (!sev_es_guest(vcpu->kvm)) {
3118 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3119 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3121 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3124 if (is_guest_mode(vcpu)) {
3127 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3129 vmexit = nested_svm_exit_special(svm);
3131 if (vmexit == NESTED_EXIT_CONTINUE)
3132 vmexit = nested_svm_exit_handled(svm);
3134 if (vmexit == NESTED_EXIT_DONE)
3138 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3139 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3140 kvm_run->fail_entry.hardware_entry_failure_reason
3141 = svm->vmcb->control.exit_code;
3142 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3147 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3148 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3149 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3150 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3151 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3153 __func__, svm->vmcb->control.exit_int_info,
3156 if (exit_fastpath != EXIT_FASTPATH_NONE)
3159 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3160 || !svm_exit_handlers[exit_code]) {
3161 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
3163 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3164 vcpu->run->internal.suberror =
3165 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3166 vcpu->run->internal.ndata = 2;
3167 vcpu->run->internal.data[0] = exit_code;
3168 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3172 #ifdef CONFIG_RETPOLINE
3173 if (exit_code == SVM_EXIT_MSR)
3174 return msr_interception(svm);
3175 else if (exit_code == SVM_EXIT_VINTR)
3176 return interrupt_window_interception(svm);
3177 else if (exit_code == SVM_EXIT_INTR)
3178 return intr_interception(svm);
3179 else if (exit_code == SVM_EXIT_HLT)
3180 return halt_interception(svm);
3181 else if (exit_code == SVM_EXIT_NPF)
3182 return npf_interception(svm);
3184 return svm_exit_handlers[exit_code](svm);
3187 static void reload_tss(struct kvm_vcpu *vcpu)
3189 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3191 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3195 static void pre_svm_run(struct vcpu_svm *svm)
3197 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3199 if (sev_guest(svm->vcpu.kvm))
3200 return pre_sev_run(svm, svm->vcpu.cpu);
3202 /* FIXME: handle wraparound of asid_generation */
3203 if (svm->asid_generation != sd->asid_generation)
3207 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3209 struct vcpu_svm *svm = to_svm(vcpu);
3211 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3212 vcpu->arch.hflags |= HF_NMI_MASK;
3213 svm_set_intercept(svm, INTERCEPT_IRET);
3214 ++vcpu->stat.nmi_injections;
3217 static void svm_set_irq(struct kvm_vcpu *vcpu)
3219 struct vcpu_svm *svm = to_svm(vcpu);
3221 BUG_ON(!(gif_set(svm)));
3223 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3224 ++vcpu->stat.irq_injections;
3226 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3227 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3230 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3232 struct vcpu_svm *svm = to_svm(vcpu);
3235 * SEV-ES guests must always keep the CR intercepts cleared. CR
3236 * tracking is done using the CR write traps.
3238 if (sev_es_guest(vcpu->kvm))
3241 if (nested_svm_virtualize_tpr(vcpu))
3244 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3250 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3253 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3255 struct vcpu_svm *svm = to_svm(vcpu);
3256 struct vmcb *vmcb = svm->vmcb;
3262 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3265 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3266 (svm->vcpu.arch.hflags & HF_NMI_MASK);
3271 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3273 struct vcpu_svm *svm = to_svm(vcpu);
3274 if (svm->nested.nested_run_pending)
3277 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3278 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3281 return !svm_nmi_blocked(vcpu);
3284 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3286 struct vcpu_svm *svm = to_svm(vcpu);
3288 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3291 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3293 struct vcpu_svm *svm = to_svm(vcpu);
3296 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3297 svm_set_intercept(svm, INTERCEPT_IRET);
3299 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3300 svm_clr_intercept(svm, INTERCEPT_IRET);
3304 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3306 struct vcpu_svm *svm = to_svm(vcpu);
3307 struct vmcb *vmcb = svm->vmcb;
3312 if (sev_es_guest(svm->vcpu.kvm)) {
3314 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3315 * bit to determine the state of the IF flag.
3317 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3319 } else if (is_guest_mode(vcpu)) {
3320 /* As long as interrupts are being delivered... */
3321 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3322 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3323 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3326 /* ... vmexits aren't blocked by the interrupt shadow */
3327 if (nested_exit_on_intr(svm))
3330 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3334 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3337 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3339 struct vcpu_svm *svm = to_svm(vcpu);
3340 if (svm->nested.nested_run_pending)
3344 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3345 * e.g. if the IRQ arrived asynchronously after checking nested events.
3347 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3350 return !svm_interrupt_blocked(vcpu);
3353 static void enable_irq_window(struct kvm_vcpu *vcpu)
3355 struct vcpu_svm *svm = to_svm(vcpu);
3358 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3359 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3360 * get that intercept, this function will be called again though and
3361 * we'll get the vintr intercept. However, if the vGIF feature is
3362 * enabled, the STGI interception will not occur. Enable the irq
3363 * window under the assumption that the hardware will set the GIF.
3365 if (vgif_enabled(svm) || gif_set(svm)) {
3367 * IRQ window is not needed when AVIC is enabled,
3368 * unless we have pending ExtINT since it cannot be injected
3369 * via AVIC. In such case, we need to temporarily disable AVIC,
3370 * and fallback to injecting IRQ via V_IRQ.
3372 svm_toggle_avic_for_irq_window(vcpu, false);
3377 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3379 struct vcpu_svm *svm = to_svm(vcpu);
3381 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3383 return; /* IRET will cause a vm exit */
3385 if (!gif_set(svm)) {
3386 if (vgif_enabled(svm))
3387 svm_set_intercept(svm, INTERCEPT_STGI);
3388 return; /* STGI will cause a vm exit */
3392 * Something prevents NMI from been injected. Single step over possible
3393 * problem (IRET or exception injection or interrupt shadow)
3395 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3396 svm->nmi_singlestep = true;
3397 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3400 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3405 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3410 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3412 struct vcpu_svm *svm = to_svm(vcpu);
3415 * Flush only the current ASID even if the TLB flush was invoked via
3416 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3417 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3418 * unconditionally does a TLB flush on both nested VM-Enter and nested
3419 * VM-Exit (via kvm_mmu_reset_context()).
3421 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3422 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3424 svm->asid_generation--;
3427 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3429 struct vcpu_svm *svm = to_svm(vcpu);
3431 invlpga(gva, svm->vmcb->control.asid);
3434 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3438 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3440 struct vcpu_svm *svm = to_svm(vcpu);
3442 if (nested_svm_virtualize_tpr(vcpu))
3445 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3446 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3447 kvm_set_cr8(vcpu, cr8);
3451 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3453 struct vcpu_svm *svm = to_svm(vcpu);
3456 if (nested_svm_virtualize_tpr(vcpu) ||
3457 kvm_vcpu_apicv_active(vcpu))
3460 cr8 = kvm_get_cr8(vcpu);
3461 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3462 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3465 static void svm_complete_interrupts(struct vcpu_svm *svm)
3469 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3470 unsigned int3_injected = svm->int3_injected;
3472 svm->int3_injected = 0;
3475 * If we've made progress since setting HF_IRET_MASK, we've
3476 * executed an IRET and can allow NMI injection.
3478 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3479 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3480 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3481 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3484 svm->vcpu.arch.nmi_injected = false;
3485 kvm_clear_exception_queue(&svm->vcpu);
3486 kvm_clear_interrupt_queue(&svm->vcpu);
3488 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3491 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3493 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3494 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3497 case SVM_EXITINTINFO_TYPE_NMI:
3498 svm->vcpu.arch.nmi_injected = true;
3500 case SVM_EXITINTINFO_TYPE_EXEPT:
3502 * Never re-inject a #VC exception.
3504 if (vector == X86_TRAP_VC)
3508 * In case of software exceptions, do not reinject the vector,
3509 * but re-execute the instruction instead. Rewind RIP first
3510 * if we emulated INT3 before.
3512 if (kvm_exception_is_soft(vector)) {
3513 if (vector == BP_VECTOR && int3_injected &&
3514 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3515 kvm_rip_write(&svm->vcpu,
3516 kvm_rip_read(&svm->vcpu) -
3520 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3521 u32 err = svm->vmcb->control.exit_int_info_err;
3522 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3525 kvm_requeue_exception(&svm->vcpu, vector);
3527 case SVM_EXITINTINFO_TYPE_INTR:
3528 kvm_queue_interrupt(&svm->vcpu, vector, false);
3535 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3537 struct vcpu_svm *svm = to_svm(vcpu);
3538 struct vmcb_control_area *control = &svm->vmcb->control;
3540 control->exit_int_info = control->event_inj;
3541 control->exit_int_info_err = control->event_inj_err;
3542 control->event_inj = 0;
3543 svm_complete_interrupts(svm);
3546 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3548 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3549 to_svm(vcpu)->vmcb->control.exit_info_1)
3550 return handle_fastpath_set_msr_irqoff(vcpu);
3552 return EXIT_FASTPATH_NONE;
3555 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3557 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3558 struct vcpu_svm *svm)
3561 * VMENTER enables interrupts (host state), but the kernel state is
3562 * interrupts disabled when this is invoked. Also tell RCU about
3563 * it. This is the same logic as for exit_to_user_mode().
3565 * This ensures that e.g. latency analysis on the host observes
3566 * guest mode as interrupt enabled.
3568 * guest_enter_irqoff() informs context tracking about the
3569 * transition to guest mode and if enabled adjusts RCU state
3572 instrumentation_begin();
3573 trace_hardirqs_on_prepare();
3574 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3575 instrumentation_end();
3577 guest_enter_irqoff();
3578 lockdep_hardirqs_on(CALLER_ADDR0);
3580 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3582 #ifdef CONFIG_X86_64
3583 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3585 loadsegment(fs, svm->host.fs);
3586 #ifndef CONFIG_X86_32_LAZY_GS
3587 loadsegment(gs, svm->host.gs);
3592 * VMEXIT disables interrupts (host state), but tracing and lockdep
3593 * have them in state 'on' as recorded before entering guest mode.
3594 * Same as enter_from_user_mode().
3596 * guest_exit_irqoff() restores host context and reinstates RCU if
3597 * enabled and required.
3599 * This needs to be done before the below as native_read_msr()
3600 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3601 * into world and some more.
3603 lockdep_hardirqs_off(CALLER_ADDR0);
3604 guest_exit_irqoff();
3606 instrumentation_begin();
3607 trace_hardirqs_off_finish();
3608 instrumentation_end();
3611 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3613 struct vcpu_svm *svm = to_svm(vcpu);
3615 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3616 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3617 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3620 * Disable singlestep if we're injecting an interrupt/exception.
3621 * We don't want our modified rflags to be pushed on the stack where
3622 * we might not be able to easily reset them if we disabled NMI
3625 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3627 * Event injection happens before external interrupts cause a
3628 * vmexit and interrupts are disabled here, so smp_send_reschedule
3629 * is enough to force an immediate vmexit.
3631 disable_nmi_singlestep(svm);
3632 smp_send_reschedule(vcpu->cpu);
3637 sync_lapic_to_cr8(vcpu);
3639 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3640 svm->vmcb->control.asid = svm->asid;
3641 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3643 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3646 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3649 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3650 svm_set_dr6(svm, vcpu->arch.dr6);
3652 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3655 kvm_load_guest_xsave_state(vcpu);
3657 kvm_wait_lapic_expire(vcpu);
3660 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3661 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3662 * is no need to worry about the conditional branch over the wrmsr
3663 * being speculatively taken.
3665 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3667 svm_vcpu_enter_exit(vcpu, svm);
3670 * We do not use IBRS in the kernel. If this vCPU has used the
3671 * SPEC_CTRL MSR it may have left it on; save the value and
3672 * turn it off. This is much more efficient than blindly adding
3673 * it to the atomic save/restore list. Especially as the former
3674 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3676 * For non-nested case:
3677 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3681 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3684 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3685 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3689 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3691 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3692 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3693 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3694 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3696 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3697 kvm_before_interrupt(&svm->vcpu);
3699 kvm_load_host_xsave_state(vcpu);
3702 /* Any pending NMI will happen here */
3704 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3705 kvm_after_interrupt(&svm->vcpu);
3707 sync_cr8_to_lapic(vcpu);
3710 if (is_guest_mode(&svm->vcpu)) {
3711 sync_nested_vmcb_control(svm);
3712 svm->nested.nested_run_pending = 0;
3715 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3716 vmcb_mark_all_clean(svm->vmcb);
3718 /* if exit due to PF check for async PF */
3719 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3720 svm->vcpu.arch.apf.host_apf_flags =
3721 kvm_read_and_reset_apf_flags();
3724 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3725 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3729 * We need to handle MC intercepts here before the vcpu has a chance to
3730 * change the physical cpu
3732 if (unlikely(svm->vmcb->control.exit_code ==
3733 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3734 svm_handle_mce(svm);
3736 svm_complete_interrupts(svm);
3738 if (is_guest_mode(vcpu))
3739 return EXIT_FASTPATH_NONE;
3741 return svm_exit_handlers_fastpath(vcpu);
3744 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3747 struct vcpu_svm *svm = to_svm(vcpu);
3750 cr3 = __sme_set(root);
3752 svm->vmcb->control.nested_cr3 = cr3;
3753 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3755 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3756 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3758 cr3 = vcpu->arch.cr3;
3761 svm->vmcb->save.cr3 = cr3;
3762 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3765 static int is_disabled(void)
3769 rdmsrl(MSR_VM_CR, vm_cr);
3770 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3777 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3780 * Patch in the VMMCALL instruction:
3782 hypercall[0] = 0x0f;
3783 hypercall[1] = 0x01;
3784 hypercall[2] = 0xd9;
3787 static int __init svm_check_processor_compat(void)
3792 static bool svm_cpu_has_accelerated_tpr(void)
3797 static bool svm_has_emulated_msr(u32 index)
3800 case MSR_IA32_MCG_EXT_CTL:
3801 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3810 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3815 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3817 struct vcpu_svm *svm = to_svm(vcpu);
3818 struct kvm_cpuid_entry2 *best;
3820 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3821 boot_cpu_has(X86_FEATURE_XSAVE) &&
3822 boot_cpu_has(X86_FEATURE_XSAVES);
3824 /* Update nrips enabled cache */
3825 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3826 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3828 /* Check again if INVPCID interception if required */
3829 svm_check_invpcid(svm);
3831 /* For sev guests, the memory encryption bit is not reserved in CR3. */
3832 if (sev_guest(vcpu->kvm)) {
3833 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3835 vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3838 if (!kvm_vcpu_apicv_active(vcpu))
3842 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3843 * is exposed to the guest, disable AVIC.
3845 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3846 kvm_request_apicv_update(vcpu->kvm, false,
3847 APICV_INHIBIT_REASON_X2APIC);
3850 * Currently, AVIC does not work with nested virtualization.
3851 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3853 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3854 kvm_request_apicv_update(vcpu->kvm, false,
3855 APICV_INHIBIT_REASON_NESTED);
3858 static bool svm_has_wbinvd_exit(void)
3863 #define PRE_EX(exit) { .exit_code = (exit), \
3864 .stage = X86_ICPT_PRE_EXCEPT, }
3865 #define POST_EX(exit) { .exit_code = (exit), \
3866 .stage = X86_ICPT_POST_EXCEPT, }
3867 #define POST_MEM(exit) { .exit_code = (exit), \
3868 .stage = X86_ICPT_POST_MEMACCESS, }
3870 static const struct __x86_intercept {
3872 enum x86_intercept_stage stage;
3873 } x86_intercept_map[] = {
3874 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3875 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3876 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3877 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3878 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3879 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3880 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
3881 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3882 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3883 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3884 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3885 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3886 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3887 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3888 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
3889 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3890 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3891 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3892 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3893 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3894 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3895 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3896 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
3897 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3898 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3899 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
3900 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3901 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3902 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3903 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3904 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3905 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3906 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3907 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3908 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
3909 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3910 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3911 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3912 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3913 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3914 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3915 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
3916 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3917 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3918 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3919 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
3920 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
3927 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3928 struct x86_instruction_info *info,
3929 enum x86_intercept_stage stage,
3930 struct x86_exception *exception)
3932 struct vcpu_svm *svm = to_svm(vcpu);
3933 int vmexit, ret = X86EMUL_CONTINUE;
3934 struct __x86_intercept icpt_info;
3935 struct vmcb *vmcb = svm->vmcb;
3937 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3940 icpt_info = x86_intercept_map[info->intercept];
3942 if (stage != icpt_info.stage)
3945 switch (icpt_info.exit_code) {
3946 case SVM_EXIT_READ_CR0:
3947 if (info->intercept == x86_intercept_cr_read)
3948 icpt_info.exit_code += info->modrm_reg;
3950 case SVM_EXIT_WRITE_CR0: {
3951 unsigned long cr0, val;
3953 if (info->intercept == x86_intercept_cr_write)
3954 icpt_info.exit_code += info->modrm_reg;
3956 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3957 info->intercept == x86_intercept_clts)
3960 if (!(vmcb_is_intercept(&svm->nested.ctl,
3961 INTERCEPT_SELECTIVE_CR0)))
3964 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3965 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3967 if (info->intercept == x86_intercept_lmsw) {
3970 /* lmsw can't clear PE - catch this here */
3971 if (cr0 & X86_CR0_PE)
3976 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3980 case SVM_EXIT_READ_DR0:
3981 case SVM_EXIT_WRITE_DR0:
3982 icpt_info.exit_code += info->modrm_reg;
3985 if (info->intercept == x86_intercept_wrmsr)
3986 vmcb->control.exit_info_1 = 1;
3988 vmcb->control.exit_info_1 = 0;
3990 case SVM_EXIT_PAUSE:
3992 * We get this for NOP only, but pause
3993 * is rep not, check this here
3995 if (info->rep_prefix != REPE_PREFIX)
3998 case SVM_EXIT_IOIO: {
4002 if (info->intercept == x86_intercept_in ||
4003 info->intercept == x86_intercept_ins) {
4004 exit_info = ((info->src_val & 0xffff) << 16) |
4006 bytes = info->dst_bytes;
4008 exit_info = (info->dst_val & 0xffff) << 16;
4009 bytes = info->src_bytes;
4012 if (info->intercept == x86_intercept_outs ||
4013 info->intercept == x86_intercept_ins)
4014 exit_info |= SVM_IOIO_STR_MASK;
4016 if (info->rep_prefix)
4017 exit_info |= SVM_IOIO_REP_MASK;
4019 bytes = min(bytes, 4u);
4021 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4023 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4025 vmcb->control.exit_info_1 = exit_info;
4026 vmcb->control.exit_info_2 = info->next_rip;
4034 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4035 if (static_cpu_has(X86_FEATURE_NRIPS))
4036 vmcb->control.next_rip = info->next_rip;
4037 vmcb->control.exit_code = icpt_info.exit_code;
4038 vmexit = nested_svm_exit_handled(svm);
4040 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4047 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4051 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4053 if (!kvm_pause_in_guest(vcpu->kvm))
4054 shrink_ple_window(vcpu);
4057 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4059 /* [63:9] are reserved. */
4060 vcpu->arch.mcg_cap &= 0x1ff;
4063 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4065 struct vcpu_svm *svm = to_svm(vcpu);
4067 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4071 return is_smm(vcpu);
4074 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4076 struct vcpu_svm *svm = to_svm(vcpu);
4077 if (svm->nested.nested_run_pending)
4080 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4081 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4084 return !svm_smi_blocked(vcpu);
4087 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4089 struct vcpu_svm *svm = to_svm(vcpu);
4092 if (is_guest_mode(vcpu)) {
4093 /* FED8h - SVM Guest */
4094 put_smstate(u64, smstate, 0x7ed8, 1);
4095 /* FEE0h - SVM Guest VMCB Physical Address */
4096 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4098 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4099 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4100 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4102 ret = nested_svm_vmexit(svm);
4109 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4111 struct vcpu_svm *svm = to_svm(vcpu);
4112 struct kvm_host_map map;
4115 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4116 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4117 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4118 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4121 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4124 if (!(saved_efer & EFER_SVME))
4127 if (kvm_vcpu_map(&svm->vcpu,
4128 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4131 if (svm_allocate_nested(svm))
4134 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4135 kvm_vcpu_unmap(&svm->vcpu, &map, true);
4142 static void enable_smi_window(struct kvm_vcpu *vcpu)
4144 struct vcpu_svm *svm = to_svm(vcpu);
4146 if (!gif_set(svm)) {
4147 if (vgif_enabled(svm))
4148 svm_set_intercept(svm, INTERCEPT_STGI);
4149 /* STGI will cause a vm exit */
4151 /* We must be in SMM; RSM will cause a vmexit anyway. */
4155 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4157 bool smep, smap, is_user;
4161 * When the guest is an SEV-ES guest, emulation is not possible.
4163 if (sev_es_guest(vcpu->kvm))
4167 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4170 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4171 * possible that CPU microcode implementing DecodeAssist will fail
4172 * to read bytes of instruction which caused #NPF. In this case,
4173 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4174 * return 0 instead of the correct guest instruction bytes.
4176 * This happens because CPU microcode reading instruction bytes
4177 * uses a special opcode which attempts to read data using CPL=0
4178 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4179 * fault, it gives up and returns no instruction bytes.
4182 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4183 * returned 0 in GuestIntrBytes field of the VMCB.
4184 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4185 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4186 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4187 * a SMEP fault instead of #NPF).
4188 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4189 * As most guests enable SMAP if they have also enabled SMEP, use above
4190 * logic in order to attempt minimize false-positive of detecting errata
4191 * while still preserving all cases semantic correctness.
4194 * To determine what instruction the guest was executing, the hypervisor
4195 * will have to decode the instruction at the instruction pointer.
4197 * In non SEV guest, hypervisor will be able to read the guest
4198 * memory to decode the instruction pointer when insn_len is zero
4199 * so we return true to indicate that decoding is possible.
4201 * But in the SEV guest, the guest memory is encrypted with the
4202 * guest specific key and hypervisor will not be able to decode the
4203 * instruction pointer so we will not able to workaround it. Lets
4204 * print the error and request to kill the guest.
4206 if (likely(!insn || insn_len))
4210 * If RIP is invalid, go ahead with emulation which will cause an
4211 * internal error exit.
4213 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4216 cr4 = kvm_read_cr4(vcpu);
4217 smep = cr4 & X86_CR4_SMEP;
4218 smap = cr4 & X86_CR4_SMAP;
4219 is_user = svm_get_cpl(vcpu) == 3;
4220 if (smap && (!smep || is_user)) {
4221 if (!sev_guest(vcpu->kvm))
4224 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4225 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4231 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4233 struct vcpu_svm *svm = to_svm(vcpu);
4236 * TODO: Last condition latch INIT signals on vCPU when
4237 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4238 * To properly emulate the INIT intercept,
4239 * svm_check_nested_events() should call nested_svm_vmexit()
4240 * if an INIT signal is pending.
4242 return !gif_set(svm) ||
4243 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4246 static void svm_vm_destroy(struct kvm *kvm)
4248 avic_vm_destroy(kvm);
4249 sev_vm_destroy(kvm);
4252 static int svm_vm_init(struct kvm *kvm)
4254 if (!pause_filter_count || !pause_filter_thresh)
4255 kvm->arch.pause_in_guest = true;
4258 int ret = avic_vm_init(kvm);
4263 kvm_apicv_init(kvm, avic);
4267 static struct kvm_x86_ops svm_x86_ops __initdata = {
4268 .hardware_unsetup = svm_hardware_teardown,
4269 .hardware_enable = svm_hardware_enable,
4270 .hardware_disable = svm_hardware_disable,
4271 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4272 .has_emulated_msr = svm_has_emulated_msr,
4274 .vcpu_create = svm_create_vcpu,
4275 .vcpu_free = svm_free_vcpu,
4276 .vcpu_reset = svm_vcpu_reset,
4278 .vm_size = sizeof(struct kvm_svm),
4279 .vm_init = svm_vm_init,
4280 .vm_destroy = svm_vm_destroy,
4282 .prepare_guest_switch = svm_prepare_guest_switch,
4283 .vcpu_load = svm_vcpu_load,
4284 .vcpu_put = svm_vcpu_put,
4285 .vcpu_blocking = svm_vcpu_blocking,
4286 .vcpu_unblocking = svm_vcpu_unblocking,
4288 .update_exception_bitmap = update_exception_bitmap,
4289 .get_msr_feature = svm_get_msr_feature,
4290 .get_msr = svm_get_msr,
4291 .set_msr = svm_set_msr,
4292 .get_segment_base = svm_get_segment_base,
4293 .get_segment = svm_get_segment,
4294 .set_segment = svm_set_segment,
4295 .get_cpl = svm_get_cpl,
4296 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4297 .set_cr0 = svm_set_cr0,
4298 .is_valid_cr4 = svm_is_valid_cr4,
4299 .set_cr4 = svm_set_cr4,
4300 .set_efer = svm_set_efer,
4301 .get_idt = svm_get_idt,
4302 .set_idt = svm_set_idt,
4303 .get_gdt = svm_get_gdt,
4304 .set_gdt = svm_set_gdt,
4305 .set_dr7 = svm_set_dr7,
4306 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4307 .cache_reg = svm_cache_reg,
4308 .get_rflags = svm_get_rflags,
4309 .set_rflags = svm_set_rflags,
4311 .tlb_flush_all = svm_flush_tlb,
4312 .tlb_flush_current = svm_flush_tlb,
4313 .tlb_flush_gva = svm_flush_tlb_gva,
4314 .tlb_flush_guest = svm_flush_tlb,
4316 .run = svm_vcpu_run,
4317 .handle_exit = handle_exit,
4318 .skip_emulated_instruction = skip_emulated_instruction,
4319 .update_emulated_instruction = NULL,
4320 .set_interrupt_shadow = svm_set_interrupt_shadow,
4321 .get_interrupt_shadow = svm_get_interrupt_shadow,
4322 .patch_hypercall = svm_patch_hypercall,
4323 .set_irq = svm_set_irq,
4324 .set_nmi = svm_inject_nmi,
4325 .queue_exception = svm_queue_exception,
4326 .cancel_injection = svm_cancel_injection,
4327 .interrupt_allowed = svm_interrupt_allowed,
4328 .nmi_allowed = svm_nmi_allowed,
4329 .get_nmi_mask = svm_get_nmi_mask,
4330 .set_nmi_mask = svm_set_nmi_mask,
4331 .enable_nmi_window = enable_nmi_window,
4332 .enable_irq_window = enable_irq_window,
4333 .update_cr8_intercept = update_cr8_intercept,
4334 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4335 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4336 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4337 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4338 .load_eoi_exitmap = svm_load_eoi_exitmap,
4339 .hwapic_irr_update = svm_hwapic_irr_update,
4340 .hwapic_isr_update = svm_hwapic_isr_update,
4341 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4342 .apicv_post_state_restore = avic_post_state_restore,
4344 .set_tss_addr = svm_set_tss_addr,
4345 .set_identity_map_addr = svm_set_identity_map_addr,
4346 .get_mt_mask = svm_get_mt_mask,
4348 .get_exit_info = svm_get_exit_info,
4350 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4352 .has_wbinvd_exit = svm_has_wbinvd_exit,
4354 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4356 .load_mmu_pgd = svm_load_mmu_pgd,
4358 .check_intercept = svm_check_intercept,
4359 .handle_exit_irqoff = svm_handle_exit_irqoff,
4361 .request_immediate_exit = __kvm_request_immediate_exit,
4363 .sched_in = svm_sched_in,
4365 .pmu_ops = &amd_pmu_ops,
4366 .nested_ops = &svm_nested_ops,
4368 .deliver_posted_interrupt = svm_deliver_avic_intr,
4369 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4370 .update_pi_irte = svm_update_pi_irte,
4371 .setup_mce = svm_setup_mce,
4373 .smi_allowed = svm_smi_allowed,
4374 .pre_enter_smm = svm_pre_enter_smm,
4375 .pre_leave_smm = svm_pre_leave_smm,
4376 .enable_smi_window = enable_smi_window,
4378 .mem_enc_op = svm_mem_enc_op,
4379 .mem_enc_reg_region = svm_register_enc_region,
4380 .mem_enc_unreg_region = svm_unregister_enc_region,
4382 .can_emulate_instruction = svm_can_emulate_instruction,
4384 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4386 .msr_filter_changed = svm_msr_filter_changed,
4387 .complete_emulated_msr = svm_complete_emulated_msr,
4390 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4391 .cpu_has_kvm_support = has_svm,
4392 .disabled_by_bios = is_disabled,
4393 .hardware_setup = svm_hardware_setup,
4394 .check_processor_compatibility = svm_check_processor_compat,
4396 .runtime_ops = &svm_x86_ops,
4399 static int __init svm_init(void)
4401 __unused_size_checks();
4403 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4404 __alignof__(struct vcpu_svm), THIS_MODULE);
4407 static void __exit svm_exit(void)
4412 module_init(svm_init)
4413 module_exit(svm_exit)