arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38
  39 #include <asm/virtext.h>
  40 #include "trace.h"
  41
  42 #include "svm.h"
  43
  44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  45
  46 MODULE_AUTHOR("Qumranet");
  47 MODULE_LICENSE("GPL");
  48
  49 #ifdef MODULE
  50 static const struct x86_cpu_id svm_cpu_id[] = {
  51         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  52         {}
  53 };
  54 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  55 #endif
  56
  57 #define IOPM_ALLOC_ORDER 2
  58 #define MSRPM_ALLOC_ORDER 1
  59
  60 #define SEG_TYPE_LDT 2
  61 #define SEG_TYPE_BUSY_TSS16 3
  62
  63 #define SVM_FEATURE_LBRV           (1 <<  1)
  64 #define SVM_FEATURE_SVML           (1 <<  2)
  65 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  66 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  67 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  68 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  69 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  70
  71 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  72
  73 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  74 #define TSC_RATIO_MIN           0x0000000000000001ULL
  75 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  76
  77 static bool erratum_383_found __read_mostly;
  78
  79 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  80
  81 /*
  82  * Set osvw_len to higher value when updated Revision Guides
  83  * are published and we know what the new status bits are
  84  */
  85 static uint64_t osvw_len = 4, osvw_status;
  86
  87 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  88 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  89
  90 static const struct svm_direct_access_msrs {
  91         u32 index;   /* Index of the MSR */
  92         bool always; /* True if intercept is always on */
  93 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  94         { .index = MSR_STAR,                            .always = true  },
  95         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  96 #ifdef CONFIG_X86_64
  97         { .index = MSR_GS_BASE,                         .always = true  },
  98         { .index = MSR_FS_BASE,                         .always = true  },
  99         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 100         { .index = MSR_LSTAR,                           .always = true  },
 101         { .index = MSR_CSTAR,                           .always = true  },
 102         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 103 #endif
 104         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 105         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 106         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 107         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 108         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 109         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 110         { .index = MSR_INVALID,                         .always = false },
 111 };
 112
 113 /* enable NPT for AMD64 and X86 with PAE */
 114 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 115 bool npt_enabled = true;
 116 #else
 117 bool npt_enabled;
 118 #endif
 119
 120 /*
 121  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 122  * pause_filter_count: On processors that support Pause filtering(indicated
 123  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 124  *      count value. On VMRUN this value is loaded into an internal counter.
 125  *      Each time a pause instruction is executed, this counter is decremented
 126  *      until it reaches zero at which time a #VMEXIT is generated if pause
 127  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 128  *      Intercept Filtering for more details.
 129  *      This also indicate if ple logic enabled.
 130  *
 131  * pause_filter_thresh: In addition, some processor families support advanced
 132  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 133  *      the amount of time a guest is allowed to execute in a pause loop.
 134  *      In this mode, a 16-bit pause filter threshold field is added in the
 135  *      VMCB. The threshold value is a cycle count that is used to reset the
 136  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 137  *      count value from VMCB into an internal counter. Then, on each pause
 138  *      instruction the hardware checks the elapsed number of cycles since
 139  *      the most recent pause instruction against the pause filter threshold.
 140  *      If the elapsed cycle count is greater than the pause filter threshold,
 141  *      then the internal pause count is reloaded from the VMCB and execution
 142  *      continues. If the elapsed cycle count is less than the pause filter
 143  *      threshold, then the internal pause count is decremented. If the count
 144  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 145  *      triggered. If advanced pause filtering is supported and pause filter
 146  *      threshold field is set to zero, the filter will operate in the simpler,
 147  *      count only mode.
 148  */
 149
 150 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 151 module_param(pause_filter_thresh, ushort, 0444);
 152
 153 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 154 module_param(pause_filter_count, ushort, 0444);
 155
 156 /* Default doubles per-vcpu window every exit. */
 157 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 158 module_param(pause_filter_count_grow, ushort, 0444);
 159
 160 /* Default resets per-vcpu window every exit to pause_filter_count. */
 161 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 162 module_param(pause_filter_count_shrink, ushort, 0444);
 163
 164 /* Default is to compute the maximum so we can never overflow. */
 165 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 166 module_param(pause_filter_count_max, ushort, 0444);
 167
 168 /* allow nested paging (virtualized MMU) for all guests */
 169 static int npt = true;
 170 module_param(npt, int, S_IRUGO);
 171
 172 /* allow nested virtualization in KVM/SVM */
 173 static int nested = true;
 174 module_param(nested, int, S_IRUGO);
 175
 176 /* enable/disable Next RIP Save */
 177 static int nrips = true;
 178 module_param(nrips, int, 0444);
 179
 180 /* enable/disable Virtual VMLOAD VMSAVE */
 181 static int vls = true;
 182 module_param(vls, int, 0444);
 183
 184 /* enable/disable Virtual GIF */
 185 static int vgif = true;
 186 module_param(vgif, int, 0444);
 187
 188 /* enable/disable SEV support */
 189 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 190 module_param(sev, int, 0444);
 191
 192 /* enable/disable SEV-ES support */
 193 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 194 module_param(sev_es, int, 0444);
 195
 196 static bool __read_mostly dump_invalid_vmcb = 0;
 197 module_param(dump_invalid_vmcb, bool, 0644);
 198
 199 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 200
 201 static void svm_complete_interrupts(struct vcpu_svm *svm);
 202
 203 static unsigned long iopm_base;
 204
 205 struct kvm_ldttss_desc {
 206         u16 limit0;
 207         u16 base0;
 208         unsigned base1:8, type:5, dpl:2, p:1;
 209         unsigned limit1:4, zero0:3, g:1, base2:8;
 210         u32 base3;
 211         u32 zero1;
 212 } __attribute__((packed));
 213
 214 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 215
 216 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 217
 218 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 219 #define MSRS_RANGE_SIZE 2048
 220 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 221
 222 u32 svm_msrpm_offset(u32 msr)
 223 {
 224         u32 offset;
 225         int i;
 226
 227         for (i = 0; i < NUM_MSR_MAPS; i++) {
 228                 if (msr < msrpm_ranges[i] ||
 229                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 230                         continue;
 231
 232                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 233                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 234
 235                 /* Now we have the u8 offset - but need the u32 offset */
 236                 return offset / 4;
 237         }
 238
 239         /* MSR not in any range */
 240         return MSR_INVALID;
 241 }
 242
 243 #define MAX_INST_SIZE 15
 244
 245 static inline void clgi(void)
 246 {
 247         asm volatile (__ex("clgi"));
 248 }
 249
 250 static inline void stgi(void)
 251 {
 252         asm volatile (__ex("stgi"));
 253 }
 254
 255 static inline void invlpga(unsigned long addr, u32 asid)
 256 {
 257         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 258 }
 259
 260 static int get_max_npt_level(void)
 261 {
 262 #ifdef CONFIG_X86_64
 263         return PT64_ROOT_4LEVEL;
 264 #else
 265         return PT32E_ROOT_LEVEL;
 266 #endif
 267 }
 268
 269 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 270 {
 271         struct vcpu_svm *svm = to_svm(vcpu);
 272         u64 old_efer = vcpu->arch.efer;
 273         vcpu->arch.efer = efer;
 274
 275         if (!npt_enabled) {
 276                 /* Shadow paging assumes NX to be available.  */
 277                 efer |= EFER_NX;
 278
 279                 if (!(efer & EFER_LMA))
 280                         efer &= ~EFER_LME;
 281         }
 282
 283         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 284                 if (!(efer & EFER_SVME)) {
 285                         svm_leave_nested(svm);
 286                         svm_set_gif(svm, true);
 287
 288                         /*
 289                          * Free the nested guest state, unless we are in SMM.
 290                          * In this case we will return to the nested guest
 291                          * as soon as we leave SMM.
 292                          */
 293                         if (!is_smm(&svm->vcpu))
 294                                 svm_free_nested(svm);
 295
 296                 } else {
 297                         int ret = svm_allocate_nested(svm);
 298
 299                         if (ret) {
 300                                 vcpu->arch.efer = old_efer;
 301                                 return ret;
 302                         }
 303                 }
 304         }
 305
 306         svm->vmcb->save.efer = efer | EFER_SVME;
 307         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 308         return 0;
 309 }
 310
 311 static int is_external_interrupt(u32 info)
 312 {
 313         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 314         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 315 }
 316
 317 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 318 {
 319         struct vcpu_svm *svm = to_svm(vcpu);
 320         u32 ret = 0;
 321
 322         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 323                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 324         return ret;
 325 }
 326
 327 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 328 {
 329         struct vcpu_svm *svm = to_svm(vcpu);
 330
 331         if (mask == 0)
 332                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 333         else
 334                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 335
 336 }
 337
 338 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 339 {
 340         struct vcpu_svm *svm = to_svm(vcpu);
 341
 342         if (nrips && svm->vmcb->control.next_rip != 0) {
 343                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 344                 svm->next_rip = svm->vmcb->control.next_rip;
 345         }
 346
 347         if (!svm->next_rip) {
 348                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 349                         return 0;
 350         } else {
 351                 kvm_rip_write(vcpu, svm->next_rip);
 352         }
 353         svm_set_interrupt_shadow(vcpu, 0);
 354
 355         return 1;
 356 }
 357
 358 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 359 {
 360         struct vcpu_svm *svm = to_svm(vcpu);
 361         unsigned nr = vcpu->arch.exception.nr;
 362         bool has_error_code = vcpu->arch.exception.has_error_code;
 363         u32 error_code = vcpu->arch.exception.error_code;
 364
 365         kvm_deliver_exception_payload(&svm->vcpu);
 366
 367         if (nr == BP_VECTOR && !nrips) {
 368                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 369
 370                 /*
 371                  * For guest debugging where we have to reinject #BP if some
 372                  * INT3 is guest-owned:
 373                  * Emulate nRIP by moving RIP forward. Will fail if injection
 374                  * raises a fault that is not intercepted. Still better than
 375                  * failing in all cases.
 376                  */
 377                 (void)skip_emulated_instruction(&svm->vcpu);
 378                 rip = kvm_rip_read(&svm->vcpu);
 379                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 380                 svm->int3_injected = rip - old_rip;
 381         }
 382
 383         svm->vmcb->control.event_inj = nr
 384                 | SVM_EVTINJ_VALID
 385                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 386                 | SVM_EVTINJ_TYPE_EXEPT;
 387         svm->vmcb->control.event_inj_err = error_code;
 388 }
 389
 390 static void svm_init_erratum_383(void)
 391 {
 392         u32 low, high;
 393         int err;
 394         u64 val;
 395
 396         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 397                 return;
 398
 399         /* Use _safe variants to not break nested virtualization */
 400         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 401         if (err)
 402                 return;
 403
 404         val |= (1ULL << 47);
 405
 406         low  = lower_32_bits(val);
 407         high = upper_32_bits(val);
 408
 409         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 410
 411         erratum_383_found = true;
 412 }
 413
 414 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 415 {
 416         /*
 417          * Guests should see errata 400 and 415 as fixed (assuming that
 418          * HLT and IO instructions are intercepted).
 419          */
 420         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 421         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 422
 423         /*
 424          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 425          * all osvw.status bits inside that length, including bit 0 (which is
 426          * reserved for erratum 298), are valid. However, if host processor's
 427          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 428          * be conservative here and therefore we tell the guest that erratum 298
 429          * is present (because we really don't know).
 430          */
 431         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 432                 vcpu->arch.osvw.status |= 1;
 433 }
 434
 435 static int has_svm(void)
 436 {
 437         const char *msg;
 438
 439         if (!cpu_has_svm(&msg)) {
 440                 printk(KERN_INFO "has_svm: %s\n", msg);
 441                 return 0;
 442         }
 443
 444         return 1;
 445 }
 446
 447 static void svm_hardware_disable(void)
 448 {
 449         /* Make sure we clean up behind us */
 450         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 451                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 452
 453         cpu_svm_disable();
 454
 455         amd_pmu_disable_virt();
 456 }
 457
 458 static int svm_hardware_enable(void)
 459 {
 460
 461         struct svm_cpu_data *sd;
 462         uint64_t efer;
 463         struct desc_struct *gdt;
 464         int me = raw_smp_processor_id();
 465
 466         rdmsrl(MSR_EFER, efer);
 467         if (efer & EFER_SVME)
 468                 return -EBUSY;
 469
 470         if (!has_svm()) {
 471                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 472                 return -EINVAL;
 473         }
 474         sd = per_cpu(svm_data, me);
 475         if (!sd) {
 476                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 477                 return -EINVAL;
 478         }
 479
 480         sd->asid_generation = 1;
 481         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 482         sd->next_asid = sd->max_asid + 1;
 483         sd->min_asid = max_sev_asid + 1;
 484
 485         gdt = get_current_gdt_rw();
 486         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 487
 488         wrmsrl(MSR_EFER, efer | EFER_SVME);
 489
 490         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 491
 492         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 493                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 494                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 495         }
 496
 497
 498         /*
 499          * Get OSVW bits.
 500          *
 501          * Note that it is possible to have a system with mixed processor
 502          * revisions and therefore different OSVW bits. If bits are not the same
 503          * on different processors then choose the worst case (i.e. if erratum
 504          * is present on one processor and not on another then assume that the
 505          * erratum is present everywhere).
 506          */
 507         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 508                 uint64_t len, status = 0;
 509                 int err;
 510
 511                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 512                 if (!err)
 513                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 514                                                       &err);
 515
 516                 if (err)
 517                         osvw_status = osvw_len = 0;
 518                 else {
 519                         if (len < osvw_len)
 520                                 osvw_len = len;
 521                         osvw_status |= status;
 522                         osvw_status &= (1ULL << osvw_len) - 1;
 523                 }
 524         } else
 525                 osvw_status = osvw_len = 0;
 526
 527         svm_init_erratum_383();
 528
 529         amd_pmu_enable_virt();
 530
 531         return 0;
 532 }
 533
 534 static void svm_cpu_uninit(int cpu)
 535 {
 536         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 537
 538         if (!sd)
 539                 return;
 540
 541         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 542         kfree(sd->sev_vmcbs);
 543         __free_page(sd->save_area);
 544         kfree(sd);
 545 }
 546
 547 static int svm_cpu_init(int cpu)
 548 {
 549         struct svm_cpu_data *sd;
 550
 551         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 552         if (!sd)
 553                 return -ENOMEM;
 554         sd->cpu = cpu;
 555         sd->save_area = alloc_page(GFP_KERNEL);
 556         if (!sd->save_area)
 557                 goto free_cpu_data;
 558
 559         if (svm_sev_enabled()) {
 560                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 561                                               sizeof(void *),
 562                                               GFP_KERNEL);
 563                 if (!sd->sev_vmcbs)
 564                         goto free_save_area;
 565         }
 566
 567         per_cpu(svm_data, cpu) = sd;
 568
 569         return 0;
 570
 571 free_save_area:
 572         __free_page(sd->save_area);
 573 free_cpu_data:
 574         kfree(sd);
 575         return -ENOMEM;
 576
 577 }
 578
 579 static int direct_access_msr_slot(u32 msr)
 580 {
 581         u32 i;
 582
 583         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 584                 if (direct_access_msrs[i].index == msr)
 585                         return i;
 586
 587         return -ENOENT;
 588 }
 589
 590 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 591                                      int write)
 592 {
 593         struct vcpu_svm *svm = to_svm(vcpu);
 594         int slot = direct_access_msr_slot(msr);
 595
 596         if (slot == -ENOENT)
 597                 return;
 598
 599         /* Set the shadow bitmaps to the desired intercept states */
 600         if (read)
 601                 set_bit(slot, svm->shadow_msr_intercept.read);
 602         else
 603                 clear_bit(slot, svm->shadow_msr_intercept.read);
 604
 605         if (write)
 606                 set_bit(slot, svm->shadow_msr_intercept.write);
 607         else
 608                 clear_bit(slot, svm->shadow_msr_intercept.write);
 609 }
 610
 611 static bool valid_msr_intercept(u32 index)
 612 {
 613         return direct_access_msr_slot(index) != -ENOENT;
 614 }
 615
 616 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 617 {
 618         u8 bit_write;
 619         unsigned long tmp;
 620         u32 offset;
 621         u32 *msrpm;
 622
 623         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 624                                       to_svm(vcpu)->msrpm;
 625
 626         offset    = svm_msrpm_offset(msr);
 627         bit_write = 2 * (msr & 0x0f) + 1;
 628         tmp       = msrpm[offset];
 629
 630         BUG_ON(offset == MSR_INVALID);
 631
 632         return !!test_bit(bit_write,  &tmp);
 633 }
 634
 635 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 636                                         u32 msr, int read, int write)
 637 {
 638         u8 bit_read, bit_write;
 639         unsigned long tmp;
 640         u32 offset;
 641
 642         /*
 643          * If this warning triggers extend the direct_access_msrs list at the
 644          * beginning of the file
 645          */
 646         WARN_ON(!valid_msr_intercept(msr));
 647
 648         /* Enforce non allowed MSRs to trap */
 649         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 650                 read = 0;
 651
 652         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 653                 write = 0;
 654
 655         offset    = svm_msrpm_offset(msr);
 656         bit_read  = 2 * (msr & 0x0f);
 657         bit_write = 2 * (msr & 0x0f) + 1;
 658         tmp       = msrpm[offset];
 659
 660         BUG_ON(offset == MSR_INVALID);
 661
 662         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 663         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 664
 665         msrpm[offset] = tmp;
 666 }
 667
 668 static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 669                                  int read, int write)
 670 {
 671         set_shadow_msr_intercept(vcpu, msr, read, write);
 672         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 673 }
 674
 675 u32 *svm_vcpu_alloc_msrpm(void)
 676 {
 677         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
 678         u32 *msrpm;
 679
 680         if (!pages)
 681                 return NULL;
 682
 683         msrpm = page_address(pages);
 684         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 685
 686         return msrpm;
 687 }
 688
 689 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 690 {
 691         int i;
 692
 693         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 694                 if (!direct_access_msrs[i].always)
 695                         continue;
 696                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 697         }
 698 }
 699
 700
 701 void svm_vcpu_free_msrpm(u32 *msrpm)
 702 {
 703         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
 704 }
 705
 706 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 707 {
 708         struct vcpu_svm *svm = to_svm(vcpu);
 709         u32 i;
 710
 711         /*
 712          * Set intercept permissions for all direct access MSRs again. They
 713          * will automatically get filtered through the MSR filter, so we are
 714          * back in sync after this.
 715          */
 716         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 717                 u32 msr = direct_access_msrs[i].index;
 718                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 719                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 720
 721                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 722         }
 723 }
 724
 725 static void add_msr_offset(u32 offset)
 726 {
 727         int i;
 728
 729         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 730
 731                 /* Offset already in list? */
 732                 if (msrpm_offsets[i] == offset)
 733                         return;
 734
 735                 /* Slot used by another offset? */
 736                 if (msrpm_offsets[i] != MSR_INVALID)
 737                         continue;
 738
 739                 /* Add offset to list */
 740                 msrpm_offsets[i] = offset;
 741
 742                 return;
 743         }
 744
 745         /*
 746          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 747          * increase MSRPM_OFFSETS in this case.
 748          */
 749         BUG();
 750 }
 751
 752 static void init_msrpm_offsets(void)
 753 {
 754         int i;
 755
 756         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 757
 758         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 759                 u32 offset;
 760
 761                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 762                 BUG_ON(offset == MSR_INVALID);
 763
 764                 add_msr_offset(offset);
 765         }
 766 }
 767
 768 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 769 {
 770         struct vcpu_svm *svm = to_svm(vcpu);
 771
 772         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 773         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 774         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 775         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 776         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 777 }
 778
 779 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 780 {
 781         struct vcpu_svm *svm = to_svm(vcpu);
 782
 783         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 784         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 785         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 786         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 787         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 788 }
 789
 790 void disable_nmi_singlestep(struct vcpu_svm *svm)
 791 {
 792         svm->nmi_singlestep = false;
 793
 794         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 795                 /* Clear our flags if they were not set by the guest */
 796                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 797                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 798                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 799                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 800         }
 801 }
 802
 803 static void grow_ple_window(struct kvm_vcpu *vcpu)
 804 {
 805         struct vcpu_svm *svm = to_svm(vcpu);
 806         struct vmcb_control_area *control = &svm->vmcb->control;
 807         int old = control->pause_filter_count;
 808
 809         control->pause_filter_count = __grow_ple_window(old,
 810                                                         pause_filter_count,
 811                                                         pause_filter_count_grow,
 812                                                         pause_filter_count_max);
 813
 814         if (control->pause_filter_count != old) {
 815                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 816                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 817                                             control->pause_filter_count, old);
 818         }
 819 }
 820
 821 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 822 {
 823         struct vcpu_svm *svm = to_svm(vcpu);
 824         struct vmcb_control_area *control = &svm->vmcb->control;
 825         int old = control->pause_filter_count;
 826
 827         control->pause_filter_count =
 828                                 __shrink_ple_window(old,
 829                                                     pause_filter_count,
 830                                                     pause_filter_count_shrink,
 831                                                     pause_filter_count);
 832         if (control->pause_filter_count != old) {
 833                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 834                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 835                                             control->pause_filter_count, old);
 836         }
 837 }
 838
 839 /*
 840  * The default MMIO mask is a single bit (excluding the present bit),
 841  * which could conflict with the memory encryption bit. Check for
 842  * memory encryption support and override the default MMIO mask if
 843  * memory encryption is enabled.
 844  */
 845 static __init void svm_adjust_mmio_mask(void)
 846 {
 847         unsigned int enc_bit, mask_bit;
 848         u64 msr, mask;
 849
 850         /* If there is no memory encryption support, use existing mask */
 851         if (cpuid_eax(0x80000000) < 0x8000001f)
 852                 return;
 853
 854         /* If memory encryption is not enabled, use existing mask */
 855         rdmsrl(MSR_K8_SYSCFG, msr);
 856         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 857                 return;
 858
 859         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 860         mask_bit = boot_cpu_data.x86_phys_bits;
 861
 862         /* Increment the mask bit if it is the same as the encryption bit */
 863         if (enc_bit == mask_bit)
 864                 mask_bit++;
 865
 866         /*
 867          * If the mask bit location is below 52, then some bits above the
 868          * physical addressing limit will always be reserved, so use the
 869          * rsvd_bits() function to generate the mask. This mask, along with
 870          * the present bit, will be used to generate a page fault with
 871          * PFER.RSV = 1.
 872          *
 873          * If the mask bit location is 52 (or above), then clear the mask.
 874          */
 875         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 876
 877         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 878 }
 879
 880 static void svm_hardware_teardown(void)
 881 {
 882         int cpu;
 883
 884         if (svm_sev_enabled())
 885                 sev_hardware_teardown();
 886
 887         for_each_possible_cpu(cpu)
 888                 svm_cpu_uninit(cpu);
 889
 890         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 891         iopm_base = 0;
 892 }
 893
 894 static __init void svm_set_cpu_caps(void)
 895 {
 896         kvm_set_cpu_caps();
 897
 898         supported_xss = 0;
 899
 900         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 901         if (nested) {
 902                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 903
 904                 if (nrips)
 905                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 906
 907                 if (npt_enabled)
 908                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 909         }
 910
 911         /* CPUID 0x80000008 */
 912         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 913             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 914                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 915
 916         /* Enable INVPCID feature */
 917         kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
 918 }
 919
 920 static __init int svm_hardware_setup(void)
 921 {
 922         int cpu;
 923         struct page *iopm_pages;
 924         void *iopm_va;
 925         int r;
 926
 927         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 928
 929         if (!iopm_pages)
 930                 return -ENOMEM;
 931
 932         iopm_va = page_address(iopm_pages);
 933         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 934         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 935
 936         init_msrpm_offsets();
 937
 938         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 939
 940         if (boot_cpu_has(X86_FEATURE_NX))
 941                 kvm_enable_efer_bits(EFER_NX);
 942
 943         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 944                 kvm_enable_efer_bits(EFER_FFXSR);
 945
 946         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 947                 kvm_has_tsc_control = true;
 948                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 949                 kvm_tsc_scaling_ratio_frac_bits = 32;
 950         }
 951
 952         /* Check for pause filtering support */
 953         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 954                 pause_filter_count = 0;
 955                 pause_filter_thresh = 0;
 956         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 957                 pause_filter_thresh = 0;
 958         }
 959
 960         if (nested) {
 961                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 962                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 963         }
 964
 965         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 966                 sev_hardware_setup();
 967         } else {
 968                 sev = false;
 969                 sev_es = false;
 970         }
 971
 972         svm_adjust_mmio_mask();
 973
 974         for_each_possible_cpu(cpu) {
 975                 r = svm_cpu_init(cpu);
 976                 if (r)
 977                         goto err;
 978         }
 979
 980         if (!boot_cpu_has(X86_FEATURE_NPT))
 981                 npt_enabled = false;
 982
 983         if (npt_enabled && !npt)
 984                 npt_enabled = false;
 985
 986         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 987         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 988
 989         if (nrips) {
 990                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
 991                         nrips = false;
 992         }
 993
 994         if (avic) {
 995                 if (!npt_enabled ||
 996                     !boot_cpu_has(X86_FEATURE_AVIC) ||
 997                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
 998                         avic = false;
 999                 } else {
1000                         pr_info("AVIC enabled\n");
1001
1002                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1003                 }
1004         }
1005
1006         if (vls) {
1007                 if (!npt_enabled ||
1008                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1009                     !IS_ENABLED(CONFIG_X86_64)) {
1010                         vls = false;
1011                 } else {
1012                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1013                 }
1014         }
1015
1016         if (vgif) {
1017                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1018                         vgif = false;
1019                 else
1020                         pr_info("Virtual GIF supported\n");
1021         }
1022
1023         svm_set_cpu_caps();
1024
1025         /*
1026          * It seems that on AMD processors PTE's accessed bit is
1027          * being set by the CPU hardware before the NPF vmexit.
1028          * This is not expected behaviour and our tests fail because
1029          * of it.
1030          * A workaround here is to disable support for
1031          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1032          * In this case userspace can know if there is support using
1033          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1034          * it
1035          * If future AMD CPU models change the behaviour described above,
1036          * this variable can be changed accordingly
1037          */
1038         allow_smaller_maxphyaddr = !npt_enabled;
1039
1040         return 0;
1041
1042 err:
1043         svm_hardware_teardown();
1044         return r;
1045 }
1046
1047 static void init_seg(struct vmcb_seg *seg)
1048 {
1049         seg->selector = 0;
1050         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1051                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1052         seg->limit = 0xffff;
1053         seg->base = 0;
1054 }
1055
1056 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1057 {
1058         seg->selector = 0;
1059         seg->attrib = SVM_SELECTOR_P_MASK | type;
1060         seg->limit = 0xffff;
1061         seg->base = 0;
1062 }
1063
1064 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1065 {
1066         struct vcpu_svm *svm = to_svm(vcpu);
1067         u64 g_tsc_offset = 0;
1068
1069         if (is_guest_mode(vcpu)) {
1070                 /* Write L1's TSC offset.  */
1071                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1072                                svm->nested.hsave->control.tsc_offset;
1073                 svm->nested.hsave->control.tsc_offset = offset;
1074         }
1075
1076         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1077                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1078                                    offset);
1079
1080         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1081
1082         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1083         return svm->vmcb->control.tsc_offset;
1084 }
1085
1086 static void svm_check_invpcid(struct vcpu_svm *svm)
1087 {
1088         /*
1089          * Intercept INVPCID instruction only if shadow page table is
1090          * enabled. Interception is not required with nested page table
1091          * enabled.
1092          */
1093         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1094                 if (!npt_enabled)
1095                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1096                 else
1097                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1098         }
1099 }
1100
1101 static void init_vmcb(struct vcpu_svm *svm)
1102 {
1103         struct vmcb_control_area *control = &svm->vmcb->control;
1104         struct vmcb_save_area *save = &svm->vmcb->save;
1105
1106         svm->vcpu.arch.hflags = 0;
1107
1108         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1109         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1110         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1111         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1112         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1113         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1114         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1115                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1116
1117         set_dr_intercepts(svm);
1118
1119         set_exception_intercept(svm, PF_VECTOR);
1120         set_exception_intercept(svm, UD_VECTOR);
1121         set_exception_intercept(svm, MC_VECTOR);
1122         set_exception_intercept(svm, AC_VECTOR);
1123         set_exception_intercept(svm, DB_VECTOR);
1124         /*
1125          * Guest access to VMware backdoor ports could legitimately
1126          * trigger #GP because of TSS I/O permission bitmap.
1127          * We intercept those #GP and allow access to them anyway
1128          * as VMware does.
1129          */
1130         if (enable_vmware_backdoor)
1131                 set_exception_intercept(svm, GP_VECTOR);
1132
1133         svm_set_intercept(svm, INTERCEPT_INTR);
1134         svm_set_intercept(svm, INTERCEPT_NMI);
1135         svm_set_intercept(svm, INTERCEPT_SMI);
1136         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1137         svm_set_intercept(svm, INTERCEPT_RDPMC);
1138         svm_set_intercept(svm, INTERCEPT_CPUID);
1139         svm_set_intercept(svm, INTERCEPT_INVD);
1140         svm_set_intercept(svm, INTERCEPT_INVLPG);
1141         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1142         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1143         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1144         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1145         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1146         svm_set_intercept(svm, INTERCEPT_VMRUN);
1147         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1148         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1149         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1150         svm_set_intercept(svm, INTERCEPT_STGI);
1151         svm_set_intercept(svm, INTERCEPT_CLGI);
1152         svm_set_intercept(svm, INTERCEPT_SKINIT);
1153         svm_set_intercept(svm, INTERCEPT_WBINVD);
1154         svm_set_intercept(svm, INTERCEPT_XSETBV);
1155         svm_set_intercept(svm, INTERCEPT_RDPRU);
1156         svm_set_intercept(svm, INTERCEPT_RSM);
1157
1158         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1159                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1160                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1161         }
1162
1163         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1164                 svm_set_intercept(svm, INTERCEPT_HLT);
1165
1166         control->iopm_base_pa = __sme_set(iopm_base);
1167         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1168         control->int_ctl = V_INTR_MASKING_MASK;
1169
1170         init_seg(&save->es);
1171         init_seg(&save->ss);
1172         init_seg(&save->ds);
1173         init_seg(&save->fs);
1174         init_seg(&save->gs);
1175
1176         save->cs.selector = 0xf000;
1177         save->cs.base = 0xffff0000;
1178         /* Executable/Readable Code Segment */
1179         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1180                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1181         save->cs.limit = 0xffff;
1182
1183         save->gdtr.limit = 0xffff;
1184         save->idtr.limit = 0xffff;
1185
1186         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1187         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1188
1189         svm_set_efer(&svm->vcpu, 0);
1190         save->dr6 = 0xffff0ff0;
1191         kvm_set_rflags(&svm->vcpu, 2);
1192         save->rip = 0x0000fff0;
1193         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1194
1195         /*
1196          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1197          * It also updates the guest-visible cr0 value.
1198          */
1199         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1200         kvm_mmu_reset_context(&svm->vcpu);
1201
1202         save->cr4 = X86_CR4_PAE;
1203         /* rdx = ?? */
1204
1205         if (npt_enabled) {
1206                 /* Setup VMCB for Nested Paging */
1207                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1208                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1209                 clr_exception_intercept(svm, PF_VECTOR);
1210                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1211                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1212                 save->g_pat = svm->vcpu.arch.pat;
1213                 save->cr3 = 0;
1214                 save->cr4 = 0;
1215         }
1216         svm->asid_generation = 0;
1217         svm->asid = 0;
1218
1219         svm->nested.vmcb12_gpa = 0;
1220         svm->vcpu.arch.hflags = 0;
1221
1222         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1223                 control->pause_filter_count = pause_filter_count;
1224                 if (pause_filter_thresh)
1225                         control->pause_filter_thresh = pause_filter_thresh;
1226                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1227         } else {
1228                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1229         }
1230
1231         svm_check_invpcid(svm);
1232
1233         if (kvm_vcpu_apicv_active(&svm->vcpu))
1234                 avic_init_vmcb(svm);
1235
1236         /*
1237          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1238          * in VMCB and clear intercepts to avoid #VMEXIT.
1239          */
1240         if (vls) {
1241                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1242                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1243                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1244         }
1245
1246         if (vgif) {
1247                 svm_clr_intercept(svm, INTERCEPT_STGI);
1248                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1249                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1250         }
1251
1252         if (sev_guest(svm->vcpu.kvm)) {
1253                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1254                 clr_exception_intercept(svm, UD_VECTOR);
1255         }
1256
1257         vmcb_mark_all_dirty(svm->vmcb);
1258
1259         enable_gif(svm);
1260
1261 }
1262
1263 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1264 {
1265         struct vcpu_svm *svm = to_svm(vcpu);
1266         u32 dummy;
1267         u32 eax = 1;
1268
1269         svm->spec_ctrl = 0;
1270         svm->virt_spec_ctrl = 0;
1271
1272         if (!init_event) {
1273                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1274                                            MSR_IA32_APICBASE_ENABLE;
1275                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1276                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1277         }
1278         init_vmcb(svm);
1279
1280         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1281         kvm_rdx_write(vcpu, eax);
1282
1283         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1284                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1285 }
1286
1287 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1288 {
1289         struct vcpu_svm *svm;
1290         struct page *vmcb_page;
1291         int err;
1292
1293         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1294         svm = to_svm(vcpu);
1295
1296         err = -ENOMEM;
1297         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1298         if (!vmcb_page)
1299                 goto out;
1300
1301         err = avic_init_vcpu(svm);
1302         if (err)
1303                 goto error_free_vmcb_page;
1304
1305         /* We initialize this flag to true to make sure that the is_running
1306          * bit would be set the first time the vcpu is loaded.
1307          */
1308         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1309                 svm->avic_is_running = true;
1310
1311         svm->msrpm = svm_vcpu_alloc_msrpm();
1312         if (!svm->msrpm)
1313                 goto error_free_vmcb_page;
1314
1315         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1316
1317         svm->vmcb = page_address(vmcb_page);
1318         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1319         svm->asid_generation = 0;
1320         init_vmcb(svm);
1321
1322         svm_init_osvw(vcpu);
1323         vcpu->arch.microcode_version = 0x01000065;
1324
1325         return 0;
1326
1327 error_free_vmcb_page:
1328         __free_page(vmcb_page);
1329 out:
1330         return err;
1331 }
1332
1333 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1334 {
1335         int i;
1336
1337         for_each_online_cpu(i)
1338                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1339 }
1340
1341 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1342 {
1343         struct vcpu_svm *svm = to_svm(vcpu);
1344
1345         /*
1346          * The vmcb page can be recycled, causing a false negative in
1347          * svm_vcpu_load(). So, ensure that no logical CPU has this
1348          * vmcb page recorded as its current vmcb.
1349          */
1350         svm_clear_current_vmcb(svm->vmcb);
1351
1352         svm_free_nested(svm);
1353
1354         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1355         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1356 }
1357
1358 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1359 {
1360         struct vcpu_svm *svm = to_svm(vcpu);
1361         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1362         int i;
1363
1364         if (unlikely(cpu != vcpu->cpu)) {
1365                 svm->asid_generation = 0;
1366                 vmcb_mark_all_dirty(svm->vmcb);
1367         }
1368
1369 #ifdef CONFIG_X86_64
1370         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1371 #endif
1372         savesegment(fs, svm->host.fs);
1373         savesegment(gs, svm->host.gs);
1374         svm->host.ldt = kvm_read_ldt();
1375
1376         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1377                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1378
1379         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1380                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1381                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1382                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1383                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1384                 }
1385         }
1386         /* This assumes that the kernel never uses MSR_TSC_AUX */
1387         if (static_cpu_has(X86_FEATURE_RDTSCP))
1388                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1389
1390         if (sd->current_vmcb != svm->vmcb) {
1391                 sd->current_vmcb = svm->vmcb;
1392                 indirect_branch_prediction_barrier();
1393         }
1394         avic_vcpu_load(vcpu, cpu);
1395 }
1396
1397 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1398 {
1399         struct vcpu_svm *svm = to_svm(vcpu);
1400         int i;
1401
1402         avic_vcpu_put(vcpu);
1403
1404         ++vcpu->stat.host_state_reload;
1405         kvm_load_ldt(svm->host.ldt);
1406 #ifdef CONFIG_X86_64
1407         loadsegment(fs, svm->host.fs);
1408         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1409         load_gs_index(svm->host.gs);
1410 #else
1411 #ifdef CONFIG_X86_32_LAZY_GS
1412         loadsegment(gs, svm->host.gs);
1413 #endif
1414 #endif
1415         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1416                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1417 }
1418
1419 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1420 {
1421         struct vcpu_svm *svm = to_svm(vcpu);
1422         unsigned long rflags = svm->vmcb->save.rflags;
1423
1424         if (svm->nmi_singlestep) {
1425                 /* Hide our flags if they were not set by the guest */
1426                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1427                         rflags &= ~X86_EFLAGS_TF;
1428                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1429                         rflags &= ~X86_EFLAGS_RF;
1430         }
1431         return rflags;
1432 }
1433
1434 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1435 {
1436         if (to_svm(vcpu)->nmi_singlestep)
1437                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1438
1439        /*
1440         * Any change of EFLAGS.VM is accompanied by a reload of SS
1441         * (caused by either a task switch or an inter-privilege IRET),
1442         * so we do not need to update the CPL here.
1443         */
1444         to_svm(vcpu)->vmcb->save.rflags = rflags;
1445 }
1446
1447 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1448 {
1449         switch (reg) {
1450         case VCPU_EXREG_PDPTR:
1451                 BUG_ON(!npt_enabled);
1452                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1453                 break;
1454         default:
1455                 WARN_ON_ONCE(1);
1456         }
1457 }
1458
1459 static void svm_set_vintr(struct vcpu_svm *svm)
1460 {
1461         struct vmcb_control_area *control;
1462
1463         /* The following fields are ignored when AVIC is enabled */
1464         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1465         svm_set_intercept(svm, INTERCEPT_VINTR);
1466
1467         /*
1468          * This is just a dummy VINTR to actually cause a vmexit to happen.
1469          * Actual injection of virtual interrupts happens through EVENTINJ.
1470          */
1471         control = &svm->vmcb->control;
1472         control->int_vector = 0x0;
1473         control->int_ctl &= ~V_INTR_PRIO_MASK;
1474         control->int_ctl |= V_IRQ_MASK |
1475                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1476         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1477 }
1478
1479 static void svm_clear_vintr(struct vcpu_svm *svm)
1480 {
1481         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1482         svm_clr_intercept(svm, INTERCEPT_VINTR);
1483
1484         /* Drop int_ctl fields related to VINTR injection.  */
1485         svm->vmcb->control.int_ctl &= mask;
1486         if (is_guest_mode(&svm->vcpu)) {
1487                 svm->nested.hsave->control.int_ctl &= mask;
1488
1489                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1490                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1491                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1492         }
1493
1494         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1495 }
1496
1497 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1498 {
1499         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1500
1501         switch (seg) {
1502         case VCPU_SREG_CS: return &save->cs;
1503         case VCPU_SREG_DS: return &save->ds;
1504         case VCPU_SREG_ES: return &save->es;
1505         case VCPU_SREG_FS: return &save->fs;
1506         case VCPU_SREG_GS: return &save->gs;
1507         case VCPU_SREG_SS: return &save->ss;
1508         case VCPU_SREG_TR: return &save->tr;
1509         case VCPU_SREG_LDTR: return &save->ldtr;
1510         }
1511         BUG();
1512         return NULL;
1513 }
1514
1515 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1516 {
1517         struct vmcb_seg *s = svm_seg(vcpu, seg);
1518
1519         return s->base;
1520 }
1521
1522 static void svm_get_segment(struct kvm_vcpu *vcpu,
1523                             struct kvm_segment *var, int seg)
1524 {
1525         struct vmcb_seg *s = svm_seg(vcpu, seg);
1526
1527         var->base = s->base;
1528         var->limit = s->limit;
1529         var->selector = s->selector;
1530         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1531         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1532         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1533         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1534         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1535         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1536         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1537
1538         /*
1539          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1540          * However, the SVM spec states that the G bit is not observed by the
1541          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1542          * So let's synthesize a legal G bit for all segments, this helps
1543          * running KVM nested. It also helps cross-vendor migration, because
1544          * Intel's vmentry has a check on the 'G' bit.
1545          */
1546         var->g = s->limit > 0xfffff;
1547
1548         /*
1549          * AMD's VMCB does not have an explicit unusable field, so emulate it
1550          * for cross vendor migration purposes by "not present"
1551          */
1552         var->unusable = !var->present;
1553
1554         switch (seg) {
1555         case VCPU_SREG_TR:
1556                 /*
1557                  * Work around a bug where the busy flag in the tr selector
1558                  * isn't exposed
1559                  */
1560                 var->type |= 0x2;
1561                 break;
1562         case VCPU_SREG_DS:
1563         case VCPU_SREG_ES:
1564         case VCPU_SREG_FS:
1565         case VCPU_SREG_GS:
1566                 /*
1567                  * The accessed bit must always be set in the segment
1568                  * descriptor cache, although it can be cleared in the
1569                  * descriptor, the cached bit always remains at 1. Since
1570                  * Intel has a check on this, set it here to support
1571                  * cross-vendor migration.
1572                  */
1573                 if (!var->unusable)
1574                         var->type |= 0x1;
1575                 break;
1576         case VCPU_SREG_SS:
1577                 /*
1578                  * On AMD CPUs sometimes the DB bit in the segment
1579                  * descriptor is left as 1, although the whole segment has
1580                  * been made unusable. Clear it here to pass an Intel VMX
1581                  * entry check when cross vendor migrating.
1582                  */
1583                 if (var->unusable)
1584                         var->db = 0;
1585                 /* This is symmetric with svm_set_segment() */
1586                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1587                 break;
1588         }
1589 }
1590
1591 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1592 {
1593         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1594
1595         return save->cpl;
1596 }
1597
1598 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1599 {
1600         struct vcpu_svm *svm = to_svm(vcpu);
1601
1602         dt->size = svm->vmcb->save.idtr.limit;
1603         dt->address = svm->vmcb->save.idtr.base;
1604 }
1605
1606 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1607 {
1608         struct vcpu_svm *svm = to_svm(vcpu);
1609
1610         svm->vmcb->save.idtr.limit = dt->size;
1611         svm->vmcb->save.idtr.base = dt->address ;
1612         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1613 }
1614
1615 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1616 {
1617         struct vcpu_svm *svm = to_svm(vcpu);
1618
1619         dt->size = svm->vmcb->save.gdtr.limit;
1620         dt->address = svm->vmcb->save.gdtr.base;
1621 }
1622
1623 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1624 {
1625         struct vcpu_svm *svm = to_svm(vcpu);
1626
1627         svm->vmcb->save.gdtr.limit = dt->size;
1628         svm->vmcb->save.gdtr.base = dt->address ;
1629         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1630 }
1631
1632 static void update_cr0_intercept(struct vcpu_svm *svm)
1633 {
1634         ulong gcr0 = svm->vcpu.arch.cr0;
1635         u64 *hcr0 = &svm->vmcb->save.cr0;
1636
1637         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1638                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1639
1640         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1641
1642         if (gcr0 == *hcr0) {
1643                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1644                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1645         } else {
1646                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1647                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1648         }
1649 }
1650
1651 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1652 {
1653         struct vcpu_svm *svm = to_svm(vcpu);
1654
1655 #ifdef CONFIG_X86_64
1656         if (vcpu->arch.efer & EFER_LME) {
1657                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1658                         vcpu->arch.efer |= EFER_LMA;
1659                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1660                 }
1661
1662                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1663                         vcpu->arch.efer &= ~EFER_LMA;
1664                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1665                 }
1666         }
1667 #endif
1668         vcpu->arch.cr0 = cr0;
1669
1670         if (!npt_enabled)
1671                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1672
1673         /*
1674          * re-enable caching here because the QEMU bios
1675          * does not do it - this results in some delay at
1676          * reboot
1677          */
1678         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1679                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1680         svm->vmcb->save.cr0 = cr0;
1681         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1682         update_cr0_intercept(svm);
1683 }
1684
1685 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1686 {
1687         return true;
1688 }
1689
1690 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1691 {
1692         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1693         unsigned long old_cr4 = vcpu->arch.cr4;
1694
1695         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1696                 svm_flush_tlb(vcpu);
1697
1698         vcpu->arch.cr4 = cr4;
1699         if (!npt_enabled)
1700                 cr4 |= X86_CR4_PAE;
1701         cr4 |= host_cr4_mce;
1702         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1703         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1704
1705         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1706                 kvm_update_cpuid_runtime(vcpu);
1707 }
1708
1709 static void svm_set_segment(struct kvm_vcpu *vcpu,
1710                             struct kvm_segment *var, int seg)
1711 {
1712         struct vcpu_svm *svm = to_svm(vcpu);
1713         struct vmcb_seg *s = svm_seg(vcpu, seg);
1714
1715         s->base = var->base;
1716         s->limit = var->limit;
1717         s->selector = var->selector;
1718         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1719         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1720         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1721         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1722         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1723         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1724         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1725         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1726
1727         /*
1728          * This is always accurate, except if SYSRET returned to a segment
1729          * with SS.DPL != 3.  Intel does not have this quirk, and always
1730          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1731          * would entail passing the CPL to userspace and back.
1732          */
1733         if (seg == VCPU_SREG_SS)
1734                 /* This is symmetric with svm_get_segment() */
1735                 svm->vmcb->save.cpl = (var->dpl & 3);
1736
1737         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1738 }
1739
1740 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1741 {
1742         struct vcpu_svm *svm = to_svm(vcpu);
1743
1744         clr_exception_intercept(svm, BP_VECTOR);
1745
1746         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1747                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1748                         set_exception_intercept(svm, BP_VECTOR);
1749         }
1750 }
1751
1752 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1753 {
1754         if (sd->next_asid > sd->max_asid) {
1755                 ++sd->asid_generation;
1756                 sd->next_asid = sd->min_asid;
1757                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1758                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1759         }
1760
1761         svm->asid_generation = sd->asid_generation;
1762         svm->asid = sd->next_asid++;
1763 }
1764
1765 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1766 {
1767         struct vmcb *vmcb = svm->vmcb;
1768
1769         if (unlikely(value != vmcb->save.dr6)) {
1770                 vmcb->save.dr6 = value;
1771                 vmcb_mark_dirty(vmcb, VMCB_DR);
1772         }
1773 }
1774
1775 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1776 {
1777         struct vcpu_svm *svm = to_svm(vcpu);
1778
1779         get_debugreg(vcpu->arch.db[0], 0);
1780         get_debugreg(vcpu->arch.db[1], 1);
1781         get_debugreg(vcpu->arch.db[2], 2);
1782         get_debugreg(vcpu->arch.db[3], 3);
1783         /*
1784          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1785          * because db_interception might need it.  We can do it before vmentry.
1786          */
1787         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1788         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1789         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1790         set_dr_intercepts(svm);
1791 }
1792
1793 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1794 {
1795         struct vcpu_svm *svm = to_svm(vcpu);
1796
1797         svm->vmcb->save.dr7 = value;
1798         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1799 }
1800
1801 static int pf_interception(struct vcpu_svm *svm)
1802 {
1803         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1804         u64 error_code = svm->vmcb->control.exit_info_1;
1805
1806         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1807                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1808                         svm->vmcb->control.insn_bytes : NULL,
1809                         svm->vmcb->control.insn_len);
1810 }
1811
1812 static int npf_interception(struct vcpu_svm *svm)
1813 {
1814         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1815         u64 error_code = svm->vmcb->control.exit_info_1;
1816
1817         trace_kvm_page_fault(fault_address, error_code);
1818         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1819                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1820                         svm->vmcb->control.insn_bytes : NULL,
1821                         svm->vmcb->control.insn_len);
1822 }
1823
1824 static int db_interception(struct vcpu_svm *svm)
1825 {
1826         struct kvm_run *kvm_run = svm->vcpu.run;
1827         struct kvm_vcpu *vcpu = &svm->vcpu;
1828
1829         if (!(svm->vcpu.guest_debug &
1830               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1831                 !svm->nmi_singlestep) {
1832                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1833                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1834                 return 1;
1835         }
1836
1837         if (svm->nmi_singlestep) {
1838                 disable_nmi_singlestep(svm);
1839                 /* Make sure we check for pending NMIs upon entry */
1840                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1841         }
1842
1843         if (svm->vcpu.guest_debug &
1844             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1845                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1846                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1847                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1848                 kvm_run->debug.arch.pc =
1849                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1850                 kvm_run->debug.arch.exception = DB_VECTOR;
1851                 return 0;
1852         }
1853
1854         return 1;
1855 }
1856
1857 static int bp_interception(struct vcpu_svm *svm)
1858 {
1859         struct kvm_run *kvm_run = svm->vcpu.run;
1860
1861         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1862         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1863         kvm_run->debug.arch.exception = BP_VECTOR;
1864         return 0;
1865 }
1866
1867 static int ud_interception(struct vcpu_svm *svm)
1868 {
1869         return handle_ud(&svm->vcpu);
1870 }
1871
1872 static int ac_interception(struct vcpu_svm *svm)
1873 {
1874         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1875         return 1;
1876 }
1877
1878 static int gp_interception(struct vcpu_svm *svm)
1879 {
1880         struct kvm_vcpu *vcpu = &svm->vcpu;
1881         u32 error_code = svm->vmcb->control.exit_info_1;
1882
1883         WARN_ON_ONCE(!enable_vmware_backdoor);
1884
1885         /*
1886          * VMware backdoor emulation on #GP interception only handles IN{S},
1887          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1888          */
1889         if (error_code) {
1890                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1891                 return 1;
1892         }
1893         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1894 }
1895
1896 static bool is_erratum_383(void)
1897 {
1898         int err, i;
1899         u64 value;
1900
1901         if (!erratum_383_found)
1902                 return false;
1903
1904         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1905         if (err)
1906                 return false;
1907
1908         /* Bit 62 may or may not be set for this mce */
1909         value &= ~(1ULL << 62);
1910
1911         if (value != 0xb600000000010015ULL)
1912                 return false;
1913
1914         /* Clear MCi_STATUS registers */
1915         for (i = 0; i < 6; ++i)
1916                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1917
1918         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1919         if (!err) {
1920                 u32 low, high;
1921
1922                 value &= ~(1ULL << 2);
1923                 low    = lower_32_bits(value);
1924                 high   = upper_32_bits(value);
1925
1926                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1927         }
1928
1929         /* Flush tlb to evict multi-match entries */
1930         __flush_tlb_all();
1931
1932         return true;
1933 }
1934
1935 static void svm_handle_mce(struct vcpu_svm *svm)
1936 {
1937         if (is_erratum_383()) {
1938                 /*
1939                  * Erratum 383 triggered. Guest state is corrupt so kill the
1940                  * guest.
1941                  */
1942                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1943
1944                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1945
1946                 return;
1947         }
1948
1949         /*
1950          * On an #MC intercept the MCE handler is not called automatically in
1951          * the host. So do it by hand here.
1952          */
1953         kvm_machine_check();
1954 }
1955
1956 static int mc_interception(struct vcpu_svm *svm)
1957 {
1958         return 1;
1959 }
1960
1961 static int shutdown_interception(struct vcpu_svm *svm)
1962 {
1963         struct kvm_run *kvm_run = svm->vcpu.run;
1964
1965         /*
1966          * VMCB is undefined after a SHUTDOWN intercept
1967          * so reinitialize it.
1968          */
1969         clear_page(svm->vmcb);
1970         init_vmcb(svm);
1971
1972         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1973         return 0;
1974 }
1975
1976 static int io_interception(struct vcpu_svm *svm)
1977 {
1978         struct kvm_vcpu *vcpu = &svm->vcpu;
1979         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1980         int size, in, string;
1981         unsigned port;
1982
1983         ++svm->vcpu.stat.io_exits;
1984         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1985         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1986         if (string)
1987                 return kvm_emulate_instruction(vcpu, 0);
1988
1989         port = io_info >> 16;
1990         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1991         svm->next_rip = svm->vmcb->control.exit_info_2;
1992
1993         return kvm_fast_pio(&svm->vcpu, size, port, in);
1994 }
1995
1996 static int nmi_interception(struct vcpu_svm *svm)
1997 {
1998         return 1;
1999 }
2000
2001 static int intr_interception(struct vcpu_svm *svm)
2002 {
2003         ++svm->vcpu.stat.irq_exits;
2004         return 1;
2005 }
2006
2007 static int nop_on_interception(struct vcpu_svm *svm)
2008 {
2009         return 1;
2010 }
2011
2012 static int halt_interception(struct vcpu_svm *svm)
2013 {
2014         return kvm_emulate_halt(&svm->vcpu);
2015 }
2016
2017 static int vmmcall_interception(struct vcpu_svm *svm)
2018 {
2019         return kvm_emulate_hypercall(&svm->vcpu);
2020 }
2021
2022 static int vmload_interception(struct vcpu_svm *svm)
2023 {
2024         struct vmcb *nested_vmcb;
2025         struct kvm_host_map map;
2026         int ret;
2027
2028         if (nested_svm_check_permissions(svm))
2029                 return 1;
2030
2031         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2032         if (ret) {
2033                 if (ret == -EINVAL)
2034                         kvm_inject_gp(&svm->vcpu, 0);
2035                 return 1;
2036         }
2037
2038         nested_vmcb = map.hva;
2039
2040         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2041
2042         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2043         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2044
2045         return ret;
2046 }
2047
2048 static int vmsave_interception(struct vcpu_svm *svm)
2049 {
2050         struct vmcb *nested_vmcb;
2051         struct kvm_host_map map;
2052         int ret;
2053
2054         if (nested_svm_check_permissions(svm))
2055                 return 1;
2056
2057         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2058         if (ret) {
2059                 if (ret == -EINVAL)
2060                         kvm_inject_gp(&svm->vcpu, 0);
2061                 return 1;
2062         }
2063
2064         nested_vmcb = map.hva;
2065
2066         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2067
2068         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2069         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2070
2071         return ret;
2072 }
2073
2074 static int vmrun_interception(struct vcpu_svm *svm)
2075 {
2076         if (nested_svm_check_permissions(svm))
2077                 return 1;
2078
2079         return nested_svm_vmrun(svm);
2080 }
2081
2082 void svm_set_gif(struct vcpu_svm *svm, bool value)
2083 {
2084         if (value) {
2085                 /*
2086                  * If VGIF is enabled, the STGI intercept is only added to
2087                  * detect the opening of the SMI/NMI window; remove it now.
2088                  * Likewise, clear the VINTR intercept, we will set it
2089                  * again while processing KVM_REQ_EVENT if needed.
2090                  */
2091                 if (vgif_enabled(svm))
2092                         svm_clr_intercept(svm, INTERCEPT_STGI);
2093                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2094                         svm_clear_vintr(svm);
2095
2096                 enable_gif(svm);
2097                 if (svm->vcpu.arch.smi_pending ||
2098                     svm->vcpu.arch.nmi_pending ||
2099                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2100                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2101         } else {
2102                 disable_gif(svm);
2103
2104                 /*
2105                  * After a CLGI no interrupts should come.  But if vGIF is
2106                  * in use, we still rely on the VINTR intercept (rather than
2107                  * STGI) to detect an open interrupt window.
2108                 */
2109                 if (!vgif_enabled(svm))
2110                         svm_clear_vintr(svm);
2111         }
2112 }
2113
2114 static int stgi_interception(struct vcpu_svm *svm)
2115 {
2116         int ret;
2117
2118         if (nested_svm_check_permissions(svm))
2119                 return 1;
2120
2121         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2122         svm_set_gif(svm, true);
2123         return ret;
2124 }
2125
2126 static int clgi_interception(struct vcpu_svm *svm)
2127 {
2128         int ret;
2129
2130         if (nested_svm_check_permissions(svm))
2131                 return 1;
2132
2133         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2134         svm_set_gif(svm, false);
2135         return ret;
2136 }
2137
2138 static int invlpga_interception(struct vcpu_svm *svm)
2139 {
2140         struct kvm_vcpu *vcpu = &svm->vcpu;
2141
2142         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2143                           kvm_rax_read(&svm->vcpu));
2144
2145         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2146         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2147
2148         return kvm_skip_emulated_instruction(&svm->vcpu);
2149 }
2150
2151 static int skinit_interception(struct vcpu_svm *svm)
2152 {
2153         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2154
2155         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2156         return 1;
2157 }
2158
2159 static int wbinvd_interception(struct vcpu_svm *svm)
2160 {
2161         return kvm_emulate_wbinvd(&svm->vcpu);
2162 }
2163
2164 static int xsetbv_interception(struct vcpu_svm *svm)
2165 {
2166         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2167         u32 index = kvm_rcx_read(&svm->vcpu);
2168
2169         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2170                 return kvm_skip_emulated_instruction(&svm->vcpu);
2171         }
2172
2173         return 1;
2174 }
2175
2176 static int rdpru_interception(struct vcpu_svm *svm)
2177 {
2178         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2179         return 1;
2180 }
2181
2182 static int task_switch_interception(struct vcpu_svm *svm)
2183 {
2184         u16 tss_selector;
2185         int reason;
2186         int int_type = svm->vmcb->control.exit_int_info &
2187                 SVM_EXITINTINFO_TYPE_MASK;
2188         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2189         uint32_t type =
2190                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2191         uint32_t idt_v =
2192                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2193         bool has_error_code = false;
2194         u32 error_code = 0;
2195
2196         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2197
2198         if (svm->vmcb->control.exit_info_2 &
2199             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2200                 reason = TASK_SWITCH_IRET;
2201         else if (svm->vmcb->control.exit_info_2 &
2202                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2203                 reason = TASK_SWITCH_JMP;
2204         else if (idt_v)
2205                 reason = TASK_SWITCH_GATE;
2206         else
2207                 reason = TASK_SWITCH_CALL;
2208
2209         if (reason == TASK_SWITCH_GATE) {
2210                 switch (type) {
2211                 case SVM_EXITINTINFO_TYPE_NMI:
2212                         svm->vcpu.arch.nmi_injected = false;
2213                         break;
2214                 case SVM_EXITINTINFO_TYPE_EXEPT:
2215                         if (svm->vmcb->control.exit_info_2 &
2216                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2217                                 has_error_code = true;
2218                                 error_code =
2219                                         (u32)svm->vmcb->control.exit_info_2;
2220                         }
2221                         kvm_clear_exception_queue(&svm->vcpu);
2222                         break;
2223                 case SVM_EXITINTINFO_TYPE_INTR:
2224                         kvm_clear_interrupt_queue(&svm->vcpu);
2225                         break;
2226                 default:
2227                         break;
2228                 }
2229         }
2230
2231         if (reason != TASK_SWITCH_GATE ||
2232             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2233             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2234              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2235                 if (!skip_emulated_instruction(&svm->vcpu))
2236                         return 0;
2237         }
2238
2239         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2240                 int_vec = -1;
2241
2242         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2243                                has_error_code, error_code);
2244 }
2245
2246 static int cpuid_interception(struct vcpu_svm *svm)
2247 {
2248         return kvm_emulate_cpuid(&svm->vcpu);
2249 }
2250
2251 static int iret_interception(struct vcpu_svm *svm)
2252 {
2253         ++svm->vcpu.stat.nmi_window_exits;
2254         svm_clr_intercept(svm, INTERCEPT_IRET);
2255         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2256         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2257         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2258         return 1;
2259 }
2260
2261 static int invd_interception(struct vcpu_svm *svm)
2262 {
2263         /* Treat an INVD instruction as a NOP and just skip it. */
2264         return kvm_skip_emulated_instruction(&svm->vcpu);
2265 }
2266
2267 static int invlpg_interception(struct vcpu_svm *svm)
2268 {
2269         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2270                 return kvm_emulate_instruction(&svm->vcpu, 0);
2271
2272         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2273         return kvm_skip_emulated_instruction(&svm->vcpu);
2274 }
2275
2276 static int emulate_on_interception(struct vcpu_svm *svm)
2277 {
2278         return kvm_emulate_instruction(&svm->vcpu, 0);
2279 }
2280
2281 static int rsm_interception(struct vcpu_svm *svm)
2282 {
2283         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2284 }
2285
2286 static int rdpmc_interception(struct vcpu_svm *svm)
2287 {
2288         int err;
2289
2290         if (!nrips)
2291                 return emulate_on_interception(svm);
2292
2293         err = kvm_rdpmc(&svm->vcpu);
2294         return kvm_complete_insn_gp(&svm->vcpu, err);
2295 }
2296
2297 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2298                                             unsigned long val)
2299 {
2300         unsigned long cr0 = svm->vcpu.arch.cr0;
2301         bool ret = false;
2302
2303         if (!is_guest_mode(&svm->vcpu) ||
2304             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2305                 return false;
2306
2307         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2308         val &= ~SVM_CR0_SELECTIVE_MASK;
2309
2310         if (cr0 ^ val) {
2311                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2312                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2313         }
2314
2315         return ret;
2316 }
2317
2318 #define CR_VALID (1ULL << 63)
2319
2320 static int cr_interception(struct vcpu_svm *svm)
2321 {
2322         int reg, cr;
2323         unsigned long val;
2324         int err;
2325
2326         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2327                 return emulate_on_interception(svm);
2328
2329         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2330                 return emulate_on_interception(svm);
2331
2332         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2333         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2334                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2335         else
2336                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2337
2338         err = 0;
2339         if (cr >= 16) { /* mov to cr */
2340                 cr -= 16;
2341                 val = kvm_register_read(&svm->vcpu, reg);
2342                 trace_kvm_cr_write(cr, val);
2343                 switch (cr) {
2344                 case 0:
2345                         if (!check_selective_cr0_intercepted(svm, val))
2346                                 err = kvm_set_cr0(&svm->vcpu, val);
2347                         else
2348                                 return 1;
2349
2350                         break;
2351                 case 3:
2352                         err = kvm_set_cr3(&svm->vcpu, val);
2353                         break;
2354                 case 4:
2355                         err = kvm_set_cr4(&svm->vcpu, val);
2356                         break;
2357                 case 8:
2358                         err = kvm_set_cr8(&svm->vcpu, val);
2359                         break;
2360                 default:
2361                         WARN(1, "unhandled write to CR%d", cr);
2362                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2363                         return 1;
2364                 }
2365         } else { /* mov from cr */
2366                 switch (cr) {
2367                 case 0:
2368                         val = kvm_read_cr0(&svm->vcpu);
2369                         break;
2370                 case 2:
2371                         val = svm->vcpu.arch.cr2;
2372                         break;
2373                 case 3:
2374                         val = kvm_read_cr3(&svm->vcpu);
2375                         break;
2376                 case 4:
2377                         val = kvm_read_cr4(&svm->vcpu);
2378                         break;
2379                 case 8:
2380                         val = kvm_get_cr8(&svm->vcpu);
2381                         break;
2382                 default:
2383                         WARN(1, "unhandled read from CR%d", cr);
2384                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2385                         return 1;
2386                 }
2387                 kvm_register_write(&svm->vcpu, reg, val);
2388                 trace_kvm_cr_read(cr, val);
2389         }
2390         return kvm_complete_insn_gp(&svm->vcpu, err);
2391 }
2392
2393 static int dr_interception(struct vcpu_svm *svm)
2394 {
2395         int reg, dr;
2396         unsigned long val;
2397
2398         if (svm->vcpu.guest_debug == 0) {
2399                 /*
2400                  * No more DR vmexits; force a reload of the debug registers
2401                  * and reenter on this instruction.  The next vmexit will
2402                  * retrieve the full state of the debug registers.
2403                  */
2404                 clr_dr_intercepts(svm);
2405                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2406                 return 1;
2407         }
2408
2409         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2410                 return emulate_on_interception(svm);
2411
2412         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2413         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2414
2415         if (dr >= 16) { /* mov to DRn */
2416                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2417                         return 1;
2418                 val = kvm_register_read(&svm->vcpu, reg);
2419                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2420         } else {
2421                 if (!kvm_require_dr(&svm->vcpu, dr))
2422                         return 1;
2423                 kvm_get_dr(&svm->vcpu, dr, &val);
2424                 kvm_register_write(&svm->vcpu, reg, val);
2425         }
2426
2427         return kvm_skip_emulated_instruction(&svm->vcpu);
2428 }
2429
2430 static int cr8_write_interception(struct vcpu_svm *svm)
2431 {
2432         struct kvm_run *kvm_run = svm->vcpu.run;
2433         int r;
2434
2435         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2436         /* instruction emulation calls kvm_set_cr8() */
2437         r = cr_interception(svm);
2438         if (lapic_in_kernel(&svm->vcpu))
2439                 return r;
2440         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2441                 return r;
2442         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2443         return 0;
2444 }
2445
2446 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2447 {
2448         msr->data = 0;
2449
2450         switch (msr->index) {
2451         case MSR_F10H_DECFG:
2452                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2453                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2454                 break;
2455         case MSR_IA32_PERF_CAPABILITIES:
2456                 return 0;
2457         default:
2458                 return KVM_MSR_RET_INVALID;
2459         }
2460
2461         return 0;
2462 }
2463
2464 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2465 {
2466         struct vcpu_svm *svm = to_svm(vcpu);
2467
2468         switch (msr_info->index) {
2469         case MSR_STAR:
2470                 msr_info->data = svm->vmcb->save.star;
2471                 break;
2472 #ifdef CONFIG_X86_64
2473         case MSR_LSTAR:
2474                 msr_info->data = svm->vmcb->save.lstar;
2475                 break;
2476         case MSR_CSTAR:
2477                 msr_info->data = svm->vmcb->save.cstar;
2478                 break;
2479         case MSR_KERNEL_GS_BASE:
2480                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2481                 break;
2482         case MSR_SYSCALL_MASK:
2483                 msr_info->data = svm->vmcb->save.sfmask;
2484                 break;
2485 #endif
2486         case MSR_IA32_SYSENTER_CS:
2487                 msr_info->data = svm->vmcb->save.sysenter_cs;
2488                 break;
2489         case MSR_IA32_SYSENTER_EIP:
2490                 msr_info->data = svm->sysenter_eip;
2491                 break;
2492         case MSR_IA32_SYSENTER_ESP:
2493                 msr_info->data = svm->sysenter_esp;
2494                 break;
2495         case MSR_TSC_AUX:
2496                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2497                         return 1;
2498                 msr_info->data = svm->tsc_aux;
2499                 break;
2500         /*
2501          * Nobody will change the following 5 values in the VMCB so we can
2502          * safely return them on rdmsr. They will always be 0 until LBRV is
2503          * implemented.
2504          */
2505         case MSR_IA32_DEBUGCTLMSR:
2506                 msr_info->data = svm->vmcb->save.dbgctl;
2507                 break;
2508         case MSR_IA32_LASTBRANCHFROMIP:
2509                 msr_info->data = svm->vmcb->save.br_from;
2510                 break;
2511         case MSR_IA32_LASTBRANCHTOIP:
2512                 msr_info->data = svm->vmcb->save.br_to;
2513                 break;
2514         case MSR_IA32_LASTINTFROMIP:
2515                 msr_info->data = svm->vmcb->save.last_excp_from;
2516                 break;
2517         case MSR_IA32_LASTINTTOIP:
2518                 msr_info->data = svm->vmcb->save.last_excp_to;
2519                 break;
2520         case MSR_VM_HSAVE_PA:
2521                 msr_info->data = svm->nested.hsave_msr;
2522                 break;
2523         case MSR_VM_CR:
2524                 msr_info->data = svm->nested.vm_cr_msr;
2525                 break;
2526         case MSR_IA32_SPEC_CTRL:
2527                 if (!msr_info->host_initiated &&
2528                     !guest_has_spec_ctrl_msr(vcpu))
2529                         return 1;
2530
2531                 msr_info->data = svm->spec_ctrl;
2532                 break;
2533         case MSR_AMD64_VIRT_SPEC_CTRL:
2534                 if (!msr_info->host_initiated &&
2535                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2536                         return 1;
2537
2538                 msr_info->data = svm->virt_spec_ctrl;
2539                 break;
2540         case MSR_F15H_IC_CFG: {
2541
2542                 int family, model;
2543
2544                 family = guest_cpuid_family(vcpu);
2545                 model  = guest_cpuid_model(vcpu);
2546
2547                 if (family < 0 || model < 0)
2548                         return kvm_get_msr_common(vcpu, msr_info);
2549
2550                 msr_info->data = 0;
2551
2552                 if (family == 0x15 &&
2553                     (model >= 0x2 && model < 0x20))
2554                         msr_info->data = 0x1E;
2555                 }
2556                 break;
2557         case MSR_F10H_DECFG:
2558                 msr_info->data = svm->msr_decfg;
2559                 break;
2560         default:
2561                 return kvm_get_msr_common(vcpu, msr_info);
2562         }
2563         return 0;
2564 }
2565
2566 static int rdmsr_interception(struct vcpu_svm *svm)
2567 {
2568         return kvm_emulate_rdmsr(&svm->vcpu);
2569 }
2570
2571 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2572 {
2573         struct vcpu_svm *svm = to_svm(vcpu);
2574         int svm_dis, chg_mask;
2575
2576         if (data & ~SVM_VM_CR_VALID_MASK)
2577                 return 1;
2578
2579         chg_mask = SVM_VM_CR_VALID_MASK;
2580
2581         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2582                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2583
2584         svm->nested.vm_cr_msr &= ~chg_mask;
2585         svm->nested.vm_cr_msr |= (data & chg_mask);
2586
2587         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2588
2589         /* check for svm_disable while efer.svme is set */
2590         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2591                 return 1;
2592
2593         return 0;
2594 }
2595
2596 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2597 {
2598         struct vcpu_svm *svm = to_svm(vcpu);
2599
2600         u32 ecx = msr->index;
2601         u64 data = msr->data;
2602         switch (ecx) {
2603         case MSR_IA32_CR_PAT:
2604                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2605                         return 1;
2606                 vcpu->arch.pat = data;
2607                 svm->vmcb->save.g_pat = data;
2608                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2609                 break;
2610         case MSR_IA32_SPEC_CTRL:
2611                 if (!msr->host_initiated &&
2612                     !guest_has_spec_ctrl_msr(vcpu))
2613                         return 1;
2614
2615                 if (kvm_spec_ctrl_test_value(data))
2616                         return 1;
2617
2618                 svm->spec_ctrl = data;
2619                 if (!data)
2620                         break;
2621
2622                 /*
2623                  * For non-nested:
2624                  * When it's written (to non-zero) for the first time, pass
2625                  * it through.
2626                  *
2627                  * For nested:
2628                  * The handling of the MSR bitmap for L2 guests is done in
2629                  * nested_svm_vmrun_msrpm.
2630                  * We update the L1 MSR bit as well since it will end up
2631                  * touching the MSR anyway now.
2632                  */
2633                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2634                 break;
2635         case MSR_IA32_PRED_CMD:
2636                 if (!msr->host_initiated &&
2637                     !guest_has_pred_cmd_msr(vcpu))
2638                         return 1;
2639
2640                 if (data & ~PRED_CMD_IBPB)
2641                         return 1;
2642                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2643                         return 1;
2644                 if (!data)
2645                         break;
2646
2647                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2648                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2649                 break;
2650         case MSR_AMD64_VIRT_SPEC_CTRL:
2651                 if (!msr->host_initiated &&
2652                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2653                         return 1;
2654
2655                 if (data & ~SPEC_CTRL_SSBD)
2656                         return 1;
2657
2658                 svm->virt_spec_ctrl = data;
2659                 break;
2660         case MSR_STAR:
2661                 svm->vmcb->save.star = data;
2662                 break;
2663 #ifdef CONFIG_X86_64
2664         case MSR_LSTAR:
2665                 svm->vmcb->save.lstar = data;
2666                 break;
2667         case MSR_CSTAR:
2668                 svm->vmcb->save.cstar = data;
2669                 break;
2670         case MSR_KERNEL_GS_BASE:
2671                 svm->vmcb->save.kernel_gs_base = data;
2672                 break;
2673         case MSR_SYSCALL_MASK:
2674                 svm->vmcb->save.sfmask = data;
2675                 break;
2676 #endif
2677         case MSR_IA32_SYSENTER_CS:
2678                 svm->vmcb->save.sysenter_cs = data;
2679                 break;
2680         case MSR_IA32_SYSENTER_EIP:
2681                 svm->sysenter_eip = data;
2682                 svm->vmcb->save.sysenter_eip = data;
2683                 break;
2684         case MSR_IA32_SYSENTER_ESP:
2685                 svm->sysenter_esp = data;
2686                 svm->vmcb->save.sysenter_esp = data;
2687                 break;
2688         case MSR_TSC_AUX:
2689                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2690                         return 1;
2691
2692                 /*
2693                  * This is rare, so we update the MSR here instead of using
2694                  * direct_access_msrs.  Doing that would require a rdmsr in
2695                  * svm_vcpu_put.
2696                  */
2697                 svm->tsc_aux = data;
2698                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2699                 break;
2700         case MSR_IA32_DEBUGCTLMSR:
2701                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2702                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2703                                     __func__, data);
2704                         break;
2705                 }
2706                 if (data & DEBUGCTL_RESERVED_BITS)
2707                         return 1;
2708
2709                 svm->vmcb->save.dbgctl = data;
2710                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2711                 if (data & (1ULL<<0))
2712                         svm_enable_lbrv(vcpu);
2713                 else
2714                         svm_disable_lbrv(vcpu);
2715                 break;
2716         case MSR_VM_HSAVE_PA:
2717                 svm->nested.hsave_msr = data;
2718                 break;
2719         case MSR_VM_CR:
2720                 return svm_set_vm_cr(vcpu, data);
2721         case MSR_VM_IGNNE:
2722                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2723                 break;
2724         case MSR_F10H_DECFG: {
2725                 struct kvm_msr_entry msr_entry;
2726
2727                 msr_entry.index = msr->index;
2728                 if (svm_get_msr_feature(&msr_entry))
2729                         return 1;
2730
2731                 /* Check the supported bits */
2732                 if (data & ~msr_entry.data)
2733                         return 1;
2734
2735                 /* Don't allow the guest to change a bit, #GP */
2736                 if (!msr->host_initiated && (data ^ msr_entry.data))
2737                         return 1;
2738
2739                 svm->msr_decfg = data;
2740                 break;
2741         }
2742         case MSR_IA32_APICBASE:
2743                 if (kvm_vcpu_apicv_active(vcpu))
2744                         avic_update_vapic_bar(to_svm(vcpu), data);
2745                 fallthrough;
2746         default:
2747                 return kvm_set_msr_common(vcpu, msr);
2748         }
2749         return 0;
2750 }
2751
2752 static int wrmsr_interception(struct vcpu_svm *svm)
2753 {
2754         return kvm_emulate_wrmsr(&svm->vcpu);
2755 }
2756
2757 static int msr_interception(struct vcpu_svm *svm)
2758 {
2759         if (svm->vmcb->control.exit_info_1)
2760                 return wrmsr_interception(svm);
2761         else
2762                 return rdmsr_interception(svm);
2763 }
2764
2765 static int interrupt_window_interception(struct vcpu_svm *svm)
2766 {
2767         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2768         svm_clear_vintr(svm);
2769
2770         /*
2771          * For AVIC, the only reason to end up here is ExtINTs.
2772          * In this case AVIC was temporarily disabled for
2773          * requesting the IRQ window and we have to re-enable it.
2774          */
2775         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2776
2777         ++svm->vcpu.stat.irq_window_exits;
2778         return 1;
2779 }
2780
2781 static int pause_interception(struct vcpu_svm *svm)
2782 {
2783         struct kvm_vcpu *vcpu = &svm->vcpu;
2784         bool in_kernel = (svm_get_cpl(vcpu) == 0);
2785
2786         if (!kvm_pause_in_guest(vcpu->kvm))
2787                 grow_ple_window(vcpu);
2788
2789         kvm_vcpu_on_spin(vcpu, in_kernel);
2790         return 1;
2791 }
2792
2793 static int nop_interception(struct vcpu_svm *svm)
2794 {
2795         return kvm_skip_emulated_instruction(&(svm->vcpu));
2796 }
2797
2798 static int monitor_interception(struct vcpu_svm *svm)
2799 {
2800         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2801         return nop_interception(svm);
2802 }
2803
2804 static int mwait_interception(struct vcpu_svm *svm)
2805 {
2806         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2807         return nop_interception(svm);
2808 }
2809
2810 static int invpcid_interception(struct vcpu_svm *svm)
2811 {
2812         struct kvm_vcpu *vcpu = &svm->vcpu;
2813         unsigned long type;
2814         gva_t gva;
2815
2816         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2817                 kvm_queue_exception(vcpu, UD_VECTOR);
2818                 return 1;
2819         }
2820
2821         /*
2822          * For an INVPCID intercept:
2823          * EXITINFO1 provides the linear address of the memory operand.
2824          * EXITINFO2 provides the contents of the register operand.
2825          */
2826         type = svm->vmcb->control.exit_info_2;
2827         gva = svm->vmcb->control.exit_info_1;
2828
2829         if (type > 3) {
2830                 kvm_inject_gp(vcpu, 0);
2831                 return 1;
2832         }
2833
2834         return kvm_handle_invpcid(vcpu, type, gva);
2835 }
2836
2837 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2838         [SVM_EXIT_READ_CR0]                     = cr_interception,
2839         [SVM_EXIT_READ_CR3]                     = cr_interception,
2840         [SVM_EXIT_READ_CR4]                     = cr_interception,
2841         [SVM_EXIT_READ_CR8]                     = cr_interception,
2842         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2843         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2844         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2845         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2846         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2847         [SVM_EXIT_READ_DR0]                     = dr_interception,
2848         [SVM_EXIT_READ_DR1]                     = dr_interception,
2849         [SVM_EXIT_READ_DR2]                     = dr_interception,
2850         [SVM_EXIT_READ_DR3]                     = dr_interception,
2851         [SVM_EXIT_READ_DR4]                     = dr_interception,
2852         [SVM_EXIT_READ_DR5]                     = dr_interception,
2853         [SVM_EXIT_READ_DR6]                     = dr_interception,
2854         [SVM_EXIT_READ_DR7]                     = dr_interception,
2855         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2856         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2857         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2858         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2859         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2860         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2861         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2862         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2863         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2864         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2865         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2866         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2867         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2868         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2869         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2870         [SVM_EXIT_INTR]                         = intr_interception,
2871         [SVM_EXIT_NMI]                          = nmi_interception,
2872         [SVM_EXIT_SMI]                          = nop_on_interception,
2873         [SVM_EXIT_INIT]                         = nop_on_interception,
2874         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2875         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
2876         [SVM_EXIT_CPUID]                        = cpuid_interception,
2877         [SVM_EXIT_IRET]                         = iret_interception,
2878         [SVM_EXIT_INVD]                         = invd_interception,
2879         [SVM_EXIT_PAUSE]                        = pause_interception,
2880         [SVM_EXIT_HLT]                          = halt_interception,
2881         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2882         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2883         [SVM_EXIT_IOIO]                         = io_interception,
2884         [SVM_EXIT_MSR]                          = msr_interception,
2885         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2886         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2887         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2888         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2889         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2890         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2891         [SVM_EXIT_STGI]                         = stgi_interception,
2892         [SVM_EXIT_CLGI]                         = clgi_interception,
2893         [SVM_EXIT_SKINIT]                       = skinit_interception,
2894         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
2895         [SVM_EXIT_MONITOR]                      = monitor_interception,
2896         [SVM_EXIT_MWAIT]                        = mwait_interception,
2897         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2898         [SVM_EXIT_RDPRU]                        = rdpru_interception,
2899         [SVM_EXIT_INVPCID]                      = invpcid_interception,
2900         [SVM_EXIT_NPF]                          = npf_interception,
2901         [SVM_EXIT_RSM]                          = rsm_interception,
2902         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
2903         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
2904 };
2905
2906 static void dump_vmcb(struct kvm_vcpu *vcpu)
2907 {
2908         struct vcpu_svm *svm = to_svm(vcpu);
2909         struct vmcb_control_area *control = &svm->vmcb->control;
2910         struct vmcb_save_area *save = &svm->vmcb->save;
2911
2912         if (!dump_invalid_vmcb) {
2913                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2914                 return;
2915         }
2916
2917         pr_err("VMCB Control Area:\n");
2918         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2919         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
2920         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2921         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
2922         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
2923         pr_err("%-20s%08x %08x\n", "intercepts:",
2924               control->intercepts[INTERCEPT_WORD3],
2925                control->intercepts[INTERCEPT_WORD4]);
2926         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2927         pr_err("%-20s%d\n", "pause filter threshold:",
2928                control->pause_filter_thresh);
2929         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2930         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2931         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2932         pr_err("%-20s%d\n", "asid:", control->asid);
2933         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2934         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2935         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2936         pr_err("%-20s%08x\n", "int_state:", control->int_state);
2937         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2938         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2939         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2940         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2941         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2942         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2943         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2944         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2945         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2946         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2947         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2948         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2949         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2950         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2951         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2952         pr_err("VMCB State Save Area:\n");
2953         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2954                "es:",
2955                save->es.selector, save->es.attrib,
2956                save->es.limit, save->es.base);
2957         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2958                "cs:",
2959                save->cs.selector, save->cs.attrib,
2960                save->cs.limit, save->cs.base);
2961         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2962                "ss:",
2963                save->ss.selector, save->ss.attrib,
2964                save->ss.limit, save->ss.base);
2965         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2966                "ds:",
2967                save->ds.selector, save->ds.attrib,
2968                save->ds.limit, save->ds.base);
2969         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2970                "fs:",
2971                save->fs.selector, save->fs.attrib,
2972                save->fs.limit, save->fs.base);
2973         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2974                "gs:",
2975                save->gs.selector, save->gs.attrib,
2976                save->gs.limit, save->gs.base);
2977         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2978                "gdtr:",
2979                save->gdtr.selector, save->gdtr.attrib,
2980                save->gdtr.limit, save->gdtr.base);
2981         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2982                "ldtr:",
2983                save->ldtr.selector, save->ldtr.attrib,
2984                save->ldtr.limit, save->ldtr.base);
2985         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2986                "idtr:",
2987                save->idtr.selector, save->idtr.attrib,
2988                save->idtr.limit, save->idtr.base);
2989         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2990                "tr:",
2991                save->tr.selector, save->tr.attrib,
2992                save->tr.limit, save->tr.base);
2993         pr_err("cpl:            %d                efer:         %016llx\n",
2994                 save->cpl, save->efer);
2995         pr_err("%-15s %016llx %-13s %016llx\n",
2996                "cr0:", save->cr0, "cr2:", save->cr2);
2997         pr_err("%-15s %016llx %-13s %016llx\n",
2998                "cr3:", save->cr3, "cr4:", save->cr4);
2999         pr_err("%-15s %016llx %-13s %016llx\n",
3000                "dr6:", save->dr6, "dr7:", save->dr7);
3001         pr_err("%-15s %016llx %-13s %016llx\n",
3002                "rip:", save->rip, "rflags:", save->rflags);
3003         pr_err("%-15s %016llx %-13s %016llx\n",
3004                "rsp:", save->rsp, "rax:", save->rax);
3005         pr_err("%-15s %016llx %-13s %016llx\n",
3006                "star:", save->star, "lstar:", save->lstar);
3007         pr_err("%-15s %016llx %-13s %016llx\n",
3008                "cstar:", save->cstar, "sfmask:", save->sfmask);
3009         pr_err("%-15s %016llx %-13s %016llx\n",
3010                "kernel_gs_base:", save->kernel_gs_base,
3011                "sysenter_cs:", save->sysenter_cs);
3012         pr_err("%-15s %016llx %-13s %016llx\n",
3013                "sysenter_esp:", save->sysenter_esp,
3014                "sysenter_eip:", save->sysenter_eip);
3015         pr_err("%-15s %016llx %-13s %016llx\n",
3016                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3017         pr_err("%-15s %016llx %-13s %016llx\n",
3018                "br_from:", save->br_from, "br_to:", save->br_to);
3019         pr_err("%-15s %016llx %-13s %016llx\n",
3020                "excp_from:", save->last_excp_from,
3021                "excp_to:", save->last_excp_to);
3022 }
3023
3024 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3025                               u32 *intr_info, u32 *error_code)
3026 {
3027         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3028
3029         *info1 = control->exit_info_1;
3030         *info2 = control->exit_info_2;
3031         *intr_info = control->exit_int_info;
3032         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3033             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3034                 *error_code = control->exit_int_info_err;
3035         else
3036                 *error_code = 0;
3037 }
3038
3039 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3040 {
3041         struct vcpu_svm *svm = to_svm(vcpu);
3042         struct kvm_run *kvm_run = vcpu->run;
3043         u32 exit_code = svm->vmcb->control.exit_code;
3044
3045         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3046
3047         if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3048                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3049         if (npt_enabled)
3050                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3051
3052         if (is_guest_mode(vcpu)) {
3053                 int vmexit;
3054
3055                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3056
3057                 vmexit = nested_svm_exit_special(svm);
3058
3059                 if (vmexit == NESTED_EXIT_CONTINUE)
3060                         vmexit = nested_svm_exit_handled(svm);
3061
3062                 if (vmexit == NESTED_EXIT_DONE)
3063                         return 1;
3064         }
3065
3066         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3067                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3068                 kvm_run->fail_entry.hardware_entry_failure_reason
3069                         = svm->vmcb->control.exit_code;
3070                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3071                 dump_vmcb(vcpu);
3072                 return 0;
3073         }
3074
3075         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3076             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3077             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3078             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3079                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3080                        "exit_code 0x%x\n",
3081                        __func__, svm->vmcb->control.exit_int_info,
3082                        exit_code);
3083
3084         if (exit_fastpath != EXIT_FASTPATH_NONE)
3085                 return 1;
3086
3087         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3088             || !svm_exit_handlers[exit_code]) {
3089                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
3090                 dump_vmcb(vcpu);
3091                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3092                 vcpu->run->internal.suberror =
3093                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3094                 vcpu->run->internal.ndata = 2;
3095                 vcpu->run->internal.data[0] = exit_code;
3096                 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3097                 return 0;
3098         }
3099
3100 #ifdef CONFIG_RETPOLINE
3101         if (exit_code == SVM_EXIT_MSR)
3102                 return msr_interception(svm);
3103         else if (exit_code == SVM_EXIT_VINTR)
3104                 return interrupt_window_interception(svm);
3105         else if (exit_code == SVM_EXIT_INTR)
3106                 return intr_interception(svm);
3107         else if (exit_code == SVM_EXIT_HLT)
3108                 return halt_interception(svm);
3109         else if (exit_code == SVM_EXIT_NPF)
3110                 return npf_interception(svm);
3111 #endif
3112         return svm_exit_handlers[exit_code](svm);
3113 }
3114
3115 static void reload_tss(struct kvm_vcpu *vcpu)
3116 {
3117         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3118
3119         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3120         load_TR_desc();
3121 }
3122
3123 static void pre_svm_run(struct vcpu_svm *svm)
3124 {
3125         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3126
3127         if (sev_guest(svm->vcpu.kvm))
3128                 return pre_sev_run(svm, svm->vcpu.cpu);
3129
3130         /* FIXME: handle wraparound of asid_generation */
3131         if (svm->asid_generation != sd->asid_generation)
3132                 new_asid(svm, sd);
3133 }
3134
3135 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3136 {
3137         struct vcpu_svm *svm = to_svm(vcpu);
3138
3139         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3140         vcpu->arch.hflags |= HF_NMI_MASK;
3141         svm_set_intercept(svm, INTERCEPT_IRET);
3142         ++vcpu->stat.nmi_injections;
3143 }
3144
3145 static void svm_set_irq(struct kvm_vcpu *vcpu)
3146 {
3147         struct vcpu_svm *svm = to_svm(vcpu);
3148
3149         BUG_ON(!(gif_set(svm)));
3150
3151         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3152         ++vcpu->stat.irq_injections;
3153
3154         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3155                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3156 }
3157
3158 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3159 {
3160         struct vcpu_svm *svm = to_svm(vcpu);
3161
3162         if (nested_svm_virtualize_tpr(vcpu))
3163                 return;
3164
3165         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3166
3167         if (irr == -1)
3168                 return;
3169
3170         if (tpr >= irr)
3171                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3172 }
3173
3174 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3175 {
3176         struct vcpu_svm *svm = to_svm(vcpu);
3177         struct vmcb *vmcb = svm->vmcb;
3178         bool ret;
3179
3180         if (!gif_set(svm))
3181                 return true;
3182
3183         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3184                 return false;
3185
3186         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3187               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3188
3189         return ret;
3190 }
3191
3192 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3193 {
3194         struct vcpu_svm *svm = to_svm(vcpu);
3195         if (svm->nested.nested_run_pending)
3196                 return -EBUSY;
3197
3198         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3199         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3200                 return -EBUSY;
3201
3202         return !svm_nmi_blocked(vcpu);
3203 }
3204
3205 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3206 {
3207         struct vcpu_svm *svm = to_svm(vcpu);
3208
3209         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3210 }
3211
3212 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3213 {
3214         struct vcpu_svm *svm = to_svm(vcpu);
3215
3216         if (masked) {
3217                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3218                 svm_set_intercept(svm, INTERCEPT_IRET);
3219         } else {
3220                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3221                 svm_clr_intercept(svm, INTERCEPT_IRET);
3222         }
3223 }
3224
3225 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3226 {
3227         struct vcpu_svm *svm = to_svm(vcpu);
3228         struct vmcb *vmcb = svm->vmcb;
3229
3230         if (!gif_set(svm))
3231                 return true;
3232
3233         if (is_guest_mode(vcpu)) {
3234                 /* As long as interrupts are being delivered...  */
3235                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3236                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3237                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3238                         return true;
3239
3240                 /* ... vmexits aren't blocked by the interrupt shadow  */
3241                 if (nested_exit_on_intr(svm))
3242                         return false;
3243         } else {
3244                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3245                         return true;
3246         }
3247
3248         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3249 }
3250
3251 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3252 {
3253         struct vcpu_svm *svm = to_svm(vcpu);
3254         if (svm->nested.nested_run_pending)
3255                 return -EBUSY;
3256
3257         /*
3258          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3259          * e.g. if the IRQ arrived asynchronously after checking nested events.
3260          */
3261         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3262                 return -EBUSY;
3263
3264         return !svm_interrupt_blocked(vcpu);
3265 }
3266
3267 static void enable_irq_window(struct kvm_vcpu *vcpu)
3268 {
3269         struct vcpu_svm *svm = to_svm(vcpu);
3270
3271         /*
3272          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3273          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3274          * get that intercept, this function will be called again though and
3275          * we'll get the vintr intercept. However, if the vGIF feature is
3276          * enabled, the STGI interception will not occur. Enable the irq
3277          * window under the assumption that the hardware will set the GIF.
3278          */
3279         if (vgif_enabled(svm) || gif_set(svm)) {
3280                 /*
3281                  * IRQ window is not needed when AVIC is enabled,
3282                  * unless we have pending ExtINT since it cannot be injected
3283                  * via AVIC. In such case, we need to temporarily disable AVIC,
3284                  * and fallback to injecting IRQ via V_IRQ.
3285                  */
3286                 svm_toggle_avic_for_irq_window(vcpu, false);
3287                 svm_set_vintr(svm);
3288         }
3289 }
3290
3291 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3292 {
3293         struct vcpu_svm *svm = to_svm(vcpu);
3294
3295         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3296             == HF_NMI_MASK)
3297                 return; /* IRET will cause a vm exit */
3298
3299         if (!gif_set(svm)) {
3300                 if (vgif_enabled(svm))
3301                         svm_set_intercept(svm, INTERCEPT_STGI);
3302                 return; /* STGI will cause a vm exit */
3303         }
3304
3305         /*
3306          * Something prevents NMI from been injected. Single step over possible
3307          * problem (IRET or exception injection or interrupt shadow)
3308          */
3309         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3310         svm->nmi_singlestep = true;
3311         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3312 }
3313
3314 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3315 {
3316         return 0;
3317 }
3318
3319 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3320 {
3321         return 0;
3322 }
3323
3324 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3325 {
3326         struct vcpu_svm *svm = to_svm(vcpu);
3327
3328         /*
3329          * Flush only the current ASID even if the TLB flush was invoked via
3330          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3331          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3332          * unconditionally does a TLB flush on both nested VM-Enter and nested
3333          * VM-Exit (via kvm_mmu_reset_context()).
3334          */
3335         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3336                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3337         else
3338                 svm->asid_generation--;
3339 }
3340
3341 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3342 {
3343         struct vcpu_svm *svm = to_svm(vcpu);
3344
3345         invlpga(gva, svm->vmcb->control.asid);
3346 }
3347
3348 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3349 {
3350 }
3351
3352 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3353 {
3354         struct vcpu_svm *svm = to_svm(vcpu);
3355
3356         if (nested_svm_virtualize_tpr(vcpu))
3357                 return;
3358
3359         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3360                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3361                 kvm_set_cr8(vcpu, cr8);
3362         }
3363 }
3364
3365 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3366 {
3367         struct vcpu_svm *svm = to_svm(vcpu);
3368         u64 cr8;
3369
3370         if (nested_svm_virtualize_tpr(vcpu) ||
3371             kvm_vcpu_apicv_active(vcpu))
3372                 return;
3373
3374         cr8 = kvm_get_cr8(vcpu);
3375         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3376         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3377 }
3378
3379 static void svm_complete_interrupts(struct vcpu_svm *svm)
3380 {
3381         u8 vector;
3382         int type;
3383         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3384         unsigned int3_injected = svm->int3_injected;
3385
3386         svm->int3_injected = 0;
3387
3388         /*
3389          * If we've made progress since setting HF_IRET_MASK, we've
3390          * executed an IRET and can allow NMI injection.
3391          */
3392         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3393             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3394                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3395                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3396         }
3397
3398         svm->vcpu.arch.nmi_injected = false;
3399         kvm_clear_exception_queue(&svm->vcpu);
3400         kvm_clear_interrupt_queue(&svm->vcpu);
3401
3402         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3403                 return;
3404
3405         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3406
3407         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3408         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3409
3410         switch (type) {
3411         case SVM_EXITINTINFO_TYPE_NMI:
3412                 svm->vcpu.arch.nmi_injected = true;
3413                 break;
3414         case SVM_EXITINTINFO_TYPE_EXEPT:
3415                 /*
3416                  * In case of software exceptions, do not reinject the vector,
3417                  * but re-execute the instruction instead. Rewind RIP first
3418                  * if we emulated INT3 before.
3419                  */
3420                 if (kvm_exception_is_soft(vector)) {
3421                         if (vector == BP_VECTOR && int3_injected &&
3422                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3423                                 kvm_rip_write(&svm->vcpu,
3424                                               kvm_rip_read(&svm->vcpu) -
3425                                               int3_injected);
3426                         break;
3427                 }
3428                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3429                         u32 err = svm->vmcb->control.exit_int_info_err;
3430                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3431
3432                 } else
3433                         kvm_requeue_exception(&svm->vcpu, vector);
3434                 break;
3435         case SVM_EXITINTINFO_TYPE_INTR:
3436                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3437                 break;
3438         default:
3439                 break;
3440         }
3441 }
3442
3443 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3444 {
3445         struct vcpu_svm *svm = to_svm(vcpu);
3446         struct vmcb_control_area *control = &svm->vmcb->control;
3447
3448         control->exit_int_info = control->event_inj;
3449         control->exit_int_info_err = control->event_inj_err;
3450         control->event_inj = 0;
3451         svm_complete_interrupts(svm);
3452 }
3453
3454 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3455 {
3456         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3457             to_svm(vcpu)->vmcb->control.exit_info_1)
3458                 return handle_fastpath_set_msr_irqoff(vcpu);
3459
3460         return EXIT_FASTPATH_NONE;
3461 }
3462
3463 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3464
3465 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3466                                         struct vcpu_svm *svm)
3467 {
3468         /*
3469          * VMENTER enables interrupts (host state), but the kernel state is
3470          * interrupts disabled when this is invoked. Also tell RCU about
3471          * it. This is the same logic as for exit_to_user_mode().
3472          *
3473          * This ensures that e.g. latency analysis on the host observes
3474          * guest mode as interrupt enabled.
3475          *
3476          * guest_enter_irqoff() informs context tracking about the
3477          * transition to guest mode and if enabled adjusts RCU state
3478          * accordingly.
3479          */
3480         instrumentation_begin();
3481         trace_hardirqs_on_prepare();
3482         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3483         instrumentation_end();
3484
3485         guest_enter_irqoff();
3486         lockdep_hardirqs_on(CALLER_ADDR0);
3487
3488         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3489
3490 #ifdef CONFIG_X86_64
3491         native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3492 #else
3493         loadsegment(fs, svm->host.fs);
3494 #ifndef CONFIG_X86_32_LAZY_GS
3495         loadsegment(gs, svm->host.gs);
3496 #endif
3497 #endif
3498
3499         /*
3500          * VMEXIT disables interrupts (host state), but tracing and lockdep
3501          * have them in state 'on' as recorded before entering guest mode.
3502          * Same as enter_from_user_mode().
3503          *
3504          * guest_exit_irqoff() restores host context and reinstates RCU if
3505          * enabled and required.
3506          *
3507          * This needs to be done before the below as native_read_msr()
3508          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3509          * into world and some more.
3510          */
3511         lockdep_hardirqs_off(CALLER_ADDR0);
3512         guest_exit_irqoff();
3513
3514         instrumentation_begin();
3515         trace_hardirqs_off_finish();
3516         instrumentation_end();
3517 }
3518
3519 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3520 {
3521         struct vcpu_svm *svm = to_svm(vcpu);
3522
3523         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3524         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3525         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3526
3527         /*
3528          * Disable singlestep if we're injecting an interrupt/exception.
3529          * We don't want our modified rflags to be pushed on the stack where
3530          * we might not be able to easily reset them if we disabled NMI
3531          * singlestep later.
3532          */
3533         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3534                 /*
3535                  * Event injection happens before external interrupts cause a
3536                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3537                  * is enough to force an immediate vmexit.
3538                  */
3539                 disable_nmi_singlestep(svm);
3540                 smp_send_reschedule(vcpu->cpu);
3541         }
3542
3543         pre_svm_run(svm);
3544
3545         sync_lapic_to_cr8(vcpu);
3546
3547         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3548                 svm->vmcb->control.asid = svm->asid;
3549                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3550         }
3551         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3552
3553         /*
3554          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3555          * of a #DB.
3556          */
3557         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3558                 svm_set_dr6(svm, vcpu->arch.dr6);
3559         else
3560                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3561
3562         clgi();
3563         kvm_load_guest_xsave_state(vcpu);
3564
3565         kvm_wait_lapic_expire(vcpu);
3566
3567         /*
3568          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3569          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3570          * is no need to worry about the conditional branch over the wrmsr
3571          * being speculatively taken.
3572          */
3573         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3574
3575         svm_vcpu_enter_exit(vcpu, svm);
3576
3577         /*
3578          * We do not use IBRS in the kernel. If this vCPU has used the
3579          * SPEC_CTRL MSR it may have left it on; save the value and
3580          * turn it off. This is much more efficient than blindly adding
3581          * it to the atomic save/restore list. Especially as the former
3582          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3583          *
3584          * For non-nested case:
3585          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3586          * save it.
3587          *
3588          * For nested case:
3589          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3590          * save it.
3591          */
3592         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3593                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3594
3595         reload_tss(vcpu);
3596
3597         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3598
3599         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3600         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3601         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3602         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3603
3604         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3605                 kvm_before_interrupt(&svm->vcpu);
3606
3607         kvm_load_host_xsave_state(vcpu);
3608         stgi();
3609
3610         /* Any pending NMI will happen here */
3611
3612         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3613                 kvm_after_interrupt(&svm->vcpu);
3614
3615         sync_cr8_to_lapic(vcpu);
3616
3617         svm->next_rip = 0;
3618         if (is_guest_mode(&svm->vcpu)) {
3619                 sync_nested_vmcb_control(svm);
3620                 svm->nested.nested_run_pending = 0;
3621         }
3622
3623         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3624         vmcb_mark_all_clean(svm->vmcb);
3625
3626         /* if exit due to PF check for async PF */
3627         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3628                 svm->vcpu.arch.apf.host_apf_flags =
3629                         kvm_read_and_reset_apf_flags();
3630
3631         if (npt_enabled) {
3632                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3633                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3634         }
3635
3636         /*
3637          * We need to handle MC intercepts here before the vcpu has a chance to
3638          * change the physical cpu
3639          */
3640         if (unlikely(svm->vmcb->control.exit_code ==
3641                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3642                 svm_handle_mce(svm);
3643
3644         svm_complete_interrupts(svm);
3645
3646         if (is_guest_mode(vcpu))
3647                 return EXIT_FASTPATH_NONE;
3648
3649         return svm_exit_handlers_fastpath(vcpu);
3650 }
3651
3652 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3653                              int root_level)
3654 {
3655         struct vcpu_svm *svm = to_svm(vcpu);
3656         unsigned long cr3;
3657
3658         cr3 = __sme_set(root);
3659         if (npt_enabled) {
3660                 svm->vmcb->control.nested_cr3 = cr3;
3661                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3662
3663                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3664                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3665                         return;
3666                 cr3 = vcpu->arch.cr3;
3667         }
3668
3669         svm->vmcb->save.cr3 = cr3;
3670         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3671 }
3672
3673 static int is_disabled(void)
3674 {
3675         u64 vm_cr;
3676
3677         rdmsrl(MSR_VM_CR, vm_cr);
3678         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3679                 return 1;
3680
3681         return 0;
3682 }
3683
3684 static void
3685 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3686 {
3687         /*
3688          * Patch in the VMMCALL instruction:
3689          */
3690         hypercall[0] = 0x0f;
3691         hypercall[1] = 0x01;
3692         hypercall[2] = 0xd9;
3693 }
3694
3695 static int __init svm_check_processor_compat(void)
3696 {
3697         return 0;
3698 }
3699
3700 static bool svm_cpu_has_accelerated_tpr(void)
3701 {
3702         return false;
3703 }
3704
3705 static bool svm_has_emulated_msr(u32 index)
3706 {
3707         switch (index) {
3708         case MSR_IA32_MCG_EXT_CTL:
3709         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3710                 return false;
3711         default:
3712                 break;
3713         }
3714
3715         return true;
3716 }
3717
3718 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3719 {
3720         return 0;
3721 }
3722
3723 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3724 {
3725         struct vcpu_svm *svm = to_svm(vcpu);
3726         struct kvm_cpuid_entry2 *best;
3727
3728         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3729                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3730                                     boot_cpu_has(X86_FEATURE_XSAVES);
3731
3732         /* Update nrips enabled cache */
3733         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3734                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3735
3736         /* Check again if INVPCID interception if required */
3737         svm_check_invpcid(svm);
3738
3739         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
3740         if (sev_guest(vcpu->kvm)) {
3741                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3742                 if (best)
3743                         vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3744         }
3745
3746         if (!kvm_vcpu_apicv_active(vcpu))
3747                 return;
3748
3749         /*
3750          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3751          * is exposed to the guest, disable AVIC.
3752          */
3753         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3754                 kvm_request_apicv_update(vcpu->kvm, false,
3755                                          APICV_INHIBIT_REASON_X2APIC);
3756
3757         /*
3758          * Currently, AVIC does not work with nested virtualization.
3759          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3760          */
3761         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3762                 kvm_request_apicv_update(vcpu->kvm, false,
3763                                          APICV_INHIBIT_REASON_NESTED);
3764 }
3765
3766 static bool svm_has_wbinvd_exit(void)
3767 {
3768         return true;
3769 }
3770
3771 #define PRE_EX(exit)  { .exit_code = (exit), \
3772                         .stage = X86_ICPT_PRE_EXCEPT, }
3773 #define POST_EX(exit) { .exit_code = (exit), \
3774                         .stage = X86_ICPT_POST_EXCEPT, }
3775 #define POST_MEM(exit) { .exit_code = (exit), \
3776                         .stage = X86_ICPT_POST_MEMACCESS, }
3777
3778 static const struct __x86_intercept {
3779         u32 exit_code;
3780         enum x86_intercept_stage stage;
3781 } x86_intercept_map[] = {
3782         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3783         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3784         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3785         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3786         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3787         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3788         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3789         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3790         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3791         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3792         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3793         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3794         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3795         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3796         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3797         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3798         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3799         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3800         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3801         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3802         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3803         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3804         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3805         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3806         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3807         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3808         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3809         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3810         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3811         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3812         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3813         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3814         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3815         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3816         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3817         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3818         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3819         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3820         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3821         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
3822         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
3823         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
3824         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
3825         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
3826         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
3827         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
3828         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
3829 };
3830
3831 #undef PRE_EX
3832 #undef POST_EX
3833 #undef POST_MEM
3834
3835 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3836                                struct x86_instruction_info *info,
3837                                enum x86_intercept_stage stage,
3838                                struct x86_exception *exception)
3839 {
3840         struct vcpu_svm *svm = to_svm(vcpu);
3841         int vmexit, ret = X86EMUL_CONTINUE;
3842         struct __x86_intercept icpt_info;
3843         struct vmcb *vmcb = svm->vmcb;
3844
3845         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3846                 goto out;
3847
3848         icpt_info = x86_intercept_map[info->intercept];
3849
3850         if (stage != icpt_info.stage)
3851                 goto out;
3852
3853         switch (icpt_info.exit_code) {
3854         case SVM_EXIT_READ_CR0:
3855                 if (info->intercept == x86_intercept_cr_read)
3856                         icpt_info.exit_code += info->modrm_reg;
3857                 break;
3858         case SVM_EXIT_WRITE_CR0: {
3859                 unsigned long cr0, val;
3860
3861                 if (info->intercept == x86_intercept_cr_write)
3862                         icpt_info.exit_code += info->modrm_reg;
3863
3864                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3865                     info->intercept == x86_intercept_clts)
3866                         break;
3867
3868                 if (!(vmcb_is_intercept(&svm->nested.ctl,
3869                                         INTERCEPT_SELECTIVE_CR0)))
3870                         break;
3871
3872                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3873                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
3874
3875                 if (info->intercept == x86_intercept_lmsw) {
3876                         cr0 &= 0xfUL;
3877                         val &= 0xfUL;
3878                         /* lmsw can't clear PE - catch this here */
3879                         if (cr0 & X86_CR0_PE)
3880                                 val |= X86_CR0_PE;
3881                 }
3882
3883                 if (cr0 ^ val)
3884                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3885
3886                 break;
3887         }
3888         case SVM_EXIT_READ_DR0:
3889         case SVM_EXIT_WRITE_DR0:
3890                 icpt_info.exit_code += info->modrm_reg;
3891                 break;
3892         case SVM_EXIT_MSR:
3893                 if (info->intercept == x86_intercept_wrmsr)
3894                         vmcb->control.exit_info_1 = 1;
3895                 else
3896                         vmcb->control.exit_info_1 = 0;
3897                 break;
3898         case SVM_EXIT_PAUSE:
3899                 /*
3900                  * We get this for NOP only, but pause
3901                  * is rep not, check this here
3902                  */
3903                 if (info->rep_prefix != REPE_PREFIX)
3904                         goto out;
3905                 break;
3906         case SVM_EXIT_IOIO: {
3907                 u64 exit_info;
3908                 u32 bytes;
3909
3910                 if (info->intercept == x86_intercept_in ||
3911                     info->intercept == x86_intercept_ins) {
3912                         exit_info = ((info->src_val & 0xffff) << 16) |
3913                                 SVM_IOIO_TYPE_MASK;
3914                         bytes = info->dst_bytes;
3915                 } else {
3916                         exit_info = (info->dst_val & 0xffff) << 16;
3917                         bytes = info->src_bytes;
3918                 }
3919
3920                 if (info->intercept == x86_intercept_outs ||
3921                     info->intercept == x86_intercept_ins)
3922                         exit_info |= SVM_IOIO_STR_MASK;
3923
3924                 if (info->rep_prefix)
3925                         exit_info |= SVM_IOIO_REP_MASK;
3926
3927                 bytes = min(bytes, 4u);
3928
3929                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3930
3931                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3932
3933                 vmcb->control.exit_info_1 = exit_info;
3934                 vmcb->control.exit_info_2 = info->next_rip;
3935
3936                 break;
3937         }
3938         default:
3939                 break;
3940         }
3941
3942         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3943         if (static_cpu_has(X86_FEATURE_NRIPS))
3944                 vmcb->control.next_rip  = info->next_rip;
3945         vmcb->control.exit_code = icpt_info.exit_code;
3946         vmexit = nested_svm_exit_handled(svm);
3947
3948         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3949                                            : X86EMUL_CONTINUE;
3950
3951 out:
3952         return ret;
3953 }
3954
3955 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3956 {
3957 }
3958
3959 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3960 {
3961         if (!kvm_pause_in_guest(vcpu->kvm))
3962                 shrink_ple_window(vcpu);
3963 }
3964
3965 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3966 {
3967         /* [63:9] are reserved. */
3968         vcpu->arch.mcg_cap &= 0x1ff;
3969 }
3970
3971 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
3972 {
3973         struct vcpu_svm *svm = to_svm(vcpu);
3974
3975         /* Per APM Vol.2 15.22.2 "Response to SMI" */
3976         if (!gif_set(svm))
3977                 return true;
3978
3979         return is_smm(vcpu);
3980 }
3981
3982 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3983 {
3984         struct vcpu_svm *svm = to_svm(vcpu);
3985         if (svm->nested.nested_run_pending)
3986                 return -EBUSY;
3987
3988         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
3989         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
3990                 return -EBUSY;
3991
3992         return !svm_smi_blocked(vcpu);
3993 }
3994
3995 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3996 {
3997         struct vcpu_svm *svm = to_svm(vcpu);
3998         int ret;
3999
4000         if (is_guest_mode(vcpu)) {
4001                 /* FED8h - SVM Guest */
4002                 put_smstate(u64, smstate, 0x7ed8, 1);
4003                 /* FEE0h - SVM Guest VMCB Physical Address */
4004                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4005
4006                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4007                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4008                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4009
4010                 ret = nested_svm_vmexit(svm);
4011                 if (ret)
4012                         return ret;
4013         }
4014         return 0;
4015 }
4016
4017 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4018 {
4019         struct vcpu_svm *svm = to_svm(vcpu);
4020         struct kvm_host_map map;
4021         int ret = 0;
4022
4023         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4024                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4025                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4026                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4027
4028                 if (guest) {
4029                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4030                                 return 1;
4031
4032                         if (!(saved_efer & EFER_SVME))
4033                                 return 1;
4034
4035                         if (kvm_vcpu_map(&svm->vcpu,
4036                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4037                                 return 1;
4038
4039                         if (svm_allocate_nested(svm))
4040                                 return 1;
4041
4042                         ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4043                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
4044                 }
4045         }
4046
4047         return ret;
4048 }
4049
4050 static void enable_smi_window(struct kvm_vcpu *vcpu)
4051 {
4052         struct vcpu_svm *svm = to_svm(vcpu);
4053
4054         if (!gif_set(svm)) {
4055                 if (vgif_enabled(svm))
4056                         svm_set_intercept(svm, INTERCEPT_STGI);
4057                 /* STGI will cause a vm exit */
4058         } else {
4059                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4060         }
4061 }
4062
4063 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4064 {
4065         bool smep, smap, is_user;
4066         unsigned long cr4;
4067
4068         /*
4069          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4070          *
4071          * Errata:
4072          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4073          * possible that CPU microcode implementing DecodeAssist will fail
4074          * to read bytes of instruction which caused #NPF. In this case,
4075          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4076          * return 0 instead of the correct guest instruction bytes.
4077          *
4078          * This happens because CPU microcode reading instruction bytes
4079          * uses a special opcode which attempts to read data using CPL=0
4080          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4081          * fault, it gives up and returns no instruction bytes.
4082          *
4083          * Detection:
4084          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4085          * returned 0 in GuestIntrBytes field of the VMCB.
4086          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4087          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4088          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4089          * a SMEP fault instead of #NPF).
4090          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4091          * As most guests enable SMAP if they have also enabled SMEP, use above
4092          * logic in order to attempt minimize false-positive of detecting errata
4093          * while still preserving all cases semantic correctness.
4094          *
4095          * Workaround:
4096          * To determine what instruction the guest was executing, the hypervisor
4097          * will have to decode the instruction at the instruction pointer.
4098          *
4099          * In non SEV guest, hypervisor will be able to read the guest
4100          * memory to decode the instruction pointer when insn_len is zero
4101          * so we return true to indicate that decoding is possible.
4102          *
4103          * But in the SEV guest, the guest memory is encrypted with the
4104          * guest specific key and hypervisor will not be able to decode the
4105          * instruction pointer so we will not able to workaround it. Lets
4106          * print the error and request to kill the guest.
4107          */
4108         if (likely(!insn || insn_len))
4109                 return true;
4110
4111         /*
4112          * If RIP is invalid, go ahead with emulation which will cause an
4113          * internal error exit.
4114          */
4115         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4116                 return true;
4117
4118         cr4 = kvm_read_cr4(vcpu);
4119         smep = cr4 & X86_CR4_SMEP;
4120         smap = cr4 & X86_CR4_SMAP;
4121         is_user = svm_get_cpl(vcpu) == 3;
4122         if (smap && (!smep || is_user)) {
4123                 if (!sev_guest(vcpu->kvm))
4124                         return true;
4125
4126                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4127                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4128         }
4129
4130         return false;
4131 }
4132
4133 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4134 {
4135         struct vcpu_svm *svm = to_svm(vcpu);
4136
4137         /*
4138          * TODO: Last condition latch INIT signals on vCPU when
4139          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4140          * To properly emulate the INIT intercept,
4141          * svm_check_nested_events() should call nested_svm_vmexit()
4142          * if an INIT signal is pending.
4143          */
4144         return !gif_set(svm) ||
4145                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4146 }
4147
4148 static void svm_vm_destroy(struct kvm *kvm)
4149 {
4150         avic_vm_destroy(kvm);
4151         sev_vm_destroy(kvm);
4152 }
4153
4154 static int svm_vm_init(struct kvm *kvm)
4155 {
4156         if (!pause_filter_count || !pause_filter_thresh)
4157                 kvm->arch.pause_in_guest = true;
4158
4159         if (avic) {
4160                 int ret = avic_vm_init(kvm);
4161                 if (ret)
4162                         return ret;
4163         }
4164
4165         kvm_apicv_init(kvm, avic);
4166         return 0;
4167 }
4168
4169 static struct kvm_x86_ops svm_x86_ops __initdata = {
4170         .hardware_unsetup = svm_hardware_teardown,
4171         .hardware_enable = svm_hardware_enable,
4172         .hardware_disable = svm_hardware_disable,
4173         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4174         .has_emulated_msr = svm_has_emulated_msr,
4175
4176         .vcpu_create = svm_create_vcpu,
4177         .vcpu_free = svm_free_vcpu,
4178         .vcpu_reset = svm_vcpu_reset,
4179
4180         .vm_size = sizeof(struct kvm_svm),
4181         .vm_init = svm_vm_init,
4182         .vm_destroy = svm_vm_destroy,
4183
4184         .prepare_guest_switch = svm_prepare_guest_switch,
4185         .vcpu_load = svm_vcpu_load,
4186         .vcpu_put = svm_vcpu_put,
4187         .vcpu_blocking = svm_vcpu_blocking,
4188         .vcpu_unblocking = svm_vcpu_unblocking,
4189
4190         .update_exception_bitmap = update_exception_bitmap,
4191         .get_msr_feature = svm_get_msr_feature,
4192         .get_msr = svm_get_msr,
4193         .set_msr = svm_set_msr,
4194         .get_segment_base = svm_get_segment_base,
4195         .get_segment = svm_get_segment,
4196         .set_segment = svm_set_segment,
4197         .get_cpl = svm_get_cpl,
4198         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4199         .set_cr0 = svm_set_cr0,
4200         .is_valid_cr4 = svm_is_valid_cr4,
4201         .set_cr4 = svm_set_cr4,
4202         .set_efer = svm_set_efer,
4203         .get_idt = svm_get_idt,
4204         .set_idt = svm_set_idt,
4205         .get_gdt = svm_get_gdt,
4206         .set_gdt = svm_set_gdt,
4207         .set_dr7 = svm_set_dr7,
4208         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4209         .cache_reg = svm_cache_reg,
4210         .get_rflags = svm_get_rflags,
4211         .set_rflags = svm_set_rflags,
4212
4213         .tlb_flush_all = svm_flush_tlb,
4214         .tlb_flush_current = svm_flush_tlb,
4215         .tlb_flush_gva = svm_flush_tlb_gva,
4216         .tlb_flush_guest = svm_flush_tlb,
4217
4218         .run = svm_vcpu_run,
4219         .handle_exit = handle_exit,
4220         .skip_emulated_instruction = skip_emulated_instruction,
4221         .update_emulated_instruction = NULL,
4222         .set_interrupt_shadow = svm_set_interrupt_shadow,
4223         .get_interrupt_shadow = svm_get_interrupt_shadow,
4224         .patch_hypercall = svm_patch_hypercall,
4225         .set_irq = svm_set_irq,
4226         .set_nmi = svm_inject_nmi,
4227         .queue_exception = svm_queue_exception,
4228         .cancel_injection = svm_cancel_injection,
4229         .interrupt_allowed = svm_interrupt_allowed,
4230         .nmi_allowed = svm_nmi_allowed,
4231         .get_nmi_mask = svm_get_nmi_mask,
4232         .set_nmi_mask = svm_set_nmi_mask,
4233         .enable_nmi_window = enable_nmi_window,
4234         .enable_irq_window = enable_irq_window,
4235         .update_cr8_intercept = update_cr8_intercept,
4236         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4237         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4238         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4239         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4240         .load_eoi_exitmap = svm_load_eoi_exitmap,
4241         .hwapic_irr_update = svm_hwapic_irr_update,
4242         .hwapic_isr_update = svm_hwapic_isr_update,
4243         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4244         .apicv_post_state_restore = avic_post_state_restore,
4245
4246         .set_tss_addr = svm_set_tss_addr,
4247         .set_identity_map_addr = svm_set_identity_map_addr,
4248         .get_mt_mask = svm_get_mt_mask,
4249
4250         .get_exit_info = svm_get_exit_info,
4251
4252         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4253
4254         .has_wbinvd_exit = svm_has_wbinvd_exit,
4255
4256         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4257
4258         .load_mmu_pgd = svm_load_mmu_pgd,
4259
4260         .check_intercept = svm_check_intercept,
4261         .handle_exit_irqoff = svm_handle_exit_irqoff,
4262
4263         .request_immediate_exit = __kvm_request_immediate_exit,
4264
4265         .sched_in = svm_sched_in,
4266
4267         .pmu_ops = &amd_pmu_ops,
4268         .nested_ops = &svm_nested_ops,
4269
4270         .deliver_posted_interrupt = svm_deliver_avic_intr,
4271         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4272         .update_pi_irte = svm_update_pi_irte,
4273         .setup_mce = svm_setup_mce,
4274
4275         .smi_allowed = svm_smi_allowed,
4276         .pre_enter_smm = svm_pre_enter_smm,
4277         .pre_leave_smm = svm_pre_leave_smm,
4278         .enable_smi_window = enable_smi_window,
4279
4280         .mem_enc_op = svm_mem_enc_op,
4281         .mem_enc_reg_region = svm_register_enc_region,
4282         .mem_enc_unreg_region = svm_unregister_enc_region,
4283
4284         .can_emulate_instruction = svm_can_emulate_instruction,
4285
4286         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4287
4288         .msr_filter_changed = svm_msr_filter_changed,
4289 };
4290
4291 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4292         .cpu_has_kvm_support = has_svm,
4293         .disabled_by_bios = is_disabled,
4294         .hardware_setup = svm_hardware_setup,
4295         .check_processor_compatibility = svm_check_processor_compat,
4296
4297         .runtime_ops = &svm_x86_ops,
4298 };
4299
4300 static int __init svm_init(void)
4301 {
4302         __unused_size_checks();
4303
4304         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4305                         __alignof__(struct vcpu_svm), THIS_MODULE);
4306 }
4307
4308 static void __exit svm_exit(void)
4309 {
4310         kvm_exit();
4311 }
4312
4313 module_init(svm_init)
4314 module_exit(svm_exit)