arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/mce.h>
  37 #include <asm/spec-ctrl.h>
  38 #include <asm/cpu_device_id.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is always on */
  94 } direct_access_msrs[] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_INVALID,                         .always = false },
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 bool npt_enabled = true;
 117 #else
 118 bool npt_enabled;
 119 #endif
 120
 121 /*
 122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 123  * pause_filter_count: On processors that support Pause filtering(indicated
 124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 125  *      count value. On VMRUN this value is loaded into an internal counter.
 126  *      Each time a pause instruction is executed, this counter is decremented
 127  *      until it reaches zero at which time a #VMEXIT is generated if pause
 128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 129  *      Intercept Filtering for more details.
 130  *      This also indicate if ple logic enabled.
 131  *
 132  * pause_filter_thresh: In addition, some processor families support advanced
 133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 134  *      the amount of time a guest is allowed to execute in a pause loop.
 135  *      In this mode, a 16-bit pause filter threshold field is added in the
 136  *      VMCB. The threshold value is a cycle count that is used to reset the
 137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 138  *      count value from VMCB into an internal counter. Then, on each pause
 139  *      instruction the hardware checks the elapsed number of cycles since
 140  *      the most recent pause instruction against the pause filter threshold.
 141  *      If the elapsed cycle count is greater than the pause filter threshold,
 142  *      then the internal pause count is reloaded from the VMCB and execution
 143  *      continues. If the elapsed cycle count is less than the pause filter
 144  *      threshold, then the internal pause count is decremented. If the count
 145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 146  *      triggered. If advanced pause filtering is supported and pause filter
 147  *      threshold field is set to zero, the filter will operate in the simpler,
 148  *      count only mode.
 149  */
 150
 151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 152 module_param(pause_filter_thresh, ushort, 0444);
 153
 154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 155 module_param(pause_filter_count, ushort, 0444);
 156
 157 /* Default doubles per-vcpu window every exit. */
 158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 159 module_param(pause_filter_count_grow, ushort, 0444);
 160
 161 /* Default resets per-vcpu window every exit to pause_filter_count. */
 162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 163 module_param(pause_filter_count_shrink, ushort, 0444);
 164
 165 /* Default is to compute the maximum so we can never overflow. */
 166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 167 module_param(pause_filter_count_max, ushort, 0444);
 168
 169 /* allow nested paging (virtualized MMU) for all guests */
 170 static int npt = true;
 171 module_param(npt, int, S_IRUGO);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 static bool __read_mostly dump_invalid_vmcb = 0;
 194 module_param(dump_invalid_vmcb, bool, 0644);
 195
 196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 197
 198 static void svm_complete_interrupts(struct vcpu_svm *svm);
 199
 200 static unsigned long iopm_base;
 201
 202 struct kvm_ldttss_desc {
 203         u16 limit0;
 204         u16 base0;
 205         unsigned base1:8, type:5, dpl:2, p:1;
 206         unsigned limit1:4, zero0:3, g:1, base2:8;
 207         u32 base3;
 208         u32 zero1;
 209 } __attribute__((packed));
 210
 211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 212
 213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 214
 215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 216 #define MSRS_RANGE_SIZE 2048
 217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 218
 219 u32 svm_msrpm_offset(u32 msr)
 220 {
 221         u32 offset;
 222         int i;
 223
 224         for (i = 0; i < NUM_MSR_MAPS; i++) {
 225                 if (msr < msrpm_ranges[i] ||
 226                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 227                         continue;
 228
 229                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 230                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 231
 232                 /* Now we have the u8 offset - but need the u32 offset */
 233                 return offset / 4;
 234         }
 235
 236         /* MSR not in any range */
 237         return MSR_INVALID;
 238 }
 239
 240 #define MAX_INST_SIZE 15
 241
 242 static inline void clgi(void)
 243 {
 244         asm volatile (__ex("clgi"));
 245 }
 246
 247 static inline void stgi(void)
 248 {
 249         asm volatile (__ex("stgi"));
 250 }
 251
 252 static inline void invlpga(unsigned long addr, u32 asid)
 253 {
 254         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 255 }
 256
 257 static int get_max_npt_level(void)
 258 {
 259 #ifdef CONFIG_X86_64
 260         return PT64_ROOT_4LEVEL;
 261 #else
 262         return PT32E_ROOT_LEVEL;
 263 #endif
 264 }
 265
 266 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 267 {
 268         struct vcpu_svm *svm = to_svm(vcpu);
 269         vcpu->arch.efer = efer;
 270
 271         if (!npt_enabled) {
 272                 /* Shadow paging assumes NX to be available.  */
 273                 efer |= EFER_NX;
 274
 275                 if (!(efer & EFER_LMA))
 276                         efer &= ~EFER_LME;
 277         }
 278
 279         if (!(efer & EFER_SVME)) {
 280                 svm_leave_nested(svm);
 281                 svm_set_gif(svm, true);
 282         }
 283
 284         svm->vmcb->save.efer = efer | EFER_SVME;
 285         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 286 }
 287
 288 static int is_external_interrupt(u32 info)
 289 {
 290         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 291         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 292 }
 293
 294 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 295 {
 296         struct vcpu_svm *svm = to_svm(vcpu);
 297         u32 ret = 0;
 298
 299         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 300                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 301         return ret;
 302 }
 303
 304 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 305 {
 306         struct vcpu_svm *svm = to_svm(vcpu);
 307
 308         if (mask == 0)
 309                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 310         else
 311                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 312
 313 }
 314
 315 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 316 {
 317         struct vcpu_svm *svm = to_svm(vcpu);
 318
 319         if (nrips && svm->vmcb->control.next_rip != 0) {
 320                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 321                 svm->next_rip = svm->vmcb->control.next_rip;
 322         }
 323
 324         if (!svm->next_rip) {
 325                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 326                         return 0;
 327         } else {
 328                 kvm_rip_write(vcpu, svm->next_rip);
 329         }
 330         svm_set_interrupt_shadow(vcpu, 0);
 331
 332         return 1;
 333 }
 334
 335 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 336 {
 337         struct vcpu_svm *svm = to_svm(vcpu);
 338         unsigned nr = vcpu->arch.exception.nr;
 339         bool has_error_code = vcpu->arch.exception.has_error_code;
 340         u32 error_code = vcpu->arch.exception.error_code;
 341
 342         kvm_deliver_exception_payload(&svm->vcpu);
 343
 344         if (nr == BP_VECTOR && !nrips) {
 345                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 346
 347                 /*
 348                  * For guest debugging where we have to reinject #BP if some
 349                  * INT3 is guest-owned:
 350                  * Emulate nRIP by moving RIP forward. Will fail if injection
 351                  * raises a fault that is not intercepted. Still better than
 352                  * failing in all cases.
 353                  */
 354                 (void)skip_emulated_instruction(&svm->vcpu);
 355                 rip = kvm_rip_read(&svm->vcpu);
 356                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 357                 svm->int3_injected = rip - old_rip;
 358         }
 359
 360         svm->vmcb->control.event_inj = nr
 361                 | SVM_EVTINJ_VALID
 362                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 363                 | SVM_EVTINJ_TYPE_EXEPT;
 364         svm->vmcb->control.event_inj_err = error_code;
 365 }
 366
 367 static void svm_init_erratum_383(void)
 368 {
 369         u32 low, high;
 370         int err;
 371         u64 val;
 372
 373         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 374                 return;
 375
 376         /* Use _safe variants to not break nested virtualization */
 377         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 378         if (err)
 379                 return;
 380
 381         val |= (1ULL << 47);
 382
 383         low  = lower_32_bits(val);
 384         high = upper_32_bits(val);
 385
 386         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 387
 388         erratum_383_found = true;
 389 }
 390
 391 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 392 {
 393         /*
 394          * Guests should see errata 400 and 415 as fixed (assuming that
 395          * HLT and IO instructions are intercepted).
 396          */
 397         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 398         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 399
 400         /*
 401          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 402          * all osvw.status bits inside that length, including bit 0 (which is
 403          * reserved for erratum 298), are valid. However, if host processor's
 404          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 405          * be conservative here and therefore we tell the guest that erratum 298
 406          * is present (because we really don't know).
 407          */
 408         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 409                 vcpu->arch.osvw.status |= 1;
 410 }
 411
 412 static int has_svm(void)
 413 {
 414         const char *msg;
 415
 416         if (!cpu_has_svm(&msg)) {
 417                 printk(KERN_INFO "has_svm: %s\n", msg);
 418                 return 0;
 419         }
 420
 421         return 1;
 422 }
 423
 424 static void svm_hardware_disable(void)
 425 {
 426         /* Make sure we clean up behind us */
 427         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 428                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 429
 430         cpu_svm_disable();
 431
 432         amd_pmu_disable_virt();
 433 }
 434
 435 static int svm_hardware_enable(void)
 436 {
 437
 438         struct svm_cpu_data *sd;
 439         uint64_t efer;
 440         struct desc_struct *gdt;
 441         int me = raw_smp_processor_id();
 442
 443         rdmsrl(MSR_EFER, efer);
 444         if (efer & EFER_SVME)
 445                 return -EBUSY;
 446
 447         if (!has_svm()) {
 448                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 449                 return -EINVAL;
 450         }
 451         sd = per_cpu(svm_data, me);
 452         if (!sd) {
 453                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 454                 return -EINVAL;
 455         }
 456
 457         sd->asid_generation = 1;
 458         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 459         sd->next_asid = sd->max_asid + 1;
 460         sd->min_asid = max_sev_asid + 1;
 461
 462         gdt = get_current_gdt_rw();
 463         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 464
 465         wrmsrl(MSR_EFER, efer | EFER_SVME);
 466
 467         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 468
 469         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 470                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 471                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 472         }
 473
 474
 475         /*
 476          * Get OSVW bits.
 477          *
 478          * Note that it is possible to have a system with mixed processor
 479          * revisions and therefore different OSVW bits. If bits are not the same
 480          * on different processors then choose the worst case (i.e. if erratum
 481          * is present on one processor and not on another then assume that the
 482          * erratum is present everywhere).
 483          */
 484         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 485                 uint64_t len, status = 0;
 486                 int err;
 487
 488                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 489                 if (!err)
 490                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 491                                                       &err);
 492
 493                 if (err)
 494                         osvw_status = osvw_len = 0;
 495                 else {
 496                         if (len < osvw_len)
 497                                 osvw_len = len;
 498                         osvw_status |= status;
 499                         osvw_status &= (1ULL << osvw_len) - 1;
 500                 }
 501         } else
 502                 osvw_status = osvw_len = 0;
 503
 504         svm_init_erratum_383();
 505
 506         amd_pmu_enable_virt();
 507
 508         return 0;
 509 }
 510
 511 static void svm_cpu_uninit(int cpu)
 512 {
 513         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 514
 515         if (!sd)
 516                 return;
 517
 518         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 519         kfree(sd->sev_vmcbs);
 520         __free_page(sd->save_area);
 521         kfree(sd);
 522 }
 523
 524 static int svm_cpu_init(int cpu)
 525 {
 526         struct svm_cpu_data *sd;
 527
 528         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 529         if (!sd)
 530                 return -ENOMEM;
 531         sd->cpu = cpu;
 532         sd->save_area = alloc_page(GFP_KERNEL);
 533         if (!sd->save_area)
 534                 goto free_cpu_data;
 535
 536         if (svm_sev_enabled()) {
 537                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 538                                               sizeof(void *),
 539                                               GFP_KERNEL);
 540                 if (!sd->sev_vmcbs)
 541                         goto free_save_area;
 542         }
 543
 544         per_cpu(svm_data, cpu) = sd;
 545
 546         return 0;
 547
 548 free_save_area:
 549         __free_page(sd->save_area);
 550 free_cpu_data:
 551         kfree(sd);
 552         return -ENOMEM;
 553
 554 }
 555
 556 static bool valid_msr_intercept(u32 index)
 557 {
 558         int i;
 559
 560         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 561                 if (direct_access_msrs[i].index == index)
 562                         return true;
 563
 564         return false;
 565 }
 566
 567 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
 568 {
 569         u8 bit_write;
 570         unsigned long tmp;
 571         u32 offset;
 572         u32 *msrpm;
 573
 574         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 575                                       to_svm(vcpu)->msrpm;
 576
 577         offset    = svm_msrpm_offset(msr);
 578         bit_write = 2 * (msr & 0x0f) + 1;
 579         tmp       = msrpm[offset];
 580
 581         BUG_ON(offset == MSR_INVALID);
 582
 583         return !!test_bit(bit_write,  &tmp);
 584 }
 585
 586 static void set_msr_interception(u32 *msrpm, unsigned msr,
 587                                  int read, int write)
 588 {
 589         u8 bit_read, bit_write;
 590         unsigned long tmp;
 591         u32 offset;
 592
 593         /*
 594          * If this warning triggers extend the direct_access_msrs list at the
 595          * beginning of the file
 596          */
 597         WARN_ON(!valid_msr_intercept(msr));
 598
 599         offset    = svm_msrpm_offset(msr);
 600         bit_read  = 2 * (msr & 0x0f);
 601         bit_write = 2 * (msr & 0x0f) + 1;
 602         tmp       = msrpm[offset];
 603
 604         BUG_ON(offset == MSR_INVALID);
 605
 606         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 607         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 608
 609         msrpm[offset] = tmp;
 610 }
 611
 612 static void svm_vcpu_init_msrpm(u32 *msrpm)
 613 {
 614         int i;
 615
 616         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 617
 618         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 619                 if (!direct_access_msrs[i].always)
 620                         continue;
 621
 622                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 623         }
 624 }
 625
 626 static void add_msr_offset(u32 offset)
 627 {
 628         int i;
 629
 630         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 631
 632                 /* Offset already in list? */
 633                 if (msrpm_offsets[i] == offset)
 634                         return;
 635
 636                 /* Slot used by another offset? */
 637                 if (msrpm_offsets[i] != MSR_INVALID)
 638                         continue;
 639
 640                 /* Add offset to list */
 641                 msrpm_offsets[i] = offset;
 642
 643                 return;
 644         }
 645
 646         /*
 647          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 648          * increase MSRPM_OFFSETS in this case.
 649          */
 650         BUG();
 651 }
 652
 653 static void init_msrpm_offsets(void)
 654 {
 655         int i;
 656
 657         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 658
 659         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 660                 u32 offset;
 661
 662                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 663                 BUG_ON(offset == MSR_INVALID);
 664
 665                 add_msr_offset(offset);
 666         }
 667 }
 668
 669 static void svm_enable_lbrv(struct vcpu_svm *svm)
 670 {
 671         u32 *msrpm = svm->msrpm;
 672
 673         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 674         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 675         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 676         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 677         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 678 }
 679
 680 static void svm_disable_lbrv(struct vcpu_svm *svm)
 681 {
 682         u32 *msrpm = svm->msrpm;
 683
 684         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 685         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 686         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 687         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 688         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 689 }
 690
 691 void disable_nmi_singlestep(struct vcpu_svm *svm)
 692 {
 693         svm->nmi_singlestep = false;
 694
 695         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 696                 /* Clear our flags if they were not set by the guest */
 697                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 698                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 699                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 700                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 701         }
 702 }
 703
 704 static void grow_ple_window(struct kvm_vcpu *vcpu)
 705 {
 706         struct vcpu_svm *svm = to_svm(vcpu);
 707         struct vmcb_control_area *control = &svm->vmcb->control;
 708         int old = control->pause_filter_count;
 709
 710         control->pause_filter_count = __grow_ple_window(old,
 711                                                         pause_filter_count,
 712                                                         pause_filter_count_grow,
 713                                                         pause_filter_count_max);
 714
 715         if (control->pause_filter_count != old) {
 716                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 717                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 718                                             control->pause_filter_count, old);
 719         }
 720 }
 721
 722 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 723 {
 724         struct vcpu_svm *svm = to_svm(vcpu);
 725         struct vmcb_control_area *control = &svm->vmcb->control;
 726         int old = control->pause_filter_count;
 727
 728         control->pause_filter_count =
 729                                 __shrink_ple_window(old,
 730                                                     pause_filter_count,
 731                                                     pause_filter_count_shrink,
 732                                                     pause_filter_count);
 733         if (control->pause_filter_count != old) {
 734                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 735                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 736                                             control->pause_filter_count, old);
 737         }
 738 }
 739
 740 /*
 741  * The default MMIO mask is a single bit (excluding the present bit),
 742  * which could conflict with the memory encryption bit. Check for
 743  * memory encryption support and override the default MMIO mask if
 744  * memory encryption is enabled.
 745  */
 746 static __init void svm_adjust_mmio_mask(void)
 747 {
 748         unsigned int enc_bit, mask_bit;
 749         u64 msr, mask;
 750
 751         /* If there is no memory encryption support, use existing mask */
 752         if (cpuid_eax(0x80000000) < 0x8000001f)
 753                 return;
 754
 755         /* If memory encryption is not enabled, use existing mask */
 756         rdmsrl(MSR_K8_SYSCFG, msr);
 757         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 758                 return;
 759
 760         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 761         mask_bit = boot_cpu_data.x86_phys_bits;
 762
 763         /* Increment the mask bit if it is the same as the encryption bit */
 764         if (enc_bit == mask_bit)
 765                 mask_bit++;
 766
 767         /*
 768          * If the mask bit location is below 52, then some bits above the
 769          * physical addressing limit will always be reserved, so use the
 770          * rsvd_bits() function to generate the mask. This mask, along with
 771          * the present bit, will be used to generate a page fault with
 772          * PFER.RSV = 1.
 773          *
 774          * If the mask bit location is 52 (or above), then clear the mask.
 775          */
 776         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 777
 778         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 779 }
 780
 781 static void svm_hardware_teardown(void)
 782 {
 783         int cpu;
 784
 785         if (svm_sev_enabled())
 786                 sev_hardware_teardown();
 787
 788         for_each_possible_cpu(cpu)
 789                 svm_cpu_uninit(cpu);
 790
 791         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 792         iopm_base = 0;
 793 }
 794
 795 static __init void svm_set_cpu_caps(void)
 796 {
 797         kvm_set_cpu_caps();
 798
 799         supported_xss = 0;
 800
 801         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 802         if (nested) {
 803                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 804
 805                 if (nrips)
 806                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 807
 808                 if (npt_enabled)
 809                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 810         }
 811
 812         /* CPUID 0x80000008 */
 813         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 814             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 815                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 816 }
 817
 818 static __init int svm_hardware_setup(void)
 819 {
 820         int cpu;
 821         struct page *iopm_pages;
 822         void *iopm_va;
 823         int r;
 824
 825         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 826
 827         if (!iopm_pages)
 828                 return -ENOMEM;
 829
 830         iopm_va = page_address(iopm_pages);
 831         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 832         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 833
 834         init_msrpm_offsets();
 835
 836         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 837
 838         if (boot_cpu_has(X86_FEATURE_NX))
 839                 kvm_enable_efer_bits(EFER_NX);
 840
 841         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 842                 kvm_enable_efer_bits(EFER_FFXSR);
 843
 844         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 845                 kvm_has_tsc_control = true;
 846                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 847                 kvm_tsc_scaling_ratio_frac_bits = 32;
 848         }
 849
 850         /* Check for pause filtering support */
 851         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 852                 pause_filter_count = 0;
 853                 pause_filter_thresh = 0;
 854         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 855                 pause_filter_thresh = 0;
 856         }
 857
 858         if (nested) {
 859                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 860                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 861         }
 862
 863         if (sev) {
 864                 if (boot_cpu_has(X86_FEATURE_SEV) &&
 865                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
 866                         r = sev_hardware_setup();
 867                         if (r)
 868                                 sev = false;
 869                 } else {
 870                         sev = false;
 871                 }
 872         }
 873
 874         svm_adjust_mmio_mask();
 875
 876         for_each_possible_cpu(cpu) {
 877                 r = svm_cpu_init(cpu);
 878                 if (r)
 879                         goto err;
 880         }
 881
 882         if (!boot_cpu_has(X86_FEATURE_NPT))
 883                 npt_enabled = false;
 884
 885         if (npt_enabled && !npt)
 886                 npt_enabled = false;
 887
 888         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 889         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 890
 891         if (nrips) {
 892                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
 893                         nrips = false;
 894         }
 895
 896         if (avic) {
 897                 if (!npt_enabled ||
 898                     !boot_cpu_has(X86_FEATURE_AVIC) ||
 899                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
 900                         avic = false;
 901                 } else {
 902                         pr_info("AVIC enabled\n");
 903
 904                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
 905                 }
 906         }
 907
 908         if (vls) {
 909                 if (!npt_enabled ||
 910                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
 911                     !IS_ENABLED(CONFIG_X86_64)) {
 912                         vls = false;
 913                 } else {
 914                         pr_info("Virtual VMLOAD VMSAVE supported\n");
 915                 }
 916         }
 917
 918         if (vgif) {
 919                 if (!boot_cpu_has(X86_FEATURE_VGIF))
 920                         vgif = false;
 921                 else
 922                         pr_info("Virtual GIF supported\n");
 923         }
 924
 925         svm_set_cpu_caps();
 926
 927         /*
 928          * It seems that on AMD processors PTE's accessed bit is
 929          * being set by the CPU hardware before the NPF vmexit.
 930          * This is not expected behaviour and our tests fail because
 931          * of it.
 932          * A workaround here is to disable support for
 933          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
 934          * In this case userspace can know if there is support using
 935          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
 936          * it
 937          * If future AMD CPU models change the behaviour described above,
 938          * this variable can be changed accordingly
 939          */
 940         allow_smaller_maxphyaddr = !npt_enabled;
 941
 942         return 0;
 943
 944 err:
 945         svm_hardware_teardown();
 946         return r;
 947 }
 948
 949 static void init_seg(struct vmcb_seg *seg)
 950 {
 951         seg->selector = 0;
 952         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 953                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 954         seg->limit = 0xffff;
 955         seg->base = 0;
 956 }
 957
 958 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 959 {
 960         seg->selector = 0;
 961         seg->attrib = SVM_SELECTOR_P_MASK | type;
 962         seg->limit = 0xffff;
 963         seg->base = 0;
 964 }
 965
 966 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969         u64 g_tsc_offset = 0;
 970
 971         if (is_guest_mode(vcpu)) {
 972                 /* Write L1's TSC offset.  */
 973                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 974                                svm->nested.hsave->control.tsc_offset;
 975                 svm->nested.hsave->control.tsc_offset = offset;
 976         }
 977
 978         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
 979                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
 980                                    offset);
 981
 982         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 983
 984         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 985         return svm->vmcb->control.tsc_offset;
 986 }
 987
 988 static void init_vmcb(struct vcpu_svm *svm)
 989 {
 990         struct vmcb_control_area *control = &svm->vmcb->control;
 991         struct vmcb_save_area *save = &svm->vmcb->save;
 992
 993         svm->vcpu.arch.hflags = 0;
 994
 995         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 996         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 997         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 998         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 999         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1000         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1001         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1002                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1003
1004         set_dr_intercepts(svm);
1005
1006         set_exception_intercept(svm, PF_VECTOR);
1007         set_exception_intercept(svm, UD_VECTOR);
1008         set_exception_intercept(svm, MC_VECTOR);
1009         set_exception_intercept(svm, AC_VECTOR);
1010         set_exception_intercept(svm, DB_VECTOR);
1011         /*
1012          * Guest access to VMware backdoor ports could legitimately
1013          * trigger #GP because of TSS I/O permission bitmap.
1014          * We intercept those #GP and allow access to them anyway
1015          * as VMware does.
1016          */
1017         if (enable_vmware_backdoor)
1018                 set_exception_intercept(svm, GP_VECTOR);
1019
1020         svm_set_intercept(svm, INTERCEPT_INTR);
1021         svm_set_intercept(svm, INTERCEPT_NMI);
1022         svm_set_intercept(svm, INTERCEPT_SMI);
1023         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1024         svm_set_intercept(svm, INTERCEPT_RDPMC);
1025         svm_set_intercept(svm, INTERCEPT_CPUID);
1026         svm_set_intercept(svm, INTERCEPT_INVD);
1027         svm_set_intercept(svm, INTERCEPT_INVLPG);
1028         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1029         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1030         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1031         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1032         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1033         svm_set_intercept(svm, INTERCEPT_VMRUN);
1034         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1035         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1036         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1037         svm_set_intercept(svm, INTERCEPT_STGI);
1038         svm_set_intercept(svm, INTERCEPT_CLGI);
1039         svm_set_intercept(svm, INTERCEPT_SKINIT);
1040         svm_set_intercept(svm, INTERCEPT_WBINVD);
1041         svm_set_intercept(svm, INTERCEPT_XSETBV);
1042         svm_set_intercept(svm, INTERCEPT_RDPRU);
1043         svm_set_intercept(svm, INTERCEPT_RSM);
1044
1045         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1046                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1047                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1048         }
1049
1050         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1051                 svm_set_intercept(svm, INTERCEPT_HLT);
1052
1053         control->iopm_base_pa = __sme_set(iopm_base);
1054         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1055         control->int_ctl = V_INTR_MASKING_MASK;
1056
1057         init_seg(&save->es);
1058         init_seg(&save->ss);
1059         init_seg(&save->ds);
1060         init_seg(&save->fs);
1061         init_seg(&save->gs);
1062
1063         save->cs.selector = 0xf000;
1064         save->cs.base = 0xffff0000;
1065         /* Executable/Readable Code Segment */
1066         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1067                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1068         save->cs.limit = 0xffff;
1069
1070         save->gdtr.limit = 0xffff;
1071         save->idtr.limit = 0xffff;
1072
1073         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1074         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1075
1076         svm_set_efer(&svm->vcpu, 0);
1077         save->dr6 = 0xffff0ff0;
1078         kvm_set_rflags(&svm->vcpu, 2);
1079         save->rip = 0x0000fff0;
1080         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1081
1082         /*
1083          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1084          * It also updates the guest-visible cr0 value.
1085          */
1086         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1087         kvm_mmu_reset_context(&svm->vcpu);
1088
1089         save->cr4 = X86_CR4_PAE;
1090         /* rdx = ?? */
1091
1092         if (npt_enabled) {
1093                 /* Setup VMCB for Nested Paging */
1094                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1095                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1096                 clr_exception_intercept(svm, PF_VECTOR);
1097                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1098                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1099                 save->g_pat = svm->vcpu.arch.pat;
1100                 save->cr3 = 0;
1101                 save->cr4 = 0;
1102         }
1103         svm->asid_generation = 0;
1104
1105         svm->nested.vmcb = 0;
1106         svm->vcpu.arch.hflags = 0;
1107
1108         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1109                 control->pause_filter_count = pause_filter_count;
1110                 if (pause_filter_thresh)
1111                         control->pause_filter_thresh = pause_filter_thresh;
1112                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1113         } else {
1114                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1115         }
1116
1117         if (kvm_vcpu_apicv_active(&svm->vcpu))
1118                 avic_init_vmcb(svm);
1119
1120         /*
1121          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1122          * in VMCB and clear intercepts to avoid #VMEXIT.
1123          */
1124         if (vls) {
1125                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1126                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1127                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1128         }
1129
1130         if (vgif) {
1131                 svm_clr_intercept(svm, INTERCEPT_STGI);
1132                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1133                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1134         }
1135
1136         if (sev_guest(svm->vcpu.kvm)) {
1137                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1138                 clr_exception_intercept(svm, UD_VECTOR);
1139         }
1140
1141         vmcb_mark_all_dirty(svm->vmcb);
1142
1143         enable_gif(svm);
1144
1145 }
1146
1147 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1148 {
1149         struct vcpu_svm *svm = to_svm(vcpu);
1150         u32 dummy;
1151         u32 eax = 1;
1152
1153         svm->spec_ctrl = 0;
1154         svm->virt_spec_ctrl = 0;
1155
1156         if (!init_event) {
1157                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1158                                            MSR_IA32_APICBASE_ENABLE;
1159                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1160                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1161         }
1162         init_vmcb(svm);
1163
1164         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1165         kvm_rdx_write(vcpu, eax);
1166
1167         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1168                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1169 }
1170
1171 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1172 {
1173         struct vcpu_svm *svm;
1174         struct page *page;
1175         struct page *msrpm_pages;
1176         struct page *hsave_page;
1177         struct page *nested_msrpm_pages;
1178         int err;
1179
1180         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1181         svm = to_svm(vcpu);
1182
1183         err = -ENOMEM;
1184         page = alloc_page(GFP_KERNEL_ACCOUNT);
1185         if (!page)
1186                 goto out;
1187
1188         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1189         if (!msrpm_pages)
1190                 goto free_page1;
1191
1192         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1193         if (!nested_msrpm_pages)
1194                 goto free_page2;
1195
1196         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
1197         if (!hsave_page)
1198                 goto free_page3;
1199
1200         err = avic_init_vcpu(svm);
1201         if (err)
1202                 goto free_page4;
1203
1204         /* We initialize this flag to true to make sure that the is_running
1205          * bit would be set the first time the vcpu is loaded.
1206          */
1207         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1208                 svm->avic_is_running = true;
1209
1210         svm->nested.hsave = page_address(hsave_page);
1211         clear_page(svm->nested.hsave);
1212
1213         svm->msrpm = page_address(msrpm_pages);
1214         svm_vcpu_init_msrpm(svm->msrpm);
1215
1216         svm->nested.msrpm = page_address(nested_msrpm_pages);
1217         svm_vcpu_init_msrpm(svm->nested.msrpm);
1218
1219         svm->vmcb = page_address(page);
1220         clear_page(svm->vmcb);
1221         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1222         svm->asid_generation = 0;
1223         init_vmcb(svm);
1224
1225         svm_init_osvw(vcpu);
1226         vcpu->arch.microcode_version = 0x01000065;
1227
1228         return 0;
1229
1230 free_page4:
1231         __free_page(hsave_page);
1232 free_page3:
1233         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1234 free_page2:
1235         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1236 free_page1:
1237         __free_page(page);
1238 out:
1239         return err;
1240 }
1241
1242 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1243 {
1244         int i;
1245
1246         for_each_online_cpu(i)
1247                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1248 }
1249
1250 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1251 {
1252         struct vcpu_svm *svm = to_svm(vcpu);
1253
1254         /*
1255          * The vmcb page can be recycled, causing a false negative in
1256          * svm_vcpu_load(). So, ensure that no logical CPU has this
1257          * vmcb page recorded as its current vmcb.
1258          */
1259         svm_clear_current_vmcb(svm->vmcb);
1260
1261         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1262         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1263         __free_page(virt_to_page(svm->nested.hsave));
1264         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1265 }
1266
1267 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1268 {
1269         struct vcpu_svm *svm = to_svm(vcpu);
1270         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1271         int i;
1272
1273         if (unlikely(cpu != vcpu->cpu)) {
1274                 svm->asid_generation = 0;
1275                 vmcb_mark_all_dirty(svm->vmcb);
1276         }
1277
1278 #ifdef CONFIG_X86_64
1279         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1280 #endif
1281         savesegment(fs, svm->host.fs);
1282         savesegment(gs, svm->host.gs);
1283         svm->host.ldt = kvm_read_ldt();
1284
1285         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1286                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1287
1288         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1289                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1290                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1291                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1292                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1293                 }
1294         }
1295         /* This assumes that the kernel never uses MSR_TSC_AUX */
1296         if (static_cpu_has(X86_FEATURE_RDTSCP))
1297                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1298
1299         if (sd->current_vmcb != svm->vmcb) {
1300                 sd->current_vmcb = svm->vmcb;
1301                 indirect_branch_prediction_barrier();
1302         }
1303         avic_vcpu_load(vcpu, cpu);
1304 }
1305
1306 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1307 {
1308         struct vcpu_svm *svm = to_svm(vcpu);
1309         int i;
1310
1311         avic_vcpu_put(vcpu);
1312
1313         ++vcpu->stat.host_state_reload;
1314         kvm_load_ldt(svm->host.ldt);
1315 #ifdef CONFIG_X86_64
1316         loadsegment(fs, svm->host.fs);
1317         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1318         load_gs_index(svm->host.gs);
1319 #else
1320 #ifdef CONFIG_X86_32_LAZY_GS
1321         loadsegment(gs, svm->host.gs);
1322 #endif
1323 #endif
1324         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1325                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1326 }
1327
1328 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1329 {
1330         struct vcpu_svm *svm = to_svm(vcpu);
1331         unsigned long rflags = svm->vmcb->save.rflags;
1332
1333         if (svm->nmi_singlestep) {
1334                 /* Hide our flags if they were not set by the guest */
1335                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1336                         rflags &= ~X86_EFLAGS_TF;
1337                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1338                         rflags &= ~X86_EFLAGS_RF;
1339         }
1340         return rflags;
1341 }
1342
1343 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1344 {
1345         if (to_svm(vcpu)->nmi_singlestep)
1346                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1347
1348        /*
1349         * Any change of EFLAGS.VM is accompanied by a reload of SS
1350         * (caused by either a task switch or an inter-privilege IRET),
1351         * so we do not need to update the CPL here.
1352         */
1353         to_svm(vcpu)->vmcb->save.rflags = rflags;
1354 }
1355
1356 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1357 {
1358         switch (reg) {
1359         case VCPU_EXREG_PDPTR:
1360                 BUG_ON(!npt_enabled);
1361                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1362                 break;
1363         default:
1364                 WARN_ON_ONCE(1);
1365         }
1366 }
1367
1368 static void svm_set_vintr(struct vcpu_svm *svm)
1369 {
1370         struct vmcb_control_area *control;
1371
1372         /* The following fields are ignored when AVIC is enabled */
1373         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1374         svm_set_intercept(svm, INTERCEPT_VINTR);
1375
1376         /*
1377          * This is just a dummy VINTR to actually cause a vmexit to happen.
1378          * Actual injection of virtual interrupts happens through EVENTINJ.
1379          */
1380         control = &svm->vmcb->control;
1381         control->int_vector = 0x0;
1382         control->int_ctl &= ~V_INTR_PRIO_MASK;
1383         control->int_ctl |= V_IRQ_MASK |
1384                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1385         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1386 }
1387
1388 static void svm_clear_vintr(struct vcpu_svm *svm)
1389 {
1390         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1391         svm_clr_intercept(svm, INTERCEPT_VINTR);
1392
1393         /* Drop int_ctl fields related to VINTR injection.  */
1394         svm->vmcb->control.int_ctl &= mask;
1395         if (is_guest_mode(&svm->vcpu)) {
1396                 svm->nested.hsave->control.int_ctl &= mask;
1397
1398                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1399                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1400                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1401         }
1402
1403         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1404 }
1405
1406 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1407 {
1408         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1409
1410         switch (seg) {
1411         case VCPU_SREG_CS: return &save->cs;
1412         case VCPU_SREG_DS: return &save->ds;
1413         case VCPU_SREG_ES: return &save->es;
1414         case VCPU_SREG_FS: return &save->fs;
1415         case VCPU_SREG_GS: return &save->gs;
1416         case VCPU_SREG_SS: return &save->ss;
1417         case VCPU_SREG_TR: return &save->tr;
1418         case VCPU_SREG_LDTR: return &save->ldtr;
1419         }
1420         BUG();
1421         return NULL;
1422 }
1423
1424 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1425 {
1426         struct vmcb_seg *s = svm_seg(vcpu, seg);
1427
1428         return s->base;
1429 }
1430
1431 static void svm_get_segment(struct kvm_vcpu *vcpu,
1432                             struct kvm_segment *var, int seg)
1433 {
1434         struct vmcb_seg *s = svm_seg(vcpu, seg);
1435
1436         var->base = s->base;
1437         var->limit = s->limit;
1438         var->selector = s->selector;
1439         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1440         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1441         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1442         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1443         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1444         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1445         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1446
1447         /*
1448          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1449          * However, the SVM spec states that the G bit is not observed by the
1450          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1451          * So let's synthesize a legal G bit for all segments, this helps
1452          * running KVM nested. It also helps cross-vendor migration, because
1453          * Intel's vmentry has a check on the 'G' bit.
1454          */
1455         var->g = s->limit > 0xfffff;
1456
1457         /*
1458          * AMD's VMCB does not have an explicit unusable field, so emulate it
1459          * for cross vendor migration purposes by "not present"
1460          */
1461         var->unusable = !var->present;
1462
1463         switch (seg) {
1464         case VCPU_SREG_TR:
1465                 /*
1466                  * Work around a bug where the busy flag in the tr selector
1467                  * isn't exposed
1468                  */
1469                 var->type |= 0x2;
1470                 break;
1471         case VCPU_SREG_DS:
1472         case VCPU_SREG_ES:
1473         case VCPU_SREG_FS:
1474         case VCPU_SREG_GS:
1475                 /*
1476                  * The accessed bit must always be set in the segment
1477                  * descriptor cache, although it can be cleared in the
1478                  * descriptor, the cached bit always remains at 1. Since
1479                  * Intel has a check on this, set it here to support
1480                  * cross-vendor migration.
1481                  */
1482                 if (!var->unusable)
1483                         var->type |= 0x1;
1484                 break;
1485         case VCPU_SREG_SS:
1486                 /*
1487                  * On AMD CPUs sometimes the DB bit in the segment
1488                  * descriptor is left as 1, although the whole segment has
1489                  * been made unusable. Clear it here to pass an Intel VMX
1490                  * entry check when cross vendor migrating.
1491                  */
1492                 if (var->unusable)
1493                         var->db = 0;
1494                 /* This is symmetric with svm_set_segment() */
1495                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1496                 break;
1497         }
1498 }
1499
1500 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1501 {
1502         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1503
1504         return save->cpl;
1505 }
1506
1507 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1508 {
1509         struct vcpu_svm *svm = to_svm(vcpu);
1510
1511         dt->size = svm->vmcb->save.idtr.limit;
1512         dt->address = svm->vmcb->save.idtr.base;
1513 }
1514
1515 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1516 {
1517         struct vcpu_svm *svm = to_svm(vcpu);
1518
1519         svm->vmcb->save.idtr.limit = dt->size;
1520         svm->vmcb->save.idtr.base = dt->address ;
1521         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1522 }
1523
1524 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1525 {
1526         struct vcpu_svm *svm = to_svm(vcpu);
1527
1528         dt->size = svm->vmcb->save.gdtr.limit;
1529         dt->address = svm->vmcb->save.gdtr.base;
1530 }
1531
1532 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1533 {
1534         struct vcpu_svm *svm = to_svm(vcpu);
1535
1536         svm->vmcb->save.gdtr.limit = dt->size;
1537         svm->vmcb->save.gdtr.base = dt->address ;
1538         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1539 }
1540
1541 static void update_cr0_intercept(struct vcpu_svm *svm)
1542 {
1543         ulong gcr0 = svm->vcpu.arch.cr0;
1544         u64 *hcr0 = &svm->vmcb->save.cr0;
1545
1546         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1547                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1548
1549         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1550
1551         if (gcr0 == *hcr0) {
1552                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1553                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1554         } else {
1555                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1556                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1557         }
1558 }
1559
1560 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1561 {
1562         struct vcpu_svm *svm = to_svm(vcpu);
1563
1564 #ifdef CONFIG_X86_64
1565         if (vcpu->arch.efer & EFER_LME) {
1566                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1567                         vcpu->arch.efer |= EFER_LMA;
1568                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1569                 }
1570
1571                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1572                         vcpu->arch.efer &= ~EFER_LMA;
1573                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1574                 }
1575         }
1576 #endif
1577         vcpu->arch.cr0 = cr0;
1578
1579         if (!npt_enabled)
1580                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1581
1582         /*
1583          * re-enable caching here because the QEMU bios
1584          * does not do it - this results in some delay at
1585          * reboot
1586          */
1587         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1588                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1589         svm->vmcb->save.cr0 = cr0;
1590         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1591         update_cr0_intercept(svm);
1592 }
1593
1594 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1595 {
1596         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1597         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1598
1599         if (cr4 & X86_CR4_VMXE)
1600                 return 1;
1601
1602         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1603                 svm_flush_tlb(vcpu);
1604
1605         vcpu->arch.cr4 = cr4;
1606         if (!npt_enabled)
1607                 cr4 |= X86_CR4_PAE;
1608         cr4 |= host_cr4_mce;
1609         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1610         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1611         return 0;
1612 }
1613
1614 static void svm_set_segment(struct kvm_vcpu *vcpu,
1615                             struct kvm_segment *var, int seg)
1616 {
1617         struct vcpu_svm *svm = to_svm(vcpu);
1618         struct vmcb_seg *s = svm_seg(vcpu, seg);
1619
1620         s->base = var->base;
1621         s->limit = var->limit;
1622         s->selector = var->selector;
1623         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1624         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1625         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1626         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1627         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1628         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1629         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1630         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1631
1632         /*
1633          * This is always accurate, except if SYSRET returned to a segment
1634          * with SS.DPL != 3.  Intel does not have this quirk, and always
1635          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1636          * would entail passing the CPL to userspace and back.
1637          */
1638         if (seg == VCPU_SREG_SS)
1639                 /* This is symmetric with svm_get_segment() */
1640                 svm->vmcb->save.cpl = (var->dpl & 3);
1641
1642         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1643 }
1644
1645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1646 {
1647         struct vcpu_svm *svm = to_svm(vcpu);
1648
1649         clr_exception_intercept(svm, BP_VECTOR);
1650
1651         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1652                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1653                         set_exception_intercept(svm, BP_VECTOR);
1654         }
1655 }
1656
1657 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1658 {
1659         if (sd->next_asid > sd->max_asid) {
1660                 ++sd->asid_generation;
1661                 sd->next_asid = sd->min_asid;
1662                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1663         }
1664
1665         svm->asid_generation = sd->asid_generation;
1666         svm->vmcb->control.asid = sd->next_asid++;
1667
1668         vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1669 }
1670
1671 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1672 {
1673         struct vmcb *vmcb = svm->vmcb;
1674
1675         if (unlikely(value != vmcb->save.dr6)) {
1676                 vmcb->save.dr6 = value;
1677                 vmcb_mark_dirty(vmcb, VMCB_DR);
1678         }
1679 }
1680
1681 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1682 {
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684
1685         get_debugreg(vcpu->arch.db[0], 0);
1686         get_debugreg(vcpu->arch.db[1], 1);
1687         get_debugreg(vcpu->arch.db[2], 2);
1688         get_debugreg(vcpu->arch.db[3], 3);
1689         /*
1690          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1691          * because db_interception might need it.  We can do it before vmentry.
1692          */
1693         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1694         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1695         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1696         set_dr_intercepts(svm);
1697 }
1698
1699 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1700 {
1701         struct vcpu_svm *svm = to_svm(vcpu);
1702
1703         svm->vmcb->save.dr7 = value;
1704         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1705 }
1706
1707 static int pf_interception(struct vcpu_svm *svm)
1708 {
1709         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1710         u64 error_code = svm->vmcb->control.exit_info_1;
1711
1712         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1713                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1714                         svm->vmcb->control.insn_bytes : NULL,
1715                         svm->vmcb->control.insn_len);
1716 }
1717
1718 static int npf_interception(struct vcpu_svm *svm)
1719 {
1720         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1721         u64 error_code = svm->vmcb->control.exit_info_1;
1722
1723         trace_kvm_page_fault(fault_address, error_code);
1724         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1725                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1726                         svm->vmcb->control.insn_bytes : NULL,
1727                         svm->vmcb->control.insn_len);
1728 }
1729
1730 static int db_interception(struct vcpu_svm *svm)
1731 {
1732         struct kvm_run *kvm_run = svm->vcpu.run;
1733         struct kvm_vcpu *vcpu = &svm->vcpu;
1734
1735         if (!(svm->vcpu.guest_debug &
1736               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1737                 !svm->nmi_singlestep) {
1738                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1739                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1740                 return 1;
1741         }
1742
1743         if (svm->nmi_singlestep) {
1744                 disable_nmi_singlestep(svm);
1745                 /* Make sure we check for pending NMIs upon entry */
1746                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1747         }
1748
1749         if (svm->vcpu.guest_debug &
1750             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1751                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1752                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1753                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1754                 kvm_run->debug.arch.pc =
1755                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1756                 kvm_run->debug.arch.exception = DB_VECTOR;
1757                 return 0;
1758         }
1759
1760         return 1;
1761 }
1762
1763 static int bp_interception(struct vcpu_svm *svm)
1764 {
1765         struct kvm_run *kvm_run = svm->vcpu.run;
1766
1767         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1768         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1769         kvm_run->debug.arch.exception = BP_VECTOR;
1770         return 0;
1771 }
1772
1773 static int ud_interception(struct vcpu_svm *svm)
1774 {
1775         return handle_ud(&svm->vcpu);
1776 }
1777
1778 static int ac_interception(struct vcpu_svm *svm)
1779 {
1780         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1781         return 1;
1782 }
1783
1784 static int gp_interception(struct vcpu_svm *svm)
1785 {
1786         struct kvm_vcpu *vcpu = &svm->vcpu;
1787         u32 error_code = svm->vmcb->control.exit_info_1;
1788
1789         WARN_ON_ONCE(!enable_vmware_backdoor);
1790
1791         /*
1792          * VMware backdoor emulation on #GP interception only handles IN{S},
1793          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1794          */
1795         if (error_code) {
1796                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1797                 return 1;
1798         }
1799         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1800 }
1801
1802 static bool is_erratum_383(void)
1803 {
1804         int err, i;
1805         u64 value;
1806
1807         if (!erratum_383_found)
1808                 return false;
1809
1810         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1811         if (err)
1812                 return false;
1813
1814         /* Bit 62 may or may not be set for this mce */
1815         value &= ~(1ULL << 62);
1816
1817         if (value != 0xb600000000010015ULL)
1818                 return false;
1819
1820         /* Clear MCi_STATUS registers */
1821         for (i = 0; i < 6; ++i)
1822                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1823
1824         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1825         if (!err) {
1826                 u32 low, high;
1827
1828                 value &= ~(1ULL << 2);
1829                 low    = lower_32_bits(value);
1830                 high   = upper_32_bits(value);
1831
1832                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1833         }
1834
1835         /* Flush tlb to evict multi-match entries */
1836         __flush_tlb_all();
1837
1838         return true;
1839 }
1840
1841 /*
1842  * Trigger machine check on the host. We assume all the MSRs are already set up
1843  * by the CPU and that we still run on the same CPU as the MCE occurred on.
1844  * We pass a fake environment to the machine check handler because we want
1845  * the guest to be always treated like user space, no matter what context
1846  * it used internally.
1847  */
1848 static void kvm_machine_check(void)
1849 {
1850 #if defined(CONFIG_X86_MCE)
1851         struct pt_regs regs = {
1852                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1853                 .flags = X86_EFLAGS_IF,
1854         };
1855
1856         do_machine_check(&regs);
1857 #endif
1858 }
1859
1860 static void svm_handle_mce(struct vcpu_svm *svm)
1861 {
1862         if (is_erratum_383()) {
1863                 /*
1864                  * Erratum 383 triggered. Guest state is corrupt so kill the
1865                  * guest.
1866                  */
1867                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1868
1869                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1870
1871                 return;
1872         }
1873
1874         /*
1875          * On an #MC intercept the MCE handler is not called automatically in
1876          * the host. So do it by hand here.
1877          */
1878         kvm_machine_check();
1879 }
1880
1881 static int mc_interception(struct vcpu_svm *svm)
1882 {
1883         return 1;
1884 }
1885
1886 static int shutdown_interception(struct vcpu_svm *svm)
1887 {
1888         struct kvm_run *kvm_run = svm->vcpu.run;
1889
1890         /*
1891          * VMCB is undefined after a SHUTDOWN intercept
1892          * so reinitialize it.
1893          */
1894         clear_page(svm->vmcb);
1895         init_vmcb(svm);
1896
1897         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1898         return 0;
1899 }
1900
1901 static int io_interception(struct vcpu_svm *svm)
1902 {
1903         struct kvm_vcpu *vcpu = &svm->vcpu;
1904         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1905         int size, in, string;
1906         unsigned port;
1907
1908         ++svm->vcpu.stat.io_exits;
1909         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1910         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1911         if (string)
1912                 return kvm_emulate_instruction(vcpu, 0);
1913
1914         port = io_info >> 16;
1915         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1916         svm->next_rip = svm->vmcb->control.exit_info_2;
1917
1918         return kvm_fast_pio(&svm->vcpu, size, port, in);
1919 }
1920
1921 static int nmi_interception(struct vcpu_svm *svm)
1922 {
1923         return 1;
1924 }
1925
1926 static int intr_interception(struct vcpu_svm *svm)
1927 {
1928         ++svm->vcpu.stat.irq_exits;
1929         return 1;
1930 }
1931
1932 static int nop_on_interception(struct vcpu_svm *svm)
1933 {
1934         return 1;
1935 }
1936
1937 static int halt_interception(struct vcpu_svm *svm)
1938 {
1939         return kvm_emulate_halt(&svm->vcpu);
1940 }
1941
1942 static int vmmcall_interception(struct vcpu_svm *svm)
1943 {
1944         return kvm_emulate_hypercall(&svm->vcpu);
1945 }
1946
1947 static int vmload_interception(struct vcpu_svm *svm)
1948 {
1949         struct vmcb *nested_vmcb;
1950         struct kvm_host_map map;
1951         int ret;
1952
1953         if (nested_svm_check_permissions(svm))
1954                 return 1;
1955
1956         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1957         if (ret) {
1958                 if (ret == -EINVAL)
1959                         kvm_inject_gp(&svm->vcpu, 0);
1960                 return 1;
1961         }
1962
1963         nested_vmcb = map.hva;
1964
1965         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1966
1967         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1968         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1969
1970         return ret;
1971 }
1972
1973 static int vmsave_interception(struct vcpu_svm *svm)
1974 {
1975         struct vmcb *nested_vmcb;
1976         struct kvm_host_map map;
1977         int ret;
1978
1979         if (nested_svm_check_permissions(svm))
1980                 return 1;
1981
1982         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1983         if (ret) {
1984                 if (ret == -EINVAL)
1985                         kvm_inject_gp(&svm->vcpu, 0);
1986                 return 1;
1987         }
1988
1989         nested_vmcb = map.hva;
1990
1991         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1992
1993         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1994         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1995
1996         return ret;
1997 }
1998
1999 static int vmrun_interception(struct vcpu_svm *svm)
2000 {
2001         if (nested_svm_check_permissions(svm))
2002                 return 1;
2003
2004         return nested_svm_vmrun(svm);
2005 }
2006
2007 void svm_set_gif(struct vcpu_svm *svm, bool value)
2008 {
2009         if (value) {
2010                 /*
2011                  * If VGIF is enabled, the STGI intercept is only added to
2012                  * detect the opening of the SMI/NMI window; remove it now.
2013                  * Likewise, clear the VINTR intercept, we will set it
2014                  * again while processing KVM_REQ_EVENT if needed.
2015                  */
2016                 if (vgif_enabled(svm))
2017                         svm_clr_intercept(svm, INTERCEPT_STGI);
2018                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2019                         svm_clear_vintr(svm);
2020
2021                 enable_gif(svm);
2022                 if (svm->vcpu.arch.smi_pending ||
2023                     svm->vcpu.arch.nmi_pending ||
2024                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2025                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2026         } else {
2027                 disable_gif(svm);
2028
2029                 /*
2030                  * After a CLGI no interrupts should come.  But if vGIF is
2031                  * in use, we still rely on the VINTR intercept (rather than
2032                  * STGI) to detect an open interrupt window.
2033                 */
2034                 if (!vgif_enabled(svm))
2035                         svm_clear_vintr(svm);
2036         }
2037 }
2038
2039 static int stgi_interception(struct vcpu_svm *svm)
2040 {
2041         int ret;
2042
2043         if (nested_svm_check_permissions(svm))
2044                 return 1;
2045
2046         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2047         svm_set_gif(svm, true);
2048         return ret;
2049 }
2050
2051 static int clgi_interception(struct vcpu_svm *svm)
2052 {
2053         int ret;
2054
2055         if (nested_svm_check_permissions(svm))
2056                 return 1;
2057
2058         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2059         svm_set_gif(svm, false);
2060         return ret;
2061 }
2062
2063 static int invlpga_interception(struct vcpu_svm *svm)
2064 {
2065         struct kvm_vcpu *vcpu = &svm->vcpu;
2066
2067         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2068                           kvm_rax_read(&svm->vcpu));
2069
2070         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2071         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2072
2073         return kvm_skip_emulated_instruction(&svm->vcpu);
2074 }
2075
2076 static int skinit_interception(struct vcpu_svm *svm)
2077 {
2078         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2079
2080         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2081         return 1;
2082 }
2083
2084 static int wbinvd_interception(struct vcpu_svm *svm)
2085 {
2086         return kvm_emulate_wbinvd(&svm->vcpu);
2087 }
2088
2089 static int xsetbv_interception(struct vcpu_svm *svm)
2090 {
2091         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2092         u32 index = kvm_rcx_read(&svm->vcpu);
2093
2094         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2095                 return kvm_skip_emulated_instruction(&svm->vcpu);
2096         }
2097
2098         return 1;
2099 }
2100
2101 static int rdpru_interception(struct vcpu_svm *svm)
2102 {
2103         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2104         return 1;
2105 }
2106
2107 static int task_switch_interception(struct vcpu_svm *svm)
2108 {
2109         u16 tss_selector;
2110         int reason;
2111         int int_type = svm->vmcb->control.exit_int_info &
2112                 SVM_EXITINTINFO_TYPE_MASK;
2113         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2114         uint32_t type =
2115                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2116         uint32_t idt_v =
2117                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2118         bool has_error_code = false;
2119         u32 error_code = 0;
2120
2121         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2122
2123         if (svm->vmcb->control.exit_info_2 &
2124             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2125                 reason = TASK_SWITCH_IRET;
2126         else if (svm->vmcb->control.exit_info_2 &
2127                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2128                 reason = TASK_SWITCH_JMP;
2129         else if (idt_v)
2130                 reason = TASK_SWITCH_GATE;
2131         else
2132                 reason = TASK_SWITCH_CALL;
2133
2134         if (reason == TASK_SWITCH_GATE) {
2135                 switch (type) {
2136                 case SVM_EXITINTINFO_TYPE_NMI:
2137                         svm->vcpu.arch.nmi_injected = false;
2138                         break;
2139                 case SVM_EXITINTINFO_TYPE_EXEPT:
2140                         if (svm->vmcb->control.exit_info_2 &
2141                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2142                                 has_error_code = true;
2143                                 error_code =
2144                                         (u32)svm->vmcb->control.exit_info_2;
2145                         }
2146                         kvm_clear_exception_queue(&svm->vcpu);
2147                         break;
2148                 case SVM_EXITINTINFO_TYPE_INTR:
2149                         kvm_clear_interrupt_queue(&svm->vcpu);
2150                         break;
2151                 default:
2152                         break;
2153                 }
2154         }
2155
2156         if (reason != TASK_SWITCH_GATE ||
2157             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2158             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2159              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2160                 if (!skip_emulated_instruction(&svm->vcpu))
2161                         return 0;
2162         }
2163
2164         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2165                 int_vec = -1;
2166
2167         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2168                                has_error_code, error_code);
2169 }
2170
2171 static int cpuid_interception(struct vcpu_svm *svm)
2172 {
2173         return kvm_emulate_cpuid(&svm->vcpu);
2174 }
2175
2176 static int iret_interception(struct vcpu_svm *svm)
2177 {
2178         ++svm->vcpu.stat.nmi_window_exits;
2179         svm_clr_intercept(svm, INTERCEPT_IRET);
2180         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2181         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2182         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2183         return 1;
2184 }
2185
2186 static int invd_interception(struct vcpu_svm *svm)
2187 {
2188         /* Treat an INVD instruction as a NOP and just skip it. */
2189         return kvm_skip_emulated_instruction(&svm->vcpu);
2190 }
2191
2192 static int invlpg_interception(struct vcpu_svm *svm)
2193 {
2194         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2195                 return kvm_emulate_instruction(&svm->vcpu, 0);
2196
2197         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2198         return kvm_skip_emulated_instruction(&svm->vcpu);
2199 }
2200
2201 static int emulate_on_interception(struct vcpu_svm *svm)
2202 {
2203         return kvm_emulate_instruction(&svm->vcpu, 0);
2204 }
2205
2206 static int rsm_interception(struct vcpu_svm *svm)
2207 {
2208         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2209 }
2210
2211 static int rdpmc_interception(struct vcpu_svm *svm)
2212 {
2213         int err;
2214
2215         if (!nrips)
2216                 return emulate_on_interception(svm);
2217
2218         err = kvm_rdpmc(&svm->vcpu);
2219         return kvm_complete_insn_gp(&svm->vcpu, err);
2220 }
2221
2222 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2223                                             unsigned long val)
2224 {
2225         unsigned long cr0 = svm->vcpu.arch.cr0;
2226         bool ret = false;
2227         u64 intercept;
2228
2229         intercept = svm->nested.ctl.intercept;
2230
2231         if (!is_guest_mode(&svm->vcpu) ||
2232             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2233                 return false;
2234
2235         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2236         val &= ~SVM_CR0_SELECTIVE_MASK;
2237
2238         if (cr0 ^ val) {
2239                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2240                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2241         }
2242
2243         return ret;
2244 }
2245
2246 #define CR_VALID (1ULL << 63)
2247
2248 static int cr_interception(struct vcpu_svm *svm)
2249 {
2250         int reg, cr;
2251         unsigned long val;
2252         int err;
2253
2254         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2255                 return emulate_on_interception(svm);
2256
2257         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2258                 return emulate_on_interception(svm);
2259
2260         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2261         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2262                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2263         else
2264                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2265
2266         err = 0;
2267         if (cr >= 16) { /* mov to cr */
2268                 cr -= 16;
2269                 val = kvm_register_read(&svm->vcpu, reg);
2270                 switch (cr) {
2271                 case 0:
2272                         if (!check_selective_cr0_intercepted(svm, val))
2273                                 err = kvm_set_cr0(&svm->vcpu, val);
2274                         else
2275                                 return 1;
2276
2277                         break;
2278                 case 3:
2279                         err = kvm_set_cr3(&svm->vcpu, val);
2280                         break;
2281                 case 4:
2282                         err = kvm_set_cr4(&svm->vcpu, val);
2283                         break;
2284                 case 8:
2285                         err = kvm_set_cr8(&svm->vcpu, val);
2286                         break;
2287                 default:
2288                         WARN(1, "unhandled write to CR%d", cr);
2289                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2290                         return 1;
2291                 }
2292         } else { /* mov from cr */
2293                 switch (cr) {
2294                 case 0:
2295                         val = kvm_read_cr0(&svm->vcpu);
2296                         break;
2297                 case 2:
2298                         val = svm->vcpu.arch.cr2;
2299                         break;
2300                 case 3:
2301                         val = kvm_read_cr3(&svm->vcpu);
2302                         break;
2303                 case 4:
2304                         val = kvm_read_cr4(&svm->vcpu);
2305                         break;
2306                 case 8:
2307                         val = kvm_get_cr8(&svm->vcpu);
2308                         break;
2309                 default:
2310                         WARN(1, "unhandled read from CR%d", cr);
2311                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2312                         return 1;
2313                 }
2314                 kvm_register_write(&svm->vcpu, reg, val);
2315         }
2316         return kvm_complete_insn_gp(&svm->vcpu, err);
2317 }
2318
2319 static int dr_interception(struct vcpu_svm *svm)
2320 {
2321         int reg, dr;
2322         unsigned long val;
2323
2324         if (svm->vcpu.guest_debug == 0) {
2325                 /*
2326                  * No more DR vmexits; force a reload of the debug registers
2327                  * and reenter on this instruction.  The next vmexit will
2328                  * retrieve the full state of the debug registers.
2329                  */
2330                 clr_dr_intercepts(svm);
2331                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2332                 return 1;
2333         }
2334
2335         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2336                 return emulate_on_interception(svm);
2337
2338         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2339         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2340
2341         if (dr >= 16) { /* mov to DRn */
2342                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2343                         return 1;
2344                 val = kvm_register_read(&svm->vcpu, reg);
2345                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2346         } else {
2347                 if (!kvm_require_dr(&svm->vcpu, dr))
2348                         return 1;
2349                 kvm_get_dr(&svm->vcpu, dr, &val);
2350                 kvm_register_write(&svm->vcpu, reg, val);
2351         }
2352
2353         return kvm_skip_emulated_instruction(&svm->vcpu);
2354 }
2355
2356 static int cr8_write_interception(struct vcpu_svm *svm)
2357 {
2358         struct kvm_run *kvm_run = svm->vcpu.run;
2359         int r;
2360
2361         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2362         /* instruction emulation calls kvm_set_cr8() */
2363         r = cr_interception(svm);
2364         if (lapic_in_kernel(&svm->vcpu))
2365                 return r;
2366         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2367                 return r;
2368         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2369         return 0;
2370 }
2371
2372 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2373 {
2374         msr->data = 0;
2375
2376         switch (msr->index) {
2377         case MSR_F10H_DECFG:
2378                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2379                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2380                 break;
2381         case MSR_IA32_PERF_CAPABILITIES:
2382                 return 0;
2383         default:
2384                 return KVM_MSR_RET_INVALID;
2385         }
2386
2387         return 0;
2388 }
2389
2390 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2391 {
2392         struct vcpu_svm *svm = to_svm(vcpu);
2393
2394         switch (msr_info->index) {
2395         case MSR_STAR:
2396                 msr_info->data = svm->vmcb->save.star;
2397                 break;
2398 #ifdef CONFIG_X86_64
2399         case MSR_LSTAR:
2400                 msr_info->data = svm->vmcb->save.lstar;
2401                 break;
2402         case MSR_CSTAR:
2403                 msr_info->data = svm->vmcb->save.cstar;
2404                 break;
2405         case MSR_KERNEL_GS_BASE:
2406                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2407                 break;
2408         case MSR_SYSCALL_MASK:
2409                 msr_info->data = svm->vmcb->save.sfmask;
2410                 break;
2411 #endif
2412         case MSR_IA32_SYSENTER_CS:
2413                 msr_info->data = svm->vmcb->save.sysenter_cs;
2414                 break;
2415         case MSR_IA32_SYSENTER_EIP:
2416                 msr_info->data = svm->sysenter_eip;
2417                 break;
2418         case MSR_IA32_SYSENTER_ESP:
2419                 msr_info->data = svm->sysenter_esp;
2420                 break;
2421         case MSR_TSC_AUX:
2422                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2423                         return 1;
2424                 msr_info->data = svm->tsc_aux;
2425                 break;
2426         /*
2427          * Nobody will change the following 5 values in the VMCB so we can
2428          * safely return them on rdmsr. They will always be 0 until LBRV is
2429          * implemented.
2430          */
2431         case MSR_IA32_DEBUGCTLMSR:
2432                 msr_info->data = svm->vmcb->save.dbgctl;
2433                 break;
2434         case MSR_IA32_LASTBRANCHFROMIP:
2435                 msr_info->data = svm->vmcb->save.br_from;
2436                 break;
2437         case MSR_IA32_LASTBRANCHTOIP:
2438                 msr_info->data = svm->vmcb->save.br_to;
2439                 break;
2440         case MSR_IA32_LASTINTFROMIP:
2441                 msr_info->data = svm->vmcb->save.last_excp_from;
2442                 break;
2443         case MSR_IA32_LASTINTTOIP:
2444                 msr_info->data = svm->vmcb->save.last_excp_to;
2445                 break;
2446         case MSR_VM_HSAVE_PA:
2447                 msr_info->data = svm->nested.hsave_msr;
2448                 break;
2449         case MSR_VM_CR:
2450                 msr_info->data = svm->nested.vm_cr_msr;
2451                 break;
2452         case MSR_IA32_SPEC_CTRL:
2453                 if (!msr_info->host_initiated &&
2454                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2455                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2456                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2457                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2458                         return 1;
2459
2460                 msr_info->data = svm->spec_ctrl;
2461                 break;
2462         case MSR_AMD64_VIRT_SPEC_CTRL:
2463                 if (!msr_info->host_initiated &&
2464                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2465                         return 1;
2466
2467                 msr_info->data = svm->virt_spec_ctrl;
2468                 break;
2469         case MSR_F15H_IC_CFG: {
2470
2471                 int family, model;
2472
2473                 family = guest_cpuid_family(vcpu);
2474                 model  = guest_cpuid_model(vcpu);
2475
2476                 if (family < 0 || model < 0)
2477                         return kvm_get_msr_common(vcpu, msr_info);
2478
2479                 msr_info->data = 0;
2480
2481                 if (family == 0x15 &&
2482                     (model >= 0x2 && model < 0x20))
2483                         msr_info->data = 0x1E;
2484                 }
2485                 break;
2486         case MSR_F10H_DECFG:
2487                 msr_info->data = svm->msr_decfg;
2488                 break;
2489         default:
2490                 return kvm_get_msr_common(vcpu, msr_info);
2491         }
2492         return 0;
2493 }
2494
2495 static int rdmsr_interception(struct vcpu_svm *svm)
2496 {
2497         return kvm_emulate_rdmsr(&svm->vcpu);
2498 }
2499
2500 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2501 {
2502         struct vcpu_svm *svm = to_svm(vcpu);
2503         int svm_dis, chg_mask;
2504
2505         if (data & ~SVM_VM_CR_VALID_MASK)
2506                 return 1;
2507
2508         chg_mask = SVM_VM_CR_VALID_MASK;
2509
2510         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2511                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2512
2513         svm->nested.vm_cr_msr &= ~chg_mask;
2514         svm->nested.vm_cr_msr |= (data & chg_mask);
2515
2516         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2517
2518         /* check for svm_disable while efer.svme is set */
2519         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2520                 return 1;
2521
2522         return 0;
2523 }
2524
2525 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2526 {
2527         struct vcpu_svm *svm = to_svm(vcpu);
2528
2529         u32 ecx = msr->index;
2530         u64 data = msr->data;
2531         switch (ecx) {
2532         case MSR_IA32_CR_PAT:
2533                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2534                         return 1;
2535                 vcpu->arch.pat = data;
2536                 svm->vmcb->save.g_pat = data;
2537                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2538                 break;
2539         case MSR_IA32_SPEC_CTRL:
2540                 if (!msr->host_initiated &&
2541                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2542                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2543                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2544                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2545                         return 1;
2546
2547                 if (kvm_spec_ctrl_test_value(data))
2548                         return 1;
2549
2550                 svm->spec_ctrl = data;
2551                 if (!data)
2552                         break;
2553
2554                 /*
2555                  * For non-nested:
2556                  * When it's written (to non-zero) for the first time, pass
2557                  * it through.
2558                  *
2559                  * For nested:
2560                  * The handling of the MSR bitmap for L2 guests is done in
2561                  * nested_svm_vmrun_msrpm.
2562                  * We update the L1 MSR bit as well since it will end up
2563                  * touching the MSR anyway now.
2564                  */
2565                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2566                 break;
2567         case MSR_IA32_PRED_CMD:
2568                 if (!msr->host_initiated &&
2569                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2570                         return 1;
2571
2572                 if (data & ~PRED_CMD_IBPB)
2573                         return 1;
2574                 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2575                         return 1;
2576                 if (!data)
2577                         break;
2578
2579                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2580                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2581                 break;
2582         case MSR_AMD64_VIRT_SPEC_CTRL:
2583                 if (!msr->host_initiated &&
2584                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2585                         return 1;
2586
2587                 if (data & ~SPEC_CTRL_SSBD)
2588                         return 1;
2589
2590                 svm->virt_spec_ctrl = data;
2591                 break;
2592         case MSR_STAR:
2593                 svm->vmcb->save.star = data;
2594                 break;
2595 #ifdef CONFIG_X86_64
2596         case MSR_LSTAR:
2597                 svm->vmcb->save.lstar = data;
2598                 break;
2599         case MSR_CSTAR:
2600                 svm->vmcb->save.cstar = data;
2601                 break;
2602         case MSR_KERNEL_GS_BASE:
2603                 svm->vmcb->save.kernel_gs_base = data;
2604                 break;
2605         case MSR_SYSCALL_MASK:
2606                 svm->vmcb->save.sfmask = data;
2607                 break;
2608 #endif
2609         case MSR_IA32_SYSENTER_CS:
2610                 svm->vmcb->save.sysenter_cs = data;
2611                 break;
2612         case MSR_IA32_SYSENTER_EIP:
2613                 svm->sysenter_eip = data;
2614                 svm->vmcb->save.sysenter_eip = data;
2615                 break;
2616         case MSR_IA32_SYSENTER_ESP:
2617                 svm->sysenter_esp = data;
2618                 svm->vmcb->save.sysenter_esp = data;
2619                 break;
2620         case MSR_TSC_AUX:
2621                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2622                         return 1;
2623
2624                 /*
2625                  * This is rare, so we update the MSR here instead of using
2626                  * direct_access_msrs.  Doing that would require a rdmsr in
2627                  * svm_vcpu_put.
2628                  */
2629                 svm->tsc_aux = data;
2630                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2631                 break;
2632         case MSR_IA32_DEBUGCTLMSR:
2633                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2634                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2635                                     __func__, data);
2636                         break;
2637                 }
2638                 if (data & DEBUGCTL_RESERVED_BITS)
2639                         return 1;
2640
2641                 svm->vmcb->save.dbgctl = data;
2642                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2643                 if (data & (1ULL<<0))
2644                         svm_enable_lbrv(svm);
2645                 else
2646                         svm_disable_lbrv(svm);
2647                 break;
2648         case MSR_VM_HSAVE_PA:
2649                 svm->nested.hsave_msr = data;
2650                 break;
2651         case MSR_VM_CR:
2652                 return svm_set_vm_cr(vcpu, data);
2653         case MSR_VM_IGNNE:
2654                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2655                 break;
2656         case MSR_F10H_DECFG: {
2657                 struct kvm_msr_entry msr_entry;
2658
2659                 msr_entry.index = msr->index;
2660                 if (svm_get_msr_feature(&msr_entry))
2661                         return 1;
2662
2663                 /* Check the supported bits */
2664                 if (data & ~msr_entry.data)
2665                         return 1;
2666
2667                 /* Don't allow the guest to change a bit, #GP */
2668                 if (!msr->host_initiated && (data ^ msr_entry.data))
2669                         return 1;
2670
2671                 svm->msr_decfg = data;
2672                 break;
2673         }
2674         case MSR_IA32_APICBASE:
2675                 if (kvm_vcpu_apicv_active(vcpu))
2676                         avic_update_vapic_bar(to_svm(vcpu), data);
2677                 fallthrough;
2678         default:
2679                 return kvm_set_msr_common(vcpu, msr);
2680         }
2681         return 0;
2682 }
2683
2684 static int wrmsr_interception(struct vcpu_svm *svm)
2685 {
2686         return kvm_emulate_wrmsr(&svm->vcpu);
2687 }
2688
2689 static int msr_interception(struct vcpu_svm *svm)
2690 {
2691         if (svm->vmcb->control.exit_info_1)
2692                 return wrmsr_interception(svm);
2693         else
2694                 return rdmsr_interception(svm);
2695 }
2696
2697 static int interrupt_window_interception(struct vcpu_svm *svm)
2698 {
2699         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2700         svm_clear_vintr(svm);
2701
2702         /*
2703          * For AVIC, the only reason to end up here is ExtINTs.
2704          * In this case AVIC was temporarily disabled for
2705          * requesting the IRQ window and we have to re-enable it.
2706          */
2707         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2708
2709         ++svm->vcpu.stat.irq_window_exits;
2710         return 1;
2711 }
2712
2713 static int pause_interception(struct vcpu_svm *svm)
2714 {
2715         struct kvm_vcpu *vcpu = &svm->vcpu;
2716         bool in_kernel = (svm_get_cpl(vcpu) == 0);
2717
2718         if (!kvm_pause_in_guest(vcpu->kvm))
2719                 grow_ple_window(vcpu);
2720
2721         kvm_vcpu_on_spin(vcpu, in_kernel);
2722         return 1;
2723 }
2724
2725 static int nop_interception(struct vcpu_svm *svm)
2726 {
2727         return kvm_skip_emulated_instruction(&(svm->vcpu));
2728 }
2729
2730 static int monitor_interception(struct vcpu_svm *svm)
2731 {
2732         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2733         return nop_interception(svm);
2734 }
2735
2736 static int mwait_interception(struct vcpu_svm *svm)
2737 {
2738         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2739         return nop_interception(svm);
2740 }
2741
2742 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2743         [SVM_EXIT_READ_CR0]                     = cr_interception,
2744         [SVM_EXIT_READ_CR3]                     = cr_interception,
2745         [SVM_EXIT_READ_CR4]                     = cr_interception,
2746         [SVM_EXIT_READ_CR8]                     = cr_interception,
2747         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2748         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2749         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2750         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2751         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2752         [SVM_EXIT_READ_DR0]                     = dr_interception,
2753         [SVM_EXIT_READ_DR1]                     = dr_interception,
2754         [SVM_EXIT_READ_DR2]                     = dr_interception,
2755         [SVM_EXIT_READ_DR3]                     = dr_interception,
2756         [SVM_EXIT_READ_DR4]                     = dr_interception,
2757         [SVM_EXIT_READ_DR5]                     = dr_interception,
2758         [SVM_EXIT_READ_DR6]                     = dr_interception,
2759         [SVM_EXIT_READ_DR7]                     = dr_interception,
2760         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2761         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2762         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2763         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2764         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2765         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2766         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2767         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2768         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2769         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2770         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2771         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2772         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2773         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2774         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2775         [SVM_EXIT_INTR]                         = intr_interception,
2776         [SVM_EXIT_NMI]                          = nmi_interception,
2777         [SVM_EXIT_SMI]                          = nop_on_interception,
2778         [SVM_EXIT_INIT]                         = nop_on_interception,
2779         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2780         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
2781         [SVM_EXIT_CPUID]                        = cpuid_interception,
2782         [SVM_EXIT_IRET]                         = iret_interception,
2783         [SVM_EXIT_INVD]                         = invd_interception,
2784         [SVM_EXIT_PAUSE]                        = pause_interception,
2785         [SVM_EXIT_HLT]                          = halt_interception,
2786         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2787         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2788         [SVM_EXIT_IOIO]                         = io_interception,
2789         [SVM_EXIT_MSR]                          = msr_interception,
2790         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2791         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2792         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2793         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2794         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2795         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2796         [SVM_EXIT_STGI]                         = stgi_interception,
2797         [SVM_EXIT_CLGI]                         = clgi_interception,
2798         [SVM_EXIT_SKINIT]                       = skinit_interception,
2799         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
2800         [SVM_EXIT_MONITOR]                      = monitor_interception,
2801         [SVM_EXIT_MWAIT]                        = mwait_interception,
2802         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2803         [SVM_EXIT_RDPRU]                        = rdpru_interception,
2804         [SVM_EXIT_NPF]                          = npf_interception,
2805         [SVM_EXIT_RSM]                          = rsm_interception,
2806         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
2807         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
2808 };
2809
2810 static void dump_vmcb(struct kvm_vcpu *vcpu)
2811 {
2812         struct vcpu_svm *svm = to_svm(vcpu);
2813         struct vmcb_control_area *control = &svm->vmcb->control;
2814         struct vmcb_save_area *save = &svm->vmcb->save;
2815
2816         if (!dump_invalid_vmcb) {
2817                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2818                 return;
2819         }
2820
2821         pr_err("VMCB Control Area:\n");
2822         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2823         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2824         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2825         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2826         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2827         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2828         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2829         pr_err("%-20s%d\n", "pause filter threshold:",
2830                control->pause_filter_thresh);
2831         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2832         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2833         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2834         pr_err("%-20s%d\n", "asid:", control->asid);
2835         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2836         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2837         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2838         pr_err("%-20s%08x\n", "int_state:", control->int_state);
2839         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2840         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2841         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2842         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2843         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2844         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2845         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2846         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2847         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2848         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2849         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2850         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2851         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2852         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2853         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2854         pr_err("VMCB State Save Area:\n");
2855         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2856                "es:",
2857                save->es.selector, save->es.attrib,
2858                save->es.limit, save->es.base);
2859         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2860                "cs:",
2861                save->cs.selector, save->cs.attrib,
2862                save->cs.limit, save->cs.base);
2863         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2864                "ss:",
2865                save->ss.selector, save->ss.attrib,
2866                save->ss.limit, save->ss.base);
2867         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2868                "ds:",
2869                save->ds.selector, save->ds.attrib,
2870                save->ds.limit, save->ds.base);
2871         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2872                "fs:",
2873                save->fs.selector, save->fs.attrib,
2874                save->fs.limit, save->fs.base);
2875         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2876                "gs:",
2877                save->gs.selector, save->gs.attrib,
2878                save->gs.limit, save->gs.base);
2879         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2880                "gdtr:",
2881                save->gdtr.selector, save->gdtr.attrib,
2882                save->gdtr.limit, save->gdtr.base);
2883         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2884                "ldtr:",
2885                save->ldtr.selector, save->ldtr.attrib,
2886                save->ldtr.limit, save->ldtr.base);
2887         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2888                "idtr:",
2889                save->idtr.selector, save->idtr.attrib,
2890                save->idtr.limit, save->idtr.base);
2891         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2892                "tr:",
2893                save->tr.selector, save->tr.attrib,
2894                save->tr.limit, save->tr.base);
2895         pr_err("cpl:            %d                efer:         %016llx\n",
2896                 save->cpl, save->efer);
2897         pr_err("%-15s %016llx %-13s %016llx\n",
2898                "cr0:", save->cr0, "cr2:", save->cr2);
2899         pr_err("%-15s %016llx %-13s %016llx\n",
2900                "cr3:", save->cr3, "cr4:", save->cr4);
2901         pr_err("%-15s %016llx %-13s %016llx\n",
2902                "dr6:", save->dr6, "dr7:", save->dr7);
2903         pr_err("%-15s %016llx %-13s %016llx\n",
2904                "rip:", save->rip, "rflags:", save->rflags);
2905         pr_err("%-15s %016llx %-13s %016llx\n",
2906                "rsp:", save->rsp, "rax:", save->rax);
2907         pr_err("%-15s %016llx %-13s %016llx\n",
2908                "star:", save->star, "lstar:", save->lstar);
2909         pr_err("%-15s %016llx %-13s %016llx\n",
2910                "cstar:", save->cstar, "sfmask:", save->sfmask);
2911         pr_err("%-15s %016llx %-13s %016llx\n",
2912                "kernel_gs_base:", save->kernel_gs_base,
2913                "sysenter_cs:", save->sysenter_cs);
2914         pr_err("%-15s %016llx %-13s %016llx\n",
2915                "sysenter_esp:", save->sysenter_esp,
2916                "sysenter_eip:", save->sysenter_eip);
2917         pr_err("%-15s %016llx %-13s %016llx\n",
2918                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2919         pr_err("%-15s %016llx %-13s %016llx\n",
2920                "br_from:", save->br_from, "br_to:", save->br_to);
2921         pr_err("%-15s %016llx %-13s %016llx\n",
2922                "excp_from:", save->last_excp_from,
2923                "excp_to:", save->last_excp_to);
2924 }
2925
2926 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2927 {
2928         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2929
2930         *info1 = control->exit_info_1;
2931         *info2 = control->exit_info_2;
2932 }
2933
2934 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
2935 {
2936         struct vcpu_svm *svm = to_svm(vcpu);
2937         struct kvm_run *kvm_run = vcpu->run;
2938         u32 exit_code = svm->vmcb->control.exit_code;
2939
2940         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2941
2942         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2943                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2944         if (npt_enabled)
2945                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2946
2947         if (is_guest_mode(vcpu)) {
2948                 int vmexit;
2949
2950                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2951                                         svm->vmcb->control.exit_info_1,
2952                                         svm->vmcb->control.exit_info_2,
2953                                         svm->vmcb->control.exit_int_info,
2954                                         svm->vmcb->control.exit_int_info_err,
2955                                         KVM_ISA_SVM);
2956
2957                 vmexit = nested_svm_exit_special(svm);
2958
2959                 if (vmexit == NESTED_EXIT_CONTINUE)
2960                         vmexit = nested_svm_exit_handled(svm);
2961
2962                 if (vmexit == NESTED_EXIT_DONE)
2963                         return 1;
2964         }
2965
2966         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2967                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2968                 kvm_run->fail_entry.hardware_entry_failure_reason
2969                         = svm->vmcb->control.exit_code;
2970                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
2971                 dump_vmcb(vcpu);
2972                 return 0;
2973         }
2974
2975         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2976             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2977             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2978             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2979                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
2980                        "exit_code 0x%x\n",
2981                        __func__, svm->vmcb->control.exit_int_info,
2982                        exit_code);
2983
2984         if (exit_fastpath != EXIT_FASTPATH_NONE)
2985                 return 1;
2986
2987         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2988             || !svm_exit_handlers[exit_code]) {
2989                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2990                 dump_vmcb(vcpu);
2991                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2992                 vcpu->run->internal.suberror =
2993                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2994                 vcpu->run->internal.ndata = 2;
2995                 vcpu->run->internal.data[0] = exit_code;
2996                 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
2997                 return 0;
2998         }
2999
3000 #ifdef CONFIG_RETPOLINE
3001         if (exit_code == SVM_EXIT_MSR)
3002                 return msr_interception(svm);
3003         else if (exit_code == SVM_EXIT_VINTR)
3004                 return interrupt_window_interception(svm);
3005         else if (exit_code == SVM_EXIT_INTR)
3006                 return intr_interception(svm);
3007         else if (exit_code == SVM_EXIT_HLT)
3008                 return halt_interception(svm);
3009         else if (exit_code == SVM_EXIT_NPF)
3010                 return npf_interception(svm);
3011 #endif
3012         return svm_exit_handlers[exit_code](svm);
3013 }
3014
3015 static void reload_tss(struct kvm_vcpu *vcpu)
3016 {
3017         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3018
3019         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3020         load_TR_desc();
3021 }
3022
3023 static void pre_svm_run(struct vcpu_svm *svm)
3024 {
3025         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3026
3027         if (sev_guest(svm->vcpu.kvm))
3028                 return pre_sev_run(svm, svm->vcpu.cpu);
3029
3030         /* FIXME: handle wraparound of asid_generation */
3031         if (svm->asid_generation != sd->asid_generation)
3032                 new_asid(svm, sd);
3033 }
3034
3035 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3036 {
3037         struct vcpu_svm *svm = to_svm(vcpu);
3038
3039         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3040         vcpu->arch.hflags |= HF_NMI_MASK;
3041         svm_set_intercept(svm, INTERCEPT_IRET);
3042         ++vcpu->stat.nmi_injections;
3043 }
3044
3045 static void svm_set_irq(struct kvm_vcpu *vcpu)
3046 {
3047         struct vcpu_svm *svm = to_svm(vcpu);
3048
3049         BUG_ON(!(gif_set(svm)));
3050
3051         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3052         ++vcpu->stat.irq_injections;
3053
3054         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3055                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3056 }
3057
3058 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3059 {
3060         struct vcpu_svm *svm = to_svm(vcpu);
3061
3062         if (nested_svm_virtualize_tpr(vcpu))
3063                 return;
3064
3065         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3066
3067         if (irr == -1)
3068                 return;
3069
3070         if (tpr >= irr)
3071                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3072 }
3073
3074 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3075 {
3076         struct vcpu_svm *svm = to_svm(vcpu);
3077         struct vmcb *vmcb = svm->vmcb;
3078         bool ret;
3079
3080         if (!gif_set(svm))
3081                 return true;
3082
3083         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3084                 return false;
3085
3086         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3087               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3088
3089         return ret;
3090 }
3091
3092 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3093 {
3094         struct vcpu_svm *svm = to_svm(vcpu);
3095         if (svm->nested.nested_run_pending)
3096                 return -EBUSY;
3097
3098         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3099         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3100                 return -EBUSY;
3101
3102         return !svm_nmi_blocked(vcpu);
3103 }
3104
3105 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3106 {
3107         struct vcpu_svm *svm = to_svm(vcpu);
3108
3109         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3110 }
3111
3112 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3113 {
3114         struct vcpu_svm *svm = to_svm(vcpu);
3115
3116         if (masked) {
3117                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3118                 svm_set_intercept(svm, INTERCEPT_IRET);
3119         } else {
3120                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3121                 svm_clr_intercept(svm, INTERCEPT_IRET);
3122         }
3123 }
3124
3125 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3126 {
3127         struct vcpu_svm *svm = to_svm(vcpu);
3128         struct vmcb *vmcb = svm->vmcb;
3129
3130         if (!gif_set(svm))
3131                 return true;
3132
3133         if (is_guest_mode(vcpu)) {
3134                 /* As long as interrupts are being delivered...  */
3135                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3136                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3137                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3138                         return true;
3139
3140                 /* ... vmexits aren't blocked by the interrupt shadow  */
3141                 if (nested_exit_on_intr(svm))
3142                         return false;
3143         } else {
3144                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3145                         return true;
3146         }
3147
3148         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3149 }
3150
3151 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3152 {
3153         struct vcpu_svm *svm = to_svm(vcpu);
3154         if (svm->nested.nested_run_pending)
3155                 return -EBUSY;
3156
3157         /*
3158          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3159          * e.g. if the IRQ arrived asynchronously after checking nested events.
3160          */
3161         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3162                 return -EBUSY;
3163
3164         return !svm_interrupt_blocked(vcpu);
3165 }
3166
3167 static void enable_irq_window(struct kvm_vcpu *vcpu)
3168 {
3169         struct vcpu_svm *svm = to_svm(vcpu);
3170
3171         /*
3172          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3173          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3174          * get that intercept, this function will be called again though and
3175          * we'll get the vintr intercept. However, if the vGIF feature is
3176          * enabled, the STGI interception will not occur. Enable the irq
3177          * window under the assumption that the hardware will set the GIF.
3178          */
3179         if (vgif_enabled(svm) || gif_set(svm)) {
3180                 /*
3181                  * IRQ window is not needed when AVIC is enabled,
3182                  * unless we have pending ExtINT since it cannot be injected
3183                  * via AVIC. In such case, we need to temporarily disable AVIC,
3184                  * and fallback to injecting IRQ via V_IRQ.
3185                  */
3186                 svm_toggle_avic_for_irq_window(vcpu, false);
3187                 svm_set_vintr(svm);
3188         }
3189 }
3190
3191 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3192 {
3193         struct vcpu_svm *svm = to_svm(vcpu);
3194
3195         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3196             == HF_NMI_MASK)
3197                 return; /* IRET will cause a vm exit */
3198
3199         if (!gif_set(svm)) {
3200                 if (vgif_enabled(svm))
3201                         svm_set_intercept(svm, INTERCEPT_STGI);
3202                 return; /* STGI will cause a vm exit */
3203         }
3204
3205         /*
3206          * Something prevents NMI from been injected. Single step over possible
3207          * problem (IRET or exception injection or interrupt shadow)
3208          */
3209         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3210         svm->nmi_singlestep = true;
3211         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3212 }
3213
3214 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3215 {
3216         return 0;
3217 }
3218
3219 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3220 {
3221         return 0;
3222 }
3223
3224 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3225 {
3226         struct vcpu_svm *svm = to_svm(vcpu);
3227
3228         /*
3229          * Flush only the current ASID even if the TLB flush was invoked via
3230          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3231          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3232          * unconditionally does a TLB flush on both nested VM-Enter and nested
3233          * VM-Exit (via kvm_mmu_reset_context()).
3234          */
3235         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3236                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3237         else
3238                 svm->asid_generation--;
3239 }
3240
3241 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3242 {
3243         struct vcpu_svm *svm = to_svm(vcpu);
3244
3245         invlpga(gva, svm->vmcb->control.asid);
3246 }
3247
3248 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3249 {
3250 }
3251
3252 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3253 {
3254         struct vcpu_svm *svm = to_svm(vcpu);
3255
3256         if (nested_svm_virtualize_tpr(vcpu))
3257                 return;
3258
3259         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3260                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3261                 kvm_set_cr8(vcpu, cr8);
3262         }
3263 }
3264
3265 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3266 {
3267         struct vcpu_svm *svm = to_svm(vcpu);
3268         u64 cr8;
3269
3270         if (nested_svm_virtualize_tpr(vcpu) ||
3271             kvm_vcpu_apicv_active(vcpu))
3272                 return;
3273
3274         cr8 = kvm_get_cr8(vcpu);
3275         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3276         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3277 }
3278
3279 static void svm_complete_interrupts(struct vcpu_svm *svm)
3280 {
3281         u8 vector;
3282         int type;
3283         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3284         unsigned int3_injected = svm->int3_injected;
3285
3286         svm->int3_injected = 0;
3287
3288         /*
3289          * If we've made progress since setting HF_IRET_MASK, we've
3290          * executed an IRET and can allow NMI injection.
3291          */
3292         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3293             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3294                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3295                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3296         }
3297
3298         svm->vcpu.arch.nmi_injected = false;
3299         kvm_clear_exception_queue(&svm->vcpu);
3300         kvm_clear_interrupt_queue(&svm->vcpu);
3301
3302         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3303                 return;
3304
3305         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3306
3307         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3308         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3309
3310         switch (type) {
3311         case SVM_EXITINTINFO_TYPE_NMI:
3312                 svm->vcpu.arch.nmi_injected = true;
3313                 break;
3314         case SVM_EXITINTINFO_TYPE_EXEPT:
3315                 /*
3316                  * In case of software exceptions, do not reinject the vector,
3317                  * but re-execute the instruction instead. Rewind RIP first
3318                  * if we emulated INT3 before.
3319                  */
3320                 if (kvm_exception_is_soft(vector)) {
3321                         if (vector == BP_VECTOR && int3_injected &&
3322                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3323                                 kvm_rip_write(&svm->vcpu,
3324                                               kvm_rip_read(&svm->vcpu) -
3325                                               int3_injected);
3326                         break;
3327                 }
3328                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3329                         u32 err = svm->vmcb->control.exit_int_info_err;
3330                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3331
3332                 } else
3333                         kvm_requeue_exception(&svm->vcpu, vector);
3334                 break;
3335         case SVM_EXITINTINFO_TYPE_INTR:
3336                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3337                 break;
3338         default:
3339                 break;
3340         }
3341 }
3342
3343 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3344 {
3345         struct vcpu_svm *svm = to_svm(vcpu);
3346         struct vmcb_control_area *control = &svm->vmcb->control;
3347
3348         control->exit_int_info = control->event_inj;
3349         control->exit_int_info_err = control->event_inj_err;
3350         control->event_inj = 0;
3351         svm_complete_interrupts(svm);
3352 }
3353
3354 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3355 {
3356         if (!is_guest_mode(vcpu) &&
3357             to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3358             to_svm(vcpu)->vmcb->control.exit_info_1)
3359                 return handle_fastpath_set_msr_irqoff(vcpu);
3360
3361         return EXIT_FASTPATH_NONE;
3362 }
3363
3364 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3365
3366 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3367                                         struct vcpu_svm *svm)
3368 {
3369         /*
3370          * VMENTER enables interrupts (host state), but the kernel state is
3371          * interrupts disabled when this is invoked. Also tell RCU about
3372          * it. This is the same logic as for exit_to_user_mode().
3373          *
3374          * This ensures that e.g. latency analysis on the host observes
3375          * guest mode as interrupt enabled.
3376          *
3377          * guest_enter_irqoff() informs context tracking about the
3378          * transition to guest mode and if enabled adjusts RCU state
3379          * accordingly.
3380          */
3381         instrumentation_begin();
3382         trace_hardirqs_on_prepare();
3383         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3384         instrumentation_end();
3385
3386         guest_enter_irqoff();
3387         lockdep_hardirqs_on(CALLER_ADDR0);
3388
3389         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3390
3391 #ifdef CONFIG_X86_64
3392         native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3393 #else
3394         loadsegment(fs, svm->host.fs);
3395 #ifndef CONFIG_X86_32_LAZY_GS
3396         loadsegment(gs, svm->host.gs);
3397 #endif
3398 #endif
3399
3400         /*
3401          * VMEXIT disables interrupts (host state), but tracing and lockdep
3402          * have them in state 'on' as recorded before entering guest mode.
3403          * Same as enter_from_user_mode().
3404          *
3405          * guest_exit_irqoff() restores host context and reinstates RCU if
3406          * enabled and required.
3407          *
3408          * This needs to be done before the below as native_read_msr()
3409          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3410          * into world and some more.
3411          */
3412         lockdep_hardirqs_off(CALLER_ADDR0);
3413         guest_exit_irqoff();
3414
3415         instrumentation_begin();
3416         trace_hardirqs_off_finish();
3417         instrumentation_end();
3418 }
3419
3420 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3421 {
3422         fastpath_t exit_fastpath;
3423         struct vcpu_svm *svm = to_svm(vcpu);
3424
3425         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3426         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3427         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3428
3429         /*
3430          * Disable singlestep if we're injecting an interrupt/exception.
3431          * We don't want our modified rflags to be pushed on the stack where
3432          * we might not be able to easily reset them if we disabled NMI
3433          * singlestep later.
3434          */
3435         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3436                 /*
3437                  * Event injection happens before external interrupts cause a
3438                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3439                  * is enough to force an immediate vmexit.
3440                  */
3441                 disable_nmi_singlestep(svm);
3442                 smp_send_reschedule(vcpu->cpu);
3443         }
3444
3445         pre_svm_run(svm);
3446
3447         sync_lapic_to_cr8(vcpu);
3448
3449         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3450
3451         /*
3452          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3453          * of a #DB.
3454          */
3455         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3456                 svm_set_dr6(svm, vcpu->arch.dr6);
3457         else
3458                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3459
3460         clgi();
3461         kvm_load_guest_xsave_state(vcpu);
3462
3463         if (lapic_in_kernel(vcpu) &&
3464                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3465                 kvm_wait_lapic_expire(vcpu);
3466
3467         /*
3468          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3469          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3470          * is no need to worry about the conditional branch over the wrmsr
3471          * being speculatively taken.
3472          */
3473         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3474
3475         svm_vcpu_enter_exit(vcpu, svm);
3476
3477         /*
3478          * We do not use IBRS in the kernel. If this vCPU has used the
3479          * SPEC_CTRL MSR it may have left it on; save the value and
3480          * turn it off. This is much more efficient than blindly adding
3481          * it to the atomic save/restore list. Especially as the former
3482          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3483          *
3484          * For non-nested case:
3485          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3486          * save it.
3487          *
3488          * For nested case:
3489          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3490          * save it.
3491          */
3492         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3493                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3494
3495         reload_tss(vcpu);
3496
3497         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3498
3499         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3500         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3501         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3502         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3503
3504         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3505                 kvm_before_interrupt(&svm->vcpu);
3506
3507         kvm_load_host_xsave_state(vcpu);
3508         stgi();
3509
3510         /* Any pending NMI will happen here */
3511
3512         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3513                 kvm_after_interrupt(&svm->vcpu);
3514
3515         sync_cr8_to_lapic(vcpu);
3516
3517         svm->next_rip = 0;
3518         if (is_guest_mode(&svm->vcpu)) {
3519                 sync_nested_vmcb_control(svm);
3520                 svm->nested.nested_run_pending = 0;
3521         }
3522
3523         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3524         vmcb_mark_all_clean(svm->vmcb);
3525
3526         /* if exit due to PF check for async PF */
3527         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3528                 svm->vcpu.arch.apf.host_apf_flags =
3529                         kvm_read_and_reset_apf_flags();
3530
3531         if (npt_enabled) {
3532                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3533                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3534         }
3535
3536         /*
3537          * We need to handle MC intercepts here before the vcpu has a chance to
3538          * change the physical cpu
3539          */
3540         if (unlikely(svm->vmcb->control.exit_code ==
3541                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3542                 svm_handle_mce(svm);
3543
3544         svm_complete_interrupts(svm);
3545         exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3546         return exit_fastpath;
3547 }
3548
3549 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3550                              int root_level)
3551 {
3552         struct vcpu_svm *svm = to_svm(vcpu);
3553         unsigned long cr3;
3554
3555         cr3 = __sme_set(root);
3556         if (npt_enabled) {
3557                 svm->vmcb->control.nested_cr3 = cr3;
3558                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3559
3560                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3561                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3562                         return;
3563                 cr3 = vcpu->arch.cr3;
3564         }
3565
3566         svm->vmcb->save.cr3 = cr3;
3567         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3568 }
3569
3570 static int is_disabled(void)
3571 {
3572         u64 vm_cr;
3573
3574         rdmsrl(MSR_VM_CR, vm_cr);
3575         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3576                 return 1;
3577
3578         return 0;
3579 }
3580
3581 static void
3582 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3583 {
3584         /*
3585          * Patch in the VMMCALL instruction:
3586          */
3587         hypercall[0] = 0x0f;
3588         hypercall[1] = 0x01;
3589         hypercall[2] = 0xd9;
3590 }
3591
3592 static int __init svm_check_processor_compat(void)
3593 {
3594         return 0;
3595 }
3596
3597 static bool svm_cpu_has_accelerated_tpr(void)
3598 {
3599         return false;
3600 }
3601
3602 static bool svm_has_emulated_msr(u32 index)
3603 {
3604         switch (index) {
3605         case MSR_IA32_MCG_EXT_CTL:
3606         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3607                 return false;
3608         default:
3609                 break;
3610         }
3611
3612         return true;
3613 }
3614
3615 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3616 {
3617         return 0;
3618 }
3619
3620 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3621 {
3622         struct vcpu_svm *svm = to_svm(vcpu);
3623
3624         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3625                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3626                                     boot_cpu_has(X86_FEATURE_XSAVES);
3627
3628         /* Update nrips enabled cache */
3629         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3630                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3631
3632         if (!kvm_vcpu_apicv_active(vcpu))
3633                 return;
3634
3635         /*
3636          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3637          * is exposed to the guest, disable AVIC.
3638          */
3639         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3640                 kvm_request_apicv_update(vcpu->kvm, false,
3641                                          APICV_INHIBIT_REASON_X2APIC);
3642
3643         /*
3644          * Currently, AVIC does not work with nested virtualization.
3645          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3646          */
3647         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3648                 kvm_request_apicv_update(vcpu->kvm, false,
3649                                          APICV_INHIBIT_REASON_NESTED);
3650 }
3651
3652 static bool svm_has_wbinvd_exit(void)
3653 {
3654         return true;
3655 }
3656
3657 #define PRE_EX(exit)  { .exit_code = (exit), \
3658                         .stage = X86_ICPT_PRE_EXCEPT, }
3659 #define POST_EX(exit) { .exit_code = (exit), \
3660                         .stage = X86_ICPT_POST_EXCEPT, }
3661 #define POST_MEM(exit) { .exit_code = (exit), \
3662                         .stage = X86_ICPT_POST_MEMACCESS, }
3663
3664 static const struct __x86_intercept {
3665         u32 exit_code;
3666         enum x86_intercept_stage stage;
3667 } x86_intercept_map[] = {
3668         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3669         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3670         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3671         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3672         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3673         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3674         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3675         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3676         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3677         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3678         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3679         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3680         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3681         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3682         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3683         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3684         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3685         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3686         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3687         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3688         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3689         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3690         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3691         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3692         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3693         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3694         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3695         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3696         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3697         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3698         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3699         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3700         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3701         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3702         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3703         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3704         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3705         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3706         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3707         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
3708         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
3709         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
3710         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
3711         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
3712         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
3713         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
3714         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
3715 };
3716
3717 #undef PRE_EX
3718 #undef POST_EX
3719 #undef POST_MEM
3720
3721 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3722                                struct x86_instruction_info *info,
3723                                enum x86_intercept_stage stage,
3724                                struct x86_exception *exception)
3725 {
3726         struct vcpu_svm *svm = to_svm(vcpu);
3727         int vmexit, ret = X86EMUL_CONTINUE;
3728         struct __x86_intercept icpt_info;
3729         struct vmcb *vmcb = svm->vmcb;
3730
3731         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3732                 goto out;
3733
3734         icpt_info = x86_intercept_map[info->intercept];
3735
3736         if (stage != icpt_info.stage)
3737                 goto out;
3738
3739         switch (icpt_info.exit_code) {
3740         case SVM_EXIT_READ_CR0:
3741                 if (info->intercept == x86_intercept_cr_read)
3742                         icpt_info.exit_code += info->modrm_reg;
3743                 break;
3744         case SVM_EXIT_WRITE_CR0: {
3745                 unsigned long cr0, val;
3746                 u64 intercept;
3747
3748                 if (info->intercept == x86_intercept_cr_write)
3749                         icpt_info.exit_code += info->modrm_reg;
3750
3751                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3752                     info->intercept == x86_intercept_clts)
3753                         break;
3754
3755                 intercept = svm->nested.ctl.intercept;
3756
3757                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3758                         break;
3759
3760                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3761                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
3762
3763                 if (info->intercept == x86_intercept_lmsw) {
3764                         cr0 &= 0xfUL;
3765                         val &= 0xfUL;
3766                         /* lmsw can't clear PE - catch this here */
3767                         if (cr0 & X86_CR0_PE)
3768                                 val |= X86_CR0_PE;
3769                 }
3770
3771                 if (cr0 ^ val)
3772                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3773
3774                 break;
3775         }
3776         case SVM_EXIT_READ_DR0:
3777         case SVM_EXIT_WRITE_DR0:
3778                 icpt_info.exit_code += info->modrm_reg;
3779                 break;
3780         case SVM_EXIT_MSR:
3781                 if (info->intercept == x86_intercept_wrmsr)
3782                         vmcb->control.exit_info_1 = 1;
3783                 else
3784                         vmcb->control.exit_info_1 = 0;
3785                 break;
3786         case SVM_EXIT_PAUSE:
3787                 /*
3788                  * We get this for NOP only, but pause
3789                  * is rep not, check this here
3790                  */
3791                 if (info->rep_prefix != REPE_PREFIX)
3792                         goto out;
3793                 break;
3794         case SVM_EXIT_IOIO: {
3795                 u64 exit_info;
3796                 u32 bytes;
3797
3798                 if (info->intercept == x86_intercept_in ||
3799                     info->intercept == x86_intercept_ins) {
3800                         exit_info = ((info->src_val & 0xffff) << 16) |
3801                                 SVM_IOIO_TYPE_MASK;
3802                         bytes = info->dst_bytes;
3803                 } else {
3804                         exit_info = (info->dst_val & 0xffff) << 16;
3805                         bytes = info->src_bytes;
3806                 }
3807
3808                 if (info->intercept == x86_intercept_outs ||
3809                     info->intercept == x86_intercept_ins)
3810                         exit_info |= SVM_IOIO_STR_MASK;
3811
3812                 if (info->rep_prefix)
3813                         exit_info |= SVM_IOIO_REP_MASK;
3814
3815                 bytes = min(bytes, 4u);
3816
3817                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3818
3819                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3820
3821                 vmcb->control.exit_info_1 = exit_info;
3822                 vmcb->control.exit_info_2 = info->next_rip;
3823
3824                 break;
3825         }
3826         default:
3827                 break;
3828         }
3829
3830         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3831         if (static_cpu_has(X86_FEATURE_NRIPS))
3832                 vmcb->control.next_rip  = info->next_rip;
3833         vmcb->control.exit_code = icpt_info.exit_code;
3834         vmexit = nested_svm_exit_handled(svm);
3835
3836         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3837                                            : X86EMUL_CONTINUE;
3838
3839 out:
3840         return ret;
3841 }
3842
3843 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3844 {
3845 }
3846
3847 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3848 {
3849         if (!kvm_pause_in_guest(vcpu->kvm))
3850                 shrink_ple_window(vcpu);
3851 }
3852
3853 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3854 {
3855         /* [63:9] are reserved. */
3856         vcpu->arch.mcg_cap &= 0x1ff;
3857 }
3858
3859 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
3860 {
3861         struct vcpu_svm *svm = to_svm(vcpu);
3862
3863         /* Per APM Vol.2 15.22.2 "Response to SMI" */
3864         if (!gif_set(svm))
3865                 return true;
3866
3867         return is_smm(vcpu);
3868 }
3869
3870 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3871 {
3872         struct vcpu_svm *svm = to_svm(vcpu);
3873         if (svm->nested.nested_run_pending)
3874                 return -EBUSY;
3875
3876         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
3877         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
3878                 return -EBUSY;
3879
3880         return !svm_smi_blocked(vcpu);
3881 }
3882
3883 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3884 {
3885         struct vcpu_svm *svm = to_svm(vcpu);
3886         int ret;
3887
3888         if (is_guest_mode(vcpu)) {
3889                 /* FED8h - SVM Guest */
3890                 put_smstate(u64, smstate, 0x7ed8, 1);
3891                 /* FEE0h - SVM Guest VMCB Physical Address */
3892                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3893
3894                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3895                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3896                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3897
3898                 ret = nested_svm_vmexit(svm);
3899                 if (ret)
3900                         return ret;
3901         }
3902         return 0;
3903 }
3904
3905 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
3906 {
3907         struct vcpu_svm *svm = to_svm(vcpu);
3908         struct kvm_host_map map;
3909         int ret = 0;
3910
3911         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
3912                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
3913                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3914                 u64 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
3915
3916                 if (guest) {
3917                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3918                                 return 1;
3919
3920                         if (!(saved_efer & EFER_SVME))
3921                                 return 1;
3922
3923                         if (kvm_vcpu_map(&svm->vcpu,
3924                                          gpa_to_gfn(vmcb), &map) == -EINVAL)
3925                                 return 1;
3926
3927                         ret = enter_svm_guest_mode(svm, vmcb, map.hva);
3928                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3929                 }
3930         }
3931
3932         return ret;
3933 }
3934
3935 static void enable_smi_window(struct kvm_vcpu *vcpu)
3936 {
3937         struct vcpu_svm *svm = to_svm(vcpu);
3938
3939         if (!gif_set(svm)) {
3940                 if (vgif_enabled(svm))
3941                         svm_set_intercept(svm, INTERCEPT_STGI);
3942                 /* STGI will cause a vm exit */
3943         } else {
3944                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
3945         }
3946 }
3947
3948 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3949 {
3950         unsigned long cr4 = kvm_read_cr4(vcpu);
3951         bool smep = cr4 & X86_CR4_SMEP;
3952         bool smap = cr4 & X86_CR4_SMAP;
3953         bool is_user = svm_get_cpl(vcpu) == 3;
3954
3955         /*
3956          * If RIP is invalid, go ahead with emulation which will cause an
3957          * internal error exit.
3958          */
3959         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3960                 return true;
3961
3962         /*
3963          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3964          *
3965          * Errata:
3966          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3967          * possible that CPU microcode implementing DecodeAssist will fail
3968          * to read bytes of instruction which caused #NPF. In this case,
3969          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3970          * return 0 instead of the correct guest instruction bytes.
3971          *
3972          * This happens because CPU microcode reading instruction bytes
3973          * uses a special opcode which attempts to read data using CPL=0
3974          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3975          * fault, it gives up and returns no instruction bytes.
3976          *
3977          * Detection:
3978          * We reach here in case CPU supports DecodeAssist, raised #NPF and
3979          * returned 0 in GuestIntrBytes field of the VMCB.
3980          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3981          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3982          * in case vCPU CPL==3 (Because otherwise guest would have triggered
3983          * a SMEP fault instead of #NPF).
3984          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3985          * As most guests enable SMAP if they have also enabled SMEP, use above
3986          * logic in order to attempt minimize false-positive of detecting errata
3987          * while still preserving all cases semantic correctness.
3988          *
3989          * Workaround:
3990          * To determine what instruction the guest was executing, the hypervisor
3991          * will have to decode the instruction at the instruction pointer.
3992          *
3993          * In non SEV guest, hypervisor will be able to read the guest
3994          * memory to decode the instruction pointer when insn_len is zero
3995          * so we return true to indicate that decoding is possible.
3996          *
3997          * But in the SEV guest, the guest memory is encrypted with the
3998          * guest specific key and hypervisor will not be able to decode the
3999          * instruction pointer so we will not able to workaround it. Lets
4000          * print the error and request to kill the guest.
4001          */
4002         if (smap && (!smep || is_user)) {
4003                 if (!sev_guest(vcpu->kvm))
4004                         return true;
4005
4006                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4007                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4008         }
4009
4010         return false;
4011 }
4012
4013 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4014 {
4015         struct vcpu_svm *svm = to_svm(vcpu);
4016
4017         /*
4018          * TODO: Last condition latch INIT signals on vCPU when
4019          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4020          * To properly emulate the INIT intercept,
4021          * svm_check_nested_events() should call nested_svm_vmexit()
4022          * if an INIT signal is pending.
4023          */
4024         return !gif_set(svm) ||
4025                    (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
4026 }
4027
4028 static void svm_vm_destroy(struct kvm *kvm)
4029 {
4030         avic_vm_destroy(kvm);
4031         sev_vm_destroy(kvm);
4032 }
4033
4034 static int svm_vm_init(struct kvm *kvm)
4035 {
4036         if (!pause_filter_count || !pause_filter_thresh)
4037                 kvm->arch.pause_in_guest = true;
4038
4039         if (avic) {
4040                 int ret = avic_vm_init(kvm);
4041                 if (ret)
4042                         return ret;
4043         }
4044
4045         kvm_apicv_init(kvm, avic);
4046         return 0;
4047 }
4048
4049 static struct kvm_x86_ops svm_x86_ops __initdata = {
4050         .hardware_unsetup = svm_hardware_teardown,
4051         .hardware_enable = svm_hardware_enable,
4052         .hardware_disable = svm_hardware_disable,
4053         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4054         .has_emulated_msr = svm_has_emulated_msr,
4055
4056         .vcpu_create = svm_create_vcpu,
4057         .vcpu_free = svm_free_vcpu,
4058         .vcpu_reset = svm_vcpu_reset,
4059
4060         .vm_size = sizeof(struct kvm_svm),
4061         .vm_init = svm_vm_init,
4062         .vm_destroy = svm_vm_destroy,
4063
4064         .prepare_guest_switch = svm_prepare_guest_switch,
4065         .vcpu_load = svm_vcpu_load,
4066         .vcpu_put = svm_vcpu_put,
4067         .vcpu_blocking = svm_vcpu_blocking,
4068         .vcpu_unblocking = svm_vcpu_unblocking,
4069
4070         .update_exception_bitmap = update_exception_bitmap,
4071         .get_msr_feature = svm_get_msr_feature,
4072         .get_msr = svm_get_msr,
4073         .set_msr = svm_set_msr,
4074         .get_segment_base = svm_get_segment_base,
4075         .get_segment = svm_get_segment,
4076         .set_segment = svm_set_segment,
4077         .get_cpl = svm_get_cpl,
4078         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4079         .set_cr0 = svm_set_cr0,
4080         .set_cr4 = svm_set_cr4,
4081         .set_efer = svm_set_efer,
4082         .get_idt = svm_get_idt,
4083         .set_idt = svm_set_idt,
4084         .get_gdt = svm_get_gdt,
4085         .set_gdt = svm_set_gdt,
4086         .set_dr7 = svm_set_dr7,
4087         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4088         .cache_reg = svm_cache_reg,
4089         .get_rflags = svm_get_rflags,
4090         .set_rflags = svm_set_rflags,
4091
4092         .tlb_flush_all = svm_flush_tlb,
4093         .tlb_flush_current = svm_flush_tlb,
4094         .tlb_flush_gva = svm_flush_tlb_gva,
4095         .tlb_flush_guest = svm_flush_tlb,
4096
4097         .run = svm_vcpu_run,
4098         .handle_exit = handle_exit,
4099         .skip_emulated_instruction = skip_emulated_instruction,
4100         .update_emulated_instruction = NULL,
4101         .set_interrupt_shadow = svm_set_interrupt_shadow,
4102         .get_interrupt_shadow = svm_get_interrupt_shadow,
4103         .patch_hypercall = svm_patch_hypercall,
4104         .set_irq = svm_set_irq,
4105         .set_nmi = svm_inject_nmi,
4106         .queue_exception = svm_queue_exception,
4107         .cancel_injection = svm_cancel_injection,
4108         .interrupt_allowed = svm_interrupt_allowed,
4109         .nmi_allowed = svm_nmi_allowed,
4110         .get_nmi_mask = svm_get_nmi_mask,
4111         .set_nmi_mask = svm_set_nmi_mask,
4112         .enable_nmi_window = enable_nmi_window,
4113         .enable_irq_window = enable_irq_window,
4114         .update_cr8_intercept = update_cr8_intercept,
4115         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4116         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4117         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4118         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4119         .load_eoi_exitmap = svm_load_eoi_exitmap,
4120         .hwapic_irr_update = svm_hwapic_irr_update,
4121         .hwapic_isr_update = svm_hwapic_isr_update,
4122         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4123         .apicv_post_state_restore = avic_post_state_restore,
4124
4125         .set_tss_addr = svm_set_tss_addr,
4126         .set_identity_map_addr = svm_set_identity_map_addr,
4127         .get_mt_mask = svm_get_mt_mask,
4128
4129         .get_exit_info = svm_get_exit_info,
4130
4131         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4132
4133         .has_wbinvd_exit = svm_has_wbinvd_exit,
4134
4135         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4136
4137         .load_mmu_pgd = svm_load_mmu_pgd,
4138
4139         .check_intercept = svm_check_intercept,
4140         .handle_exit_irqoff = svm_handle_exit_irqoff,
4141
4142         .request_immediate_exit = __kvm_request_immediate_exit,
4143
4144         .sched_in = svm_sched_in,
4145
4146         .pmu_ops = &amd_pmu_ops,
4147         .nested_ops = &svm_nested_ops,
4148
4149         .deliver_posted_interrupt = svm_deliver_avic_intr,
4150         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4151         .update_pi_irte = svm_update_pi_irte,
4152         .setup_mce = svm_setup_mce,
4153
4154         .smi_allowed = svm_smi_allowed,
4155         .pre_enter_smm = svm_pre_enter_smm,
4156         .pre_leave_smm = svm_pre_leave_smm,
4157         .enable_smi_window = enable_smi_window,
4158
4159         .mem_enc_op = svm_mem_enc_op,
4160         .mem_enc_reg_region = svm_register_enc_region,
4161         .mem_enc_unreg_region = svm_unregister_enc_region,
4162
4163         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4164
4165         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4166 };
4167
4168 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4169         .cpu_has_kvm_support = has_svm,
4170         .disabled_by_bios = is_disabled,
4171         .hardware_setup = svm_hardware_setup,
4172         .check_processor_compatibility = svm_check_processor_compat,
4173
4174         .runtime_ops = &svm_x86_ops,
4175 };
4176
4177 static int __init svm_init(void)
4178 {
4179         __unused_size_checks();
4180
4181         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4182                         __alignof__(struct vcpu_svm), THIS_MODULE);
4183 }
4184
4185 static void __exit svm_exit(void)
4186 {
4187         kvm_exit();
4188 }
4189
4190 module_init(svm_init)
4191 module_exit(svm_exit)