KVM: SVM: Add support for CR0 write traps for an SEV-ES guest
[linux-2.6-microblaze.git] / arch / x86 / kvm / svm / svm.c
1 #define pr_fmt(fmt) "SVM: " fmt
2
3 #include <linux/kvm_host.h>
4
5 #include "irq.h"
6 #include "mmu.h"
7 #include "kvm_cache_regs.h"
8 #include "x86.h"
9 #include "cpuid.h"
10 #include "pmu.h"
11
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
28
29 #include <asm/apic.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
32 #include <asm/desc.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
39
40 #include <asm/virtext.h>
41 #include "trace.h"
42
43 #include "svm.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 #ifdef MODULE
51 static const struct x86_cpu_id svm_cpu_id[] = {
52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
53         {}
54 };
55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
56 #endif
57
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
60
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
63
64 #define SVM_FEATURE_LBRV           (1 <<  1)
65 #define SVM_FEATURE_SVML           (1 <<  2)
66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
71
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
75 #define TSC_RATIO_MIN           0x0000000000000001ULL
76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
77
78 static bool erratum_383_found __read_mostly;
79
80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
81
82 /*
83  * Set osvw_len to higher value when updated Revision Guides
84  * are published and we know what the new status bits are
85  */
86 static uint64_t osvw_len = 4, osvw_status;
87
88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
90
91 static const struct svm_direct_access_msrs {
92         u32 index;   /* Index of the MSR */
93         bool always; /* True if intercept is always on */
94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
95         { .index = MSR_STAR,                            .always = true  },
96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
97 #ifdef CONFIG_X86_64
98         { .index = MSR_GS_BASE,                         .always = true  },
99         { .index = MSR_FS_BASE,                         .always = true  },
100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
101         { .index = MSR_LSTAR,                           .always = true  },
102         { .index = MSR_CSTAR,                           .always = true  },
103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
104 #endif
105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
111         { .index = MSR_INVALID,                         .always = false },
112 };
113
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 bool npt_enabled = true;
117 #else
118 bool npt_enabled;
119 #endif
120
121 /*
122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123  * pause_filter_count: On processors that support Pause filtering(indicated
124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125  *      count value. On VMRUN this value is loaded into an internal counter.
126  *      Each time a pause instruction is executed, this counter is decremented
127  *      until it reaches zero at which time a #VMEXIT is generated if pause
128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
129  *      Intercept Filtering for more details.
130  *      This also indicate if ple logic enabled.
131  *
132  * pause_filter_thresh: In addition, some processor families support advanced
133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134  *      the amount of time a guest is allowed to execute in a pause loop.
135  *      In this mode, a 16-bit pause filter threshold field is added in the
136  *      VMCB. The threshold value is a cycle count that is used to reset the
137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
138  *      count value from VMCB into an internal counter. Then, on each pause
139  *      instruction the hardware checks the elapsed number of cycles since
140  *      the most recent pause instruction against the pause filter threshold.
141  *      If the elapsed cycle count is greater than the pause filter threshold,
142  *      then the internal pause count is reloaded from the VMCB and execution
143  *      continues. If the elapsed cycle count is less than the pause filter
144  *      threshold, then the internal pause count is decremented. If the count
145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146  *      triggered. If advanced pause filtering is supported and pause filter
147  *      threshold field is set to zero, the filter will operate in the simpler,
148  *      count only mode.
149  */
150
151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152 module_param(pause_filter_thresh, ushort, 0444);
153
154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155 module_param(pause_filter_count, ushort, 0444);
156
157 /* Default doubles per-vcpu window every exit. */
158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159 module_param(pause_filter_count_grow, ushort, 0444);
160
161 /* Default resets per-vcpu window every exit to pause_filter_count. */
162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163 module_param(pause_filter_count_shrink, ushort, 0444);
164
165 /* Default is to compute the maximum so we can never overflow. */
166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167 module_param(pause_filter_count_max, ushort, 0444);
168
169 /* allow nested paging (virtualized MMU) for all guests */
170 static int npt = true;
171 module_param(npt, int, S_IRUGO);
172
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
176
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
180
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
184
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
188
189 /* enable/disable SEV support */
190 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191 module_param(sev, int, 0444);
192
193 /* enable/disable SEV-ES support */
194 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
195 module_param(sev_es, int, 0444);
196
197 bool __read_mostly dump_invalid_vmcb;
198 module_param(dump_invalid_vmcb, bool, 0644);
199
200 static u8 rsm_ins_bytes[] = "\x0f\xaa";
201
202 static void svm_complete_interrupts(struct vcpu_svm *svm);
203
204 static unsigned long iopm_base;
205
206 struct kvm_ldttss_desc {
207         u16 limit0;
208         u16 base0;
209         unsigned base1:8, type:5, dpl:2, p:1;
210         unsigned limit1:4, zero0:3, g:1, base2:8;
211         u32 base3;
212         u32 zero1;
213 } __attribute__((packed));
214
215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
216
217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
218
219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
220 #define MSRS_RANGE_SIZE 2048
221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
222
223 u32 svm_msrpm_offset(u32 msr)
224 {
225         u32 offset;
226         int i;
227
228         for (i = 0; i < NUM_MSR_MAPS; i++) {
229                 if (msr < msrpm_ranges[i] ||
230                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
231                         continue;
232
233                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
234                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
235
236                 /* Now we have the u8 offset - but need the u32 offset */
237                 return offset / 4;
238         }
239
240         /* MSR not in any range */
241         return MSR_INVALID;
242 }
243
244 #define MAX_INST_SIZE 15
245
246 static inline void clgi(void)
247 {
248         asm volatile (__ex("clgi"));
249 }
250
251 static inline void stgi(void)
252 {
253         asm volatile (__ex("stgi"));
254 }
255
256 static inline void invlpga(unsigned long addr, u32 asid)
257 {
258         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
259 }
260
261 static int get_max_npt_level(void)
262 {
263 #ifdef CONFIG_X86_64
264         return PT64_ROOT_4LEVEL;
265 #else
266         return PT32E_ROOT_LEVEL;
267 #endif
268 }
269
270 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
271 {
272         struct vcpu_svm *svm = to_svm(vcpu);
273         u64 old_efer = vcpu->arch.efer;
274         vcpu->arch.efer = efer;
275
276         if (!npt_enabled) {
277                 /* Shadow paging assumes NX to be available.  */
278                 efer |= EFER_NX;
279
280                 if (!(efer & EFER_LMA))
281                         efer &= ~EFER_LME;
282         }
283
284         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
285                 if (!(efer & EFER_SVME)) {
286                         svm_leave_nested(svm);
287                         svm_set_gif(svm, true);
288
289                         /*
290                          * Free the nested guest state, unless we are in SMM.
291                          * In this case we will return to the nested guest
292                          * as soon as we leave SMM.
293                          */
294                         if (!is_smm(&svm->vcpu))
295                                 svm_free_nested(svm);
296
297                 } else {
298                         int ret = svm_allocate_nested(svm);
299
300                         if (ret) {
301                                 vcpu->arch.efer = old_efer;
302                                 return ret;
303                         }
304                 }
305         }
306
307         svm->vmcb->save.efer = efer | EFER_SVME;
308         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
309         return 0;
310 }
311
312 static int is_external_interrupt(u32 info)
313 {
314         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
315         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
316 }
317
318 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
319 {
320         struct vcpu_svm *svm = to_svm(vcpu);
321         u32 ret = 0;
322
323         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
324                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
325         return ret;
326 }
327
328 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
329 {
330         struct vcpu_svm *svm = to_svm(vcpu);
331
332         if (mask == 0)
333                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
334         else
335                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
336
337 }
338
339 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
340 {
341         struct vcpu_svm *svm = to_svm(vcpu);
342
343         /*
344          * SEV-ES does not expose the next RIP. The RIP update is controlled by
345          * the type of exit and the #VC handler in the guest.
346          */
347         if (sev_es_guest(vcpu->kvm))
348                 goto done;
349
350         if (nrips && svm->vmcb->control.next_rip != 0) {
351                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
352                 svm->next_rip = svm->vmcb->control.next_rip;
353         }
354
355         if (!svm->next_rip) {
356                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
357                         return 0;
358         } else {
359                 kvm_rip_write(vcpu, svm->next_rip);
360         }
361
362 done:
363         svm_set_interrupt_shadow(vcpu, 0);
364
365         return 1;
366 }
367
368 static void svm_queue_exception(struct kvm_vcpu *vcpu)
369 {
370         struct vcpu_svm *svm = to_svm(vcpu);
371         unsigned nr = vcpu->arch.exception.nr;
372         bool has_error_code = vcpu->arch.exception.has_error_code;
373         u32 error_code = vcpu->arch.exception.error_code;
374
375         kvm_deliver_exception_payload(&svm->vcpu);
376
377         if (nr == BP_VECTOR && !nrips) {
378                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
379
380                 /*
381                  * For guest debugging where we have to reinject #BP if some
382                  * INT3 is guest-owned:
383                  * Emulate nRIP by moving RIP forward. Will fail if injection
384                  * raises a fault that is not intercepted. Still better than
385                  * failing in all cases.
386                  */
387                 (void)skip_emulated_instruction(&svm->vcpu);
388                 rip = kvm_rip_read(&svm->vcpu);
389                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
390                 svm->int3_injected = rip - old_rip;
391         }
392
393         svm->vmcb->control.event_inj = nr
394                 | SVM_EVTINJ_VALID
395                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
396                 | SVM_EVTINJ_TYPE_EXEPT;
397         svm->vmcb->control.event_inj_err = error_code;
398 }
399
400 static void svm_init_erratum_383(void)
401 {
402         u32 low, high;
403         int err;
404         u64 val;
405
406         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
407                 return;
408
409         /* Use _safe variants to not break nested virtualization */
410         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
411         if (err)
412                 return;
413
414         val |= (1ULL << 47);
415
416         low  = lower_32_bits(val);
417         high = upper_32_bits(val);
418
419         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
420
421         erratum_383_found = true;
422 }
423
424 static void svm_init_osvw(struct kvm_vcpu *vcpu)
425 {
426         /*
427          * Guests should see errata 400 and 415 as fixed (assuming that
428          * HLT and IO instructions are intercepted).
429          */
430         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
431         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
432
433         /*
434          * By increasing VCPU's osvw.length to 3 we are telling the guest that
435          * all osvw.status bits inside that length, including bit 0 (which is
436          * reserved for erratum 298), are valid. However, if host processor's
437          * osvw_len is 0 then osvw_status[0] carries no information. We need to
438          * be conservative here and therefore we tell the guest that erratum 298
439          * is present (because we really don't know).
440          */
441         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
442                 vcpu->arch.osvw.status |= 1;
443 }
444
445 static int has_svm(void)
446 {
447         const char *msg;
448
449         if (!cpu_has_svm(&msg)) {
450                 printk(KERN_INFO "has_svm: %s\n", msg);
451                 return 0;
452         }
453
454         return 1;
455 }
456
457 static void svm_hardware_disable(void)
458 {
459         /* Make sure we clean up behind us */
460         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
461                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
462
463         cpu_svm_disable();
464
465         amd_pmu_disable_virt();
466 }
467
468 static int svm_hardware_enable(void)
469 {
470
471         struct svm_cpu_data *sd;
472         uint64_t efer;
473         struct desc_struct *gdt;
474         int me = raw_smp_processor_id();
475
476         rdmsrl(MSR_EFER, efer);
477         if (efer & EFER_SVME)
478                 return -EBUSY;
479
480         if (!has_svm()) {
481                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
482                 return -EINVAL;
483         }
484         sd = per_cpu(svm_data, me);
485         if (!sd) {
486                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
487                 return -EINVAL;
488         }
489
490         sd->asid_generation = 1;
491         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
492         sd->next_asid = sd->max_asid + 1;
493         sd->min_asid = max_sev_asid + 1;
494
495         gdt = get_current_gdt_rw();
496         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
497
498         wrmsrl(MSR_EFER, efer | EFER_SVME);
499
500         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
501
502         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
503                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
504                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
505         }
506
507
508         /*
509          * Get OSVW bits.
510          *
511          * Note that it is possible to have a system with mixed processor
512          * revisions and therefore different OSVW bits. If bits are not the same
513          * on different processors then choose the worst case (i.e. if erratum
514          * is present on one processor and not on another then assume that the
515          * erratum is present everywhere).
516          */
517         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
518                 uint64_t len, status = 0;
519                 int err;
520
521                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
522                 if (!err)
523                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
524                                                       &err);
525
526                 if (err)
527                         osvw_status = osvw_len = 0;
528                 else {
529                         if (len < osvw_len)
530                                 osvw_len = len;
531                         osvw_status |= status;
532                         osvw_status &= (1ULL << osvw_len) - 1;
533                 }
534         } else
535                 osvw_status = osvw_len = 0;
536
537         svm_init_erratum_383();
538
539         amd_pmu_enable_virt();
540
541         return 0;
542 }
543
544 static void svm_cpu_uninit(int cpu)
545 {
546         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
547
548         if (!sd)
549                 return;
550
551         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
552         kfree(sd->sev_vmcbs);
553         __free_page(sd->save_area);
554         kfree(sd);
555 }
556
557 static int svm_cpu_init(int cpu)
558 {
559         struct svm_cpu_data *sd;
560
561         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
562         if (!sd)
563                 return -ENOMEM;
564         sd->cpu = cpu;
565         sd->save_area = alloc_page(GFP_KERNEL);
566         if (!sd->save_area)
567                 goto free_cpu_data;
568
569         if (svm_sev_enabled()) {
570                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
571                                               sizeof(void *),
572                                               GFP_KERNEL);
573                 if (!sd->sev_vmcbs)
574                         goto free_save_area;
575         }
576
577         per_cpu(svm_data, cpu) = sd;
578
579         return 0;
580
581 free_save_area:
582         __free_page(sd->save_area);
583 free_cpu_data:
584         kfree(sd);
585         return -ENOMEM;
586
587 }
588
589 static int direct_access_msr_slot(u32 msr)
590 {
591         u32 i;
592
593         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
594                 if (direct_access_msrs[i].index == msr)
595                         return i;
596
597         return -ENOENT;
598 }
599
600 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
601                                      int write)
602 {
603         struct vcpu_svm *svm = to_svm(vcpu);
604         int slot = direct_access_msr_slot(msr);
605
606         if (slot == -ENOENT)
607                 return;
608
609         /* Set the shadow bitmaps to the desired intercept states */
610         if (read)
611                 set_bit(slot, svm->shadow_msr_intercept.read);
612         else
613                 clear_bit(slot, svm->shadow_msr_intercept.read);
614
615         if (write)
616                 set_bit(slot, svm->shadow_msr_intercept.write);
617         else
618                 clear_bit(slot, svm->shadow_msr_intercept.write);
619 }
620
621 static bool valid_msr_intercept(u32 index)
622 {
623         return direct_access_msr_slot(index) != -ENOENT;
624 }
625
626 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
627 {
628         u8 bit_write;
629         unsigned long tmp;
630         u32 offset;
631         u32 *msrpm;
632
633         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
634                                       to_svm(vcpu)->msrpm;
635
636         offset    = svm_msrpm_offset(msr);
637         bit_write = 2 * (msr & 0x0f) + 1;
638         tmp       = msrpm[offset];
639
640         BUG_ON(offset == MSR_INVALID);
641
642         return !!test_bit(bit_write,  &tmp);
643 }
644
645 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
646                                         u32 msr, int read, int write)
647 {
648         u8 bit_read, bit_write;
649         unsigned long tmp;
650         u32 offset;
651
652         /*
653          * If this warning triggers extend the direct_access_msrs list at the
654          * beginning of the file
655          */
656         WARN_ON(!valid_msr_intercept(msr));
657
658         /* Enforce non allowed MSRs to trap */
659         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
660                 read = 0;
661
662         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
663                 write = 0;
664
665         offset    = svm_msrpm_offset(msr);
666         bit_read  = 2 * (msr & 0x0f);
667         bit_write = 2 * (msr & 0x0f) + 1;
668         tmp       = msrpm[offset];
669
670         BUG_ON(offset == MSR_INVALID);
671
672         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
673         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
674
675         msrpm[offset] = tmp;
676 }
677
678 static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
679                                  int read, int write)
680 {
681         set_shadow_msr_intercept(vcpu, msr, read, write);
682         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
683 }
684
685 u32 *svm_vcpu_alloc_msrpm(void)
686 {
687         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
688         u32 *msrpm;
689
690         if (!pages)
691                 return NULL;
692
693         msrpm = page_address(pages);
694         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
695
696         return msrpm;
697 }
698
699 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
700 {
701         int i;
702
703         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
704                 if (!direct_access_msrs[i].always)
705                         continue;
706                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
707         }
708 }
709
710
711 void svm_vcpu_free_msrpm(u32 *msrpm)
712 {
713         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
714 }
715
716 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
717 {
718         struct vcpu_svm *svm = to_svm(vcpu);
719         u32 i;
720
721         /*
722          * Set intercept permissions for all direct access MSRs again. They
723          * will automatically get filtered through the MSR filter, so we are
724          * back in sync after this.
725          */
726         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
727                 u32 msr = direct_access_msrs[i].index;
728                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
729                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
730
731                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
732         }
733 }
734
735 static void add_msr_offset(u32 offset)
736 {
737         int i;
738
739         for (i = 0; i < MSRPM_OFFSETS; ++i) {
740
741                 /* Offset already in list? */
742                 if (msrpm_offsets[i] == offset)
743                         return;
744
745                 /* Slot used by another offset? */
746                 if (msrpm_offsets[i] != MSR_INVALID)
747                         continue;
748
749                 /* Add offset to list */
750                 msrpm_offsets[i] = offset;
751
752                 return;
753         }
754
755         /*
756          * If this BUG triggers the msrpm_offsets table has an overflow. Just
757          * increase MSRPM_OFFSETS in this case.
758          */
759         BUG();
760 }
761
762 static void init_msrpm_offsets(void)
763 {
764         int i;
765
766         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
767
768         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
769                 u32 offset;
770
771                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
772                 BUG_ON(offset == MSR_INVALID);
773
774                 add_msr_offset(offset);
775         }
776 }
777
778 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
779 {
780         struct vcpu_svm *svm = to_svm(vcpu);
781
782         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
783         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
784         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
785         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
786         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
787 }
788
789 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
790 {
791         struct vcpu_svm *svm = to_svm(vcpu);
792
793         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
794         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
795         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
796         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
797         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
798 }
799
800 void disable_nmi_singlestep(struct vcpu_svm *svm)
801 {
802         svm->nmi_singlestep = false;
803
804         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
805                 /* Clear our flags if they were not set by the guest */
806                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
807                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
808                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
809                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
810         }
811 }
812
813 static void grow_ple_window(struct kvm_vcpu *vcpu)
814 {
815         struct vcpu_svm *svm = to_svm(vcpu);
816         struct vmcb_control_area *control = &svm->vmcb->control;
817         int old = control->pause_filter_count;
818
819         control->pause_filter_count = __grow_ple_window(old,
820                                                         pause_filter_count,
821                                                         pause_filter_count_grow,
822                                                         pause_filter_count_max);
823
824         if (control->pause_filter_count != old) {
825                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
826                 trace_kvm_ple_window_update(vcpu->vcpu_id,
827                                             control->pause_filter_count, old);
828         }
829 }
830
831 static void shrink_ple_window(struct kvm_vcpu *vcpu)
832 {
833         struct vcpu_svm *svm = to_svm(vcpu);
834         struct vmcb_control_area *control = &svm->vmcb->control;
835         int old = control->pause_filter_count;
836
837         control->pause_filter_count =
838                                 __shrink_ple_window(old,
839                                                     pause_filter_count,
840                                                     pause_filter_count_shrink,
841                                                     pause_filter_count);
842         if (control->pause_filter_count != old) {
843                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
844                 trace_kvm_ple_window_update(vcpu->vcpu_id,
845                                             control->pause_filter_count, old);
846         }
847 }
848
849 /*
850  * The default MMIO mask is a single bit (excluding the present bit),
851  * which could conflict with the memory encryption bit. Check for
852  * memory encryption support and override the default MMIO mask if
853  * memory encryption is enabled.
854  */
855 static __init void svm_adjust_mmio_mask(void)
856 {
857         unsigned int enc_bit, mask_bit;
858         u64 msr, mask;
859
860         /* If there is no memory encryption support, use existing mask */
861         if (cpuid_eax(0x80000000) < 0x8000001f)
862                 return;
863
864         /* If memory encryption is not enabled, use existing mask */
865         rdmsrl(MSR_K8_SYSCFG, msr);
866         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
867                 return;
868
869         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
870         mask_bit = boot_cpu_data.x86_phys_bits;
871
872         /* Increment the mask bit if it is the same as the encryption bit */
873         if (enc_bit == mask_bit)
874                 mask_bit++;
875
876         /*
877          * If the mask bit location is below 52, then some bits above the
878          * physical addressing limit will always be reserved, so use the
879          * rsvd_bits() function to generate the mask. This mask, along with
880          * the present bit, will be used to generate a page fault with
881          * PFER.RSV = 1.
882          *
883          * If the mask bit location is 52 (or above), then clear the mask.
884          */
885         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
886
887         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
888 }
889
890 static void svm_hardware_teardown(void)
891 {
892         int cpu;
893
894         if (svm_sev_enabled())
895                 sev_hardware_teardown();
896
897         for_each_possible_cpu(cpu)
898                 svm_cpu_uninit(cpu);
899
900         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
901         iopm_base = 0;
902 }
903
904 static __init void svm_set_cpu_caps(void)
905 {
906         kvm_set_cpu_caps();
907
908         supported_xss = 0;
909
910         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
911         if (nested) {
912                 kvm_cpu_cap_set(X86_FEATURE_SVM);
913
914                 if (nrips)
915                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
916
917                 if (npt_enabled)
918                         kvm_cpu_cap_set(X86_FEATURE_NPT);
919         }
920
921         /* CPUID 0x80000008 */
922         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
923             boot_cpu_has(X86_FEATURE_AMD_SSBD))
924                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
925
926         /* Enable INVPCID feature */
927         kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
928 }
929
930 static __init int svm_hardware_setup(void)
931 {
932         int cpu;
933         struct page *iopm_pages;
934         void *iopm_va;
935         int r;
936
937         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
938
939         if (!iopm_pages)
940                 return -ENOMEM;
941
942         iopm_va = page_address(iopm_pages);
943         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
944         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
945
946         init_msrpm_offsets();
947
948         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
949
950         if (boot_cpu_has(X86_FEATURE_NX))
951                 kvm_enable_efer_bits(EFER_NX);
952
953         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
954                 kvm_enable_efer_bits(EFER_FFXSR);
955
956         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
957                 kvm_has_tsc_control = true;
958                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
959                 kvm_tsc_scaling_ratio_frac_bits = 32;
960         }
961
962         /* Check for pause filtering support */
963         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
964                 pause_filter_count = 0;
965                 pause_filter_thresh = 0;
966         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
967                 pause_filter_thresh = 0;
968         }
969
970         if (nested) {
971                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
972                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
973         }
974
975         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
976                 sev_hardware_setup();
977         } else {
978                 sev = false;
979                 sev_es = false;
980         }
981
982         svm_adjust_mmio_mask();
983
984         for_each_possible_cpu(cpu) {
985                 r = svm_cpu_init(cpu);
986                 if (r)
987                         goto err;
988         }
989
990         if (!boot_cpu_has(X86_FEATURE_NPT))
991                 npt_enabled = false;
992
993         if (npt_enabled && !npt)
994                 npt_enabled = false;
995
996         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
997         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
998
999         if (nrips) {
1000                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1001                         nrips = false;
1002         }
1003
1004         if (avic) {
1005                 if (!npt_enabled ||
1006                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1007                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1008                         avic = false;
1009                 } else {
1010                         pr_info("AVIC enabled\n");
1011
1012                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1013                 }
1014         }
1015
1016         if (vls) {
1017                 if (!npt_enabled ||
1018                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1019                     !IS_ENABLED(CONFIG_X86_64)) {
1020                         vls = false;
1021                 } else {
1022                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1023                 }
1024         }
1025
1026         if (vgif) {
1027                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1028                         vgif = false;
1029                 else
1030                         pr_info("Virtual GIF supported\n");
1031         }
1032
1033         svm_set_cpu_caps();
1034
1035         /*
1036          * It seems that on AMD processors PTE's accessed bit is
1037          * being set by the CPU hardware before the NPF vmexit.
1038          * This is not expected behaviour and our tests fail because
1039          * of it.
1040          * A workaround here is to disable support for
1041          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1042          * In this case userspace can know if there is support using
1043          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1044          * it
1045          * If future AMD CPU models change the behaviour described above,
1046          * this variable can be changed accordingly
1047          */
1048         allow_smaller_maxphyaddr = !npt_enabled;
1049
1050         return 0;
1051
1052 err:
1053         svm_hardware_teardown();
1054         return r;
1055 }
1056
1057 static void init_seg(struct vmcb_seg *seg)
1058 {
1059         seg->selector = 0;
1060         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1061                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1062         seg->limit = 0xffff;
1063         seg->base = 0;
1064 }
1065
1066 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1067 {
1068         seg->selector = 0;
1069         seg->attrib = SVM_SELECTOR_P_MASK | type;
1070         seg->limit = 0xffff;
1071         seg->base = 0;
1072 }
1073
1074 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1075 {
1076         struct vcpu_svm *svm = to_svm(vcpu);
1077         u64 g_tsc_offset = 0;
1078
1079         if (is_guest_mode(vcpu)) {
1080                 /* Write L1's TSC offset.  */
1081                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1082                                svm->nested.hsave->control.tsc_offset;
1083                 svm->nested.hsave->control.tsc_offset = offset;
1084         }
1085
1086         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1087                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1088                                    offset);
1089
1090         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1091
1092         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1093         return svm->vmcb->control.tsc_offset;
1094 }
1095
1096 static void svm_check_invpcid(struct vcpu_svm *svm)
1097 {
1098         /*
1099          * Intercept INVPCID instruction only if shadow page table is
1100          * enabled. Interception is not required with nested page table
1101          * enabled.
1102          */
1103         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1104                 if (!npt_enabled)
1105                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1106                 else
1107                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1108         }
1109 }
1110
1111 static void init_vmcb(struct vcpu_svm *svm)
1112 {
1113         struct vmcb_control_area *control = &svm->vmcb->control;
1114         struct vmcb_save_area *save = &svm->vmcb->save;
1115
1116         svm->vcpu.arch.hflags = 0;
1117
1118         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1119         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1120         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1121         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1122         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1123         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1124         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1125                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1126
1127         set_dr_intercepts(svm);
1128
1129         set_exception_intercept(svm, PF_VECTOR);
1130         set_exception_intercept(svm, UD_VECTOR);
1131         set_exception_intercept(svm, MC_VECTOR);
1132         set_exception_intercept(svm, AC_VECTOR);
1133         set_exception_intercept(svm, DB_VECTOR);
1134         /*
1135          * Guest access to VMware backdoor ports could legitimately
1136          * trigger #GP because of TSS I/O permission bitmap.
1137          * We intercept those #GP and allow access to them anyway
1138          * as VMware does.
1139          */
1140         if (enable_vmware_backdoor)
1141                 set_exception_intercept(svm, GP_VECTOR);
1142
1143         svm_set_intercept(svm, INTERCEPT_INTR);
1144         svm_set_intercept(svm, INTERCEPT_NMI);
1145         svm_set_intercept(svm, INTERCEPT_SMI);
1146         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1147         svm_set_intercept(svm, INTERCEPT_RDPMC);
1148         svm_set_intercept(svm, INTERCEPT_CPUID);
1149         svm_set_intercept(svm, INTERCEPT_INVD);
1150         svm_set_intercept(svm, INTERCEPT_INVLPG);
1151         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1152         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1153         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1154         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1155         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1156         svm_set_intercept(svm, INTERCEPT_VMRUN);
1157         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1158         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1159         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1160         svm_set_intercept(svm, INTERCEPT_STGI);
1161         svm_set_intercept(svm, INTERCEPT_CLGI);
1162         svm_set_intercept(svm, INTERCEPT_SKINIT);
1163         svm_set_intercept(svm, INTERCEPT_WBINVD);
1164         svm_set_intercept(svm, INTERCEPT_XSETBV);
1165         svm_set_intercept(svm, INTERCEPT_RDPRU);
1166         svm_set_intercept(svm, INTERCEPT_RSM);
1167
1168         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1169                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1170                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1171         }
1172
1173         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1174                 svm_set_intercept(svm, INTERCEPT_HLT);
1175
1176         control->iopm_base_pa = __sme_set(iopm_base);
1177         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1178         control->int_ctl = V_INTR_MASKING_MASK;
1179
1180         init_seg(&save->es);
1181         init_seg(&save->ss);
1182         init_seg(&save->ds);
1183         init_seg(&save->fs);
1184         init_seg(&save->gs);
1185
1186         save->cs.selector = 0xf000;
1187         save->cs.base = 0xffff0000;
1188         /* Executable/Readable Code Segment */
1189         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1190                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1191         save->cs.limit = 0xffff;
1192
1193         save->gdtr.limit = 0xffff;
1194         save->idtr.limit = 0xffff;
1195
1196         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1197         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1198
1199         svm_set_efer(&svm->vcpu, 0);
1200         save->dr6 = 0xffff0ff0;
1201         kvm_set_rflags(&svm->vcpu, 2);
1202         save->rip = 0x0000fff0;
1203         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1204
1205         /*
1206          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1207          * It also updates the guest-visible cr0 value.
1208          */
1209         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1210         kvm_mmu_reset_context(&svm->vcpu);
1211
1212         save->cr4 = X86_CR4_PAE;
1213         /* rdx = ?? */
1214
1215         if (npt_enabled) {
1216                 /* Setup VMCB for Nested Paging */
1217                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1218                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1219                 clr_exception_intercept(svm, PF_VECTOR);
1220                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1221                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1222                 save->g_pat = svm->vcpu.arch.pat;
1223                 save->cr3 = 0;
1224                 save->cr4 = 0;
1225         }
1226         svm->asid_generation = 0;
1227         svm->asid = 0;
1228
1229         svm->nested.vmcb12_gpa = 0;
1230         svm->vcpu.arch.hflags = 0;
1231
1232         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1233                 control->pause_filter_count = pause_filter_count;
1234                 if (pause_filter_thresh)
1235                         control->pause_filter_thresh = pause_filter_thresh;
1236                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1237         } else {
1238                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1239         }
1240
1241         svm_check_invpcid(svm);
1242
1243         if (kvm_vcpu_apicv_active(&svm->vcpu))
1244                 avic_init_vmcb(svm);
1245
1246         /*
1247          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1248          * in VMCB and clear intercepts to avoid #VMEXIT.
1249          */
1250         if (vls) {
1251                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1252                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1253                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1254         }
1255
1256         if (vgif) {
1257                 svm_clr_intercept(svm, INTERCEPT_STGI);
1258                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1259                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1260         }
1261
1262         if (sev_guest(svm->vcpu.kvm)) {
1263                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1264                 clr_exception_intercept(svm, UD_VECTOR);
1265         }
1266
1267         vmcb_mark_all_dirty(svm->vmcb);
1268
1269         enable_gif(svm);
1270
1271 }
1272
1273 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1274 {
1275         struct vcpu_svm *svm = to_svm(vcpu);
1276         u32 dummy;
1277         u32 eax = 1;
1278
1279         svm->spec_ctrl = 0;
1280         svm->virt_spec_ctrl = 0;
1281
1282         if (!init_event) {
1283                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1284                                            MSR_IA32_APICBASE_ENABLE;
1285                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1286                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1287         }
1288         init_vmcb(svm);
1289
1290         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1291         kvm_rdx_write(vcpu, eax);
1292
1293         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1294                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1295 }
1296
1297 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1298 {
1299         struct vcpu_svm *svm;
1300         struct page *vmcb_page;
1301         struct page *vmsa_page = NULL;
1302         int err;
1303
1304         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1305         svm = to_svm(vcpu);
1306
1307         err = -ENOMEM;
1308         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1309         if (!vmcb_page)
1310                 goto out;
1311
1312         if (sev_es_guest(svm->vcpu.kvm)) {
1313                 /*
1314                  * SEV-ES guests require a separate VMSA page used to contain
1315                  * the encrypted register state of the guest.
1316                  */
1317                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1318                 if (!vmsa_page)
1319                         goto error_free_vmcb_page;
1320         }
1321
1322         err = avic_init_vcpu(svm);
1323         if (err)
1324                 goto error_free_vmsa_page;
1325
1326         /* We initialize this flag to true to make sure that the is_running
1327          * bit would be set the first time the vcpu is loaded.
1328          */
1329         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1330                 svm->avic_is_running = true;
1331
1332         svm->msrpm = svm_vcpu_alloc_msrpm();
1333         if (!svm->msrpm)
1334                 goto error_free_vmsa_page;
1335
1336         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1337
1338         svm->vmcb = page_address(vmcb_page);
1339         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1340
1341         if (vmsa_page)
1342                 svm->vmsa = page_address(vmsa_page);
1343
1344         svm->asid_generation = 0;
1345         init_vmcb(svm);
1346
1347         svm_init_osvw(vcpu);
1348         vcpu->arch.microcode_version = 0x01000065;
1349
1350         return 0;
1351
1352 error_free_vmsa_page:
1353         if (vmsa_page)
1354                 __free_page(vmsa_page);
1355 error_free_vmcb_page:
1356         __free_page(vmcb_page);
1357 out:
1358         return err;
1359 }
1360
1361 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1362 {
1363         int i;
1364
1365         for_each_online_cpu(i)
1366                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1367 }
1368
1369 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1370 {
1371         struct vcpu_svm *svm = to_svm(vcpu);
1372
1373         /*
1374          * The vmcb page can be recycled, causing a false negative in
1375          * svm_vcpu_load(). So, ensure that no logical CPU has this
1376          * vmcb page recorded as its current vmcb.
1377          */
1378         svm_clear_current_vmcb(svm->vmcb);
1379
1380         svm_free_nested(svm);
1381
1382         sev_free_vcpu(vcpu);
1383
1384         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1385         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1386 }
1387
1388 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1389 {
1390         struct vcpu_svm *svm = to_svm(vcpu);
1391         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1392         int i;
1393
1394         if (unlikely(cpu != vcpu->cpu)) {
1395                 svm->asid_generation = 0;
1396                 vmcb_mark_all_dirty(svm->vmcb);
1397         }
1398
1399 #ifdef CONFIG_X86_64
1400         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1401 #endif
1402         savesegment(fs, svm->host.fs);
1403         savesegment(gs, svm->host.gs);
1404         svm->host.ldt = kvm_read_ldt();
1405
1406         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1407                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1408
1409         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1410                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1411                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1412                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1413                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1414                 }
1415         }
1416         /* This assumes that the kernel never uses MSR_TSC_AUX */
1417         if (static_cpu_has(X86_FEATURE_RDTSCP))
1418                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1419
1420         if (sd->current_vmcb != svm->vmcb) {
1421                 sd->current_vmcb = svm->vmcb;
1422                 indirect_branch_prediction_barrier();
1423         }
1424         avic_vcpu_load(vcpu, cpu);
1425 }
1426
1427 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1428 {
1429         struct vcpu_svm *svm = to_svm(vcpu);
1430         int i;
1431
1432         avic_vcpu_put(vcpu);
1433
1434         ++vcpu->stat.host_state_reload;
1435         kvm_load_ldt(svm->host.ldt);
1436 #ifdef CONFIG_X86_64
1437         loadsegment(fs, svm->host.fs);
1438         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1439         load_gs_index(svm->host.gs);
1440 #else
1441 #ifdef CONFIG_X86_32_LAZY_GS
1442         loadsegment(gs, svm->host.gs);
1443 #endif
1444 #endif
1445         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1446                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1447 }
1448
1449 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1450 {
1451         struct vcpu_svm *svm = to_svm(vcpu);
1452         unsigned long rflags = svm->vmcb->save.rflags;
1453
1454         if (svm->nmi_singlestep) {
1455                 /* Hide our flags if they were not set by the guest */
1456                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1457                         rflags &= ~X86_EFLAGS_TF;
1458                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1459                         rflags &= ~X86_EFLAGS_RF;
1460         }
1461         return rflags;
1462 }
1463
1464 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1465 {
1466         if (to_svm(vcpu)->nmi_singlestep)
1467                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1468
1469        /*
1470         * Any change of EFLAGS.VM is accompanied by a reload of SS
1471         * (caused by either a task switch or an inter-privilege IRET),
1472         * so we do not need to update the CPL here.
1473         */
1474         to_svm(vcpu)->vmcb->save.rflags = rflags;
1475 }
1476
1477 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1478 {
1479         switch (reg) {
1480         case VCPU_EXREG_PDPTR:
1481                 BUG_ON(!npt_enabled);
1482                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1483                 break;
1484         default:
1485                 WARN_ON_ONCE(1);
1486         }
1487 }
1488
1489 static void svm_set_vintr(struct vcpu_svm *svm)
1490 {
1491         struct vmcb_control_area *control;
1492
1493         /* The following fields are ignored when AVIC is enabled */
1494         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1495         svm_set_intercept(svm, INTERCEPT_VINTR);
1496
1497         /*
1498          * This is just a dummy VINTR to actually cause a vmexit to happen.
1499          * Actual injection of virtual interrupts happens through EVENTINJ.
1500          */
1501         control = &svm->vmcb->control;
1502         control->int_vector = 0x0;
1503         control->int_ctl &= ~V_INTR_PRIO_MASK;
1504         control->int_ctl |= V_IRQ_MASK |
1505                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1506         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1507 }
1508
1509 static void svm_clear_vintr(struct vcpu_svm *svm)
1510 {
1511         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1512         svm_clr_intercept(svm, INTERCEPT_VINTR);
1513
1514         /* Drop int_ctl fields related to VINTR injection.  */
1515         svm->vmcb->control.int_ctl &= mask;
1516         if (is_guest_mode(&svm->vcpu)) {
1517                 svm->nested.hsave->control.int_ctl &= mask;
1518
1519                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1520                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1521                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1522         }
1523
1524         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1525 }
1526
1527 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1528 {
1529         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1530
1531         switch (seg) {
1532         case VCPU_SREG_CS: return &save->cs;
1533         case VCPU_SREG_DS: return &save->ds;
1534         case VCPU_SREG_ES: return &save->es;
1535         case VCPU_SREG_FS: return &save->fs;
1536         case VCPU_SREG_GS: return &save->gs;
1537         case VCPU_SREG_SS: return &save->ss;
1538         case VCPU_SREG_TR: return &save->tr;
1539         case VCPU_SREG_LDTR: return &save->ldtr;
1540         }
1541         BUG();
1542         return NULL;
1543 }
1544
1545 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1546 {
1547         struct vmcb_seg *s = svm_seg(vcpu, seg);
1548
1549         return s->base;
1550 }
1551
1552 static void svm_get_segment(struct kvm_vcpu *vcpu,
1553                             struct kvm_segment *var, int seg)
1554 {
1555         struct vmcb_seg *s = svm_seg(vcpu, seg);
1556
1557         var->base = s->base;
1558         var->limit = s->limit;
1559         var->selector = s->selector;
1560         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1561         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1562         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1563         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1564         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1565         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1566         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1567
1568         /*
1569          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1570          * However, the SVM spec states that the G bit is not observed by the
1571          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1572          * So let's synthesize a legal G bit for all segments, this helps
1573          * running KVM nested. It also helps cross-vendor migration, because
1574          * Intel's vmentry has a check on the 'G' bit.
1575          */
1576         var->g = s->limit > 0xfffff;
1577
1578         /*
1579          * AMD's VMCB does not have an explicit unusable field, so emulate it
1580          * for cross vendor migration purposes by "not present"
1581          */
1582         var->unusable = !var->present;
1583
1584         switch (seg) {
1585         case VCPU_SREG_TR:
1586                 /*
1587                  * Work around a bug where the busy flag in the tr selector
1588                  * isn't exposed
1589                  */
1590                 var->type |= 0x2;
1591                 break;
1592         case VCPU_SREG_DS:
1593         case VCPU_SREG_ES:
1594         case VCPU_SREG_FS:
1595         case VCPU_SREG_GS:
1596                 /*
1597                  * The accessed bit must always be set in the segment
1598                  * descriptor cache, although it can be cleared in the
1599                  * descriptor, the cached bit always remains at 1. Since
1600                  * Intel has a check on this, set it here to support
1601                  * cross-vendor migration.
1602                  */
1603                 if (!var->unusable)
1604                         var->type |= 0x1;
1605                 break;
1606         case VCPU_SREG_SS:
1607                 /*
1608                  * On AMD CPUs sometimes the DB bit in the segment
1609                  * descriptor is left as 1, although the whole segment has
1610                  * been made unusable. Clear it here to pass an Intel VMX
1611                  * entry check when cross vendor migrating.
1612                  */
1613                 if (var->unusable)
1614                         var->db = 0;
1615                 /* This is symmetric with svm_set_segment() */
1616                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1617                 break;
1618         }
1619 }
1620
1621 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1622 {
1623         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1624
1625         return save->cpl;
1626 }
1627
1628 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1629 {
1630         struct vcpu_svm *svm = to_svm(vcpu);
1631
1632         dt->size = svm->vmcb->save.idtr.limit;
1633         dt->address = svm->vmcb->save.idtr.base;
1634 }
1635
1636 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1637 {
1638         struct vcpu_svm *svm = to_svm(vcpu);
1639
1640         svm->vmcb->save.idtr.limit = dt->size;
1641         svm->vmcb->save.idtr.base = dt->address ;
1642         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1643 }
1644
1645 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1646 {
1647         struct vcpu_svm *svm = to_svm(vcpu);
1648
1649         dt->size = svm->vmcb->save.gdtr.limit;
1650         dt->address = svm->vmcb->save.gdtr.base;
1651 }
1652
1653 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1654 {
1655         struct vcpu_svm *svm = to_svm(vcpu);
1656
1657         svm->vmcb->save.gdtr.limit = dt->size;
1658         svm->vmcb->save.gdtr.base = dt->address ;
1659         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1660 }
1661
1662 static void update_cr0_intercept(struct vcpu_svm *svm)
1663 {
1664         ulong gcr0;
1665         u64 *hcr0;
1666
1667         /*
1668          * SEV-ES guests must always keep the CR intercepts cleared. CR
1669          * tracking is done using the CR write traps.
1670          */
1671         if (sev_es_guest(svm->vcpu.kvm))
1672                 return;
1673
1674         gcr0 = svm->vcpu.arch.cr0;
1675         hcr0 = &svm->vmcb->save.cr0;
1676         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1677                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1678
1679         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1680
1681         if (gcr0 == *hcr0) {
1682                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1683                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1684         } else {
1685                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1686                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1687         }
1688 }
1689
1690 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1691 {
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693
1694 #ifdef CONFIG_X86_64
1695         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1696                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1697                         vcpu->arch.efer |= EFER_LMA;
1698                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1699                 }
1700
1701                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1702                         vcpu->arch.efer &= ~EFER_LMA;
1703                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1704                 }
1705         }
1706 #endif
1707         vcpu->arch.cr0 = cr0;
1708
1709         if (!npt_enabled)
1710                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1711
1712         /*
1713          * re-enable caching here because the QEMU bios
1714          * does not do it - this results in some delay at
1715          * reboot
1716          */
1717         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1718                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1719         svm->vmcb->save.cr0 = cr0;
1720         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1721         update_cr0_intercept(svm);
1722 }
1723
1724 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1725 {
1726         return true;
1727 }
1728
1729 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1730 {
1731         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1732         unsigned long old_cr4 = vcpu->arch.cr4;
1733
1734         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1735                 svm_flush_tlb(vcpu);
1736
1737         vcpu->arch.cr4 = cr4;
1738         if (!npt_enabled)
1739                 cr4 |= X86_CR4_PAE;
1740         cr4 |= host_cr4_mce;
1741         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1742         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1743
1744         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1745                 kvm_update_cpuid_runtime(vcpu);
1746 }
1747
1748 static void svm_set_segment(struct kvm_vcpu *vcpu,
1749                             struct kvm_segment *var, int seg)
1750 {
1751         struct vcpu_svm *svm = to_svm(vcpu);
1752         struct vmcb_seg *s = svm_seg(vcpu, seg);
1753
1754         s->base = var->base;
1755         s->limit = var->limit;
1756         s->selector = var->selector;
1757         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1758         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1759         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1760         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1761         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1762         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1763         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1764         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1765
1766         /*
1767          * This is always accurate, except if SYSRET returned to a segment
1768          * with SS.DPL != 3.  Intel does not have this quirk, and always
1769          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1770          * would entail passing the CPL to userspace and back.
1771          */
1772         if (seg == VCPU_SREG_SS)
1773                 /* This is symmetric with svm_get_segment() */
1774                 svm->vmcb->save.cpl = (var->dpl & 3);
1775
1776         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1777 }
1778
1779 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1780 {
1781         struct vcpu_svm *svm = to_svm(vcpu);
1782
1783         clr_exception_intercept(svm, BP_VECTOR);
1784
1785         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1786                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1787                         set_exception_intercept(svm, BP_VECTOR);
1788         }
1789 }
1790
1791 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1792 {
1793         if (sd->next_asid > sd->max_asid) {
1794                 ++sd->asid_generation;
1795                 sd->next_asid = sd->min_asid;
1796                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1797                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1798         }
1799
1800         svm->asid_generation = sd->asid_generation;
1801         svm->asid = sd->next_asid++;
1802 }
1803
1804 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1805 {
1806         struct vmcb *vmcb = svm->vmcb;
1807
1808         if (svm->vcpu.arch.guest_state_protected)
1809                 return;
1810
1811         if (unlikely(value != vmcb->save.dr6)) {
1812                 vmcb->save.dr6 = value;
1813                 vmcb_mark_dirty(vmcb, VMCB_DR);
1814         }
1815 }
1816
1817 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1818 {
1819         struct vcpu_svm *svm = to_svm(vcpu);
1820
1821         if (vcpu->arch.guest_state_protected)
1822                 return;
1823
1824         get_debugreg(vcpu->arch.db[0], 0);
1825         get_debugreg(vcpu->arch.db[1], 1);
1826         get_debugreg(vcpu->arch.db[2], 2);
1827         get_debugreg(vcpu->arch.db[3], 3);
1828         /*
1829          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1830          * because db_interception might need it.  We can do it before vmentry.
1831          */
1832         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1833         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1834         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1835         set_dr_intercepts(svm);
1836 }
1837
1838 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1839 {
1840         struct vcpu_svm *svm = to_svm(vcpu);
1841
1842         if (vcpu->arch.guest_state_protected)
1843                 return;
1844
1845         svm->vmcb->save.dr7 = value;
1846         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1847 }
1848
1849 static int pf_interception(struct vcpu_svm *svm)
1850 {
1851         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1852         u64 error_code = svm->vmcb->control.exit_info_1;
1853
1854         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1855                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1856                         svm->vmcb->control.insn_bytes : NULL,
1857                         svm->vmcb->control.insn_len);
1858 }
1859
1860 static int npf_interception(struct vcpu_svm *svm)
1861 {
1862         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1863         u64 error_code = svm->vmcb->control.exit_info_1;
1864
1865         trace_kvm_page_fault(fault_address, error_code);
1866         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1867                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1868                         svm->vmcb->control.insn_bytes : NULL,
1869                         svm->vmcb->control.insn_len);
1870 }
1871
1872 static int db_interception(struct vcpu_svm *svm)
1873 {
1874         struct kvm_run *kvm_run = svm->vcpu.run;
1875         struct kvm_vcpu *vcpu = &svm->vcpu;
1876
1877         if (!(svm->vcpu.guest_debug &
1878               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1879                 !svm->nmi_singlestep) {
1880                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1881                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1882                 return 1;
1883         }
1884
1885         if (svm->nmi_singlestep) {
1886                 disable_nmi_singlestep(svm);
1887                 /* Make sure we check for pending NMIs upon entry */
1888                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1889         }
1890
1891         if (svm->vcpu.guest_debug &
1892             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1893                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1894                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1895                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1896                 kvm_run->debug.arch.pc =
1897                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1898                 kvm_run->debug.arch.exception = DB_VECTOR;
1899                 return 0;
1900         }
1901
1902         return 1;
1903 }
1904
1905 static int bp_interception(struct vcpu_svm *svm)
1906 {
1907         struct kvm_run *kvm_run = svm->vcpu.run;
1908
1909         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1910         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1911         kvm_run->debug.arch.exception = BP_VECTOR;
1912         return 0;
1913 }
1914
1915 static int ud_interception(struct vcpu_svm *svm)
1916 {
1917         return handle_ud(&svm->vcpu);
1918 }
1919
1920 static int ac_interception(struct vcpu_svm *svm)
1921 {
1922         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1923         return 1;
1924 }
1925
1926 static int gp_interception(struct vcpu_svm *svm)
1927 {
1928         struct kvm_vcpu *vcpu = &svm->vcpu;
1929         u32 error_code = svm->vmcb->control.exit_info_1;
1930
1931         WARN_ON_ONCE(!enable_vmware_backdoor);
1932
1933         /*
1934          * VMware backdoor emulation on #GP interception only handles IN{S},
1935          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1936          */
1937         if (error_code) {
1938                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1939                 return 1;
1940         }
1941         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1942 }
1943
1944 static bool is_erratum_383(void)
1945 {
1946         int err, i;
1947         u64 value;
1948
1949         if (!erratum_383_found)
1950                 return false;
1951
1952         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1953         if (err)
1954                 return false;
1955
1956         /* Bit 62 may or may not be set for this mce */
1957         value &= ~(1ULL << 62);
1958
1959         if (value != 0xb600000000010015ULL)
1960                 return false;
1961
1962         /* Clear MCi_STATUS registers */
1963         for (i = 0; i < 6; ++i)
1964                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1965
1966         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1967         if (!err) {
1968                 u32 low, high;
1969
1970                 value &= ~(1ULL << 2);
1971                 low    = lower_32_bits(value);
1972                 high   = upper_32_bits(value);
1973
1974                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1975         }
1976
1977         /* Flush tlb to evict multi-match entries */
1978         __flush_tlb_all();
1979
1980         return true;
1981 }
1982
1983 static void svm_handle_mce(struct vcpu_svm *svm)
1984 {
1985         if (is_erratum_383()) {
1986                 /*
1987                  * Erratum 383 triggered. Guest state is corrupt so kill the
1988                  * guest.
1989                  */
1990                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1991
1992                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1993
1994                 return;
1995         }
1996
1997         /*
1998          * On an #MC intercept the MCE handler is not called automatically in
1999          * the host. So do it by hand here.
2000          */
2001         kvm_machine_check();
2002 }
2003
2004 static int mc_interception(struct vcpu_svm *svm)
2005 {
2006         return 1;
2007 }
2008
2009 static int shutdown_interception(struct vcpu_svm *svm)
2010 {
2011         struct kvm_run *kvm_run = svm->vcpu.run;
2012
2013         /*
2014          * The VM save area has already been encrypted so it
2015          * cannot be reinitialized - just terminate.
2016          */
2017         if (sev_es_guest(svm->vcpu.kvm))
2018                 return -EINVAL;
2019
2020         /*
2021          * VMCB is undefined after a SHUTDOWN intercept
2022          * so reinitialize it.
2023          */
2024         clear_page(svm->vmcb);
2025         init_vmcb(svm);
2026
2027         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2028         return 0;
2029 }
2030
2031 static int io_interception(struct vcpu_svm *svm)
2032 {
2033         struct kvm_vcpu *vcpu = &svm->vcpu;
2034         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2035         int size, in, string;
2036         unsigned port;
2037
2038         ++svm->vcpu.stat.io_exits;
2039         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2040         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2041         port = io_info >> 16;
2042         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2043
2044         if (string) {
2045                 if (sev_es_guest(vcpu->kvm))
2046                         return sev_es_string_io(svm, size, port, in);
2047                 else
2048                         return kvm_emulate_instruction(vcpu, 0);
2049         }
2050
2051         svm->next_rip = svm->vmcb->control.exit_info_2;
2052
2053         return kvm_fast_pio(&svm->vcpu, size, port, in);
2054 }
2055
2056 static int nmi_interception(struct vcpu_svm *svm)
2057 {
2058         return 1;
2059 }
2060
2061 static int intr_interception(struct vcpu_svm *svm)
2062 {
2063         ++svm->vcpu.stat.irq_exits;
2064         return 1;
2065 }
2066
2067 static int nop_on_interception(struct vcpu_svm *svm)
2068 {
2069         return 1;
2070 }
2071
2072 static int halt_interception(struct vcpu_svm *svm)
2073 {
2074         return kvm_emulate_halt(&svm->vcpu);
2075 }
2076
2077 static int vmmcall_interception(struct vcpu_svm *svm)
2078 {
2079         return kvm_emulate_hypercall(&svm->vcpu);
2080 }
2081
2082 static int vmload_interception(struct vcpu_svm *svm)
2083 {
2084         struct vmcb *nested_vmcb;
2085         struct kvm_host_map map;
2086         int ret;
2087
2088         if (nested_svm_check_permissions(svm))
2089                 return 1;
2090
2091         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2092         if (ret) {
2093                 if (ret == -EINVAL)
2094                         kvm_inject_gp(&svm->vcpu, 0);
2095                 return 1;
2096         }
2097
2098         nested_vmcb = map.hva;
2099
2100         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2101
2102         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2103         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2104
2105         return ret;
2106 }
2107
2108 static int vmsave_interception(struct vcpu_svm *svm)
2109 {
2110         struct vmcb *nested_vmcb;
2111         struct kvm_host_map map;
2112         int ret;
2113
2114         if (nested_svm_check_permissions(svm))
2115                 return 1;
2116
2117         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2118         if (ret) {
2119                 if (ret == -EINVAL)
2120                         kvm_inject_gp(&svm->vcpu, 0);
2121                 return 1;
2122         }
2123
2124         nested_vmcb = map.hva;
2125
2126         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2127
2128         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2129         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2130
2131         return ret;
2132 }
2133
2134 static int vmrun_interception(struct vcpu_svm *svm)
2135 {
2136         if (nested_svm_check_permissions(svm))
2137                 return 1;
2138
2139         return nested_svm_vmrun(svm);
2140 }
2141
2142 void svm_set_gif(struct vcpu_svm *svm, bool value)
2143 {
2144         if (value) {
2145                 /*
2146                  * If VGIF is enabled, the STGI intercept is only added to
2147                  * detect the opening of the SMI/NMI window; remove it now.
2148                  * Likewise, clear the VINTR intercept, we will set it
2149                  * again while processing KVM_REQ_EVENT if needed.
2150                  */
2151                 if (vgif_enabled(svm))
2152                         svm_clr_intercept(svm, INTERCEPT_STGI);
2153                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2154                         svm_clear_vintr(svm);
2155
2156                 enable_gif(svm);
2157                 if (svm->vcpu.arch.smi_pending ||
2158                     svm->vcpu.arch.nmi_pending ||
2159                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2160                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2161         } else {
2162                 disable_gif(svm);
2163
2164                 /*
2165                  * After a CLGI no interrupts should come.  But if vGIF is
2166                  * in use, we still rely on the VINTR intercept (rather than
2167                  * STGI) to detect an open interrupt window.
2168                 */
2169                 if (!vgif_enabled(svm))
2170                         svm_clear_vintr(svm);
2171         }
2172 }
2173
2174 static int stgi_interception(struct vcpu_svm *svm)
2175 {
2176         int ret;
2177
2178         if (nested_svm_check_permissions(svm))
2179                 return 1;
2180
2181         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2182         svm_set_gif(svm, true);
2183         return ret;
2184 }
2185
2186 static int clgi_interception(struct vcpu_svm *svm)
2187 {
2188         int ret;
2189
2190         if (nested_svm_check_permissions(svm))
2191                 return 1;
2192
2193         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2194         svm_set_gif(svm, false);
2195         return ret;
2196 }
2197
2198 static int invlpga_interception(struct vcpu_svm *svm)
2199 {
2200         struct kvm_vcpu *vcpu = &svm->vcpu;
2201
2202         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2203                           kvm_rax_read(&svm->vcpu));
2204
2205         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2206         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2207
2208         return kvm_skip_emulated_instruction(&svm->vcpu);
2209 }
2210
2211 static int skinit_interception(struct vcpu_svm *svm)
2212 {
2213         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2214
2215         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2216         return 1;
2217 }
2218
2219 static int wbinvd_interception(struct vcpu_svm *svm)
2220 {
2221         return kvm_emulate_wbinvd(&svm->vcpu);
2222 }
2223
2224 static int xsetbv_interception(struct vcpu_svm *svm)
2225 {
2226         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2227         u32 index = kvm_rcx_read(&svm->vcpu);
2228
2229         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2230                 return kvm_skip_emulated_instruction(&svm->vcpu);
2231         }
2232
2233         return 1;
2234 }
2235
2236 static int rdpru_interception(struct vcpu_svm *svm)
2237 {
2238         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2239         return 1;
2240 }
2241
2242 static int task_switch_interception(struct vcpu_svm *svm)
2243 {
2244         u16 tss_selector;
2245         int reason;
2246         int int_type = svm->vmcb->control.exit_int_info &
2247                 SVM_EXITINTINFO_TYPE_MASK;
2248         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2249         uint32_t type =
2250                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2251         uint32_t idt_v =
2252                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2253         bool has_error_code = false;
2254         u32 error_code = 0;
2255
2256         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2257
2258         if (svm->vmcb->control.exit_info_2 &
2259             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2260                 reason = TASK_SWITCH_IRET;
2261         else if (svm->vmcb->control.exit_info_2 &
2262                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2263                 reason = TASK_SWITCH_JMP;
2264         else if (idt_v)
2265                 reason = TASK_SWITCH_GATE;
2266         else
2267                 reason = TASK_SWITCH_CALL;
2268
2269         if (reason == TASK_SWITCH_GATE) {
2270                 switch (type) {
2271                 case SVM_EXITINTINFO_TYPE_NMI:
2272                         svm->vcpu.arch.nmi_injected = false;
2273                         break;
2274                 case SVM_EXITINTINFO_TYPE_EXEPT:
2275                         if (svm->vmcb->control.exit_info_2 &
2276                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2277                                 has_error_code = true;
2278                                 error_code =
2279                                         (u32)svm->vmcb->control.exit_info_2;
2280                         }
2281                         kvm_clear_exception_queue(&svm->vcpu);
2282                         break;
2283                 case SVM_EXITINTINFO_TYPE_INTR:
2284                         kvm_clear_interrupt_queue(&svm->vcpu);
2285                         break;
2286                 default:
2287                         break;
2288                 }
2289         }
2290
2291         if (reason != TASK_SWITCH_GATE ||
2292             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2293             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2294              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2295                 if (!skip_emulated_instruction(&svm->vcpu))
2296                         return 0;
2297         }
2298
2299         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2300                 int_vec = -1;
2301
2302         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2303                                has_error_code, error_code);
2304 }
2305
2306 static int cpuid_interception(struct vcpu_svm *svm)
2307 {
2308         return kvm_emulate_cpuid(&svm->vcpu);
2309 }
2310
2311 static int iret_interception(struct vcpu_svm *svm)
2312 {
2313         ++svm->vcpu.stat.nmi_window_exits;
2314         svm_clr_intercept(svm, INTERCEPT_IRET);
2315         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2316         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2317         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2318         return 1;
2319 }
2320
2321 static int invd_interception(struct vcpu_svm *svm)
2322 {
2323         /* Treat an INVD instruction as a NOP and just skip it. */
2324         return kvm_skip_emulated_instruction(&svm->vcpu);
2325 }
2326
2327 static int invlpg_interception(struct vcpu_svm *svm)
2328 {
2329         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2330                 return kvm_emulate_instruction(&svm->vcpu, 0);
2331
2332         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2333         return kvm_skip_emulated_instruction(&svm->vcpu);
2334 }
2335
2336 static int emulate_on_interception(struct vcpu_svm *svm)
2337 {
2338         return kvm_emulate_instruction(&svm->vcpu, 0);
2339 }
2340
2341 static int rsm_interception(struct vcpu_svm *svm)
2342 {
2343         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2344 }
2345
2346 static int rdpmc_interception(struct vcpu_svm *svm)
2347 {
2348         int err;
2349
2350         if (!nrips)
2351                 return emulate_on_interception(svm);
2352
2353         err = kvm_rdpmc(&svm->vcpu);
2354         return kvm_complete_insn_gp(&svm->vcpu, err);
2355 }
2356
2357 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2358                                             unsigned long val)
2359 {
2360         unsigned long cr0 = svm->vcpu.arch.cr0;
2361         bool ret = false;
2362
2363         if (!is_guest_mode(&svm->vcpu) ||
2364             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2365                 return false;
2366
2367         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2368         val &= ~SVM_CR0_SELECTIVE_MASK;
2369
2370         if (cr0 ^ val) {
2371                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2372                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2373         }
2374
2375         return ret;
2376 }
2377
2378 #define CR_VALID (1ULL << 63)
2379
2380 static int cr_interception(struct vcpu_svm *svm)
2381 {
2382         int reg, cr;
2383         unsigned long val;
2384         int err;
2385
2386         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2387                 return emulate_on_interception(svm);
2388
2389         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2390                 return emulate_on_interception(svm);
2391
2392         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2393         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2394                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2395         else
2396                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2397
2398         err = 0;
2399         if (cr >= 16) { /* mov to cr */
2400                 cr -= 16;
2401                 val = kvm_register_read(&svm->vcpu, reg);
2402                 trace_kvm_cr_write(cr, val);
2403                 switch (cr) {
2404                 case 0:
2405                         if (!check_selective_cr0_intercepted(svm, val))
2406                                 err = kvm_set_cr0(&svm->vcpu, val);
2407                         else
2408                                 return 1;
2409
2410                         break;
2411                 case 3:
2412                         err = kvm_set_cr3(&svm->vcpu, val);
2413                         break;
2414                 case 4:
2415                         err = kvm_set_cr4(&svm->vcpu, val);
2416                         break;
2417                 case 8:
2418                         err = kvm_set_cr8(&svm->vcpu, val);
2419                         break;
2420                 default:
2421                         WARN(1, "unhandled write to CR%d", cr);
2422                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2423                         return 1;
2424                 }
2425         } else { /* mov from cr */
2426                 switch (cr) {
2427                 case 0:
2428                         val = kvm_read_cr0(&svm->vcpu);
2429                         break;
2430                 case 2:
2431                         val = svm->vcpu.arch.cr2;
2432                         break;
2433                 case 3:
2434                         val = kvm_read_cr3(&svm->vcpu);
2435                         break;
2436                 case 4:
2437                         val = kvm_read_cr4(&svm->vcpu);
2438                         break;
2439                 case 8:
2440                         val = kvm_get_cr8(&svm->vcpu);
2441                         break;
2442                 default:
2443                         WARN(1, "unhandled read from CR%d", cr);
2444                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2445                         return 1;
2446                 }
2447                 kvm_register_write(&svm->vcpu, reg, val);
2448                 trace_kvm_cr_read(cr, val);
2449         }
2450         return kvm_complete_insn_gp(&svm->vcpu, err);
2451 }
2452
2453 static int cr_trap(struct vcpu_svm *svm)
2454 {
2455         struct kvm_vcpu *vcpu = &svm->vcpu;
2456         unsigned long old_value, new_value;
2457         unsigned int cr;
2458
2459         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2460
2461         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2462         switch (cr) {
2463         case 0:
2464                 old_value = kvm_read_cr0(vcpu);
2465                 svm_set_cr0(vcpu, new_value);
2466
2467                 kvm_post_set_cr0(vcpu, old_value, new_value);
2468                 break;
2469         default:
2470                 WARN(1, "unhandled CR%d write trap", cr);
2471                 kvm_queue_exception(vcpu, UD_VECTOR);
2472                 return 1;
2473         }
2474
2475         return kvm_complete_insn_gp(vcpu, 0);
2476 }
2477
2478 static int dr_interception(struct vcpu_svm *svm)
2479 {
2480         int reg, dr;
2481         unsigned long val;
2482
2483         if (svm->vcpu.guest_debug == 0) {
2484                 /*
2485                  * No more DR vmexits; force a reload of the debug registers
2486                  * and reenter on this instruction.  The next vmexit will
2487                  * retrieve the full state of the debug registers.
2488                  */
2489                 clr_dr_intercepts(svm);
2490                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2491                 return 1;
2492         }
2493
2494         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2495                 return emulate_on_interception(svm);
2496
2497         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2498         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2499
2500         if (dr >= 16) { /* mov to DRn */
2501                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2502                         return 1;
2503                 val = kvm_register_read(&svm->vcpu, reg);
2504                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2505         } else {
2506                 if (!kvm_require_dr(&svm->vcpu, dr))
2507                         return 1;
2508                 kvm_get_dr(&svm->vcpu, dr, &val);
2509                 kvm_register_write(&svm->vcpu, reg, val);
2510         }
2511
2512         return kvm_skip_emulated_instruction(&svm->vcpu);
2513 }
2514
2515 static int cr8_write_interception(struct vcpu_svm *svm)
2516 {
2517         struct kvm_run *kvm_run = svm->vcpu.run;
2518         int r;
2519
2520         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2521         /* instruction emulation calls kvm_set_cr8() */
2522         r = cr_interception(svm);
2523         if (lapic_in_kernel(&svm->vcpu))
2524                 return r;
2525         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2526                 return r;
2527         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2528         return 0;
2529 }
2530
2531 static int efer_trap(struct vcpu_svm *svm)
2532 {
2533         struct msr_data msr_info;
2534         int ret;
2535
2536         /*
2537          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2538          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2539          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2540          * the guest doesn't have X86_FEATURE_SVM.
2541          */
2542         msr_info.host_initiated = false;
2543         msr_info.index = MSR_EFER;
2544         msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2545         ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2546
2547         return kvm_complete_insn_gp(&svm->vcpu, ret);
2548 }
2549
2550 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2551 {
2552         msr->data = 0;
2553
2554         switch (msr->index) {
2555         case MSR_F10H_DECFG:
2556                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2557                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2558                 break;
2559         case MSR_IA32_PERF_CAPABILITIES:
2560                 return 0;
2561         default:
2562                 return KVM_MSR_RET_INVALID;
2563         }
2564
2565         return 0;
2566 }
2567
2568 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2569 {
2570         struct vcpu_svm *svm = to_svm(vcpu);
2571
2572         switch (msr_info->index) {
2573         case MSR_STAR:
2574                 msr_info->data = svm->vmcb->save.star;
2575                 break;
2576 #ifdef CONFIG_X86_64
2577         case MSR_LSTAR:
2578                 msr_info->data = svm->vmcb->save.lstar;
2579                 break;
2580         case MSR_CSTAR:
2581                 msr_info->data = svm->vmcb->save.cstar;
2582                 break;
2583         case MSR_KERNEL_GS_BASE:
2584                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2585                 break;
2586         case MSR_SYSCALL_MASK:
2587                 msr_info->data = svm->vmcb->save.sfmask;
2588                 break;
2589 #endif
2590         case MSR_IA32_SYSENTER_CS:
2591                 msr_info->data = svm->vmcb->save.sysenter_cs;
2592                 break;
2593         case MSR_IA32_SYSENTER_EIP:
2594                 msr_info->data = svm->sysenter_eip;
2595                 break;
2596         case MSR_IA32_SYSENTER_ESP:
2597                 msr_info->data = svm->sysenter_esp;
2598                 break;
2599         case MSR_TSC_AUX:
2600                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2601                         return 1;
2602                 msr_info->data = svm->tsc_aux;
2603                 break;
2604         /*
2605          * Nobody will change the following 5 values in the VMCB so we can
2606          * safely return them on rdmsr. They will always be 0 until LBRV is
2607          * implemented.
2608          */
2609         case MSR_IA32_DEBUGCTLMSR:
2610                 msr_info->data = svm->vmcb->save.dbgctl;
2611                 break;
2612         case MSR_IA32_LASTBRANCHFROMIP:
2613                 msr_info->data = svm->vmcb->save.br_from;
2614                 break;
2615         case MSR_IA32_LASTBRANCHTOIP:
2616                 msr_info->data = svm->vmcb->save.br_to;
2617                 break;
2618         case MSR_IA32_LASTINTFROMIP:
2619                 msr_info->data = svm->vmcb->save.last_excp_from;
2620                 break;
2621         case MSR_IA32_LASTINTTOIP:
2622                 msr_info->data = svm->vmcb->save.last_excp_to;
2623                 break;
2624         case MSR_VM_HSAVE_PA:
2625                 msr_info->data = svm->nested.hsave_msr;
2626                 break;
2627         case MSR_VM_CR:
2628                 msr_info->data = svm->nested.vm_cr_msr;
2629                 break;
2630         case MSR_IA32_SPEC_CTRL:
2631                 if (!msr_info->host_initiated &&
2632                     !guest_has_spec_ctrl_msr(vcpu))
2633                         return 1;
2634
2635                 msr_info->data = svm->spec_ctrl;
2636                 break;
2637         case MSR_AMD64_VIRT_SPEC_CTRL:
2638                 if (!msr_info->host_initiated &&
2639                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2640                         return 1;
2641
2642                 msr_info->data = svm->virt_spec_ctrl;
2643                 break;
2644         case MSR_F15H_IC_CFG: {
2645
2646                 int family, model;
2647
2648                 family = guest_cpuid_family(vcpu);
2649                 model  = guest_cpuid_model(vcpu);
2650
2651                 if (family < 0 || model < 0)
2652                         return kvm_get_msr_common(vcpu, msr_info);
2653
2654                 msr_info->data = 0;
2655
2656                 if (family == 0x15 &&
2657                     (model >= 0x2 && model < 0x20))
2658                         msr_info->data = 0x1E;
2659                 }
2660                 break;
2661         case MSR_F10H_DECFG:
2662                 msr_info->data = svm->msr_decfg;
2663                 break;
2664         default:
2665                 return kvm_get_msr_common(vcpu, msr_info);
2666         }
2667         return 0;
2668 }
2669
2670 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2671 {
2672         struct vcpu_svm *svm = to_svm(vcpu);
2673         if (!sev_es_guest(svm->vcpu.kvm) || !err)
2674                 return kvm_complete_insn_gp(&svm->vcpu, err);
2675
2676         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2677         ghcb_set_sw_exit_info_2(svm->ghcb,
2678                                 X86_TRAP_GP |
2679                                 SVM_EVTINJ_TYPE_EXEPT |
2680                                 SVM_EVTINJ_VALID);
2681         return 1;
2682 }
2683
2684 static int rdmsr_interception(struct vcpu_svm *svm)
2685 {
2686         return kvm_emulate_rdmsr(&svm->vcpu);
2687 }
2688
2689 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2690 {
2691         struct vcpu_svm *svm = to_svm(vcpu);
2692         int svm_dis, chg_mask;
2693
2694         if (data & ~SVM_VM_CR_VALID_MASK)
2695                 return 1;
2696
2697         chg_mask = SVM_VM_CR_VALID_MASK;
2698
2699         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2700                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2701
2702         svm->nested.vm_cr_msr &= ~chg_mask;
2703         svm->nested.vm_cr_msr |= (data & chg_mask);
2704
2705         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2706
2707         /* check for svm_disable while efer.svme is set */
2708         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2709                 return 1;
2710
2711         return 0;
2712 }
2713
2714 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2715 {
2716         struct vcpu_svm *svm = to_svm(vcpu);
2717
2718         u32 ecx = msr->index;
2719         u64 data = msr->data;
2720         switch (ecx) {
2721         case MSR_IA32_CR_PAT:
2722                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2723                         return 1;
2724                 vcpu->arch.pat = data;
2725                 svm->vmcb->save.g_pat = data;
2726                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2727                 break;
2728         case MSR_IA32_SPEC_CTRL:
2729                 if (!msr->host_initiated &&
2730                     !guest_has_spec_ctrl_msr(vcpu))
2731                         return 1;
2732
2733                 if (kvm_spec_ctrl_test_value(data))
2734                         return 1;
2735
2736                 svm->spec_ctrl = data;
2737                 if (!data)
2738                         break;
2739
2740                 /*
2741                  * For non-nested:
2742                  * When it's written (to non-zero) for the first time, pass
2743                  * it through.
2744                  *
2745                  * For nested:
2746                  * The handling of the MSR bitmap for L2 guests is done in
2747                  * nested_svm_vmrun_msrpm.
2748                  * We update the L1 MSR bit as well since it will end up
2749                  * touching the MSR anyway now.
2750                  */
2751                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2752                 break;
2753         case MSR_IA32_PRED_CMD:
2754                 if (!msr->host_initiated &&
2755                     !guest_has_pred_cmd_msr(vcpu))
2756                         return 1;
2757
2758                 if (data & ~PRED_CMD_IBPB)
2759                         return 1;
2760                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2761                         return 1;
2762                 if (!data)
2763                         break;
2764
2765                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2766                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2767                 break;
2768         case MSR_AMD64_VIRT_SPEC_CTRL:
2769                 if (!msr->host_initiated &&
2770                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2771                         return 1;
2772
2773                 if (data & ~SPEC_CTRL_SSBD)
2774                         return 1;
2775
2776                 svm->virt_spec_ctrl = data;
2777                 break;
2778         case MSR_STAR:
2779                 svm->vmcb->save.star = data;
2780                 break;
2781 #ifdef CONFIG_X86_64
2782         case MSR_LSTAR:
2783                 svm->vmcb->save.lstar = data;
2784                 break;
2785         case MSR_CSTAR:
2786                 svm->vmcb->save.cstar = data;
2787                 break;
2788         case MSR_KERNEL_GS_BASE:
2789                 svm->vmcb->save.kernel_gs_base = data;
2790                 break;
2791         case MSR_SYSCALL_MASK:
2792                 svm->vmcb->save.sfmask = data;
2793                 break;
2794 #endif
2795         case MSR_IA32_SYSENTER_CS:
2796                 svm->vmcb->save.sysenter_cs = data;
2797                 break;
2798         case MSR_IA32_SYSENTER_EIP:
2799                 svm->sysenter_eip = data;
2800                 svm->vmcb->save.sysenter_eip = data;
2801                 break;
2802         case MSR_IA32_SYSENTER_ESP:
2803                 svm->sysenter_esp = data;
2804                 svm->vmcb->save.sysenter_esp = data;
2805                 break;
2806         case MSR_TSC_AUX:
2807                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2808                         return 1;
2809
2810                 /*
2811                  * This is rare, so we update the MSR here instead of using
2812                  * direct_access_msrs.  Doing that would require a rdmsr in
2813                  * svm_vcpu_put.
2814                  */
2815                 svm->tsc_aux = data;
2816                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2817                 break;
2818         case MSR_IA32_DEBUGCTLMSR:
2819                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2820                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2821                                     __func__, data);
2822                         break;
2823                 }
2824                 if (data & DEBUGCTL_RESERVED_BITS)
2825                         return 1;
2826
2827                 svm->vmcb->save.dbgctl = data;
2828                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2829                 if (data & (1ULL<<0))
2830                         svm_enable_lbrv(vcpu);
2831                 else
2832                         svm_disable_lbrv(vcpu);
2833                 break;
2834         case MSR_VM_HSAVE_PA:
2835                 svm->nested.hsave_msr = data;
2836                 break;
2837         case MSR_VM_CR:
2838                 return svm_set_vm_cr(vcpu, data);
2839         case MSR_VM_IGNNE:
2840                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2841                 break;
2842         case MSR_F10H_DECFG: {
2843                 struct kvm_msr_entry msr_entry;
2844
2845                 msr_entry.index = msr->index;
2846                 if (svm_get_msr_feature(&msr_entry))
2847                         return 1;
2848
2849                 /* Check the supported bits */
2850                 if (data & ~msr_entry.data)
2851                         return 1;
2852
2853                 /* Don't allow the guest to change a bit, #GP */
2854                 if (!msr->host_initiated && (data ^ msr_entry.data))
2855                         return 1;
2856
2857                 svm->msr_decfg = data;
2858                 break;
2859         }
2860         case MSR_IA32_APICBASE:
2861                 if (kvm_vcpu_apicv_active(vcpu))
2862                         avic_update_vapic_bar(to_svm(vcpu), data);
2863                 fallthrough;
2864         default:
2865                 return kvm_set_msr_common(vcpu, msr);
2866         }
2867         return 0;
2868 }
2869
2870 static int wrmsr_interception(struct vcpu_svm *svm)
2871 {
2872         return kvm_emulate_wrmsr(&svm->vcpu);
2873 }
2874
2875 static int msr_interception(struct vcpu_svm *svm)
2876 {
2877         if (svm->vmcb->control.exit_info_1)
2878                 return wrmsr_interception(svm);
2879         else
2880                 return rdmsr_interception(svm);
2881 }
2882
2883 static int interrupt_window_interception(struct vcpu_svm *svm)
2884 {
2885         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2886         svm_clear_vintr(svm);
2887
2888         /*
2889          * For AVIC, the only reason to end up here is ExtINTs.
2890          * In this case AVIC was temporarily disabled for
2891          * requesting the IRQ window and we have to re-enable it.
2892          */
2893         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2894
2895         ++svm->vcpu.stat.irq_window_exits;
2896         return 1;
2897 }
2898
2899 static int pause_interception(struct vcpu_svm *svm)
2900 {
2901         struct kvm_vcpu *vcpu = &svm->vcpu;
2902         bool in_kernel;
2903
2904         /*
2905          * CPL is not made available for an SEV-ES guest, therefore
2906          * vcpu->arch.preempted_in_kernel can never be true.  Just
2907          * set in_kernel to false as well.
2908          */
2909         in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
2910
2911         if (!kvm_pause_in_guest(vcpu->kvm))
2912                 grow_ple_window(vcpu);
2913
2914         kvm_vcpu_on_spin(vcpu, in_kernel);
2915         return 1;
2916 }
2917
2918 static int nop_interception(struct vcpu_svm *svm)
2919 {
2920         return kvm_skip_emulated_instruction(&(svm->vcpu));
2921 }
2922
2923 static int monitor_interception(struct vcpu_svm *svm)
2924 {
2925         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2926         return nop_interception(svm);
2927 }
2928
2929 static int mwait_interception(struct vcpu_svm *svm)
2930 {
2931         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2932         return nop_interception(svm);
2933 }
2934
2935 static int invpcid_interception(struct vcpu_svm *svm)
2936 {
2937         struct kvm_vcpu *vcpu = &svm->vcpu;
2938         unsigned long type;
2939         gva_t gva;
2940
2941         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2942                 kvm_queue_exception(vcpu, UD_VECTOR);
2943                 return 1;
2944         }
2945
2946         /*
2947          * For an INVPCID intercept:
2948          * EXITINFO1 provides the linear address of the memory operand.
2949          * EXITINFO2 provides the contents of the register operand.
2950          */
2951         type = svm->vmcb->control.exit_info_2;
2952         gva = svm->vmcb->control.exit_info_1;
2953
2954         if (type > 3) {
2955                 kvm_inject_gp(vcpu, 0);
2956                 return 1;
2957         }
2958
2959         return kvm_handle_invpcid(vcpu, type, gva);
2960 }
2961
2962 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2963         [SVM_EXIT_READ_CR0]                     = cr_interception,
2964         [SVM_EXIT_READ_CR3]                     = cr_interception,
2965         [SVM_EXIT_READ_CR4]                     = cr_interception,
2966         [SVM_EXIT_READ_CR8]                     = cr_interception,
2967         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2968         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2969         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2970         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2971         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2972         [SVM_EXIT_READ_DR0]                     = dr_interception,
2973         [SVM_EXIT_READ_DR1]                     = dr_interception,
2974         [SVM_EXIT_READ_DR2]                     = dr_interception,
2975         [SVM_EXIT_READ_DR3]                     = dr_interception,
2976         [SVM_EXIT_READ_DR4]                     = dr_interception,
2977         [SVM_EXIT_READ_DR5]                     = dr_interception,
2978         [SVM_EXIT_READ_DR6]                     = dr_interception,
2979         [SVM_EXIT_READ_DR7]                     = dr_interception,
2980         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2981         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2982         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2983         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2984         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2985         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2986         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2987         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2988         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2989         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2990         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2991         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2992         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2993         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2994         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2995         [SVM_EXIT_INTR]                         = intr_interception,
2996         [SVM_EXIT_NMI]                          = nmi_interception,
2997         [SVM_EXIT_SMI]                          = nop_on_interception,
2998         [SVM_EXIT_INIT]                         = nop_on_interception,
2999         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3000         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3001         [SVM_EXIT_CPUID]                        = cpuid_interception,
3002         [SVM_EXIT_IRET]                         = iret_interception,
3003         [SVM_EXIT_INVD]                         = invd_interception,
3004         [SVM_EXIT_PAUSE]                        = pause_interception,
3005         [SVM_EXIT_HLT]                          = halt_interception,
3006         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3007         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3008         [SVM_EXIT_IOIO]                         = io_interception,
3009         [SVM_EXIT_MSR]                          = msr_interception,
3010         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3011         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3012         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3013         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3014         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3015         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3016         [SVM_EXIT_STGI]                         = stgi_interception,
3017         [SVM_EXIT_CLGI]                         = clgi_interception,
3018         [SVM_EXIT_SKINIT]                       = skinit_interception,
3019         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3020         [SVM_EXIT_MONITOR]                      = monitor_interception,
3021         [SVM_EXIT_MWAIT]                        = mwait_interception,
3022         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3023         [SVM_EXIT_RDPRU]                        = rdpru_interception,
3024         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3025         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3026         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3027         [SVM_EXIT_NPF]                          = npf_interception,
3028         [SVM_EXIT_RSM]                          = rsm_interception,
3029         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3030         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3031         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3032 };
3033
3034 static void dump_vmcb(struct kvm_vcpu *vcpu)
3035 {
3036         struct vcpu_svm *svm = to_svm(vcpu);
3037         struct vmcb_control_area *control = &svm->vmcb->control;
3038         struct vmcb_save_area *save = &svm->vmcb->save;
3039
3040         if (!dump_invalid_vmcb) {
3041                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3042                 return;
3043         }
3044
3045         pr_err("VMCB Control Area:\n");
3046         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3047         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3048         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3049         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3050         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3051         pr_err("%-20s%08x %08x\n", "intercepts:",
3052               control->intercepts[INTERCEPT_WORD3],
3053                control->intercepts[INTERCEPT_WORD4]);
3054         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3055         pr_err("%-20s%d\n", "pause filter threshold:",
3056                control->pause_filter_thresh);
3057         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3058         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3059         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3060         pr_err("%-20s%d\n", "asid:", control->asid);
3061         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3062         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3063         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3064         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3065         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3066         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3067         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3068         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3069         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3070         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3071         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3072         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3073         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3074         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3075         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3076         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3077         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3078         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3079         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3080         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3081         pr_err("VMCB State Save Area:\n");
3082         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3083                "es:",
3084                save->es.selector, save->es.attrib,
3085                save->es.limit, save->es.base);
3086         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3087                "cs:",
3088                save->cs.selector, save->cs.attrib,
3089                save->cs.limit, save->cs.base);
3090         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3091                "ss:",
3092                save->ss.selector, save->ss.attrib,
3093                save->ss.limit, save->ss.base);
3094         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3095                "ds:",
3096                save->ds.selector, save->ds.attrib,
3097                save->ds.limit, save->ds.base);
3098         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3099                "fs:",
3100                save->fs.selector, save->fs.attrib,
3101                save->fs.limit, save->fs.base);
3102         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3103                "gs:",
3104                save->gs.selector, save->gs.attrib,
3105                save->gs.limit, save->gs.base);
3106         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3107                "gdtr:",
3108                save->gdtr.selector, save->gdtr.attrib,
3109                save->gdtr.limit, save->gdtr.base);
3110         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3111                "ldtr:",
3112                save->ldtr.selector, save->ldtr.attrib,
3113                save->ldtr.limit, save->ldtr.base);
3114         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3115                "idtr:",
3116                save->idtr.selector, save->idtr.attrib,
3117                save->idtr.limit, save->idtr.base);
3118         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3119                "tr:",
3120                save->tr.selector, save->tr.attrib,
3121                save->tr.limit, save->tr.base);
3122         pr_err("cpl:            %d                efer:         %016llx\n",
3123                 save->cpl, save->efer);
3124         pr_err("%-15s %016llx %-13s %016llx\n",
3125                "cr0:", save->cr0, "cr2:", save->cr2);
3126         pr_err("%-15s %016llx %-13s %016llx\n",
3127                "cr3:", save->cr3, "cr4:", save->cr4);
3128         pr_err("%-15s %016llx %-13s %016llx\n",
3129                "dr6:", save->dr6, "dr7:", save->dr7);
3130         pr_err("%-15s %016llx %-13s %016llx\n",
3131                "rip:", save->rip, "rflags:", save->rflags);
3132         pr_err("%-15s %016llx %-13s %016llx\n",
3133                "rsp:", save->rsp, "rax:", save->rax);
3134         pr_err("%-15s %016llx %-13s %016llx\n",
3135                "star:", save->star, "lstar:", save->lstar);
3136         pr_err("%-15s %016llx %-13s %016llx\n",
3137                "cstar:", save->cstar, "sfmask:", save->sfmask);
3138         pr_err("%-15s %016llx %-13s %016llx\n",
3139                "kernel_gs_base:", save->kernel_gs_base,
3140                "sysenter_cs:", save->sysenter_cs);
3141         pr_err("%-15s %016llx %-13s %016llx\n",
3142                "sysenter_esp:", save->sysenter_esp,
3143                "sysenter_eip:", save->sysenter_eip);
3144         pr_err("%-15s %016llx %-13s %016llx\n",
3145                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3146         pr_err("%-15s %016llx %-13s %016llx\n",
3147                "br_from:", save->br_from, "br_to:", save->br_to);
3148         pr_err("%-15s %016llx %-13s %016llx\n",
3149                "excp_from:", save->last_excp_from,
3150                "excp_to:", save->last_excp_to);
3151 }
3152
3153 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3154 {
3155         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3156             svm_exit_handlers[exit_code])
3157                 return 0;
3158
3159         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3160         dump_vmcb(vcpu);
3161         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3162         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3163         vcpu->run->internal.ndata = 2;
3164         vcpu->run->internal.data[0] = exit_code;
3165         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3166
3167         return -EINVAL;
3168 }
3169
3170 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3171 {
3172         if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3173                 return 0;
3174
3175 #ifdef CONFIG_RETPOLINE
3176         if (exit_code == SVM_EXIT_MSR)
3177                 return msr_interception(svm);
3178         else if (exit_code == SVM_EXIT_VINTR)
3179                 return interrupt_window_interception(svm);
3180         else if (exit_code == SVM_EXIT_INTR)
3181                 return intr_interception(svm);
3182         else if (exit_code == SVM_EXIT_HLT)
3183                 return halt_interception(svm);
3184         else if (exit_code == SVM_EXIT_NPF)
3185                 return npf_interception(svm);
3186 #endif
3187         return svm_exit_handlers[exit_code](svm);
3188 }
3189
3190 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3191                               u32 *intr_info, u32 *error_code)
3192 {
3193         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3194
3195         *info1 = control->exit_info_1;
3196         *info2 = control->exit_info_2;
3197         *intr_info = control->exit_int_info;
3198         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3199             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3200                 *error_code = control->exit_int_info_err;
3201         else
3202                 *error_code = 0;
3203 }
3204
3205 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3206 {
3207         struct vcpu_svm *svm = to_svm(vcpu);
3208         struct kvm_run *kvm_run = vcpu->run;
3209         u32 exit_code = svm->vmcb->control.exit_code;
3210
3211         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3212
3213         /* SEV-ES guests must use the CR write traps to track CR registers. */
3214         if (!sev_es_guest(vcpu->kvm)) {
3215                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3216                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3217                 if (npt_enabled)
3218                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3219         }
3220
3221         if (is_guest_mode(vcpu)) {
3222                 int vmexit;
3223
3224                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3225
3226                 vmexit = nested_svm_exit_special(svm);
3227
3228                 if (vmexit == NESTED_EXIT_CONTINUE)
3229                         vmexit = nested_svm_exit_handled(svm);
3230
3231                 if (vmexit == NESTED_EXIT_DONE)
3232                         return 1;
3233         }
3234
3235         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3236                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3237                 kvm_run->fail_entry.hardware_entry_failure_reason
3238                         = svm->vmcb->control.exit_code;
3239                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3240                 dump_vmcb(vcpu);
3241                 return 0;
3242         }
3243
3244         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3245             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3246             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3247             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3248                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3249                        "exit_code 0x%x\n",
3250                        __func__, svm->vmcb->control.exit_int_info,
3251                        exit_code);
3252
3253         if (exit_fastpath != EXIT_FASTPATH_NONE)
3254                 return 1;
3255
3256         return svm_invoke_exit_handler(svm, exit_code);
3257 }
3258
3259 static void reload_tss(struct kvm_vcpu *vcpu)
3260 {
3261         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3262
3263         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3264         load_TR_desc();
3265 }
3266
3267 static void pre_svm_run(struct vcpu_svm *svm)
3268 {
3269         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3270
3271         if (sev_guest(svm->vcpu.kvm))
3272                 return pre_sev_run(svm, svm->vcpu.cpu);
3273
3274         /* FIXME: handle wraparound of asid_generation */
3275         if (svm->asid_generation != sd->asid_generation)
3276                 new_asid(svm, sd);
3277 }
3278
3279 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3280 {
3281         struct vcpu_svm *svm = to_svm(vcpu);
3282
3283         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3284         vcpu->arch.hflags |= HF_NMI_MASK;
3285         svm_set_intercept(svm, INTERCEPT_IRET);
3286         ++vcpu->stat.nmi_injections;
3287 }
3288
3289 static void svm_set_irq(struct kvm_vcpu *vcpu)
3290 {
3291         struct vcpu_svm *svm = to_svm(vcpu);
3292
3293         BUG_ON(!(gif_set(svm)));
3294
3295         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3296         ++vcpu->stat.irq_injections;
3297
3298         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3299                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3300 }
3301
3302 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3303 {
3304         struct vcpu_svm *svm = to_svm(vcpu);
3305
3306         /*
3307          * SEV-ES guests must always keep the CR intercepts cleared. CR
3308          * tracking is done using the CR write traps.
3309          */
3310         if (sev_es_guest(vcpu->kvm))
3311                 return;
3312
3313         if (nested_svm_virtualize_tpr(vcpu))
3314                 return;
3315
3316         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3317
3318         if (irr == -1)
3319                 return;
3320
3321         if (tpr >= irr)
3322                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3323 }
3324
3325 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3326 {
3327         struct vcpu_svm *svm = to_svm(vcpu);
3328         struct vmcb *vmcb = svm->vmcb;
3329         bool ret;
3330
3331         if (!gif_set(svm))
3332                 return true;
3333
3334         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3335                 return false;
3336
3337         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3338               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3339
3340         return ret;
3341 }
3342
3343 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3344 {
3345         struct vcpu_svm *svm = to_svm(vcpu);
3346         if (svm->nested.nested_run_pending)
3347                 return -EBUSY;
3348
3349         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3350         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3351                 return -EBUSY;
3352
3353         return !svm_nmi_blocked(vcpu);
3354 }
3355
3356 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3357 {
3358         struct vcpu_svm *svm = to_svm(vcpu);
3359
3360         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3361 }
3362
3363 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3364 {
3365         struct vcpu_svm *svm = to_svm(vcpu);
3366
3367         if (masked) {
3368                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3369                 svm_set_intercept(svm, INTERCEPT_IRET);
3370         } else {
3371                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3372                 svm_clr_intercept(svm, INTERCEPT_IRET);
3373         }
3374 }
3375
3376 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3377 {
3378         struct vcpu_svm *svm = to_svm(vcpu);
3379         struct vmcb *vmcb = svm->vmcb;
3380
3381         if (!gif_set(svm))
3382                 return true;
3383
3384         if (sev_es_guest(svm->vcpu.kvm)) {
3385                 /*
3386                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3387                  * bit to determine the state of the IF flag.
3388                  */
3389                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3390                         return true;
3391         } else if (is_guest_mode(vcpu)) {
3392                 /* As long as interrupts are being delivered...  */
3393                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3394                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3395                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3396                         return true;
3397
3398                 /* ... vmexits aren't blocked by the interrupt shadow  */
3399                 if (nested_exit_on_intr(svm))
3400                         return false;
3401         } else {
3402                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3403                         return true;
3404         }
3405
3406         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3407 }
3408
3409 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3410 {
3411         struct vcpu_svm *svm = to_svm(vcpu);
3412         if (svm->nested.nested_run_pending)
3413                 return -EBUSY;
3414
3415         /*
3416          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3417          * e.g. if the IRQ arrived asynchronously after checking nested events.
3418          */
3419         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3420                 return -EBUSY;
3421
3422         return !svm_interrupt_blocked(vcpu);
3423 }
3424
3425 static void enable_irq_window(struct kvm_vcpu *vcpu)
3426 {
3427         struct vcpu_svm *svm = to_svm(vcpu);
3428
3429         /*
3430          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3431          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3432          * get that intercept, this function will be called again though and
3433          * we'll get the vintr intercept. However, if the vGIF feature is
3434          * enabled, the STGI interception will not occur. Enable the irq
3435          * window under the assumption that the hardware will set the GIF.
3436          */
3437         if (vgif_enabled(svm) || gif_set(svm)) {
3438                 /*
3439                  * IRQ window is not needed when AVIC is enabled,
3440                  * unless we have pending ExtINT since it cannot be injected
3441                  * via AVIC. In such case, we need to temporarily disable AVIC,
3442                  * and fallback to injecting IRQ via V_IRQ.
3443                  */
3444                 svm_toggle_avic_for_irq_window(vcpu, false);
3445                 svm_set_vintr(svm);
3446         }
3447 }
3448
3449 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3450 {
3451         struct vcpu_svm *svm = to_svm(vcpu);
3452
3453         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3454             == HF_NMI_MASK)
3455                 return; /* IRET will cause a vm exit */
3456
3457         if (!gif_set(svm)) {
3458                 if (vgif_enabled(svm))
3459                         svm_set_intercept(svm, INTERCEPT_STGI);
3460                 return; /* STGI will cause a vm exit */
3461         }
3462
3463         /*
3464          * Something prevents NMI from been injected. Single step over possible
3465          * problem (IRET or exception injection or interrupt shadow)
3466          */
3467         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3468         svm->nmi_singlestep = true;
3469         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3470 }
3471
3472 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3473 {
3474         return 0;
3475 }
3476
3477 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3478 {
3479         return 0;
3480 }
3481
3482 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3483 {
3484         struct vcpu_svm *svm = to_svm(vcpu);
3485
3486         /*
3487          * Flush only the current ASID even if the TLB flush was invoked via
3488          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3489          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3490          * unconditionally does a TLB flush on both nested VM-Enter and nested
3491          * VM-Exit (via kvm_mmu_reset_context()).
3492          */
3493         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3494                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3495         else
3496                 svm->asid_generation--;
3497 }
3498
3499 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3500 {
3501         struct vcpu_svm *svm = to_svm(vcpu);
3502
3503         invlpga(gva, svm->vmcb->control.asid);
3504 }
3505
3506 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3507 {
3508 }
3509
3510 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3511 {
3512         struct vcpu_svm *svm = to_svm(vcpu);
3513
3514         if (nested_svm_virtualize_tpr(vcpu))
3515                 return;
3516
3517         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3518                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3519                 kvm_set_cr8(vcpu, cr8);
3520         }
3521 }
3522
3523 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3524 {
3525         struct vcpu_svm *svm = to_svm(vcpu);
3526         u64 cr8;
3527
3528         if (nested_svm_virtualize_tpr(vcpu) ||
3529             kvm_vcpu_apicv_active(vcpu))
3530                 return;
3531
3532         cr8 = kvm_get_cr8(vcpu);
3533         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3534         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3535 }
3536
3537 static void svm_complete_interrupts(struct vcpu_svm *svm)
3538 {
3539         u8 vector;
3540         int type;
3541         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3542         unsigned int3_injected = svm->int3_injected;
3543
3544         svm->int3_injected = 0;
3545
3546         /*
3547          * If we've made progress since setting HF_IRET_MASK, we've
3548          * executed an IRET and can allow NMI injection.
3549          */
3550         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3551             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3552                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3553                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3554         }
3555
3556         svm->vcpu.arch.nmi_injected = false;
3557         kvm_clear_exception_queue(&svm->vcpu);
3558         kvm_clear_interrupt_queue(&svm->vcpu);
3559
3560         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3561                 return;
3562
3563         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3564
3565         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3566         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3567
3568         switch (type) {
3569         case SVM_EXITINTINFO_TYPE_NMI:
3570                 svm->vcpu.arch.nmi_injected = true;
3571                 break;
3572         case SVM_EXITINTINFO_TYPE_EXEPT:
3573                 /*
3574                  * Never re-inject a #VC exception.
3575                  */
3576                 if (vector == X86_TRAP_VC)
3577                         break;
3578
3579                 /*
3580                  * In case of software exceptions, do not reinject the vector,
3581                  * but re-execute the instruction instead. Rewind RIP first
3582                  * if we emulated INT3 before.
3583                  */
3584                 if (kvm_exception_is_soft(vector)) {
3585                         if (vector == BP_VECTOR && int3_injected &&
3586                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3587                                 kvm_rip_write(&svm->vcpu,
3588                                               kvm_rip_read(&svm->vcpu) -
3589                                               int3_injected);
3590                         break;
3591                 }
3592                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3593                         u32 err = svm->vmcb->control.exit_int_info_err;
3594                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3595
3596                 } else
3597                         kvm_requeue_exception(&svm->vcpu, vector);
3598                 break;
3599         case SVM_EXITINTINFO_TYPE_INTR:
3600                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3601                 break;
3602         default:
3603                 break;
3604         }
3605 }
3606
3607 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3608 {
3609         struct vcpu_svm *svm = to_svm(vcpu);
3610         struct vmcb_control_area *control = &svm->vmcb->control;
3611
3612         control->exit_int_info = control->event_inj;
3613         control->exit_int_info_err = control->event_inj_err;
3614         control->event_inj = 0;
3615         svm_complete_interrupts(svm);
3616 }
3617
3618 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3619 {
3620         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3621             to_svm(vcpu)->vmcb->control.exit_info_1)
3622                 return handle_fastpath_set_msr_irqoff(vcpu);
3623
3624         return EXIT_FASTPATH_NONE;
3625 }
3626
3627 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3628
3629 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3630                                         struct vcpu_svm *svm)
3631 {
3632         /*
3633          * VMENTER enables interrupts (host state), but the kernel state is
3634          * interrupts disabled when this is invoked. Also tell RCU about
3635          * it. This is the same logic as for exit_to_user_mode().
3636          *
3637          * This ensures that e.g. latency analysis on the host observes
3638          * guest mode as interrupt enabled.
3639          *
3640          * guest_enter_irqoff() informs context tracking about the
3641          * transition to guest mode and if enabled adjusts RCU state
3642          * accordingly.
3643          */
3644         instrumentation_begin();
3645         trace_hardirqs_on_prepare();
3646         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3647         instrumentation_end();
3648
3649         guest_enter_irqoff();
3650         lockdep_hardirqs_on(CALLER_ADDR0);
3651
3652         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3653
3654 #ifdef CONFIG_X86_64
3655         native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3656 #else
3657         loadsegment(fs, svm->host.fs);
3658 #ifndef CONFIG_X86_32_LAZY_GS
3659         loadsegment(gs, svm->host.gs);
3660 #endif
3661 #endif
3662
3663         /*
3664          * VMEXIT disables interrupts (host state), but tracing and lockdep
3665          * have them in state 'on' as recorded before entering guest mode.
3666          * Same as enter_from_user_mode().
3667          *
3668          * guest_exit_irqoff() restores host context and reinstates RCU if
3669          * enabled and required.
3670          *
3671          * This needs to be done before the below as native_read_msr()
3672          * contains a tracepoint and x86_spec_ctrl_restore_host() calls