1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Enable support of hierarchical irqdomains
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/seq_file.h>
13 #include <linux/init.h>
14 #include <linux/compiler.h>
15 #include <linux/slab.h>
16 #include <asm/irqdomain.h>
17 #include <asm/hw_irq.h>
18 #include <asm/traps.h>
20 #include <asm/i8259.h>
22 #include <asm/irq_remapping.h>
24 #include <asm/trace/irq_vectors.h>
26 struct apic_chip_data {
27 struct irq_cfg hw_irq_cfg;
29 unsigned int prev_vector;
31 unsigned int prev_cpu;
33 struct hlist_node clist;
34 unsigned int move_in_progress : 1,
40 struct irq_domain *x86_vector_domain;
41 EXPORT_SYMBOL_GPL(x86_vector_domain);
42 static DEFINE_RAW_SPINLOCK(vector_lock);
43 static cpumask_var_t vector_searchmask;
44 static struct irq_chip lapic_controller;
45 static struct irq_matrix *vector_matrix;
47 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
50 void lock_vector_lock(void)
52 /* Used to the online set of cpus does not change
53 * during assign_irq_vector.
55 raw_spin_lock(&vector_lock);
58 void unlock_vector_lock(void)
60 raw_spin_unlock(&vector_lock);
63 void init_irq_alloc_info(struct irq_alloc_info *info,
64 const struct cpumask *mask)
66 memset(info, 0, sizeof(*info));
70 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
75 memset(dst, 0, sizeof(*dst));
78 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
83 while (irqd->parent_data)
84 irqd = irqd->parent_data;
86 return irqd->chip_data;
89 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
91 struct apic_chip_data *apicd = apic_chip_data(irqd);
93 return apicd ? &apicd->hw_irq_cfg : NULL;
95 EXPORT_SYMBOL_GPL(irqd_cfg);
97 struct irq_cfg *irq_cfg(unsigned int irq)
99 return irqd_cfg(irq_get_irq_data(irq));
102 static struct apic_chip_data *alloc_apic_chip_data(int node)
104 struct apic_chip_data *apicd;
106 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
108 INIT_HLIST_NODE(&apicd->clist);
112 static void free_apic_chip_data(struct apic_chip_data *apicd)
117 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
120 struct apic_chip_data *apicd = apic_chip_data(irqd);
122 lockdep_assert_held(&vector_lock);
124 apicd->hw_irq_cfg.vector = vector;
125 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
126 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
127 trace_vector_config(irqd->irq, vector, cpu,
128 apicd->hw_irq_cfg.dest_apicid);
131 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
134 struct apic_chip_data *apicd = apic_chip_data(irqd);
135 struct irq_desc *desc = irq_data_to_desc(irqd);
136 bool managed = irqd_affinity_is_managed(irqd);
138 lockdep_assert_held(&vector_lock);
140 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
144 * If there is no vector associated or if the associated vector is
145 * the shutdown vector, which is associated to make PCI/MSI
146 * shutdown mode work, then there is nothing to release. Clear out
147 * prev_vector for this and the offlined target case.
149 apicd->prev_vector = 0;
150 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
153 * If the target CPU of the previous vector is online, then mark
154 * the vector as move in progress and store it for cleanup when the
155 * first interrupt on the new vector arrives. If the target CPU is
156 * offline then the regular release mechanism via the cleanup
157 * vector is not possible and the vector can be immediately freed
158 * in the underlying matrix allocator.
160 if (cpu_online(apicd->cpu)) {
161 apicd->move_in_progress = true;
162 apicd->prev_vector = apicd->vector;
163 apicd->prev_cpu = apicd->cpu;
164 WARN_ON_ONCE(apicd->cpu == newcpu);
166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
171 apicd->vector = newvec;
173 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
174 per_cpu(vector_irq, newcpu)[newvec] = desc;
177 static void vector_assign_managed_shutdown(struct irq_data *irqd)
179 unsigned int cpu = cpumask_first(cpu_online_mask);
181 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
184 static int reserve_managed_vector(struct irq_data *irqd)
186 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
187 struct apic_chip_data *apicd = apic_chip_data(irqd);
191 raw_spin_lock_irqsave(&vector_lock, flags);
192 apicd->is_managed = true;
193 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
194 raw_spin_unlock_irqrestore(&vector_lock, flags);
195 trace_vector_reserve_managed(irqd->irq, ret);
199 static void reserve_irq_vector_locked(struct irq_data *irqd)
201 struct apic_chip_data *apicd = apic_chip_data(irqd);
203 irq_matrix_reserve(vector_matrix);
204 apicd->can_reserve = true;
205 apicd->has_reserved = true;
206 irqd_set_can_reserve(irqd);
207 trace_vector_reserve(irqd->irq, 0);
208 vector_assign_managed_shutdown(irqd);
211 static int reserve_irq_vector(struct irq_data *irqd)
215 raw_spin_lock_irqsave(&vector_lock, flags);
216 reserve_irq_vector_locked(irqd);
217 raw_spin_unlock_irqrestore(&vector_lock, flags);
222 assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest)
224 struct apic_chip_data *apicd = apic_chip_data(irqd);
225 bool resvd = apicd->has_reserved;
226 unsigned int cpu = apicd->cpu;
227 int vector = apicd->vector;
229 lockdep_assert_held(&vector_lock);
232 * If the current target CPU is online and in the new requested
233 * affinity mask, there is no point in moving the interrupt from
234 * one CPU to another.
236 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
240 * Careful here. @apicd might either have move_in_progress set or
241 * be enqueued for cleanup. Assigning a new vector would either
242 * leave a stale vector on some CPU around or in case of a pending
243 * cleanup corrupt the hlist.
245 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
248 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
249 trace_vector_alloc(irqd->irq, vector, resvd, vector);
252 apic_update_vector(irqd, vector, cpu);
253 apic_update_irq_cfg(irqd, vector, cpu);
258 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
263 raw_spin_lock_irqsave(&vector_lock, flags);
264 cpumask_and(vector_searchmask, dest, cpu_online_mask);
265 ret = assign_vector_locked(irqd, vector_searchmask);
266 raw_spin_unlock_irqrestore(&vector_lock, flags);
270 static int assign_irq_vector_any_locked(struct irq_data *irqd)
272 /* Get the affinity mask - either irq_default_affinity or (user) set */
273 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
274 int node = irq_data_get_node(irqd);
276 if (node != NUMA_NO_NODE) {
277 /* Try the intersection of @affmsk and node mask */
278 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
279 if (!assign_vector_locked(irqd, vector_searchmask))
283 /* Try the full affinity mask */
284 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
285 if (!assign_vector_locked(irqd, vector_searchmask))
288 if (node != NUMA_NO_NODE) {
289 /* Try the node mask */
290 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
294 /* Try the full online mask */
295 return assign_vector_locked(irqd, cpu_online_mask);
299 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
301 if (irqd_affinity_is_managed(irqd))
302 return reserve_managed_vector(irqd);
304 return assign_irq_vector(irqd, info->mask);
306 * Make only a global reservation with no guarantee. A real vector
307 * is associated at activation time.
309 return reserve_irq_vector(irqd);
313 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
315 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
316 struct apic_chip_data *apicd = apic_chip_data(irqd);
319 cpumask_and(vector_searchmask, dest, affmsk);
321 /* set_affinity might call here for nothing */
322 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
324 vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask,
326 trace_vector_alloc_managed(irqd->irq, vector, vector);
329 apic_update_vector(irqd, vector, cpu);
330 apic_update_irq_cfg(irqd, vector, cpu);
334 static void clear_irq_vector(struct irq_data *irqd)
336 struct apic_chip_data *apicd = apic_chip_data(irqd);
337 bool managed = irqd_affinity_is_managed(irqd);
338 unsigned int vector = apicd->vector;
340 lockdep_assert_held(&vector_lock);
345 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
348 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_SHUTDOWN;
349 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
352 /* Clean up move in progress */
353 vector = apicd->prev_vector;
357 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_SHUTDOWN;
358 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
359 apicd->prev_vector = 0;
360 apicd->move_in_progress = 0;
361 hlist_del_init(&apicd->clist);
364 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
366 struct apic_chip_data *apicd = apic_chip_data(irqd);
369 trace_vector_deactivate(irqd->irq, apicd->is_managed,
370 apicd->can_reserve, false);
372 /* Regular fixed assigned interrupt */
373 if (!apicd->is_managed && !apicd->can_reserve)
375 /* If the interrupt has a global reservation, nothing to do */
376 if (apicd->has_reserved)
379 raw_spin_lock_irqsave(&vector_lock, flags);
380 clear_irq_vector(irqd);
381 if (apicd->can_reserve)
382 reserve_irq_vector_locked(irqd);
384 vector_assign_managed_shutdown(irqd);
385 raw_spin_unlock_irqrestore(&vector_lock, flags);
388 static int activate_reserved(struct irq_data *irqd)
390 struct apic_chip_data *apicd = apic_chip_data(irqd);
393 ret = assign_irq_vector_any_locked(irqd);
395 apicd->has_reserved = false;
397 * Core might have disabled reservation mode after
398 * allocating the irq descriptor. Ideally this should
399 * happen before allocation time, but that would require
400 * completely convoluted ways of transporting that
403 if (!irqd_can_reserve(irqd))
404 apicd->can_reserve = false;
408 * Check to ensure that the effective affinity mask is a subset
409 * the user supplied affinity mask, and warn the user if it is not
411 if (!cpumask_subset(irq_data_get_effective_affinity_mask(irqd),
412 irq_data_get_affinity_mask(irqd))) {
413 pr_warn("irq %u: Affinity broken due to vector space exhaustion.\n",
420 static int activate_managed(struct irq_data *irqd)
422 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
425 cpumask_and(vector_searchmask, dest, cpu_online_mask);
426 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
427 /* Something in the core code broke! Survive gracefully */
428 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
432 ret = assign_managed_vector(irqd, vector_searchmask);
434 * This should not happen. The vector reservation got buggered. Handle
437 if (WARN_ON_ONCE(ret < 0)) {
438 pr_err("Managed startup irq %u, no vector available\n",
444 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
447 struct apic_chip_data *apicd = apic_chip_data(irqd);
451 trace_vector_activate(irqd->irq, apicd->is_managed,
452 apicd->can_reserve, reserve);
454 raw_spin_lock_irqsave(&vector_lock, flags);
455 if (!apicd->can_reserve && !apicd->is_managed)
456 assign_irq_vector_any_locked(irqd);
457 else if (reserve || irqd_is_managed_and_shutdown(irqd))
458 vector_assign_managed_shutdown(irqd);
459 else if (apicd->is_managed)
460 ret = activate_managed(irqd);
461 else if (apicd->has_reserved)
462 ret = activate_reserved(irqd);
463 raw_spin_unlock_irqrestore(&vector_lock, flags);
467 static void vector_free_reserved_and_managed(struct irq_data *irqd)
469 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
470 struct apic_chip_data *apicd = apic_chip_data(irqd);
472 trace_vector_teardown(irqd->irq, apicd->is_managed,
473 apicd->has_reserved);
475 if (apicd->has_reserved)
476 irq_matrix_remove_reserved(vector_matrix);
477 if (apicd->is_managed)
478 irq_matrix_remove_managed(vector_matrix, dest);
481 static void x86_vector_free_irqs(struct irq_domain *domain,
482 unsigned int virq, unsigned int nr_irqs)
484 struct apic_chip_data *apicd;
485 struct irq_data *irqd;
489 for (i = 0; i < nr_irqs; i++) {
490 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
491 if (irqd && irqd->chip_data) {
492 raw_spin_lock_irqsave(&vector_lock, flags);
493 clear_irq_vector(irqd);
494 vector_free_reserved_and_managed(irqd);
495 apicd = irqd->chip_data;
496 irq_domain_reset_irq_data(irqd);
497 raw_spin_unlock_irqrestore(&vector_lock, flags);
498 free_apic_chip_data(apicd);
503 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
504 struct apic_chip_data *apicd)
507 bool realloc = false;
509 apicd->vector = ISA_IRQ_VECTOR(virq);
512 raw_spin_lock_irqsave(&vector_lock, flags);
514 * If the interrupt is activated, then it must stay at this vector
515 * position. That's usually the timer interrupt (0).
517 if (irqd_is_activated(irqd)) {
518 trace_vector_setup(virq, true, 0);
519 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
521 /* Release the vector */
522 apicd->can_reserve = true;
523 irqd_set_can_reserve(irqd);
524 clear_irq_vector(irqd);
527 raw_spin_unlock_irqrestore(&vector_lock, flags);
531 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
532 unsigned int nr_irqs, void *arg)
534 struct irq_alloc_info *info = arg;
535 struct apic_chip_data *apicd;
536 struct irq_data *irqd;
542 /* Currently vector allocator can't guarantee contiguous allocations */
543 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
547 * Catch any attempt to touch the cascade interrupt on a PIC
550 if (WARN_ON_ONCE(info->flags & X86_IRQ_ALLOC_LEGACY &&
551 virq == PIC_CASCADE_IR))
554 for (i = 0; i < nr_irqs; i++) {
555 irqd = irq_domain_get_irq_data(domain, virq + i);
557 node = irq_data_get_node(irqd);
558 WARN_ON_ONCE(irqd->chip_data);
559 apicd = alloc_apic_chip_data(node);
565 apicd->irq = virq + i;
566 irqd->chip = &lapic_controller;
567 irqd->chip_data = apicd;
568 irqd->hwirq = virq + i;
569 irqd_set_single_target(irqd);
571 * Prevent that any of these interrupts is invoked in
572 * non interrupt context via e.g. generic_handle_irq()
573 * as that can corrupt the affinity move state.
575 irqd_set_handle_enforce_irqctx(irqd);
577 /* Don't invoke affinity setter on deactivated interrupts */
578 irqd_set_affinity_on_activate(irqd);
581 * Legacy vectors are already assigned when the IOAPIC
582 * takes them over. They stay on the same vector. This is
583 * required for check_timer() to work correctly as it might
584 * switch back to legacy mode. Only update the hardware
587 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
588 if (!vector_configure_legacy(virq + i, irqd, apicd))
592 err = assign_irq_vector_policy(irqd, info);
593 trace_vector_setup(virq + i, false, err);
595 irqd->chip_data = NULL;
596 free_apic_chip_data(apicd);
604 x86_vector_free_irqs(domain, virq, i);
608 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
609 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
610 struct irq_data *irqd, int ind)
612 struct apic_chip_data apicd;
617 irq_matrix_debug_show(m, vector_matrix, ind);
622 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
623 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
624 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
628 if (!irqd->chip_data) {
629 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
633 raw_spin_lock_irqsave(&vector_lock, flags);
634 memcpy(&apicd, irqd->chip_data, sizeof(apicd));
635 raw_spin_unlock_irqrestore(&vector_lock, flags);
637 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
638 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
639 if (apicd.prev_vector) {
640 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
641 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
643 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
644 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0);
645 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0);
646 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0);
647 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist));
651 int x86_fwspec_is_ioapic(struct irq_fwspec *fwspec)
653 if (fwspec->param_count != 1)
656 if (is_fwnode_irqchip(fwspec->fwnode)) {
657 const char *fwname = fwnode_get_name(fwspec->fwnode);
658 return fwname && !strncmp(fwname, "IO-APIC-", 8) &&
659 simple_strtol(fwname+8, NULL, 10) == fwspec->param[0];
661 return to_of_node(fwspec->fwnode) &&
662 of_device_is_compatible(to_of_node(fwspec->fwnode),
663 "intel,ce4100-ioapic");
666 int x86_fwspec_is_hpet(struct irq_fwspec *fwspec)
668 if (fwspec->param_count != 1)
671 if (is_fwnode_irqchip(fwspec->fwnode)) {
672 const char *fwname = fwnode_get_name(fwspec->fwnode);
673 return fwname && !strncmp(fwname, "HPET-MSI-", 9) &&
674 simple_strtol(fwname+9, NULL, 10) == fwspec->param[0];
679 static int x86_vector_select(struct irq_domain *d, struct irq_fwspec *fwspec,
680 enum irq_domain_bus_token bus_token)
683 * HPET and I/OAPIC cannot be parented in the vector domain
684 * if IRQ remapping is enabled. APIC IDs above 15 bits are
685 * only permitted if IRQ remapping is enabled, so check that.
687 if (apic->apic_id_valid(32768))
690 return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec);
693 static const struct irq_domain_ops x86_vector_domain_ops = {
694 .select = x86_vector_select,
695 .alloc = x86_vector_alloc_irqs,
696 .free = x86_vector_free_irqs,
697 .activate = x86_vector_activate,
698 .deactivate = x86_vector_deactivate,
699 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
700 .debug_show = x86_vector_debug_show,
704 int __init arch_probe_nr_irqs(void)
708 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
709 nr_irqs = NR_VECTORS * nr_cpu_ids;
711 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
712 #if defined(CONFIG_PCI_MSI)
714 * for MSI and HT dyn irq
716 if (gsi_top <= NR_IRQS_LEGACY)
717 nr += 8 * nr_cpu_ids;
725 * We don't know if PIC is present at this point so we need to do
726 * probe() to get the right number of legacy IRQs.
728 return legacy_pic->probe();
731 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
734 * Use assign system here so it wont get accounted as allocated
735 * and moveable in the cpu hotplug check and it prevents managed
736 * irq reservation from touching it.
738 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
741 void __init lapic_assign_system_vectors(void)
743 unsigned int i, vector = 0;
745 for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
746 irq_matrix_assign_system(vector_matrix, vector, false);
748 if (nr_legacy_irqs() > 1)
749 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
751 /* System vectors are reserved, online it */
752 irq_matrix_online(vector_matrix);
754 /* Mark the preallocated legacy interrupts */
755 for (i = 0; i < nr_legacy_irqs(); i++) {
757 * Don't touch the cascade interrupt. It's unusable
758 * on PIC equipped machines. See the large comment
759 * in the IO/APIC code.
761 if (i != PIC_CASCADE_IR)
762 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
766 int __init arch_early_irq_init(void)
768 struct fwnode_handle *fn;
770 fn = irq_domain_alloc_named_fwnode("VECTOR");
772 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
774 BUG_ON(x86_vector_domain == NULL);
775 irq_set_default_host(x86_vector_domain);
777 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
780 * Allocate the vector matrix allocator data structure and limit the
783 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
784 FIRST_SYSTEM_VECTOR);
785 BUG_ON(!vector_matrix);
787 return arch_early_ioapic_init();
792 static struct irq_desc *__setup_vector_irq(int vector)
794 int isairq = vector - ISA_IRQ_VECTOR(0);
796 /* Check whether the irq is in the legacy space */
797 if (isairq < 0 || isairq >= nr_legacy_irqs())
798 return VECTOR_UNUSED;
799 /* Check whether the irq is handled by the IOAPIC */
800 if (test_bit(isairq, &io_apic_irqs))
801 return VECTOR_UNUSED;
802 return irq_to_desc(isairq);
805 /* Online the local APIC infrastructure and initialize the vectors */
806 void lapic_online(void)
810 lockdep_assert_held(&vector_lock);
812 /* Online the vector matrix array for this CPU */
813 irq_matrix_online(vector_matrix);
816 * The interrupt affinity logic never targets interrupts to offline
817 * CPUs. The exception are the legacy PIC interrupts. In general
818 * they are only targeted to CPU0, but depending on the platform
819 * they can be distributed to any online CPU in hardware. The
820 * kernel has no influence on that. So all active legacy vectors
821 * must be installed on all CPUs. All non legacy interrupts can be
824 for (vector = 0; vector < NR_VECTORS; vector++)
825 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
828 void lapic_offline(void)
831 irq_matrix_offline(vector_matrix);
832 unlock_vector_lock();
835 static int apic_set_affinity(struct irq_data *irqd,
836 const struct cpumask *dest, bool force)
840 if (WARN_ON_ONCE(!irqd_is_activated(irqd)))
843 raw_spin_lock(&vector_lock);
844 cpumask_and(vector_searchmask, dest, cpu_online_mask);
845 if (irqd_affinity_is_managed(irqd))
846 err = assign_managed_vector(irqd, vector_searchmask);
848 err = assign_vector_locked(irqd, vector_searchmask);
849 raw_spin_unlock(&vector_lock);
850 return err ? err : IRQ_SET_MASK_OK;
854 # define apic_set_affinity NULL
857 static int apic_retrigger_irq(struct irq_data *irqd)
859 struct apic_chip_data *apicd = apic_chip_data(irqd);
862 raw_spin_lock_irqsave(&vector_lock, flags);
863 apic->send_IPI(apicd->cpu, apicd->vector);
864 raw_spin_unlock_irqrestore(&vector_lock, flags);
869 void apic_ack_irq(struct irq_data *irqd)
875 void apic_ack_edge(struct irq_data *irqd)
877 irq_complete_move(irqd_cfg(irqd));
881 static void x86_vector_msi_compose_msg(struct irq_data *data,
884 __irq_msi_compose_msg(irqd_cfg(data), msg, false);
887 static struct irq_chip lapic_controller = {
889 .irq_ack = apic_ack_edge,
890 .irq_set_affinity = apic_set_affinity,
891 .irq_compose_msi_msg = x86_vector_msi_compose_msg,
892 .irq_retrigger = apic_retrigger_irq,
897 static void free_moved_vector(struct apic_chip_data *apicd)
899 unsigned int vector = apicd->prev_vector;
900 unsigned int cpu = apicd->prev_cpu;
901 bool managed = apicd->is_managed;
904 * Managed interrupts are usually not migrated away
905 * from an online CPU, but CPU isolation 'managed_irq'
906 * can make that happen.
907 * 1) Activation does not take the isolation into account
908 * to keep the code simple
909 * 2) Migration away from an isolated CPU can happen when
910 * a non-isolated CPU which is in the calculated
911 * affinity mask comes online.
913 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
914 irq_matrix_free(vector_matrix, cpu, vector, managed);
915 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
916 hlist_del_init(&apicd->clist);
917 apicd->prev_vector = 0;
918 apicd->move_in_progress = 0;
921 DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_cleanup)
923 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
924 struct apic_chip_data *apicd;
925 struct hlist_node *tmp;
928 /* Prevent vectors vanishing under us */
929 raw_spin_lock(&vector_lock);
931 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
932 unsigned int irr, vector = apicd->prev_vector;
935 * Paranoia: Check if the vector that needs to be cleaned
936 * up is registered at the APICs IRR. If so, then this is
937 * not the best time to clean it up. Clean it up in the
938 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
939 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
940 * priority external vector, so on return from this
941 * interrupt the device interrupt will happen first.
943 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
944 if (irr & (1U << (vector % 32))) {
945 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
948 free_moved_vector(apicd);
951 raw_spin_unlock(&vector_lock);
954 static void __send_cleanup_vector(struct apic_chip_data *apicd)
958 raw_spin_lock(&vector_lock);
959 apicd->move_in_progress = 0;
960 cpu = apicd->prev_cpu;
961 if (cpu_online(cpu)) {
962 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
963 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
965 apicd->prev_vector = 0;
967 raw_spin_unlock(&vector_lock);
970 void send_cleanup_vector(struct irq_cfg *cfg)
972 struct apic_chip_data *apicd;
974 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
975 if (apicd->move_in_progress)
976 __send_cleanup_vector(apicd);
979 void irq_complete_move(struct irq_cfg *cfg)
981 struct apic_chip_data *apicd;
983 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
984 if (likely(!apicd->move_in_progress))
988 * If the interrupt arrived on the new target CPU, cleanup the
989 * vector on the old target CPU. A vector check is not required
990 * because an interrupt can never move from one vector to another
993 if (apicd->cpu == smp_processor_id())
994 __send_cleanup_vector(apicd);
998 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
1000 void irq_force_complete_move(struct irq_desc *desc)
1002 struct apic_chip_data *apicd;
1003 struct irq_data *irqd;
1004 unsigned int vector;
1007 * The function is called for all descriptors regardless of which
1008 * irqdomain they belong to. For example if an IRQ is provided by
1009 * an irq_chip as part of a GPIO driver, the chip data for that
1010 * descriptor is specific to the irq_chip in question.
1012 * Check first that the chip_data is what we expect
1013 * (apic_chip_data) before touching it any further.
1015 irqd = irq_domain_get_irq_data(x86_vector_domain,
1016 irq_desc_get_irq(desc));
1020 raw_spin_lock(&vector_lock);
1021 apicd = apic_chip_data(irqd);
1026 * If prev_vector is empty, no action required.
1028 vector = apicd->prev_vector;
1033 * This is tricky. If the cleanup of the old vector has not been
1034 * done yet, then the following setaffinity call will fail with
1035 * -EBUSY. This can leave the interrupt in a stale state.
1037 * All CPUs are stuck in stop machine with interrupts disabled so
1038 * calling __irq_complete_move() would be completely pointless.
1040 * 1) The interrupt is in move_in_progress state. That means that we
1041 * have not seen an interrupt since the io_apic was reprogrammed to
1044 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
1045 * have not been processed yet.
1047 if (apicd->move_in_progress) {
1049 * In theory there is a race:
1051 * set_ioapic(new_vector) <-- Interrupt is raised before update
1052 * is effective, i.e. it's raised on
1055 * So if the target cpu cannot handle that interrupt before
1056 * the old vector is cleaned up, we get a spurious interrupt
1057 * and in the worst case the ioapic irq line becomes stale.
1059 * But in case of cpu hotplug this should be a non issue
1060 * because if the affinity update happens right before all
1061 * cpus rendezvous in stop machine, there is no way that the
1062 * interrupt can be blocked on the target cpu because all cpus
1063 * loops first with interrupts enabled in stop machine, so the
1064 * old vector is not yet cleaned up when the interrupt fires.
1066 * So the only way to run into this issue is if the delivery
1067 * of the interrupt on the apic/system bus would be delayed
1068 * beyond the point where the target cpu disables interrupts
1069 * in stop machine. I doubt that it can happen, but at least
1070 * there is a theoretical chance. Virtualization might be
1071 * able to expose this, but AFAICT the IOAPIC emulation is not
1072 * as stupid as the real hardware.
1074 * Anyway, there is nothing we can do about that at this point
1075 * w/o refactoring the whole fixup_irq() business completely.
1076 * We print at least the irq number and the old vector number,
1077 * so we have the necessary information when a problem in that
1080 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1083 free_moved_vector(apicd);
1085 raw_spin_unlock(&vector_lock);
1088 #ifdef CONFIG_HOTPLUG_CPU
1090 * Note, this is not accurate accounting, but at least good enough to
1091 * prevent that the actual interrupt move will run out of vectors.
1093 int lapic_can_unplug_cpu(void)
1095 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1098 raw_spin_lock(&vector_lock);
1099 tomove = irq_matrix_allocated(vector_matrix);
1100 avl = irq_matrix_available(vector_matrix, true);
1102 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1107 rsvd = irq_matrix_reserved(vector_matrix);
1109 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1113 raw_spin_unlock(&vector_lock);
1116 #endif /* HOTPLUG_CPU */
1119 static void __init print_APIC_field(int base)
1125 for (i = 0; i < 8; i++)
1126 pr_cont("%08x", apic_read(base + i*0x10));
1131 static void __init print_local_APIC(void *dummy)
1133 unsigned int i, v, ver, maxlvt;
1136 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1137 smp_processor_id(), hard_smp_processor_id());
1138 v = apic_read(APIC_ID);
1139 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1140 v = apic_read(APIC_LVR);
1141 pr_info("... APIC VERSION: %08x\n", v);
1142 ver = GET_APIC_VERSION(v);
1143 maxlvt = lapic_get_maxlvt();
1145 v = apic_read(APIC_TASKPRI);
1146 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1149 if (APIC_INTEGRATED(ver)) {
1150 if (!APIC_XAPIC(ver)) {
1151 v = apic_read(APIC_ARBPRI);
1152 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1153 v, v & APIC_ARBPRI_MASK);
1155 v = apic_read(APIC_PROCPRI);
1156 pr_debug("... APIC PROCPRI: %08x\n", v);
1160 * Remote read supported only in the 82489DX and local APIC for
1161 * Pentium processors.
1163 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1164 v = apic_read(APIC_RRR);
1165 pr_debug("... APIC RRR: %08x\n", v);
1168 v = apic_read(APIC_LDR);
1169 pr_debug("... APIC LDR: %08x\n", v);
1170 if (!x2apic_enabled()) {
1171 v = apic_read(APIC_DFR);
1172 pr_debug("... APIC DFR: %08x\n", v);
1174 v = apic_read(APIC_SPIV);
1175 pr_debug("... APIC SPIV: %08x\n", v);
1177 pr_debug("... APIC ISR field:\n");
1178 print_APIC_field(APIC_ISR);
1179 pr_debug("... APIC TMR field:\n");
1180 print_APIC_field(APIC_TMR);
1181 pr_debug("... APIC IRR field:\n");
1182 print_APIC_field(APIC_IRR);
1185 if (APIC_INTEGRATED(ver)) {
1186 /* Due to the Pentium erratum 3AP. */
1188 apic_write(APIC_ESR, 0);
1190 v = apic_read(APIC_ESR);
1191 pr_debug("... APIC ESR: %08x\n", v);
1194 icr = apic_icr_read();
1195 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1196 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1198 v = apic_read(APIC_LVTT);
1199 pr_debug("... APIC LVTT: %08x\n", v);
1203 v = apic_read(APIC_LVTPC);
1204 pr_debug("... APIC LVTPC: %08x\n", v);
1206 v = apic_read(APIC_LVT0);
1207 pr_debug("... APIC LVT0: %08x\n", v);
1208 v = apic_read(APIC_LVT1);
1209 pr_debug("... APIC LVT1: %08x\n", v);
1213 v = apic_read(APIC_LVTERR);
1214 pr_debug("... APIC LVTERR: %08x\n", v);
1217 v = apic_read(APIC_TMICT);
1218 pr_debug("... APIC TMICT: %08x\n", v);
1219 v = apic_read(APIC_TMCCT);
1220 pr_debug("... APIC TMCCT: %08x\n", v);
1221 v = apic_read(APIC_TDCR);
1222 pr_debug("... APIC TDCR: %08x\n", v);
1224 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1225 v = apic_read(APIC_EFEAT);
1226 maxlvt = (v >> 16) & 0xff;
1227 pr_debug("... APIC EFEAT: %08x\n", v);
1228 v = apic_read(APIC_ECTRL);
1229 pr_debug("... APIC ECTRL: %08x\n", v);
1230 for (i = 0; i < maxlvt; i++) {
1231 v = apic_read(APIC_EILVTn(i));
1232 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1238 static void __init print_local_APICs(int maxcpu)
1246 for_each_online_cpu(cpu) {
1249 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1254 static void __init print_PIC(void)
1257 unsigned long flags;
1259 if (!nr_legacy_irqs())
1262 pr_debug("\nprinting PIC contents\n");
1264 raw_spin_lock_irqsave(&i8259A_lock, flags);
1266 v = inb(0xa1) << 8 | inb(0x21);
1267 pr_debug("... PIC IMR: %04x\n", v);
1269 v = inb(0xa0) << 8 | inb(0x20);
1270 pr_debug("... PIC IRR: %04x\n", v);
1274 v = inb(0xa0) << 8 | inb(0x20);
1278 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1280 pr_debug("... PIC ISR: %04x\n", v);
1282 v = inb(0x4d1) << 8 | inb(0x4d0);
1283 pr_debug("... PIC ELCR: %04x\n", v);
1286 static int show_lapic __initdata = 1;
1287 static __init int setup_show_lapic(char *arg)
1291 if (strcmp(arg, "all") == 0) {
1292 show_lapic = CONFIG_NR_CPUS;
1294 get_option(&arg, &num);
1301 __setup("show_lapic=", setup_show_lapic);
1303 static int __init print_ICs(void)
1305 if (apic_verbosity == APIC_QUIET)
1310 /* don't print out if apic is not there */
1311 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1314 print_local_APICs(show_lapic);
1320 late_initcall(print_ICs);