arch/sh/boards/mach-se/7722/irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
   4  *
   5  * Copyright (C) 2007  Nobuhiro Iwamatsu
   6  * Copyright (C) 2012  Paul Mundt
   7  */
   8 #define DRV_NAME "SE7722-FPGA"
   9 #define pr_fmt(fmt) DRV_NAME ": " fmt
  10
  11 #include <linux/init.h>
  12 #include <linux/irq.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/io.h>
  16 #include <linux/err.h>
  17 #include <linux/sizes.h>
  18 #include <mach-se/mach/se7722.h>
  19
  20 #define IRQ01_BASE_ADDR 0x11800000
  21 #define IRQ01_MODE_REG  0
  22 #define IRQ01_STS_REG   4
  23 #define IRQ01_MASK_REG  8
  24
  25 static void __iomem *se7722_irq_regs;
  26 struct irq_domain *se7722_irq_domain;
  27
  28 static void se7722_irq_demux(struct irq_desc *desc)
  29 {
  30         struct irq_data *data = irq_desc_get_irq_data(desc);
  31         struct irq_chip *chip = irq_data_get_irq_chip(data);
  32         unsigned long mask;
  33         int bit;
  34
  35         chip->irq_mask_ack(data);
  36
  37         mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
  38
  39         for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
  40                 generic_handle_domain_irq(se7722_irq_domain, bit);
  41
  42         chip->irq_unmask(data);
  43 }
  44
  45 static void __init se7722_domain_init(void)
  46 {
  47         int i;
  48
  49         se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
  50                                                   &irq_domain_simple_ops, NULL);
  51         if (unlikely(!se7722_irq_domain)) {
  52                 printk("Failed to get IRQ domain\n");
  53                 return;
  54         }
  55
  56         for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
  57                 int irq = irq_create_mapping(se7722_irq_domain, i);
  58
  59                 if (unlikely(irq == 0)) {
  60                         printk("Failed to allocate IRQ %d\n", i);
  61                         return;
  62                 }
  63         }
  64 }
  65
  66 static void __init se7722_gc_init(void)
  67 {
  68         struct irq_chip_generic *gc;
  69         struct irq_chip_type *ct;
  70         unsigned int irq_base;
  71
  72         irq_base = irq_linear_revmap(se7722_irq_domain, 0);
  73
  74         gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
  75                                     handle_level_irq);
  76         if (unlikely(!gc))
  77                 return;
  78
  79         ct = gc->chip_types;
  80         ct->chip.irq_mask = irq_gc_mask_set_bit;
  81         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  82
  83         ct->regs.mask = IRQ01_MASK_REG;
  84
  85         irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
  86                                IRQ_GC_INIT_MASK_CACHE,
  87                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  88
  89         irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
  90         irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
  91
  92         irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
  93         irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
  94 }
  95
  96 /*
  97  * Initialize FPGA IRQs
  98  */
  99 void __init init_se7722_IRQ(void)
 100 {
 101         se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
 102         if (unlikely(!se7722_irq_regs)) {
 103                 printk("Failed to remap IRQ01 regs\n");
 104                 return;
 105         }
 106
 107         /*
 108          * All FPGA IRQs disabled by default
 109          */
 110         iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
 111
 112         __raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */
 113
 114         se7722_domain_init();
 115         se7722_gc_init();
 116 }