arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5
   6 / {
   7         #address-cells = <2>;
   8         #size-cells = <2>;
   9         model = "Microchip MPFS Icicle Kit";
  10         compatible = "microchip,mpfs-icicle-kit";
  11
  12         chosen {
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         clock-frequency = <0>;
  21                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
  22                         device_type = "cpu";
  23                         i-cache-block-size = <64>;
  24                         i-cache-sets = <128>;
  25                         i-cache-size = <16384>;
  26                         reg = <0>;
  27                         riscv,isa = "rv64imac";
  28                         status = "disabled";
  29
  30                         cpu0_intc: interrupt-controller {
  31                                 #interrupt-cells = <1>;
  32                                 compatible = "riscv,cpu-intc";
  33                                 interrupt-controller;
  34                         };
  35                 };
  36
  37                 cpu@1 {
  38                         clock-frequency = <0>;
  39                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  40                         d-cache-block-size = <64>;
  41                         d-cache-sets = <64>;
  42                         d-cache-size = <32768>;
  43                         d-tlb-sets = <1>;
  44                         d-tlb-size = <32>;
  45                         device_type = "cpu";
  46                         i-cache-block-size = <64>;
  47                         i-cache-sets = <64>;
  48                         i-cache-size = <32768>;
  49                         i-tlb-sets = <1>;
  50                         i-tlb-size = <32>;
  51                         mmu-type = "riscv,sv39";
  52                         reg = <1>;
  53                         riscv,isa = "rv64imafdc";
  54                         tlb-split;
  55                         status = "okay";
  56
  57                         cpu1_intc: interrupt-controller {
  58                                 #interrupt-cells = <1>;
  59                                 compatible = "riscv,cpu-intc";
  60                                 interrupt-controller;
  61                         };
  62                 };
  63
  64                 cpu@2 {
  65                         clock-frequency = <0>;
  66                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  67                         d-cache-block-size = <64>;
  68                         d-cache-sets = <64>;
  69                         d-cache-size = <32768>;
  70                         d-tlb-sets = <1>;
  71                         d-tlb-size = <32>;
  72                         device_type = "cpu";
  73                         i-cache-block-size = <64>;
  74                         i-cache-sets = <64>;
  75                         i-cache-size = <32768>;
  76                         i-tlb-sets = <1>;
  77                         i-tlb-size = <32>;
  78                         mmu-type = "riscv,sv39";
  79                         reg = <2>;
  80                         riscv,isa = "rv64imafdc";
  81                         tlb-split;
  82                         status = "okay";
  83
  84                         cpu2_intc: interrupt-controller {
  85                                 #interrupt-cells = <1>;
  86                                 compatible = "riscv,cpu-intc";
  87                                 interrupt-controller;
  88                         };
  89                 };
  90
  91                 cpu@3 {
  92                         clock-frequency = <0>;
  93                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  94                         d-cache-block-size = <64>;
  95                         d-cache-sets = <64>;
  96                         d-cache-size = <32768>;
  97                         d-tlb-sets = <1>;
  98                         d-tlb-size = <32>;
  99                         device_type = "cpu";
 100                         i-cache-block-size = <64>;
 101                         i-cache-sets = <64>;
 102                         i-cache-size = <32768>;
 103                         i-tlb-sets = <1>;
 104                         i-tlb-size = <32>;
 105                         mmu-type = "riscv,sv39";
 106                         reg = <3>;
 107                         riscv,isa = "rv64imafdc";
 108                         tlb-split;
 109                         status = "okay";
 110
 111                         cpu3_intc: interrupt-controller {
 112                                 #interrupt-cells = <1>;
 113                                 compatible = "riscv,cpu-intc";
 114                                 interrupt-controller;
 115                         };
 116                 };
 117
 118                 cpu@4 {
 119                         clock-frequency = <0>;
 120                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 121                         d-cache-block-size = <64>;
 122                         d-cache-sets = <64>;
 123                         d-cache-size = <32768>;
 124                         d-tlb-sets = <1>;
 125                         d-tlb-size = <32>;
 126                         device_type = "cpu";
 127                         i-cache-block-size = <64>;
 128                         i-cache-sets = <64>;
 129                         i-cache-size = <32768>;
 130                         i-tlb-sets = <1>;
 131                         i-tlb-size = <32>;
 132                         mmu-type = "riscv,sv39";
 133                         reg = <4>;
 134                         riscv,isa = "rv64imafdc";
 135                         tlb-split;
 136                         status = "okay";
 137                         cpu4_intc: interrupt-controller {
 138                                 #interrupt-cells = <1>;
 139                                 compatible = "riscv,cpu-intc";
 140                                 interrupt-controller;
 141                         };
 142                 };
 143         };
 144
 145         soc {
 146                 #address-cells = <2>;
 147                 #size-cells = <2>;
 148                 compatible = "simple-bus";
 149                 ranges;
 150
 151                 cache-controller@2010000 {
 152                         compatible = "sifive,fu540-c000-ccache", "cache";
 153                         cache-block-size = <64>;
 154                         cache-level = <2>;
 155                         cache-sets = <1024>;
 156                         cache-size = <2097152>;
 157                         cache-unified;
 158                         interrupt-parent = <&plic>;
 159                         interrupts = <1 2 3>;
 160                         reg = <0x0 0x2010000 0x0 0x1000>;
 161                 };
 162
 163                 clint@2000000 {
 164                         compatible = "sifive,clint0";
 165                         reg = <0x0 0x2000000 0x0 0xC000>;
 166                         interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 167                                                 &cpu1_intc 3 &cpu1_intc 7
 168                                                 &cpu2_intc 3 &cpu2_intc 7
 169                                                 &cpu3_intc 3 &cpu3_intc 7
 170                                                 &cpu4_intc 3 &cpu4_intc 7>;
 171                 };
 172
 173                 plic: interrupt-controller@c000000 {
 174                         #interrupt-cells = <1>;
 175                         compatible = "sifive,plic-1.0.0";
 176                         reg = <0x0 0xc000000 0x0 0x4000000>;
 177                         riscv,ndev = <186>;
 178                         interrupt-controller;
 179                         interrupts-extended = <&cpu0_intc 11
 180                                         &cpu1_intc 11 &cpu1_intc 9
 181                                         &cpu2_intc 11 &cpu2_intc 9
 182                                         &cpu3_intc 11 &cpu3_intc 9
 183                                         &cpu4_intc 11 &cpu4_intc 9>;
 184                 };
 185
 186                 dma@3000000 {
 187                         compatible = "sifive,fu540-c000-pdma";
 188                         reg = <0x0 0x3000000 0x0 0x8000>;
 189                         interrupt-parent = <&plic>;
 190                         interrupts = <23 24 25 26 27 28 29 30>;
 191                         #dma-cells = <1>;
 192                 };
 193
 194                 refclk: refclk {
 195                         compatible = "fixed-clock";
 196                         #clock-cells = <0>;
 197                         clock-frequency = <600000000>;
 198                         clock-output-names = "msspllclk";
 199                 };
 200
 201                 clkcfg: clkcfg@20002000 {
 202                         compatible = "microchip,mpfs-clkcfg";
 203                         reg = <0x0 0x20002000 0x0 0x1000>;
 204                         reg-names = "mss_sysreg";
 205                         clocks = <&refclk>;
 206                         #clock-cells = <1>;
 207                         clock-output-names = "cpu", "axi", "ahb", "envm",       /* 0-3   */
 208                                  "mac0", "mac1", "mmc", "timer",                /* 4-7   */
 209                                 "mmuart0", "mmuart1", "mmuart2", "mmuart3",     /* 8-11  */
 210                                 "mmuart4", "spi0", "spi1", "i2c0",              /* 12-15 */
 211                                 "i2c1", "can0", "can1", "usb",                  /* 16-19 */
 212                                 "rsvd", "rtc", "qspi", "gpio0",                 /* 20-23 */
 213                                 "gpio1", "gpio2", "ddrc", "fic0",               /* 24-27 */
 214                                 "fic1", "fic2", "fic3", "athena", "cfm";        /* 28-32 */
 215                 };
 216
 217                 serial0: serial@20000000 {
 218                         compatible = "ns16550a";
 219                         reg = <0x0 0x20000000 0x0 0x400>;
 220                         reg-io-width = <4>;
 221                         reg-shift = <2>;
 222                         interrupt-parent = <&plic>;
 223                         interrupts = <90>;
 224                         current-speed = <115200>;
 225                         clocks = <&clkcfg 8>;
 226                         status = "disabled";
 227                 };
 228
 229                 serial1: serial@20100000 {
 230                         compatible = "ns16550a";
 231                         reg = <0x0 0x20100000 0x0 0x400>;
 232                         reg-io-width = <4>;
 233                         reg-shift = <2>;
 234                         interrupt-parent = <&plic>;
 235                         interrupts = <91>;
 236                         current-speed = <115200>;
 237                         clocks = <&clkcfg 9>;
 238                         status = "disabled";
 239                 };
 240
 241                 serial2: serial@20102000 {
 242                         compatible = "ns16550a";
 243                         reg = <0x0 0x20102000 0x0 0x400>;
 244                         reg-io-width = <4>;
 245                         reg-shift = <2>;
 246                         interrupt-parent = <&plic>;
 247                         interrupts = <92>;
 248                         current-speed = <115200>;
 249                         clocks = <&clkcfg 10>;
 250                         status = "disabled";
 251                 };
 252
 253                 serial3: serial@20104000 {
 254                         compatible = "ns16550a";
 255                         reg = <0x0 0x20104000 0x0 0x400>;
 256                         reg-io-width = <4>;
 257                         reg-shift = <2>;
 258                         interrupt-parent = <&plic>;
 259                         interrupts = <93>;
 260                         current-speed = <115200>;
 261                         clocks = <&clkcfg 11>;
 262                         status = "disabled";
 263                 };
 264
 265                 emmc: mmc@20008000 {
 266                         compatible = "cdns,sd4hc";
 267                         reg = <0x0 0x20008000 0x0 0x1000>;
 268                         interrupt-parent = <&plic>;
 269                         interrupts = <88 89>;
 270                         pinctrl-names = "default";
 271                         clocks = <&clkcfg 6>;
 272                         bus-width = <4>;
 273                         cap-mmc-highspeed;
 274                         mmc-ddr-3_3v;
 275                         max-frequency = <200000000>;
 276                         non-removable;
 277                         no-sd;
 278                         no-sdio;
 279                         voltage-ranges = <3300 3300>;
 280                         status = "disabled";
 281                 };
 282
 283                 sdcard: sdhc@20008000 {
 284                         compatible = "cdns,sd4hc";
 285                         reg = <0x0 0x20008000 0x0 0x1000>;
 286                         interrupt-parent = <&plic>;
 287                         interrupts = <88>;
 288                         pinctrl-names = "default";
 289                         clocks = <&clkcfg 6>;
 290                         bus-width = <4>;
 291                         disable-wp;
 292                         cap-sd-highspeed;
 293                         card-detect-delay = <200>;
 294                         sd-uhs-sdr12;
 295                         sd-uhs-sdr25;
 296                         sd-uhs-sdr50;
 297                         sd-uhs-sdr104;
 298                         max-frequency = <200000000>;
 299                         status = "disabled";
 300                 };
 301
 302                 emac0: ethernet@20110000 {
 303                         compatible = "cdns,macb";
 304                         reg = <0x0 0x20110000 0x0 0x2000>;
 305                         interrupt-parent = <&plic>;
 306                         interrupts = <64 65 66 67>;
 307                         local-mac-address = [00 00 00 00 00 00];
 308                         clocks = <&clkcfg 4>, <&clkcfg 2>;
 309                         clock-names = "pclk", "hclk";
 310                         status = "disabled";
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                 };
 314
 315                 emac1: ethernet@20112000 {
 316                         compatible = "cdns,macb";
 317                         reg = <0x0 0x20112000 0x0 0x2000>;
 318                         interrupt-parent = <&plic>;
 319                         interrupts = <70 71 72 73>;
 320                         local-mac-address = [00 00 00 00 00 00];
 321                         clocks = <&clkcfg 5>, <&clkcfg 2>;
 322                         status = "disabled";
 323                         clock-names = "pclk", "hclk";
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                 };
 327
 328         };
 329 };