arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5
   6 #include "microchip-mpfs.dtsi"
   7
   8 /* Clock frequency (in Hz) of the rtcclk */
   9 #define RTCCLK_FREQ             1000000
  10
  11 / {
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         model = "Microchip PolarFire-SoC Icicle Kit";
  15         compatible = "microchip,mpfs-icicle-kit";
  16
  17         aliases {
  18                 ethernet0 = &emac1;
  19         };
  20
  21         chosen {
  22                 stdout-path = &serial0;
  23         };
  24
  25         cpus {
  26                 timebase-frequency = <RTCCLK_FREQ>;
  27         };
  28
  29         memory@80000000 {
  30                 device_type = "memory";
  31                 reg = <0x0 0x80000000 0x0 0x40000000>;
  32                 clocks = <&clkcfg 26>;
  33         };
  34
  35         soc {
  36         };
  37 };
  38
  39 &serial0 {
  40         status = "okay";
  41 };
  42
  43 &serial1 {
  44         status = "okay";
  45 };
  46
  47 &serial2 {
  48         status = "okay";
  49 };
  50
  51 &serial3 {
  52         status = "okay";
  53 };
  54
  55 &sdcard {
  56         status = "okay";
  57 };
  58
  59 &emac0 {
  60         phy-mode = "sgmii";
  61         phy-handle = <&phy0>;
  62         phy0: ethernet-phy@8 {
  63                 reg = <8>;
  64                 ti,fifo-depth = <0x01>;
  65         };
  66 };
  67
  68 &emac1 {
  69         status = "okay";
  70         phy-mode = "sgmii";
  71         phy-handle = <&phy1>;
  72         phy1: ethernet-phy@9 {
  73                 reg = <9>;
  74                 ti,fifo-depth = <0x01>;
  75         };
  76 };