arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5
   6 #include "microchip-mpfs.dtsi"
   7
   8 /* Clock frequency (in Hz) of the rtcclk */
   9 #define RTCCLK_FREQ             1000000
  10
  11 / {
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         model = "Microchip PolarFire-SoC Icicle Kit";
  15         compatible = "microchip,mpfs-icicle-kit";
  16
  17         aliases {
  18                 ethernet0 = &emac1;
  19                 serial0 = &serial0;
  20                 serial1 = &serial1;
  21                 serial2 = &serial2;
  22                 serial3 = &serial3;
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27         };
  28
  29         cpus {
  30                 timebase-frequency = <RTCCLK_FREQ>;
  31         };
  32
  33         memory@80000000 {
  34                 device_type = "memory";
  35                 reg = <0x0 0x80000000 0x0 0x40000000>;
  36                 clocks = <&clkcfg 26>;
  37         };
  38
  39         soc {
  40         };
  41 };
  42
  43 &serial0 {
  44         status = "okay";
  45 };
  46
  47 &serial1 {
  48         status = "okay";
  49 };
  50
  51 &serial2 {
  52         status = "okay";
  53 };
  54
  55 &serial3 {
  56         status = "okay";
  57 };
  58
  59 &sdcard {
  60         status = "okay";
  61 };
  62
  63 &emac0 {
  64         phy-mode = "sgmii";
  65         phy-handle = <&phy0>;
  66         phy0: ethernet-phy@8 {
  67                 reg = <8>;
  68                 ti,fifo-depth = <0x01>;
  69         };
  70 };
  71
  72 &emac1 {
  73         status = "okay";
  74         phy-mode = "sgmii";
  75         phy-handle = <&phy1>;
  76         phy1: ethernet-phy@9 {
  77                 reg = <9>;
  78                 ti,fifo-depth = <0x01>;
  79         };
  80 };