1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
7 #include <linux/types.h>
8 #include <linux/string.h>
10 #include <linux/kvm_host.h>
11 #include <linux/hugetlb.h>
12 #include <linux/module.h>
13 #include <linux/log2.h>
14 #include <linux/sizes.h>
16 #include <asm/trace.h>
17 #include <asm/kvm_ppc.h>
18 #include <asm/kvm_book3s.h>
19 #include <asm/book3s/64/mmu-hash.h>
20 #include <asm/hvcall.h>
21 #include <asm/synch.h>
22 #include <asm/ppc-opcode.h>
23 #include <asm/pte-walk.h>
25 /* Translate address of a vmalloc'd thing to a linear map address */
26 static void *real_vmalloc_addr(void *addr)
28 return __va(ppc_find_vmap_phys((unsigned long)addr));
31 /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
32 static int global_invalidates(struct kvm *kvm)
38 * If there is only one vcore, and it's currently running,
39 * as indicated by local_paca->kvm_hstate.kvm_vcpu being set,
40 * we can use tlbiel as long as we mark all other physical
41 * cores as potentially having stale TLB entries for this lpid.
42 * Otherwise, don't use tlbiel.
44 if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcpu)
50 /* any other core might now have stale TLB entries... */
52 cpumask_setall(&kvm->arch.need_tlb_flush);
53 cpu = local_paca->kvm_hstate.kvm_vcore->pcpu;
55 * On POWER9, threads are independent but the TLB is shared,
56 * so use the bit for the first thread to represent the core.
58 if (cpu_has_feature(CPU_FTR_ARCH_300))
59 cpu = cpu_first_thread_sibling(cpu);
60 cpumask_clear_cpu(cpu, &kvm->arch.need_tlb_flush);
67 * Add this HPTE into the chain for the real page.
68 * Must be called with the chain locked; it unlocks the chain.
70 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
71 unsigned long *rmap, long pte_index, int realmode)
73 struct revmap_entry *head, *tail;
76 if (*rmap & KVMPPC_RMAP_PRESENT) {
77 i = *rmap & KVMPPC_RMAP_INDEX;
78 head = &kvm->arch.hpt.rev[i];
80 head = real_vmalloc_addr(head);
81 tail = &kvm->arch.hpt.rev[head->back];
83 tail = real_vmalloc_addr(tail);
85 rev->back = head->back;
86 tail->forw = pte_index;
87 head->back = pte_index;
89 rev->forw = rev->back = pte_index;
90 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
91 pte_index | KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_HPT;
95 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
97 /* Update the dirty bitmap of a memslot */
98 void kvmppc_update_dirty_map(const struct kvm_memory_slot *memslot,
99 unsigned long gfn, unsigned long psize)
101 unsigned long npages;
103 if (!psize || !memslot->dirty_bitmap)
105 npages = (psize + PAGE_SIZE - 1) / PAGE_SIZE;
106 gfn -= memslot->base_gfn;
107 set_dirty_bits_atomic(memslot->dirty_bitmap, gfn, npages);
109 EXPORT_SYMBOL_GPL(kvmppc_update_dirty_map);
111 static void kvmppc_set_dirty_from_hpte(struct kvm *kvm,
112 unsigned long hpte_v, unsigned long hpte_gr)
114 struct kvm_memory_slot *memslot;
118 psize = kvmppc_actual_pgsz(hpte_v, hpte_gr);
119 gfn = hpte_rpn(hpte_gr, psize);
120 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
121 if (memslot && memslot->dirty_bitmap)
122 kvmppc_update_dirty_map(memslot, gfn, psize);
125 /* Returns a pointer to the revmap entry for the page mapped by a HPTE */
126 static unsigned long *revmap_for_hpte(struct kvm *kvm, unsigned long hpte_v,
127 unsigned long hpte_gr,
128 struct kvm_memory_slot **memslotp,
131 struct kvm_memory_slot *memslot;
135 gfn = hpte_rpn(hpte_gr, kvmppc_actual_pgsz(hpte_v, hpte_gr));
136 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
144 rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
148 /* Remove this HPTE from the chain for a real page */
149 static void remove_revmap_chain(struct kvm *kvm, long pte_index,
150 struct revmap_entry *rev,
151 unsigned long hpte_v, unsigned long hpte_r)
153 struct revmap_entry *next, *prev;
154 unsigned long ptel, head;
156 unsigned long rcbits;
157 struct kvm_memory_slot *memslot;
160 rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
161 ptel = rev->guest_rpte |= rcbits;
162 rmap = revmap_for_hpte(kvm, hpte_v, ptel, &memslot, &gfn);
167 head = *rmap & KVMPPC_RMAP_INDEX;
168 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]);
169 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]);
170 next->back = rev->back;
171 prev->forw = rev->forw;
172 if (head == pte_index) {
174 if (head == pte_index)
175 *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
177 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
179 *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
180 if (rcbits & HPTE_R_C)
181 kvmppc_update_dirty_map(memslot, gfn,
182 kvmppc_actual_pgsz(hpte_v, hpte_r));
186 long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
187 long pte_index, unsigned long pteh, unsigned long ptel,
188 pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
190 unsigned long i, pa, gpa, gfn, psize;
191 unsigned long slot_fn, hva;
193 struct revmap_entry *rev;
194 unsigned long g_ptel;
195 struct kvm_memory_slot *memslot;
196 unsigned hpage_shift;
200 unsigned int writing;
201 unsigned long mmu_seq;
202 unsigned long rcbits;
204 if (kvm_is_radix(kvm))
206 psize = kvmppc_actual_pgsz(pteh, ptel);
209 writing = hpte_is_writable(ptel);
210 pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
211 ptel &= ~HPTE_GR_RESERVED;
214 /* used later to detect if we might have been invalidated */
215 mmu_seq = kvm->mmu_notifier_seq;
218 /* Find the memslot (if any) for this address */
219 gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
220 gfn = gpa >> PAGE_SHIFT;
221 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
225 if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
226 /* Emulated MMIO - mark this with key=31 */
227 pteh |= HPTE_V_ABSENT;
228 ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
232 /* Check if the requested page fits entirely in the memslot. */
233 if (!slot_is_aligned(memslot, psize))
235 slot_fn = gfn - memslot->base_gfn;
236 rmap = &memslot->arch.rmap[slot_fn];
238 /* Translate to host virtual address */
239 hva = __gfn_to_hva_memslot(memslot, gfn);
241 arch_spin_lock(&kvm->mmu_lock.rlock.raw_lock);
242 ptep = find_kvm_host_pte(kvm, mmu_seq, hva, &hpage_shift);
245 unsigned int host_pte_size;
248 host_pte_size = 1ul << hpage_shift;
250 host_pte_size = PAGE_SIZE;
252 * We should always find the guest page size
253 * to <= host page size, if host is using hugepage
255 if (host_pte_size < psize) {
256 arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
259 pte = kvmppc_read_update_linux_pte(ptep, writing);
260 if (pte_present(pte) && !pte_protnone(pte)) {
261 if (writing && !__pte_write(pte))
262 /* make the actual HPTE be read-only */
263 ptel = hpte_make_readonly(ptel);
265 pa = pte_pfn(pte) << PAGE_SHIFT;
266 pa |= hva & (host_pte_size - 1);
267 pa |= gpa & ~PAGE_MASK;
270 arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
272 ptel &= HPTE_R_KEY | HPTE_R_PP0 | (psize-1);
276 pteh |= HPTE_V_VALID;
278 pteh |= HPTE_V_ABSENT;
279 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
282 /*If we had host pte mapping then Check WIMG */
283 if (ptep && !hpte_cache_flags_ok(ptel, is_ci)) {
287 * Allow guest to map emulated device memory as
288 * uncacheable, but actually make it cacheable.
290 ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
294 /* Find and lock the HPTEG slot to use */
296 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
298 if (likely((flags & H_EXACT) == 0)) {
300 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
301 for (i = 0; i < 8; ++i) {
302 if ((be64_to_cpu(*hpte) & HPTE_V_VALID) == 0 &&
303 try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
310 * Since try_lock_hpte doesn't retry (not even stdcx.
311 * failures), it could be that there is a free slot
312 * but we transiently failed to lock it. Try again,
313 * actually locking each slot and checking it.
316 for (i = 0; i < 8; ++i) {
318 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
320 pte = be64_to_cpu(hpte[0]);
321 if (!(pte & (HPTE_V_VALID | HPTE_V_ABSENT)))
323 __unlock_hpte(hpte, pte);
331 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
332 if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
334 /* Lock the slot and check again */
337 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
339 pte = be64_to_cpu(hpte[0]);
340 if (pte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
341 __unlock_hpte(hpte, pte);
347 /* Save away the guest's idea of the second HPTE dword */
348 rev = &kvm->arch.hpt.rev[pte_index];
350 rev = real_vmalloc_addr(rev);
352 rev->guest_rpte = g_ptel;
353 note_hpte_modification(kvm, rev);
356 /* Link HPTE into reverse-map chain */
357 if (pteh & HPTE_V_VALID) {
359 rmap = real_vmalloc_addr(rmap);
361 /* Check for pending invalidations under the rmap chain lock */
362 if (mmu_notifier_retry(kvm, mmu_seq)) {
363 /* inval in progress, write a non-present HPTE */
364 pteh |= HPTE_V_ABSENT;
365 pteh &= ~HPTE_V_VALID;
366 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
369 kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
371 /* Only set R/C in real HPTE if already set in *rmap */
372 rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
373 ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
377 /* Convert to new format on P9 */
378 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
379 ptel = hpte_old_to_new_r(pteh, ptel);
380 pteh = hpte_old_to_new_v(pteh);
382 hpte[1] = cpu_to_be64(ptel);
384 /* Write the first HPTE dword, unlocking the HPTE and making it valid */
386 __unlock_hpte(hpte, pteh);
387 asm volatile("ptesync" : : : "memory");
389 *pte_idx_ret = pte_index;
392 EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
394 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
395 long pte_index, unsigned long pteh, unsigned long ptel)
397 return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
398 vcpu->arch.pgdir, true,
399 &vcpu->arch.regs.gpr[4]);
402 #ifdef __BIG_ENDIAN__
403 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
405 #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
408 static inline int is_mmio_hpte(unsigned long v, unsigned long r)
410 return ((v & HPTE_V_ABSENT) &&
411 (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
412 (HPTE_R_KEY_HI | HPTE_R_KEY_LO));
415 static inline void fixup_tlbie_lpid(unsigned long rb_value, unsigned long lpid)
418 if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
419 /* Radix flush for a hash guest */
421 unsigned long rb,rs,prs,r,ric;
423 rb = PPC_BIT(52); /* IS = 2 */
424 rs = 0; /* lpid = 0 */
425 prs = 0; /* partition scoped */
426 r = 1; /* radix format */
427 ric = 0; /* RIC_FLSUH_TLB */
430 * Need the extra ptesync to make sure we don't
433 asm volatile("ptesync": : :"memory");
434 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
435 : : "r"(rb), "i"(r), "i"(prs),
436 "i"(ric), "r"(rs) : "memory");
439 if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
440 asm volatile("ptesync": : :"memory");
441 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
442 "r" (rb_value), "r" (lpid));
446 static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
447 long npages, int global, bool need_sync)
452 * We use the POWER9 5-operand versions of tlbie and tlbiel here.
453 * Since we are using RIC=0 PRS=0 R=0, and P7/P8 tlbiel ignores
454 * the RS field, this is backwards-compatible with P7 and P8.
458 asm volatile("ptesync" : : : "memory");
459 for (i = 0; i < npages; ++i) {
460 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
461 "r" (rbvalues[i]), "r" (kvm->arch.lpid));
464 fixup_tlbie_lpid(rbvalues[i - 1], kvm->arch.lpid);
465 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
468 asm volatile("ptesync" : : : "memory");
469 for (i = 0; i < npages; ++i) {
470 asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : :
471 "r" (rbvalues[i]), "r" (0));
473 asm volatile("ptesync" : : : "memory");
477 long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
478 unsigned long pte_index, unsigned long avpn,
479 unsigned long *hpret)
482 unsigned long v, r, rb;
483 struct revmap_entry *rev;
484 u64 pte, orig_pte, pte_r;
486 if (kvm_is_radix(kvm))
488 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
490 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
491 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
493 pte = orig_pte = be64_to_cpu(hpte[0]);
494 pte_r = be64_to_cpu(hpte[1]);
495 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
496 pte = hpte_new_to_old_v(pte, pte_r);
497 pte_r = hpte_new_to_old_r(pte_r);
499 if ((pte & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
500 ((flags & H_AVPN) && (pte & ~0x7fUL) != avpn) ||
501 ((flags & H_ANDCOND) && (pte & avpn) != 0)) {
502 __unlock_hpte(hpte, orig_pte);
506 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
507 v = pte & ~HPTE_V_HVLOCK;
508 if (v & HPTE_V_VALID) {
509 hpte[0] &= ~cpu_to_be64(HPTE_V_VALID);
510 rb = compute_tlbie_rb(v, pte_r, pte_index);
511 do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
513 * The reference (R) and change (C) bits in a HPT
514 * entry can be set by hardware at any time up until
515 * the HPTE is invalidated and the TLB invalidation
516 * sequence has completed. This means that when
517 * removing a HPTE, we need to re-read the HPTE after
518 * the invalidation sequence has completed in order to
519 * obtain reliable values of R and C.
521 remove_revmap_chain(kvm, pte_index, rev, v,
522 be64_to_cpu(hpte[1]));
524 r = rev->guest_rpte & ~HPTE_GR_RESERVED;
525 note_hpte_modification(kvm, rev);
526 unlock_hpte(hpte, 0);
528 if (is_mmio_hpte(v, pte_r))
529 atomic64_inc(&kvm->arch.mmio_update);
531 if (v & HPTE_V_ABSENT)
532 v = (v & ~HPTE_V_ABSENT) | HPTE_V_VALID;
537 EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
539 long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
540 unsigned long pte_index, unsigned long avpn)
542 return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
543 &vcpu->arch.regs.gpr[4]);
546 long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
548 struct kvm *kvm = vcpu->kvm;
549 unsigned long *args = &vcpu->arch.regs.gpr[4];
550 __be64 *hp, *hptes[4];
551 unsigned long tlbrb[4];
552 long int i, j, k, n, found, indexes[4];
553 unsigned long flags, req, pte_index, rcbits;
555 long int ret = H_SUCCESS;
556 struct revmap_entry *rev, *revs[4];
559 if (kvm_is_radix(kvm))
561 global = global_invalidates(kvm);
562 for (i = 0; i < 4 && ret == H_SUCCESS; ) {
567 flags = pte_index >> 56;
568 pte_index &= ((1ul << 56) - 1);
571 if (req == 3) { /* no more requests */
575 if (req != 1 || flags == 3 ||
576 pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) {
577 /* parameter error */
578 args[j] = ((0xa0 | flags) << 56) + pte_index;
582 hp = (__be64 *) (kvm->arch.hpt.virt + (pte_index << 4));
583 /* to avoid deadlock, don't spin except for first */
584 if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
587 while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
591 hp0 = be64_to_cpu(hp[0]);
592 hp1 = be64_to_cpu(hp[1]);
593 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
594 hp0 = hpte_new_to_old_v(hp0, hp1);
595 hp1 = hpte_new_to_old_r(hp1);
597 if (hp0 & (HPTE_V_ABSENT | HPTE_V_VALID)) {
599 case 0: /* absolute */
602 case 1: /* andcond */
603 if (!(hp0 & args[j + 1]))
607 if ((hp0 & ~0x7fUL) == args[j + 1])
613 hp[0] &= ~cpu_to_be64(HPTE_V_HVLOCK);
614 args[j] = ((0x90 | flags) << 56) + pte_index;
618 args[j] = ((0x80 | flags) << 56) + pte_index;
619 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
620 note_hpte_modification(kvm, rev);
622 if (!(hp0 & HPTE_V_VALID)) {
623 /* insert R and C bits from PTE */
624 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
625 args[j] |= rcbits << (56 - 5);
627 if (is_mmio_hpte(hp0, hp1))
628 atomic64_inc(&kvm->arch.mmio_update);
632 /* leave it locked */
633 hp[0] &= ~cpu_to_be64(HPTE_V_VALID);
634 tlbrb[n] = compute_tlbie_rb(hp0, hp1, pte_index);
644 /* Now that we've collected a batch, do the tlbies */
645 do_tlbies(kvm, tlbrb, n, global, true);
647 /* Read PTE low words after tlbie to get final R/C values */
648 for (k = 0; k < n; ++k) {
650 pte_index = args[j] & ((1ul << 56) - 1);
653 remove_revmap_chain(kvm, pte_index, rev,
654 be64_to_cpu(hp[0]), be64_to_cpu(hp[1]));
655 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
656 args[j] |= rcbits << (56 - 5);
657 __unlock_hpte(hp, 0);
664 long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
665 unsigned long pte_index, unsigned long avpn)
667 struct kvm *kvm = vcpu->kvm;
669 struct revmap_entry *rev;
670 unsigned long v, r, rb, mask, bits;
673 if (kvm_is_radix(kvm))
675 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
678 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
679 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
681 v = pte_v = be64_to_cpu(hpte[0]);
682 if (cpu_has_feature(CPU_FTR_ARCH_300))
683 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[1]));
684 if ((v & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
685 ((flags & H_AVPN) && (v & ~0x7fUL) != avpn)) {
686 __unlock_hpte(hpte, pte_v);
690 pte_r = be64_to_cpu(hpte[1]);
691 bits = (flags << 55) & HPTE_R_PP0;
692 bits |= (flags << 48) & HPTE_R_KEY_HI;
693 bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
695 /* Update guest view of 2nd HPTE dword */
696 mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
697 HPTE_R_KEY_HI | HPTE_R_KEY_LO;
698 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
700 r = (rev->guest_rpte & ~mask) | bits;
702 note_hpte_modification(kvm, rev);
706 if (v & HPTE_V_VALID) {
708 * If the page is valid, don't let it transition from
709 * readonly to writable. If it should be writable, we'll
710 * take a trap and let the page fault code sort it out.
712 r = (pte_r & ~mask) | bits;
713 if (hpte_is_writable(r) && !hpte_is_writable(pte_r))
714 r = hpte_make_readonly(r);
715 /* If the PTE is changing, invalidate it first */
717 rb = compute_tlbie_rb(v, r, pte_index);
718 hpte[0] = cpu_to_be64((pte_v & ~HPTE_V_VALID) |
720 do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
721 /* Don't lose R/C bit updates done by hardware */
722 r |= be64_to_cpu(hpte[1]) & (HPTE_R_R | HPTE_R_C);
723 hpte[1] = cpu_to_be64(r);
726 unlock_hpte(hpte, pte_v & ~HPTE_V_HVLOCK);
727 asm volatile("ptesync" : : : "memory");
728 if (is_mmio_hpte(v, pte_r))
729 atomic64_inc(&kvm->arch.mmio_update);
734 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
735 unsigned long pte_index)
737 struct kvm *kvm = vcpu->kvm;
741 struct revmap_entry *rev = NULL;
743 if (kvm_is_radix(kvm))
745 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
747 if (flags & H_READ_4) {
751 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
752 for (i = 0; i < n; ++i, ++pte_index) {
753 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
754 v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
755 r = be64_to_cpu(hpte[1]);
756 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
757 v = hpte_new_to_old_v(v, r);
758 r = hpte_new_to_old_r(r);
760 if (v & HPTE_V_ABSENT) {
764 if (v & HPTE_V_VALID) {
765 r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
766 r &= ~HPTE_GR_RESERVED;
768 vcpu->arch.regs.gpr[4 + i * 2] = v;
769 vcpu->arch.regs.gpr[5 + i * 2] = r;
774 long kvmppc_h_clear_ref(struct kvm_vcpu *vcpu, unsigned long flags,
775 unsigned long pte_index)
777 struct kvm *kvm = vcpu->kvm;
779 unsigned long v, r, gr;
780 struct revmap_entry *rev;
782 long ret = H_NOT_FOUND;
784 if (kvm_is_radix(kvm))
786 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
789 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
790 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
791 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
793 v = be64_to_cpu(hpte[0]);
794 r = be64_to_cpu(hpte[1]);
795 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
798 gr = rev->guest_rpte;
799 if (rev->guest_rpte & HPTE_R_R) {
800 rev->guest_rpte &= ~HPTE_R_R;
801 note_hpte_modification(kvm, rev);
803 if (v & HPTE_V_VALID) {
804 gr |= r & (HPTE_R_R | HPTE_R_C);
806 kvmppc_clear_ref_hpte(kvm, hpte, pte_index);
807 rmap = revmap_for_hpte(kvm, v, gr, NULL, NULL);
810 *rmap |= KVMPPC_RMAP_REFERENCED;
815 vcpu->arch.regs.gpr[4] = gr;
818 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
822 long kvmppc_h_clear_mod(struct kvm_vcpu *vcpu, unsigned long flags,
823 unsigned long pte_index)
825 struct kvm *kvm = vcpu->kvm;
827 unsigned long v, r, gr;
828 struct revmap_entry *rev;
829 long ret = H_NOT_FOUND;
831 if (kvm_is_radix(kvm))
833 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
836 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
837 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
838 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
840 v = be64_to_cpu(hpte[0]);
841 r = be64_to_cpu(hpte[1]);
842 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
845 gr = rev->guest_rpte;
847 rev->guest_rpte &= ~HPTE_R_C;
848 note_hpte_modification(kvm, rev);
850 if (v & HPTE_V_VALID) {
851 /* need to make it temporarily absent so C is stable */
852 hpte[0] |= cpu_to_be64(HPTE_V_ABSENT);
853 kvmppc_invalidate_hpte(kvm, hpte, pte_index);
854 r = be64_to_cpu(hpte[1]);
855 gr |= r & (HPTE_R_R | HPTE_R_C);
857 hpte[1] = cpu_to_be64(r & ~HPTE_R_C);
859 kvmppc_set_dirty_from_hpte(kvm, v, gr);
862 vcpu->arch.regs.gpr[4] = gr;
865 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
869 static int kvmppc_get_hpa(struct kvm_vcpu *vcpu, unsigned long mmu_seq,
870 unsigned long gpa, int writing, unsigned long *hpa,
871 struct kvm_memory_slot **memslot_p)
873 struct kvm *kvm = vcpu->kvm;
874 struct kvm_memory_slot *memslot;
875 unsigned long gfn, hva, pa, psize = PAGE_SHIFT;
879 /* Find the memslot for this address */
880 gfn = gpa >> PAGE_SHIFT;
881 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
882 if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID))
885 /* Translate to host virtual address */
886 hva = __gfn_to_hva_memslot(memslot, gfn);
888 /* Try to find the host pte for that virtual address */
889 ptep = find_kvm_host_pte(kvm, mmu_seq, hva, &shift);
892 pte = kvmppc_read_update_linux_pte(ptep, writing);
893 if (!pte_present(pte))
896 /* Convert to a physical address */
898 psize = 1UL << shift;
899 pa = pte_pfn(pte) << PAGE_SHIFT;
900 pa |= hva & (psize - 1);
901 pa |= gpa & ~PAGE_MASK;
906 *memslot_p = memslot;
911 static long kvmppc_do_h_page_init_zero(struct kvm_vcpu *vcpu,
914 struct kvm_memory_slot *memslot;
915 struct kvm *kvm = vcpu->kvm;
916 unsigned long pa, mmu_seq;
917 long ret = H_SUCCESS;
920 /* Used later to detect if we might have been invalidated */
921 mmu_seq = kvm->mmu_notifier_seq;
924 arch_spin_lock(&kvm->mmu_lock.rlock.raw_lock);
926 ret = kvmppc_get_hpa(vcpu, mmu_seq, dest, 1, &pa, &memslot);
927 if (ret != H_SUCCESS)
931 for (i = 0; i < SZ_4K; i += L1_CACHE_BYTES, pa += L1_CACHE_BYTES)
933 kvmppc_update_dirty_map(memslot, dest >> PAGE_SHIFT, PAGE_SIZE);
936 arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
940 static long kvmppc_do_h_page_init_copy(struct kvm_vcpu *vcpu,
941 unsigned long dest, unsigned long src)
943 unsigned long dest_pa, src_pa, mmu_seq;
944 struct kvm_memory_slot *dest_memslot;
945 struct kvm *kvm = vcpu->kvm;
946 long ret = H_SUCCESS;
948 /* Used later to detect if we might have been invalidated */
949 mmu_seq = kvm->mmu_notifier_seq;
952 arch_spin_lock(&kvm->mmu_lock.rlock.raw_lock);
953 ret = kvmppc_get_hpa(vcpu, mmu_seq, dest, 1, &dest_pa, &dest_memslot);
954 if (ret != H_SUCCESS)
957 ret = kvmppc_get_hpa(vcpu, mmu_seq, src, 0, &src_pa, NULL);
958 if (ret != H_SUCCESS)
962 memcpy((void *)dest_pa, (void *)src_pa, SZ_4K);
964 kvmppc_update_dirty_map(dest_memslot, dest >> PAGE_SHIFT, PAGE_SIZE);
967 arch_spin_unlock(&kvm->mmu_lock.rlock.raw_lock);
971 long kvmppc_rm_h_page_init(struct kvm_vcpu *vcpu, unsigned long flags,
972 unsigned long dest, unsigned long src)
974 struct kvm *kvm = vcpu->kvm;
975 u64 pg_mask = SZ_4K - 1; /* 4K page size */
976 long ret = H_SUCCESS;
978 /* Don't handle radix mode here, go up to the virtual mode handler */
979 if (kvm_is_radix(kvm))
982 /* Check for invalid flags (H_PAGE_SET_LOANED covers all CMO flags) */
983 if (flags & ~(H_ICACHE_INVALIDATE | H_ICACHE_SYNCHRONIZE |
984 H_ZERO_PAGE | H_COPY_PAGE | H_PAGE_SET_LOANED))
987 /* dest (and src if copy_page flag set) must be page aligned */
988 if ((dest & pg_mask) || ((flags & H_COPY_PAGE) && (src & pg_mask)))
991 /* zero and/or copy the page as determined by the flags */
992 if (flags & H_COPY_PAGE)
993 ret = kvmppc_do_h_page_init_copy(vcpu, dest, src);
994 else if (flags & H_ZERO_PAGE)
995 ret = kvmppc_do_h_page_init_zero(vcpu, dest);
997 /* We can ignore the other flags */
1002 void kvmppc_invalidate_hpte(struct kvm *kvm, __be64 *hptep,
1003 unsigned long pte_index)
1008 hptep[0] &= ~cpu_to_be64(HPTE_V_VALID);
1009 hp0 = be64_to_cpu(hptep[0]);
1010 hp1 = be64_to_cpu(hptep[1]);
1011 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1012 hp0 = hpte_new_to_old_v(hp0, hp1);
1013 hp1 = hpte_new_to_old_r(hp1);
1015 rb = compute_tlbie_rb(hp0, hp1, pte_index);
1016 do_tlbies(kvm, &rb, 1, 1, true);
1018 EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
1020 void kvmppc_clear_ref_hpte(struct kvm *kvm, __be64 *hptep,
1021 unsigned long pte_index)
1024 unsigned char rbyte;
1027 hp0 = be64_to_cpu(hptep[0]);
1028 hp1 = be64_to_cpu(hptep[1]);
1029 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1030 hp0 = hpte_new_to_old_v(hp0, hp1);
1031 hp1 = hpte_new_to_old_r(hp1);
1033 rb = compute_tlbie_rb(hp0, hp1, pte_index);
1034 rbyte = (be64_to_cpu(hptep[1]) & ~HPTE_R_R) >> 8;
1035 /* modify only the second-last byte, which contains the ref bit */
1036 *((char *)hptep + 14) = rbyte;
1037 do_tlbies(kvm, &rb, 1, 1, false);
1039 EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
1041 static int slb_base_page_shift[4] = {
1045 20, /* 1M, unsupported */
1048 static struct mmio_hpte_cache_entry *mmio_cache_search(struct kvm_vcpu *vcpu,
1049 unsigned long eaddr, unsigned long slb_v, long mmio_update)
1051 struct mmio_hpte_cache_entry *entry = NULL;
1052 unsigned int pshift;
1055 for (i = 0; i < MMIO_HPTE_CACHE_SIZE; i++) {
1056 entry = &vcpu->arch.mmio_cache.entry[i];
1057 if (entry->mmio_update == mmio_update) {
1058 pshift = entry->slb_base_pshift;
1059 if ((entry->eaddr >> pshift) == (eaddr >> pshift) &&
1060 entry->slb_v == slb_v)
1067 static struct mmio_hpte_cache_entry *
1068 next_mmio_cache_entry(struct kvm_vcpu *vcpu)
1070 unsigned int index = vcpu->arch.mmio_cache.index;
1072 vcpu->arch.mmio_cache.index++;
1073 if (vcpu->arch.mmio_cache.index == MMIO_HPTE_CACHE_SIZE)
1074 vcpu->arch.mmio_cache.index = 0;
1076 return &vcpu->arch.mmio_cache.entry[index];
1079 /* When called from virtmode, this func should be protected by
1080 * preempt_disable(), otherwise, the holding of HPTE_V_HVLOCK
1081 * can trigger deadlock issue.
1083 long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
1084 unsigned long valid)
1087 unsigned int pshift;
1088 unsigned long somask;
1089 unsigned long vsid, hash;
1092 unsigned long mask, val;
1093 unsigned long v, r, orig_v;
1095 /* Get page shift, work out hash and AVPN etc. */
1096 mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
1099 if (slb_v & SLB_VSID_L) {
1100 mask |= HPTE_V_LARGE;
1101 val |= HPTE_V_LARGE;
1102 pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
1104 if (slb_v & SLB_VSID_B_1T) {
1105 somask = (1UL << 40) - 1;
1106 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
1109 somask = (1UL << 28) - 1;
1110 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
1112 hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvmppc_hpt_mask(&kvm->arch.hpt);
1113 avpn = slb_v & ~(somask >> 16); /* also includes B */
1114 avpn |= (eaddr & somask) >> 16;
1117 avpn &= ~((1UL << (pshift - 16)) - 1);
1123 hpte = (__be64 *)(kvm->arch.hpt.virt + (hash << 7));
1125 for (i = 0; i < 16; i += 2) {
1126 /* Read the PTE racily */
1127 v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
1128 if (cpu_has_feature(CPU_FTR_ARCH_300))
1129 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[i+1]));
1131 /* Check valid/absent, hash, segment size and AVPN */
1132 if (!(v & valid) || (v & mask) != val)
1135 /* Lock the PTE and read it under the lock */
1136 while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
1138 v = orig_v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
1139 r = be64_to_cpu(hpte[i+1]);
1140 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1141 v = hpte_new_to_old_v(v, r);
1142 r = hpte_new_to_old_r(r);
1146 * Check the HPTE again, including base page size
1148 if ((v & valid) && (v & mask) == val &&
1149 kvmppc_hpte_base_page_shift(v, r) == pshift)
1150 /* Return with the HPTE still locked */
1151 return (hash << 3) + (i >> 1);
1153 __unlock_hpte(&hpte[i], orig_v);
1156 if (val & HPTE_V_SECONDARY)
1158 val |= HPTE_V_SECONDARY;
1159 hash = hash ^ kvmppc_hpt_mask(&kvm->arch.hpt);
1163 EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
1166 * Called in real mode to check whether an HPTE not found fault
1167 * is due to accessing a paged-out page or an emulated MMIO page,
1168 * or if a protection fault is due to accessing a page that the
1169 * guest wanted read/write access to but which we made read-only.
1170 * Returns a possibly modified status (DSISR) value if not
1171 * (i.e. pass the interrupt to the guest),
1172 * -1 to pass the fault up to host kernel mode code, -2 to do that
1173 * and also load the instruction word (for MMIO emulation),
1174 * or 0 if we should make the guest retry the access.
1176 long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
1177 unsigned long slb_v, unsigned int status, bool data)
1179 struct kvm *kvm = vcpu->kvm;
1181 unsigned long v, r, gr, orig_v;
1183 unsigned long valid;
1184 struct revmap_entry *rev;
1185 unsigned long pp, key;
1186 struct mmio_hpte_cache_entry *cache_entry = NULL;
1187 long mmio_update = 0;
1189 /* For protection fault, expect to find a valid HPTE */
1190 valid = HPTE_V_VALID;
1191 if (status & DSISR_NOHPTE) {
1192 valid |= HPTE_V_ABSENT;
1193 mmio_update = atomic64_read(&kvm->arch.mmio_update);
1194 cache_entry = mmio_cache_search(vcpu, addr, slb_v, mmio_update);
1197 index = cache_entry->pte_index;
1198 v = cache_entry->hpte_v;
1199 r = cache_entry->hpte_r;
1200 gr = cache_entry->rpte;
1202 index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
1204 if (status & DSISR_NOHPTE)
1205 return status; /* there really was no HPTE */
1206 return 0; /* for prot fault, HPTE disappeared */
1208 hpte = (__be64 *)(kvm->arch.hpt.virt + (index << 4));
1209 v = orig_v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
1210 r = be64_to_cpu(hpte[1]);
1211 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1212 v = hpte_new_to_old_v(v, r);
1213 r = hpte_new_to_old_r(r);
1215 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[index]);
1216 gr = rev->guest_rpte;
1218 unlock_hpte(hpte, orig_v);
1221 /* For not found, if the HPTE is valid by now, retry the instruction */
1222 if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
1225 /* Check access permissions to the page */
1226 pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
1227 key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
1228 status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
1230 if (gr & (HPTE_R_N | HPTE_R_G))
1231 return status | SRR1_ISI_N_G_OR_CIP;
1232 if (!hpte_read_permission(pp, slb_v & key))
1233 return status | SRR1_ISI_PROT;
1234 } else if (status & DSISR_ISSTORE) {
1235 /* check write permission */
1236 if (!hpte_write_permission(pp, slb_v & key))
1237 return status | DSISR_PROTFAULT;
1239 if (!hpte_read_permission(pp, slb_v & key))
1240 return status | DSISR_PROTFAULT;
1243 /* Check storage key, if applicable */
1244 if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
1245 unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
1246 if (status & DSISR_ISSTORE)
1249 return status | DSISR_KEYFAULT;
1252 /* Save HPTE info for virtual-mode handler */
1253 vcpu->arch.pgfault_addr = addr;
1254 vcpu->arch.pgfault_index = index;
1255 vcpu->arch.pgfault_hpte[0] = v;
1256 vcpu->arch.pgfault_hpte[1] = r;
1257 vcpu->arch.pgfault_cache = cache_entry;
1259 /* Check the storage key to see if it is possibly emulated MMIO */
1260 if ((r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
1261 (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) {
1263 unsigned int pshift = 12;
1264 unsigned int pshift_index;
1266 if (slb_v & SLB_VSID_L) {
1267 pshift_index = ((slb_v & SLB_VSID_LP) >> 4);
1268 pshift = slb_base_page_shift[pshift_index];
1270 cache_entry = next_mmio_cache_entry(vcpu);
1271 cache_entry->eaddr = addr;
1272 cache_entry->slb_base_pshift = pshift;
1273 cache_entry->pte_index = index;
1274 cache_entry->hpte_v = v;
1275 cache_entry->hpte_r = r;
1276 cache_entry->rpte = gr;
1277 cache_entry->slb_v = slb_v;
1278 cache_entry->mmio_update = mmio_update;
1280 if (data && (vcpu->arch.shregs.msr & MSR_IR))
1281 return -2; /* MMIO emulation - load instr word */
1284 return -1; /* send fault up to host kernel mode */