1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/process.c
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
12 #include <linux/compat.h>
13 #include <linux/efi.h>
14 #include <linux/elf.h>
15 #include <linux/export.h>
16 #include <linux/sched.h>
17 #include <linux/sched/debug.h>
18 #include <linux/sched/task.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/kernel.h>
21 #include <linux/mman.h>
23 #include <linux/nospec.h>
24 #include <linux/stddef.h>
25 #include <linux/sysctl.h>
26 #include <linux/unistd.h>
27 #include <linux/user.h>
28 #include <linux/delay.h>
29 #include <linux/reboot.h>
30 #include <linux/interrupt.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/elfcore.h>
35 #include <linux/tick.h>
36 #include <linux/utsname.h>
37 #include <linux/uaccess.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/personality.h>
41 #include <linux/notifier.h>
42 #include <trace/events/power.h>
43 #include <linux/percpu.h>
44 #include <linux/thread_info.h>
45 #include <linux/prctl.h>
47 #include <asm/alternative.h>
48 #include <asm/compat.h>
49 #include <asm/cpufeature.h>
50 #include <asm/cacheflush.h>
52 #include <asm/fpsimd.h>
53 #include <asm/mmu_context.h>
55 #include <asm/processor.h>
56 #include <asm/pointer_auth.h>
57 #include <asm/stacktrace.h>
58 #include <asm/switch_to.h>
59 #include <asm/system_misc.h>
61 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
62 #include <linux/stackprotector.h>
63 unsigned long __stack_chk_guard __read_mostly;
64 EXPORT_SYMBOL(__stack_chk_guard);
68 * Function pointers to optional machine specific functions
70 void (*pm_power_off)(void);
71 EXPORT_SYMBOL_GPL(pm_power_off);
73 #ifdef CONFIG_HOTPLUG_CPU
74 void arch_cpu_idle_dead(void)
81 * Called by kexec, immediately prior to machine_kexec().
83 * This must completely disable all secondary CPUs; simply causing those CPUs
84 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
85 * kexec'd kernel to use any and all RAM as it sees fit, without having to
86 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
87 * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
89 void machine_shutdown(void)
91 smp_shutdown_nonboot_cpus(reboot_cpu);
95 * Halting simply requires that the secondary CPUs stop performing any
96 * activity (executing tasks, handling interrupts). smp_send_stop()
99 void machine_halt(void)
107 * Power-off simply requires that the secondary CPUs stop performing any
108 * activity (executing tasks, handling interrupts). smp_send_stop()
109 * achieves this. When the system power is turned off, it will take all CPUs
112 void machine_power_off(void)
121 * Restart requires that the secondary CPUs stop performing any activity
122 * while the primary CPU resets the system. Systems with multiple CPUs must
123 * provide a HW restart implementation, to ensure that all CPUs reset at once.
124 * This is required so that any code running after reset on the primary CPU
125 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
126 * executing pre-reset code, and using RAM that the primary CPU's code wishes
127 * to use. Implementing such co-ordination would be essentially impossible.
129 void machine_restart(char *cmd)
131 /* Disable interrupts first */
136 * UpdateCapsule() depends on the system being reset via
139 if (efi_enabled(EFI_RUNTIME_SERVICES))
140 efi_reboot(reboot_mode, NULL);
142 /* Now call the architecture specific reboot code. */
143 do_kernel_restart(cmd);
146 * Whoops - the architecture was unable to reboot.
148 printk("Reboot failed -- System halted\n");
152 #define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
153 static const char *const btypes[] = {
161 static void print_pstate(struct pt_regs *regs)
163 u64 pstate = regs->pstate;
165 if (compat_user_mode(regs)) {
166 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c %cDIT %cSSBS)\n",
168 pstate & PSR_AA32_N_BIT ? 'N' : 'n',
169 pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
170 pstate & PSR_AA32_C_BIT ? 'C' : 'c',
171 pstate & PSR_AA32_V_BIT ? 'V' : 'v',
172 pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
173 pstate & PSR_AA32_T_BIT ? "T32" : "A32",
174 pstate & PSR_AA32_E_BIT ? "BE" : "LE",
175 pstate & PSR_AA32_A_BIT ? 'A' : 'a',
176 pstate & PSR_AA32_I_BIT ? 'I' : 'i',
177 pstate & PSR_AA32_F_BIT ? 'F' : 'f',
178 pstate & PSR_AA32_DIT_BIT ? '+' : '-',
179 pstate & PSR_AA32_SSBS_BIT ? '+' : '-');
181 const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
184 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
186 pstate & PSR_N_BIT ? 'N' : 'n',
187 pstate & PSR_Z_BIT ? 'Z' : 'z',
188 pstate & PSR_C_BIT ? 'C' : 'c',
189 pstate & PSR_V_BIT ? 'V' : 'v',
190 pstate & PSR_D_BIT ? 'D' : 'd',
191 pstate & PSR_A_BIT ? 'A' : 'a',
192 pstate & PSR_I_BIT ? 'I' : 'i',
193 pstate & PSR_F_BIT ? 'F' : 'f',
194 pstate & PSR_PAN_BIT ? '+' : '-',
195 pstate & PSR_UAO_BIT ? '+' : '-',
196 pstate & PSR_TCO_BIT ? '+' : '-',
197 pstate & PSR_DIT_BIT ? '+' : '-',
198 pstate & PSR_SSBS_BIT ? '+' : '-',
203 void __show_regs(struct pt_regs *regs)
208 if (compat_user_mode(regs)) {
209 lr = regs->compat_lr;
210 sp = regs->compat_sp;
218 show_regs_print_info(KERN_DEFAULT);
221 if (!user_mode(regs)) {
222 printk("pc : %pS\n", (void *)regs->pc);
223 printk("lr : %pS\n", (void *)ptrauth_strip_insn_pac(lr));
225 printk("pc : %016llx\n", regs->pc);
226 printk("lr : %016llx\n", lr);
229 printk("sp : %016llx\n", sp);
231 if (system_uses_irq_prio_masking())
232 printk("pmr_save: %08llx\n", regs->pmr_save);
237 printk("x%-2d: %016llx", i, regs->regs[i]);
240 pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
246 void show_regs(struct pt_regs *regs)
249 dump_backtrace(regs, NULL, KERN_DEFAULT);
252 static void tls_thread_flush(void)
254 write_sysreg(0, tpidr_el0);
256 if (is_compat_task()) {
257 current->thread.uw.tp_value = 0;
260 * We need to ensure ordering between the shadow state and the
261 * hardware state, so that we don't corrupt the hardware state
262 * with a stale shadow state during context switch.
265 write_sysreg(0, tpidrro_el0);
269 static void flush_tagged_addr_state(void)
271 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
272 clear_thread_flag(TIF_TAGGED_ADDR);
275 void flush_thread(void)
277 fpsimd_flush_thread();
279 flush_ptrace_hw_breakpoint(current);
280 flush_tagged_addr_state();
283 void release_thread(struct task_struct *dead_task)
287 void arch_release_task_struct(struct task_struct *tsk)
289 fpsimd_release_task(tsk);
292 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
295 fpsimd_preserve_current_state();
298 /* We rely on the above assignment to initialize dst's thread_flags: */
299 BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK));
302 * Detach src's sve_state (if any) from dst so that it does not
303 * get erroneously used or freed prematurely. dst's sve_state
304 * will be allocated on demand later on if dst uses SVE.
305 * For consistency, also clear TIF_SVE here: this could be done
306 * later in copy_process(), but to avoid tripping up future
307 * maintainers it is best not to leave TIF_SVE and sve_state in
308 * an inconsistent state, even temporarily.
310 dst->thread.sve_state = NULL;
311 clear_tsk_thread_flag(dst, TIF_SVE);
313 /* clear any pending asynchronous tag fault raised by the parent */
314 clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
319 asmlinkage void ret_from_fork(void) asm("ret_from_fork");
321 int copy_thread(unsigned long clone_flags, unsigned long stack_start,
322 unsigned long stk_sz, struct task_struct *p, unsigned long tls)
324 struct pt_regs *childregs = task_pt_regs(p);
326 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
329 * In case p was allocated the same task_struct pointer as some
330 * other recently-exited task, make sure p is disassociated from
331 * any cpu that may have run that now-exited task recently.
332 * Otherwise we could erroneously skip reloading the FPSIMD
335 fpsimd_flush_task_state(p);
337 ptrauth_thread_init_kernel(p);
339 if (likely(!(p->flags & (PF_KTHREAD | PF_IO_WORKER)))) {
340 *childregs = *current_pt_regs();
341 childregs->regs[0] = 0;
344 * Read the current TLS pointer from tpidr_el0 as it may be
345 * out-of-sync with the saved value.
347 *task_user_tls(p) = read_sysreg(tpidr_el0);
350 if (is_compat_thread(task_thread_info(p)))
351 childregs->compat_sp = stack_start;
353 childregs->sp = stack_start;
357 * If a TLS pointer was passed to clone, use it for the new
360 if (clone_flags & CLONE_SETTLS)
361 p->thread.uw.tp_value = tls;
364 * A kthread has no context to ERET to, so ensure any buggy
365 * ERET is treated as an illegal exception return.
367 * When a user task is created from a kthread, childregs will
368 * be initialized by start_thread() or start_compat_thread().
370 memset(childregs, 0, sizeof(struct pt_regs));
371 childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
373 p->thread.cpu_context.x19 = stack_start;
374 p->thread.cpu_context.x20 = stk_sz;
376 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
377 p->thread.cpu_context.sp = (unsigned long)childregs;
379 * For the benefit of the unwinder, set up childregs->stackframe
380 * as the final frame for the new task.
382 p->thread.cpu_context.fp = (unsigned long)childregs->stackframe;
384 ptrace_hw_copy_thread(p);
389 void tls_preserve_current_state(void)
391 *task_user_tls(current) = read_sysreg(tpidr_el0);
394 static void tls_thread_switch(struct task_struct *next)
396 tls_preserve_current_state();
398 if (is_compat_thread(task_thread_info(next)))
399 write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
400 else if (!arm64_kernel_unmapped_at_el0())
401 write_sysreg(0, tpidrro_el0);
403 write_sysreg(*task_user_tls(next), tpidr_el0);
407 * Force SSBS state on context-switch, since it may be lost after migrating
408 * from a CPU which treats the bit as RES0 in a heterogeneous system.
410 static void ssbs_thread_switch(struct task_struct *next)
413 * Nothing to do for kernel threads, but 'regs' may be junk
414 * (e.g. idle task) so check the flags and bail early.
416 if (unlikely(next->flags & PF_KTHREAD))
420 * If all CPUs implement the SSBS extension, then we just need to
421 * context-switch the PSTATE field.
423 if (cpus_have_const_cap(ARM64_SSBS))
426 spectre_v4_enable_task_mitigation(next);
430 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
431 * shadow copy so that we can restore this upon entry from userspace.
433 * This is *only* for exception entry from EL0, and is not valid until we
434 * __switch_to() a user task.
436 DEFINE_PER_CPU(struct task_struct *, __entry_task);
438 static void entry_task_switch(struct task_struct *next)
440 __this_cpu_write(__entry_task, next);
444 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
445 * Assuming the virtual counter is enabled at the beginning of times:
447 * - disable access when switching from a 64bit task to a 32bit task
448 * - enable access when switching from a 32bit task to a 64bit task
450 static void erratum_1418040_thread_switch(struct task_struct *prev,
451 struct task_struct *next)
456 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040))
459 prev32 = is_compat_thread(task_thread_info(prev));
460 next32 = is_compat_thread(task_thread_info(next));
462 if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
465 val = read_sysreg(cntkctl_el1);
468 val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
470 val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
472 write_sysreg(val, cntkctl_el1);
475 static void compat_thread_switch(struct task_struct *next)
477 if (!is_compat_thread(task_thread_info(next)))
480 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
481 set_tsk_thread_flag(next, TIF_NOTIFY_RESUME);
485 * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
486 * this function must be called with preemption disabled and the update to
487 * sctlr_user must be made in the same preemption disabled block so that
488 * __switch_to() does not see the variable update before the SCTLR_EL1 one.
490 void update_sctlr_el1(u64 sctlr)
493 * EnIA must not be cleared while in the kernel as this is necessary for
494 * in-kernel PAC. It will be cleared on kernel exit if needed.
496 sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
498 /* ISB required for the kernel uaccess routines when setting TCF0. */
505 __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
506 struct task_struct *next)
508 struct task_struct *last;
510 fpsimd_thread_switch(next);
511 tls_thread_switch(next);
512 hw_breakpoint_thread_switch(next);
513 contextidr_thread_switch(next);
514 entry_task_switch(next);
515 ssbs_thread_switch(next);
516 erratum_1418040_thread_switch(prev, next);
517 ptrauth_thread_switch_user(next);
518 compat_thread_switch(next);
521 * Complete any pending TLB or cache maintenance on this CPU in case
522 * the thread migrates to a different CPU.
523 * This full barrier is also required by the membarrier system
529 * MTE thread switching must happen after the DSB above to ensure that
530 * any asynchronous tag check faults have been logged in the TFSR*_EL1
533 mte_thread_switch(next);
534 /* avoid expensive SCTLR_EL1 accesses if no change */
535 if (prev->thread.sctlr_user != next->thread.sctlr_user)
536 update_sctlr_el1(next->thread.sctlr_user);
538 /* the actual thread switch */
539 last = cpu_switch_to(prev, next);
544 unsigned long get_wchan(struct task_struct *p)
546 struct stackframe frame;
547 unsigned long stack_page, ret = 0;
549 if (!p || p == current || task_is_running(p))
552 stack_page = (unsigned long)try_get_task_stack(p);
556 start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p));
559 if (unwind_frame(p, &frame))
561 if (!in_sched_functions(frame.pc)) {
565 } while (count++ < 16);
572 unsigned long arch_align_stack(unsigned long sp)
574 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
575 sp -= get_random_int() & ~PAGE_MASK;
580 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
582 void arch_setup_new_exec(void)
584 unsigned long mmflags = 0;
586 if (is_compat_task()) {
587 mmflags = MMCF_AARCH32;
588 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
589 set_tsk_thread_flag(current, TIF_NOTIFY_RESUME);
592 current->mm->context.flags = mmflags;
593 ptrauth_thread_init_user();
594 mte_thread_init_user();
596 if (task_spec_ssb_noexec(current)) {
597 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
602 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
604 * Control the relaxed ABI allowing tagged user addresses into the kernel.
606 static unsigned int tagged_addr_disabled;
608 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
610 unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
611 struct thread_info *ti = task_thread_info(task);
613 if (is_compat_thread(ti))
616 if (system_supports_mte())
617 valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK;
619 if (arg & ~valid_mask)
623 * Do not allow the enabling of the tagged address ABI if globally
624 * disabled via sysctl abi.tagged_addr_disabled.
626 if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
629 if (set_mte_ctrl(task, arg) != 0)
632 update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
637 long get_tagged_addr_ctrl(struct task_struct *task)
640 struct thread_info *ti = task_thread_info(task);
642 if (is_compat_thread(ti))
645 if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
646 ret = PR_TAGGED_ADDR_ENABLE;
648 ret |= get_mte_ctrl(task);
654 * Global sysctl to disable the tagged user addresses support. This control
655 * only prevents the tagged address ABI enabling via prctl() and does not
656 * disable it for tasks that already opted in to the relaxed ABI.
659 static struct ctl_table tagged_addr_sysctl_table[] = {
661 .procname = "tagged_addr_disabled",
663 .data = &tagged_addr_disabled,
664 .maxlen = sizeof(int),
665 .proc_handler = proc_dointvec_minmax,
666 .extra1 = SYSCTL_ZERO,
667 .extra2 = SYSCTL_ONE,
672 static int __init tagged_addr_init(void)
674 if (!register_sysctl("abi", tagged_addr_sysctl_table))
679 core_initcall(tagged_addr_init);
680 #endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
682 #ifdef CONFIG_BINFMT_ELF
683 int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
684 bool has_interp, bool is_interp)
687 * For dynamically linked executables the interpreter is
688 * responsible for setting PROT_BTI on everything except
691 if (is_interp != has_interp)
694 if (!(state->flags & ARM64_ELF_BTI))
697 if (prot & PROT_EXEC)