1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req
40 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
42 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
49 alternative_else_nop_endif
53 sub sp, sp, #PT_REGS_SIZE
54 #ifdef CONFIG_VMAP_STACK
56 * Test whether the SP has overflowed, without corrupting a GPR.
57 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
58 * should always be zero.
60 add sp, sp, x0 // sp' = sp + x0
61 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
62 tbnz x0, #THREAD_SHIFT, 0f
63 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
64 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
65 b el\el\ht\()_\regsize\()_\label
69 * Either we've just detected an overflow, or we've taken an exception
70 * while on the overflow stack. Either way, we won't return to
71 * userspace, and can clobber EL0 registers to free up GPRs.
74 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
77 /* Recover the original x0 value and stash it in tpidrro_el0 */
81 /* Switch to the overflow stack */
82 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
85 * Check whether we were already on the overflow stack. This may happen
86 * after panic() re-enables interrupts.
88 mrs x0, tpidr_el0 // sp of interrupted context
89 sub x0, sp, x0 // delta with top of overflow stack
90 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
91 b.ne __bad_stack // no? -> bad stack pointer
93 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
97 b el\el\ht\()_\regsize\()_\label
100 .macro tramp_alias, dst, sym
101 mov_q \dst, TRAMP_VALIAS
102 add \dst, \dst, #(\sym - .entry.tramp.text)
106 * This macro corrupts x0-x3. It is the caller's duty to save/restore
109 .macro apply_ssbd, state, tmp1, tmp2
110 alternative_cb spectre_v4_patch_fw_mitigation_enable
111 b .L__asm_ssbd_skip\@ // Patched to NOP
113 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
114 cbz \tmp2, .L__asm_ssbd_skip\@
115 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
116 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
117 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
119 alternative_cb spectre_v4_patch_fw_mitigation_conduit
120 nop // Patched to SMC/HVC #0
125 /* Check for MTE asynchronous tag check faults */
126 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr
127 #ifdef CONFIG_ARM64_MTE
129 alternative_if_not ARM64_MTE
131 alternative_else_nop_endif
133 * Asynchronous tag check faults are only possible in ASYNC (2) or
134 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is
135 * set, so skip the check if it is unset.
137 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
138 mrs_s \tmp, SYS_TFSRE0_EL1
139 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
140 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
141 mov \tmp, #_TIF_MTE_ASYNC_FAULT
142 add \ti_flags, tsk, #TSK_TI_FLAGS
143 stset \tmp, [\ti_flags]
148 /* Clear the MTE asynchronous tag check faults */
149 .macro clear_mte_async_tcf thread_sctlr
150 #ifdef CONFIG_ARM64_MTE
151 alternative_if ARM64_MTE
152 /* See comment in check_mte_async_tcf above. */
153 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
155 msr_s SYS_TFSRE0_EL1, xzr
157 alternative_else_nop_endif
161 .macro mte_set_gcr, mte_ctrl, tmp
162 #ifdef CONFIG_ARM64_MTE
163 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
164 orr \tmp, \tmp, #SYS_GCR_EL1_RRND
165 msr_s SYS_GCR_EL1, \tmp
169 .macro mte_set_kernel_gcr, tmp, tmp2
170 #ifdef CONFIG_KASAN_HW_TAGS
171 alternative_if_not ARM64_MTE
173 alternative_else_nop_endif
174 mov \tmp, KERNEL_GCR_EL1
175 msr_s SYS_GCR_EL1, \tmp
180 .macro mte_set_user_gcr, tsk, tmp, tmp2
181 #ifdef CONFIG_ARM64_MTE
182 alternative_if_not ARM64_MTE
184 alternative_else_nop_endif
185 ldr \tmp, [\tsk, #THREAD_MTE_CTRL]
187 mte_set_gcr \tmp, \tmp2
192 .macro kernel_entry, el, regsize = 64
194 mov w0, w0 // zero upper 32 bits of x0
196 stp x0, x1, [sp, #16 * 0]
197 stp x2, x3, [sp, #16 * 1]
198 stp x4, x5, [sp, #16 * 2]
199 stp x6, x7, [sp, #16 * 3]
200 stp x8, x9, [sp, #16 * 4]
201 stp x10, x11, [sp, #16 * 5]
202 stp x12, x13, [sp, #16 * 6]
203 stp x14, x15, [sp, #16 * 7]
204 stp x16, x17, [sp, #16 * 8]
205 stp x18, x19, [sp, #16 * 9]
206 stp x20, x21, [sp, #16 * 10]
207 stp x22, x23, [sp, #16 * 11]
208 stp x24, x25, [sp, #16 * 12]
209 stp x26, x27, [sp, #16 * 13]
210 stp x28, x29, [sp, #16 * 14]
215 ldr_this_cpu tsk, __entry_task, x20
219 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
222 ldr x19, [tsk, #TSK_TI_FLAGS]
223 disable_step_tsk x19, x20
225 /* Check for asynchronous tag check faults in user space */
226 ldr x0, [tsk, THREAD_SCTLR_USER]
227 check_mte_async_tcf x22, x23, x0
229 #ifdef CONFIG_ARM64_PTR_AUTH
230 alternative_if ARM64_HAS_ADDRESS_AUTH
232 * Enable IA for in-kernel PAC if the task had it disabled. Although
233 * this could be implemented with an unconditional MRS which would avoid
234 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
236 * Install the kernel IA key only if IA was enabled in the task. If IA
237 * was disabled on kernel exit then we would have left the kernel IA
238 * installed so there is no need to install it again.
240 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
241 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
245 orr x0, x0, SCTLR_ELx_ENIA
248 alternative_else_nop_endif
251 apply_ssbd 1, x22, x23
253 mte_set_kernel_gcr x22, x23
256 * Any non-self-synchronizing system register updates required for
257 * kernel entry should be placed before this point.
259 alternative_if ARM64_MTE
262 alternative_else_nop_endif
263 alternative_if ARM64_HAS_ADDRESS_AUTH
265 alternative_else_nop_endif
270 add x21, sp, #PT_REGS_SIZE
272 .endif /* \el == 0 */
275 stp lr, x21, [sp, #S_LR]
278 * For exceptions from EL0, create a final frame record.
279 * For exceptions from EL1, create a synthetic frame record so the
280 * interrupted code shows up in the backtrace.
283 stp xzr, xzr, [sp, #S_STACKFRAME]
285 stp x29, x22, [sp, #S_STACKFRAME]
287 add x29, sp, #S_STACKFRAME
289 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
290 alternative_if_not ARM64_HAS_PAN
291 bl __swpan_entry_el\el
292 alternative_else_nop_endif
295 stp x22, x23, [sp, #S_PC]
297 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
300 str w21, [sp, #S_SYSCALLNO]
304 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
305 mrs_s x20, SYS_ICC_PMR_EL1
306 str x20, [sp, #S_PMR_SAVE]
307 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
308 msr_s SYS_ICC_PMR_EL1, x20
309 alternative_else_nop_endif
311 /* Re-enable tag checking (TCO set on exception entry) */
312 #ifdef CONFIG_ARM64_MTE
313 alternative_if ARM64_MTE
315 alternative_else_nop_endif
319 * Registers that may be useful after this macro is invoked:
324 * x23 - aborted PSTATE
328 .macro kernel_exit, el
334 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
335 ldr x20, [sp, #S_PMR_SAVE]
336 msr_s SYS_ICC_PMR_EL1, x20
337 mrs_s x21, SYS_ICC_CTLR_EL1
338 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
339 dsb sy // Ensure priority change is seen by redistributor
341 alternative_else_nop_endif
343 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
345 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
346 alternative_if_not ARM64_HAS_PAN
347 bl __swpan_exit_el\el
348 alternative_else_nop_endif
352 ldr x23, [sp, #S_SP] // load return stack pointer
354 tst x22, #PSR_MODE32_BIT // native task?
357 #ifdef CONFIG_ARM64_ERRATUM_845719
358 alternative_if ARM64_WORKAROUND_845719
359 #ifdef CONFIG_PID_IN_CONTEXTIDR
360 mrs x29, contextidr_el1
361 msr contextidr_el1, x29
363 msr contextidr_el1, xzr
365 alternative_else_nop_endif
370 /* Ignore asynchronous tag check faults in the uaccess routines */
371 ldr x0, [tsk, THREAD_SCTLR_USER]
372 clear_mte_async_tcf x0
374 #ifdef CONFIG_ARM64_PTR_AUTH
375 alternative_if ARM64_HAS_ADDRESS_AUTH
377 * IA was enabled for in-kernel PAC. Disable it now if needed, or
378 * alternatively install the user's IA. All other per-task keys and
379 * SCTLR bits were updated on task switch.
381 * No kernel C function calls after this.
383 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
384 __ptrauth_keys_install_user tsk, x0, x1, x2
388 bic x0, x0, SCTLR_ELx_ENIA
391 alternative_else_nop_endif
394 mte_set_user_gcr tsk, x0, x1
399 msr elr_el1, x21 // set up the return data
401 ldp x0, x1, [sp, #16 * 0]
402 ldp x2, x3, [sp, #16 * 1]
403 ldp x4, x5, [sp, #16 * 2]
404 ldp x6, x7, [sp, #16 * 3]
405 ldp x8, x9, [sp, #16 * 4]
406 ldp x10, x11, [sp, #16 * 5]
407 ldp x12, x13, [sp, #16 * 6]
408 ldp x14, x15, [sp, #16 * 7]
409 ldp x16, x17, [sp, #16 * 8]
410 ldp x18, x19, [sp, #16 * 9]
411 ldp x20, x21, [sp, #16 * 10]
412 ldp x22, x23, [sp, #16 * 11]
413 ldp x24, x25, [sp, #16 * 12]
414 ldp x26, x27, [sp, #16 * 13]
415 ldp x28, x29, [sp, #16 * 14]
417 add sp, sp, #PT_REGS_SIZE // restore sp
420 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
421 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
424 tramp_alias x30, tramp_exit_native
427 tramp_alias x30, tramp_exit_compat
431 /* Ensure any device/NC reads complete */
432 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
439 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
441 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
442 * EL0, there is no need to check the state of TTBR0_EL1 since
443 * accesses are always enabled.
444 * Note that the meaning of this bit differs from the ARMv8.1 PAN
445 * feature as all TTBR0_EL1 accesses are disabled, not just those to
448 SYM_CODE_START_LOCAL(__swpan_entry_el1)
450 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
451 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
452 b.eq 1f // TTBR0 access already disabled
453 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
454 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
455 __uaccess_ttbr0_disable x21
457 SYM_CODE_END(__swpan_entry_el1)
460 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
463 SYM_CODE_START_LOCAL(__swpan_exit_el1)
464 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
465 __uaccess_ttbr0_enable x0, x1
466 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
468 SYM_CODE_END(__swpan_exit_el1)
470 SYM_CODE_START_LOCAL(__swpan_exit_el0)
471 __uaccess_ttbr0_enable x0, x1
473 * Enable errata workarounds only if returning to user. The only
474 * workaround currently required for TTBR0_EL1 changes are for the
475 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
478 b post_ttbr_update_workaround
479 SYM_CODE_END(__swpan_exit_el0)
482 /* GPRs used by entry code */
483 tsk .req x28 // current thread_info
490 .pushsection ".entry.text", "ax"
493 SYM_CODE_START(vectors)
494 kernel_ventry 1, t, 64, sync // Synchronous EL1t
495 kernel_ventry 1, t, 64, irq // IRQ EL1t
496 kernel_ventry 1, t, 64, fiq // FIQ EL1h
497 kernel_ventry 1, t, 64, error // Error EL1t
499 kernel_ventry 1, h, 64, sync // Synchronous EL1h
500 kernel_ventry 1, h, 64, irq // IRQ EL1h
501 kernel_ventry 1, h, 64, fiq // FIQ EL1h
502 kernel_ventry 1, h, 64, error // Error EL1h
504 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
505 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
506 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
507 kernel_ventry 0, t, 64, error // Error 64-bit EL0
509 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
510 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
511 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
512 kernel_ventry 0, t, 32, error // Error 32-bit EL0
513 SYM_CODE_END(vectors)
515 #ifdef CONFIG_VMAP_STACK
516 SYM_CODE_START_LOCAL(__bad_stack)
518 * We detected an overflow in kernel_ventry, which switched to the
519 * overflow stack. Stash the exception regs, and head to our overflow
523 /* Restore the original x0 value */
527 * Store the original GPRs to the new stack. The orginal SP (minus
528 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
530 sub sp, sp, #PT_REGS_SIZE
533 add x0, x0, #PT_REGS_SIZE
536 /* Stash the regs for handle_bad_stack */
542 SYM_CODE_END(__bad_stack)
543 #endif /* CONFIG_VMAP_STACK */
546 .macro entry_handler el:req, ht:req, regsize:req, label:req
547 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label)
548 kernel_entry \el, \regsize
550 bl el\el\ht\()_\regsize\()_\label\()_handler
556 SYM_CODE_END(el\el\ht\()_\regsize\()_\label)
560 * Early exception handlers
562 entry_handler 1, t, 64, sync
563 entry_handler 1, t, 64, irq
564 entry_handler 1, t, 64, fiq
565 entry_handler 1, t, 64, error
567 entry_handler 1, h, 64, sync
568 entry_handler 1, h, 64, irq
569 entry_handler 1, h, 64, fiq
570 entry_handler 1, h, 64, error
572 entry_handler 0, t, 64, sync
573 entry_handler 0, t, 64, irq
574 entry_handler 0, t, 64, fiq
575 entry_handler 0, t, 64, error
577 entry_handler 0, t, 32, sync
578 entry_handler 0, t, 32, irq
579 entry_handler 0, t, 32, fiq
580 entry_handler 0, t, 32, error
582 SYM_CODE_START_LOCAL(ret_to_kernel)
584 SYM_CODE_END(ret_to_kernel)
586 SYM_CODE_START_LOCAL(ret_to_user)
587 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
588 enable_step_tsk x19, x2
589 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
593 SYM_CODE_END(ret_to_user)
595 .popsection // .entry.text
597 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
599 * Exception vectors trampoline.
601 .pushsection ".entry.tramp.text", "ax"
603 // Move from tramp_pg_dir to swapper_pg_dir
604 .macro tramp_map_kernel, tmp
606 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
607 bic \tmp, \tmp, #USER_ASID_FLAG
609 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
610 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
611 /* ASID already in \tmp[63:48] */
612 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
613 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
614 /* 2MB boundary containing the vectors, so we nobble the walk cache */
615 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
619 alternative_else_nop_endif
620 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
623 // Move from swapper_pg_dir to tramp_pg_dir
624 .macro tramp_unmap_kernel, tmp
626 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
627 orr \tmp, \tmp, #USER_ASID_FLAG
630 * We avoid running the post_ttbr_update_workaround here because
631 * it's only needed by Cavium ThunderX, which requires KPTI to be
636 .macro tramp_ventry, regsize = 64
640 msr tpidrro_el0, x30 // Restored in kernel_ventry
643 * Defend against branch aliasing attacks by pushing a dummy
644 * entry onto the return stack and using a RET instruction to
645 * enter the full-fat kernel vectors.
651 #ifdef CONFIG_RANDOMIZE_BASE
652 adr x30, tramp_vectors + PAGE_SIZE
653 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
658 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
659 prfm plil1strm, [x30, #(1b - tramp_vectors)]
660 alternative_else_nop_endif
662 add x30, x30, #(1b - tramp_vectors)
667 .macro tramp_exit, regsize = 64
668 adr x30, tramp_vectors
670 tramp_unmap_kernel x30
679 SYM_CODE_START_NOALIGN(tramp_vectors)
691 SYM_CODE_END(tramp_vectors)
693 SYM_CODE_START(tramp_exit_native)
695 SYM_CODE_END(tramp_exit_native)
697 SYM_CODE_START(tramp_exit_compat)
699 SYM_CODE_END(tramp_exit_compat)
702 .popsection // .entry.tramp.text
703 #ifdef CONFIG_RANDOMIZE_BASE
704 .pushsection ".rodata", "a"
706 SYM_DATA_START(__entry_tramp_data_start)
708 SYM_DATA_END(__entry_tramp_data_start)
709 .popsection // .rodata
710 #endif /* CONFIG_RANDOMIZE_BASE */
711 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
714 * Register switch for AArch64. The callee-saved registers need to be saved
715 * and restored. On entry:
716 * x0 = previous task_struct (must be preserved across the switch)
717 * x1 = next task_struct
718 * Previous and next are guaranteed not to be the same.
721 SYM_FUNC_START(cpu_switch_to)
722 mov x10, #THREAD_CPU_CONTEXT
725 stp x19, x20, [x8], #16 // store callee-saved registers
726 stp x21, x22, [x8], #16
727 stp x23, x24, [x8], #16
728 stp x25, x26, [x8], #16
729 stp x27, x28, [x8], #16
730 stp x29, x9, [x8], #16
733 ldp x19, x20, [x8], #16 // restore callee-saved registers
734 ldp x21, x22, [x8], #16
735 ldp x23, x24, [x8], #16
736 ldp x25, x26, [x8], #16
737 ldp x27, x28, [x8], #16
738 ldp x29, x9, [x8], #16
742 ptrauth_keys_install_kernel x1, x8, x9, x10
746 SYM_FUNC_END(cpu_switch_to)
747 NOKPROBE(cpu_switch_to)
750 * This is how we return from a fork.
752 SYM_CODE_START(ret_from_fork)
754 cbz x19, 1f // not a kernel thread
757 1: get_current_task tsk
759 bl asm_exit_to_user_mode
761 SYM_CODE_END(ret_from_fork)
762 NOKPROBE(ret_from_fork)
765 * void call_on_irq_stack(struct pt_regs *regs,
766 * void (*func)(struct pt_regs *));
768 * Calls func(regs) using this CPU's irq stack and shadow irq stack.
770 SYM_FUNC_START(call_on_irq_stack)
771 #ifdef CONFIG_SHADOW_CALL_STACK
772 stp scs_sp, xzr, [sp, #-16]!
773 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17
775 /* Create a frame record to save our LR and SP (implicit in FP) */
776 stp x29, x30, [sp, #-16]!
779 ldr_this_cpu x16, irq_stack_ptr, x17
780 mov x15, #IRQ_STACK_SIZE
783 /* Move to the new stack and call the function there */
788 * Restore the SP from the FP, and restore the FP and LR from the frame
792 ldp x29, x30, [sp], #16
793 #ifdef CONFIG_SHADOW_CALL_STACK
794 ldp scs_sp, xzr, [sp], #16
797 SYM_FUNC_END(call_on_irq_stack)
798 NOKPROBE(call_on_irq_stack)
800 #ifdef CONFIG_ARM_SDE_INTERFACE
802 #include <asm/sdei.h>
803 #include <uapi/linux/arm_sdei.h>
805 .macro sdei_handler_exit exit_mode
806 /* On success, this call never returns... */
807 cmp \exit_mode, #SDEI_EXIT_SMC
815 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
817 * The regular SDEI entry point may have been unmapped along with the rest of
818 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
819 * argument accessible.
821 * This clobbers x4, __sdei_handler() will restore this from firmware's
825 .pushsection ".entry.tramp.text", "ax"
826 SYM_CODE_START(__sdei_asm_entry_trampoline)
828 tbz x4, #USER_ASID_BIT, 1f
830 tramp_map_kernel tmp=x4
835 * Remember whether to unmap the kernel on exit.
837 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
839 #ifdef CONFIG_RANDOMIZE_BASE
840 adr x4, tramp_vectors + PAGE_SIZE
841 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
844 ldr x4, =__sdei_asm_handler
847 SYM_CODE_END(__sdei_asm_entry_trampoline)
848 NOKPROBE(__sdei_asm_entry_trampoline)
851 * Make the exit call and restore the original ttbr1_el1
853 * x0 & x1: setup for the exit API call
855 * x4: struct sdei_registered_event argument from registration time.
857 SYM_CODE_START(__sdei_asm_exit_trampoline)
858 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
861 tramp_unmap_kernel tmp=x4
863 1: sdei_handler_exit exit_mode=x2
864 SYM_CODE_END(__sdei_asm_exit_trampoline)
865 NOKPROBE(__sdei_asm_exit_trampoline)
867 .popsection // .entry.tramp.text
868 #ifdef CONFIG_RANDOMIZE_BASE
869 .pushsection ".rodata", "a"
870 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
871 .quad __sdei_asm_handler
872 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
873 .popsection // .rodata
874 #endif /* CONFIG_RANDOMIZE_BASE */
875 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
878 * Software Delegated Exception entry point.
881 * x1: struct sdei_registered_event argument from registration time.
883 * x3: interrupted PSTATE
884 * x4: maybe clobbered by the trampoline
886 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
887 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
890 SYM_CODE_START(__sdei_asm_handler)
891 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
892 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
893 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
894 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
895 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
896 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
897 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
898 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
899 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
900 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
901 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
902 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
903 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
904 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
906 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
910 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
911 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
914 #ifdef CONFIG_VMAP_STACK
916 * entry.S may have been using sp as a scratch register, find whether
917 * this is a normal or critical event and switch to the appropriate
918 * stack for this CPU.
921 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
923 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
924 2: mov x6, #SDEI_STACK_SIZE
929 #ifdef CONFIG_SHADOW_CALL_STACK
930 /* Use a separate shadow call stack for normal and critical events */
932 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
934 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
939 * We may have interrupted userspace, or a guest, or exit-from or
940 * return-to either of these. We can't trust sp_el0, restore it.
943 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
946 /* If we interrupted the kernel point to the previous stack/frame. */
950 csel x29, x29, xzr, eq // fp, or zero
951 csel x4, x2, xzr, eq // elr, or zero
953 stp x29, x4, [sp, #-16]!
956 add x0, x19, #SDEI_EVENT_INTREGS
961 /* restore regs >x17 that we clobbered */
962 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
963 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
964 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
965 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
968 mov x1, x0 // address to complete_and_resume
969 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
971 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
972 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
975 ldr_l x2, sdei_exit_mode
977 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
978 sdei_handler_exit exit_mode=x2
979 alternative_else_nop_endif
981 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
982 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
985 SYM_CODE_END(__sdei_asm_handler)
986 NOKPROBE(__sdei_asm_handler)
987 #endif /* CONFIG_ARM_SDE_INTERFACE */