arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy.h>
   8 #include <dt-bindings/mux/mux.h>
   9 #include <dt-bindings/mux/ti-serdes.h>
  10
  11 &cbass_main {
  12         msmc_ram: sram@70000000 {
  13                 compatible = "mmio-sram";
  14                 reg = <0x0 0x70000000 0x0 0x800000>;
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x0 0x0 0x70000000 0x800000>;
  18
  19                 atf-sram@0 {
  20                         reg = <0x0 0x20000>;
  21                 };
  22         };
  23
  24         scm_conf: scm-conf@100000 {
  25                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  26                 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges = <0x0 0x0 0x00100000 0x1c000>;
  30
  31                 serdes_ln_ctrl: mux@4080 {
  32                         compatible = "mmio-mux";
  33                         reg = <0x00004080 0x50>;
  34                         #mux-control-cells = <1>;
  35                         mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
  36                                         <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
  37                                         <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
  38                                         <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
  39                                         <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
  40                                         /* SERDES4 lane0/1/2/3 select */
  41                         idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
  42                                       <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
  43                                       <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
  44                                       <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
  45                                       <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
  46                                       <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
  47                 };
  48
  49                 usb_serdes_mux: mux-controller@4000 {
  50                         compatible = "mmio-mux";
  51                         #mux-control-cells = <1>;
  52                         mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
  53                                         <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
  54             };
  55         };
  56
  57         gic500: interrupt-controller@1800000 {
  58                 compatible = "arm,gic-v3";
  59                 #address-cells = <2>;
  60                 #size-cells = <2>;
  61                 ranges;
  62                 #interrupt-cells = <3>;
  63                 interrupt-controller;
  64                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  65                       <0x00 0x01900000 0x00 0x100000>;  /* GICR */
  66
  67                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  68                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  69
  70                 gic_its: msi-controller@1820000 {
  71                         compatible = "arm,gic-v3-its";
  72                         reg = <0x00 0x01820000 0x00 0x10000>;
  73                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  74                         msi-controller;
  75                         #msi-cells = <1>;
  76                 };
  77         };
  78
  79         main_gpio_intr: interrupt-controller0 {
  80                 compatible = "ti,sci-intr";
  81                 ti,intr-trigger-type = <1>;
  82                 interrupt-controller;
  83                 interrupt-parent = <&gic500>;
  84                 #interrupt-cells = <1>;
  85                 ti,sci = <&dmsc>;
  86                 ti,sci-dev-id = <131>;
  87                 ti,interrupt-ranges = <8 392 56>;
  88         };
  89
  90         main-navss {
  91                 compatible = "simple-mfd";
  92                 #address-cells = <2>;
  93                 #size-cells = <2>;
  94                 ranges;
  95                 dma-coherent;
  96                 dma-ranges;
  97
  98                 ti,sci-dev-id = <199>;
  99
 100                 main_navss_intr: interrupt-controller1 {
 101                         compatible = "ti,sci-intr";
 102                         ti,intr-trigger-type = <4>;
 103                         interrupt-controller;
 104                         interrupt-parent = <&gic500>;
 105                         #interrupt-cells = <1>;
 106                         ti,sci = <&dmsc>;
 107                         ti,sci-dev-id = <213>;
 108                         ti,interrupt-ranges = <0 64 64>,
 109                                               <64 448 64>,
 110                                               <128 672 64>;
 111                 };
 112
 113                 main_udmass_inta: interrupt-controller@33d00000 {
 114                         compatible = "ti,sci-inta";
 115                         reg = <0x0 0x33d00000 0x0 0x100000>;
 116                         interrupt-controller;
 117                         interrupt-parent = <&main_navss_intr>;
 118                         msi-controller;
 119                         #interrupt-cells = <0>;
 120                         ti,sci = <&dmsc>;
 121                         ti,sci-dev-id = <209>;
 122                         ti,interrupt-ranges = <0 0 256>;
 123                 };
 124
 125                 secure_proxy_main: mailbox@32c00000 {
 126                         compatible = "ti,am654-secure-proxy";
 127                         #mbox-cells = <1>;
 128                         reg-names = "target_data", "rt", "scfg";
 129                         reg = <0x00 0x32c00000 0x00 0x100000>,
 130                               <0x00 0x32400000 0x00 0x100000>,
 131                               <0x00 0x32800000 0x00 0x100000>;
 132                         interrupt-names = "rx_011";
 133                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 134                 };
 135
 136                 smmu0: iommu@36600000 {
 137                         compatible = "arm,smmu-v3";
 138                         reg = <0x0 0x36600000 0x0 0x100000>;
 139                         interrupt-parent = <&gic500>;
 140                         interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
 141                                      <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
 142                         interrupt-names = "eventq", "gerror";
 143                         #iommu-cells = <1>;
 144                 };
 145
 146                 hwspinlock: spinlock@30e00000 {
 147                         compatible = "ti,am654-hwspinlock";
 148                         reg = <0x00 0x30e00000 0x00 0x1000>;
 149                         #hwlock-cells = <1>;
 150                 };
 151
 152                 mailbox0_cluster0: mailbox@31f80000 {
 153                         compatible = "ti,am654-mailbox";
 154                         reg = <0x00 0x31f80000 0x00 0x200>;
 155                         #mbox-cells = <1>;
 156                         ti,mbox-num-users = <4>;
 157                         ti,mbox-num-fifos = <16>;
 158                         interrupt-parent = <&main_navss_intr>;
 159                 };
 160
 161                 mailbox0_cluster1: mailbox@31f81000 {
 162                         compatible = "ti,am654-mailbox";
 163                         reg = <0x00 0x31f81000 0x00 0x200>;
 164                         #mbox-cells = <1>;
 165                         ti,mbox-num-users = <4>;
 166                         ti,mbox-num-fifos = <16>;
 167                         interrupt-parent = <&main_navss_intr>;
 168                 };
 169
 170                 mailbox0_cluster2: mailbox@31f82000 {
 171                         compatible = "ti,am654-mailbox";
 172                         reg = <0x00 0x31f82000 0x00 0x200>;
 173                         #mbox-cells = <1>;
 174                         ti,mbox-num-users = <4>;
 175                         ti,mbox-num-fifos = <16>;
 176                         interrupt-parent = <&main_navss_intr>;
 177                 };
 178
 179                 mailbox0_cluster3: mailbox@31f83000 {
 180                         compatible = "ti,am654-mailbox";
 181                         reg = <0x00 0x31f83000 0x00 0x200>;
 182                         #mbox-cells = <1>;
 183                         ti,mbox-num-users = <4>;
 184                         ti,mbox-num-fifos = <16>;
 185                         interrupt-parent = <&main_navss_intr>;
 186                 };
 187
 188                 mailbox0_cluster4: mailbox@31f84000 {
 189                         compatible = "ti,am654-mailbox";
 190                         reg = <0x00 0x31f84000 0x00 0x200>;
 191                         #mbox-cells = <1>;
 192                         ti,mbox-num-users = <4>;
 193                         ti,mbox-num-fifos = <16>;
 194                         interrupt-parent = <&main_navss_intr>;
 195                 };
 196
 197                 mailbox0_cluster5: mailbox@31f85000 {
 198                         compatible = "ti,am654-mailbox";
 199                         reg = <0x00 0x31f85000 0x00 0x200>;
 200                         #mbox-cells = <1>;
 201                         ti,mbox-num-users = <4>;
 202                         ti,mbox-num-fifos = <16>;
 203                         interrupt-parent = <&main_navss_intr>;
 204                 };
 205
 206                 mailbox0_cluster6: mailbox@31f86000 {
 207                         compatible = "ti,am654-mailbox";
 208                         reg = <0x00 0x31f86000 0x00 0x200>;
 209                         #mbox-cells = <1>;
 210                         ti,mbox-num-users = <4>;
 211                         ti,mbox-num-fifos = <16>;
 212                         interrupt-parent = <&main_navss_intr>;
 213                 };
 214
 215                 mailbox0_cluster7: mailbox@31f87000 {
 216                         compatible = "ti,am654-mailbox";
 217                         reg = <0x00 0x31f87000 0x00 0x200>;
 218                         #mbox-cells = <1>;
 219                         ti,mbox-num-users = <4>;
 220                         ti,mbox-num-fifos = <16>;
 221                         interrupt-parent = <&main_navss_intr>;
 222                 };
 223
 224                 mailbox0_cluster8: mailbox@31f88000 {
 225                         compatible = "ti,am654-mailbox";
 226                         reg = <0x00 0x31f88000 0x00 0x200>;
 227                         #mbox-cells = <1>;
 228                         ti,mbox-num-users = <4>;
 229                         ti,mbox-num-fifos = <16>;
 230                         interrupt-parent = <&main_navss_intr>;
 231                 };
 232
 233                 mailbox0_cluster9: mailbox@31f89000 {
 234                         compatible = "ti,am654-mailbox";
 235                         reg = <0x00 0x31f89000 0x00 0x200>;
 236                         #mbox-cells = <1>;
 237                         ti,mbox-num-users = <4>;
 238                         ti,mbox-num-fifos = <16>;
 239                         interrupt-parent = <&main_navss_intr>;
 240                 };
 241
 242                 mailbox0_cluster10: mailbox@31f8a000 {
 243                         compatible = "ti,am654-mailbox";
 244                         reg = <0x00 0x31f8a000 0x00 0x200>;
 245                         #mbox-cells = <1>;
 246                         ti,mbox-num-users = <4>;
 247                         ti,mbox-num-fifos = <16>;
 248                         interrupt-parent = <&main_navss_intr>;
 249                 };
 250
 251                 mailbox0_cluster11: mailbox@31f8b000 {
 252                         compatible = "ti,am654-mailbox";
 253                         reg = <0x00 0x31f8b000 0x00 0x200>;
 254                         #mbox-cells = <1>;
 255                         ti,mbox-num-users = <4>;
 256                         ti,mbox-num-fifos = <16>;
 257                         interrupt-parent = <&main_navss_intr>;
 258                 };
 259
 260                 main_ringacc: ringacc@3c000000 {
 261                         compatible = "ti,am654-navss-ringacc";
 262                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 263                                 <0x0 0x38000000 0x0 0x400000>,
 264                                 <0x0 0x31120000 0x0 0x100>,
 265                                 <0x0 0x33000000 0x0 0x40000>;
 266                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 267                         ti,num-rings = <1024>;
 268                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 269                         ti,sci = <&dmsc>;
 270                         ti,sci-dev-id = <211>;
 271                         msi-parent = <&main_udmass_inta>;
 272                 };
 273
 274                 main_udmap: dma-controller@31150000 {
 275                         compatible = "ti,j721e-navss-main-udmap";
 276                         reg =   <0x0 0x31150000 0x0 0x100>,
 277                                 <0x0 0x34000000 0x0 0x100000>,
 278                                 <0x0 0x35000000 0x0 0x100000>;
 279                         reg-names = "gcfg", "rchanrt", "tchanrt";
 280                         msi-parent = <&main_udmass_inta>;
 281                         #dma-cells = <1>;
 282
 283                         ti,sci = <&dmsc>;
 284                         ti,sci-dev-id = <212>;
 285                         ti,ringacc = <&main_ringacc>;
 286
 287                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 288                                                 <0x0f>, /* TX_HCHAN */
 289                                                 <0x10>; /* TX_UHCHAN */
 290                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 291                                                 <0x0b>, /* RX_HCHAN */
 292                                                 <0x0c>; /* RX_UHCHAN */
 293                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 294                 };
 295
 296                 cpts@310d0000 {
 297                         compatible = "ti,j721e-cpts";
 298                         reg = <0x0 0x310d0000 0x0 0x400>;
 299                         reg-names = "cpts";
 300                         clocks = <&k3_clks 201 1>;
 301                         clock-names = "cpts";
 302                         interrupts-extended = <&main_navss_intr 391>;
 303                         interrupt-names = "cpts";
 304                         ti,cpts-periodic-outputs = <6>;
 305                         ti,cpts-ext-ts-inputs = <8>;
 306                 };
 307         };
 308
 309         main_crypto: crypto@4e00000 {
 310                 compatible = "ti,j721e-sa2ul";
 311                 reg = <0x0 0x4e00000 0x0 0x1200>;
 312                 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
 313                 #address-cells = <2>;
 314                 #size-cells = <2>;
 315                 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
 316
 317                 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
 318                                 <&main_udmap 0x4001>;
 319                 dma-names = "tx", "rx1", "rx2";
 320                 dma-coherent;
 321
 322                 rng: rng@4e10000 {
 323                         compatible = "inside-secure,safexcel-eip76";
 324                         reg = <0x0 0x4e10000 0x0 0x7d>;
 325                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&k3_clks 264 1>;
 327                 };
 328         };
 329
 330         main_pmx0: pinctrl@11c000 {
 331                 compatible = "pinctrl-single";
 332                 /* Proxy 0 addressing */
 333                 reg = <0x0 0x11c000 0x0 0x2b4>;
 334                 #pinctrl-cells = <1>;
 335                 pinctrl-single,register-width = <32>;
 336                 pinctrl-single,function-mask = <0xffffffff>;
 337         };
 338
 339         dummy_cmn_refclk: dummy-cmn-refclk {
 340                 #clock-cells = <0>;
 341                 compatible = "fixed-clock";
 342                 clock-frequency = <100000000>;
 343         };
 344
 345         dummy_cmn_refclk1: dummy-cmn-refclk1 {
 346                 #clock-cells = <0>;
 347                 compatible = "fixed-clock";
 348                 clock-frequency = <100000000>;
 349         };
 350
 351         serdes_wiz0: wiz@5000000 {
 352                 compatible = "ti,j721e-wiz-16g";
 353                 #address-cells = <1>;
 354                 #size-cells = <1>;
 355                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 356                 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
 357                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 358                 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
 359                 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
 360                 num-lanes = <2>;
 361                 #reset-cells = <1>;
 362                 ranges = <0x5000000 0x0 0x5000000 0x10000>;
 363
 364                 wiz0_pll0_refclk: pll0-refclk {
 365                         clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
 366                         #clock-cells = <0>;
 367                         assigned-clocks = <&wiz0_pll0_refclk>;
 368                         assigned-clock-parents = <&k3_clks 292 11>;
 369                 };
 370
 371                 wiz0_pll1_refclk: pll1-refclk {
 372                         clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
 373                         #clock-cells = <0>;
 374                         assigned-clocks = <&wiz0_pll1_refclk>;
 375                         assigned-clock-parents = <&k3_clks 292 0>;
 376                 };
 377
 378                 wiz0_refclk_dig: refclk-dig {
 379                         clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 380                         #clock-cells = <0>;
 381                         assigned-clocks = <&wiz0_refclk_dig>;
 382                         assigned-clock-parents = <&k3_clks 292 11>;
 383                 };
 384
 385                 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
 386                         clocks = <&wiz0_refclk_dig>;
 387                         #clock-cells = <0>;
 388                 };
 389
 390                 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 391                         clocks = <&wiz0_pll1_refclk>;
 392                         #clock-cells = <0>;
 393                 };
 394
 395                 serdes0: serdes@5000000 {
 396                         compatible = "ti,sierra-phy-t0";
 397                         reg-names = "serdes";
 398                         reg = <0x5000000 0x10000>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         resets = <&serdes_wiz0 0>;
 402                         reset-names = "sierra_reset";
 403                         clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
 404                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 405                 };
 406         };
 407
 408         serdes_wiz1: wiz@5010000 {
 409                 compatible = "ti,j721e-wiz-16g";
 410                 #address-cells = <1>;
 411                 #size-cells = <1>;
 412                 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
 413                 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
 414                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 415                 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
 416                 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
 417                 num-lanes = <2>;
 418                 #reset-cells = <1>;
 419                 ranges = <0x5010000 0x0 0x5010000 0x10000>;
 420
 421                 wiz1_pll0_refclk: pll0-refclk {
 422                         clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
 423                         #clock-cells = <0>;
 424                         assigned-clocks = <&wiz1_pll0_refclk>;
 425                         assigned-clock-parents = <&k3_clks 293 13>;
 426                 };
 427
 428                 wiz1_pll1_refclk: pll1-refclk {
 429                         clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
 430                         #clock-cells = <0>;
 431                         assigned-clocks = <&wiz1_pll1_refclk>;
 432                         assigned-clock-parents = <&k3_clks 293 0>;
 433                 };
 434
 435                 wiz1_refclk_dig: refclk-dig {
 436                         clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 437                         #clock-cells = <0>;
 438                         assigned-clocks = <&wiz1_refclk_dig>;
 439                         assigned-clock-parents = <&k3_clks 293 13>;
 440                 };
 441
 442                 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
 443                         clocks = <&wiz1_refclk_dig>;
 444                         #clock-cells = <0>;
 445                 };
 446
 447                 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 448                         clocks = <&wiz1_pll1_refclk>;
 449                         #clock-cells = <0>;
 450                 };
 451
 452                 serdes1: serdes@5010000 {
 453                         compatible = "ti,sierra-phy-t0";
 454                         reg-names = "serdes";
 455                         reg = <0x5010000 0x10000>;
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         resets = <&serdes_wiz1 0>;
 459                         reset-names = "sierra_reset";
 460                         clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
 461                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 462                 };
 463         };
 464
 465         serdes_wiz2: wiz@5020000 {
 466                 compatible = "ti,j721e-wiz-16g";
 467                 #address-cells = <1>;
 468                 #size-cells = <1>;
 469                 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
 470                 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
 471                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 472                 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
 473                 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
 474                 num-lanes = <2>;
 475                 #reset-cells = <1>;
 476                 ranges = <0x5020000 0x0 0x5020000 0x10000>;
 477
 478                 wiz2_pll0_refclk: pll0-refclk {
 479                         clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
 480                         #clock-cells = <0>;
 481                         assigned-clocks = <&wiz2_pll0_refclk>;
 482                         assigned-clock-parents = <&k3_clks 294 11>;
 483                 };
 484
 485                 wiz2_pll1_refclk: pll1-refclk {
 486                         clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
 487                         #clock-cells = <0>;
 488                         assigned-clocks = <&wiz2_pll1_refclk>;
 489                         assigned-clock-parents = <&k3_clks 294 0>;
 490                 };
 491
 492                 wiz2_refclk_dig: refclk-dig {
 493                         clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 494                         #clock-cells = <0>;
 495                         assigned-clocks = <&wiz2_refclk_dig>;
 496                         assigned-clock-parents = <&k3_clks 294 11>;
 497                 };
 498
 499                 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
 500                         clocks = <&wiz2_refclk_dig>;
 501                         #clock-cells = <0>;
 502                 };
 503
 504                 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 505                         clocks = <&wiz2_pll1_refclk>;
 506                         #clock-cells = <0>;
 507                 };
 508
 509                 serdes2: serdes@5020000 {
 510                         compatible = "ti,sierra-phy-t0";
 511                         reg-names = "serdes";
 512                         reg = <0x5020000 0x10000>;
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         resets = <&serdes_wiz2 0>;
 516                         reset-names = "sierra_reset";
 517                         clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
 518                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 519                 };
 520         };
 521
 522         serdes_wiz3: wiz@5030000 {
 523                 compatible = "ti,j721e-wiz-16g";
 524                 #address-cells = <1>;
 525                 #size-cells = <1>;
 526                 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
 527                 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
 528                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 529                 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
 530                 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
 531                 num-lanes = <2>;
 532                 #reset-cells = <1>;
 533                 ranges = <0x5030000 0x0 0x5030000 0x10000>;
 534
 535                 wiz3_pll0_refclk: pll0-refclk {
 536                         clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
 537                         #clock-cells = <0>;
 538                         assigned-clocks = <&wiz3_pll0_refclk>;
 539                         assigned-clock-parents = <&k3_clks 295 9>;
 540                 };
 541
 542                 wiz3_pll1_refclk: pll1-refclk {
 543                         clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
 544                         #clock-cells = <0>;
 545                         assigned-clocks = <&wiz3_pll1_refclk>;
 546                         assigned-clock-parents = <&k3_clks 295 0>;
 547                 };
 548
 549                 wiz3_refclk_dig: refclk-dig {
 550                         clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 551                         #clock-cells = <0>;
 552                         assigned-clocks = <&wiz3_refclk_dig>;
 553                         assigned-clock-parents = <&k3_clks 295 9>;
 554                 };
 555
 556                 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
 557                         clocks = <&wiz3_refclk_dig>;
 558                         #clock-cells = <0>;
 559                 };
 560
 561                 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 562                         clocks = <&wiz3_pll1_refclk>;
 563                         #clock-cells = <0>;
 564                 };
 565
 566                 serdes3: serdes@5030000 {
 567                         compatible = "ti,sierra-phy-t0";
 568                         reg-names = "serdes";
 569                         reg = <0x5030000 0x10000>;
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         resets = <&serdes_wiz3 0>;
 573                         reset-names = "sierra_reset";
 574                         clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
 575                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 576                 };
 577         };
 578
 579         pcie0_rc: pcie@2900000 {
 580                 compatible = "ti,j721e-pcie-host";
 581                 reg = <0x00 0x02900000 0x00 0x1000>,
 582                       <0x00 0x02907000 0x00 0x400>,
 583                       <0x00 0x0d000000 0x00 0x00800000>,
 584                       <0x00 0x10000000 0x00 0x00001000>;
 585                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 586                 interrupt-names = "link_state";
 587                 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
 588                 device_type = "pci";
 589                 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
 590                 max-link-speed = <3>;
 591                 num-lanes = <2>;
 592                 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
 593                 clocks = <&k3_clks 239 1>;
 594                 clock-names = "fck";
 595                 #address-cells = <3>;
 596                 #size-cells = <2>;
 597                 bus-range = <0x0 0xf>;
 598                 vendor-id = <0x104c>;
 599                 device-id = <0xb00d>;
 600                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 601                 dma-coherent;
 602                 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
 603                          <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
 604                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 605         };
 606
 607         pcie0_ep: pcie-ep@2900000 {
 608                 compatible = "ti,j721e-pcie-ep";
 609                 reg = <0x00 0x02900000 0x00 0x1000>,
 610                       <0x00 0x02907000 0x00 0x400>,
 611                       <0x00 0x0d000000 0x00 0x00800000>,
 612                       <0x00 0x10000000 0x00 0x08000000>;
 613                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 614                 interrupt-names = "link_state";
 615                 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
 616                 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
 617                 max-link-speed = <3>;
 618                 num-lanes = <2>;
 619                 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
 620                 clocks = <&k3_clks 239 1>;
 621                 clock-names = "fck";
 622                 max-functions = /bits/ 8 <6>;
 623                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 624                 dma-coherent;
 625         };
 626
 627         pcie1_rc: pcie@2910000 {
 628                 compatible = "ti,j721e-pcie-host";
 629                 reg = <0x00 0x02910000 0x00 0x1000>,
 630                       <0x00 0x02917000 0x00 0x400>,
 631                       <0x00 0x0d800000 0x00 0x00800000>,
 632                       <0x00 0x18000000 0x00 0x00001000>;
 633                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 634                 interrupt-names = "link_state";
 635                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 636                 device_type = "pci";
 637                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 638                 max-link-speed = <3>;
 639                 num-lanes = <2>;
 640                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 641                 clocks = <&k3_clks 240 1>;
 642                 clock-names = "fck";
 643                 #address-cells = <3>;
 644                 #size-cells = <2>;
 645                 bus-range = <0x0 0xf>;
 646                 vendor-id = <0x104c>;
 647                 device-id = <0xb00d>;
 648                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 649                 dma-coherent;
 650                 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
 651                          <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
 652                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 653         };
 654
 655         pcie1_ep: pcie-ep@2910000 {
 656                 compatible = "ti,j721e-pcie-ep";
 657                 reg = <0x00 0x02910000 0x00 0x1000>,
 658                       <0x00 0x02917000 0x00 0x400>,
 659                       <0x00 0x0d800000 0x00 0x00800000>,
 660                       <0x00 0x18000000 0x00 0x08000000>;
 661                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 662                 interrupt-names = "link_state";
 663                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 664                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 665                 max-link-speed = <3>;
 666                 num-lanes = <2>;
 667                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 668                 clocks = <&k3_clks 240 1>;
 669                 clock-names = "fck";
 670                 max-functions = /bits/ 8 <6>;
 671                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 672                 dma-coherent;
 673         };
 674
 675         pcie2_rc: pcie@2920000 {
 676                 compatible = "ti,j721e-pcie-host";
 677                 reg = <0x00 0x02920000 0x00 0x1000>,
 678                       <0x00 0x02927000 0x00 0x400>,
 679                       <0x00 0x0e000000 0x00 0x00800000>,
 680                       <0x44 0x00000000 0x00 0x00001000>;
 681                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 682                 interrupt-names = "link_state";
 683                 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
 684                 device_type = "pci";
 685                 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
 686                 max-link-speed = <3>;
 687                 num-lanes = <2>;
 688                 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
 689                 clocks = <&k3_clks 241 1>;
 690                 clock-names = "fck";
 691                 #address-cells = <3>;
 692                 #size-cells = <2>;
 693                 bus-range = <0x0 0xf>;
 694                 vendor-id = <0x104c>;
 695                 device-id = <0xb00d>;
 696                 msi-map = <0x0 &gic_its 0x20000 0x10000>;
 697                 dma-coherent;
 698                 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
 699                          <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
 700                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 701         };
 702
 703         pcie2_ep: pcie-ep@2920000 {
 704                 compatible = "ti,j721e-pcie-ep";
 705                 reg = <0x00 0x02920000 0x00 0x1000>,
 706                       <0x00 0x02927000 0x00 0x400>,
 707                       <0x00 0x0e000000 0x00 0x00800000>,
 708                       <0x44 0x00000000 0x00 0x08000000>;
 709                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 710                 interrupt-names = "link_state";
 711                 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
 712                 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
 713                 max-link-speed = <3>;
 714                 num-lanes = <2>;
 715                 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
 716                 clocks = <&k3_clks 241 1>;
 717                 clock-names = "fck";
 718                 max-functions = /bits/ 8 <6>;
 719                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 720                 dma-coherent;
 721         };
 722
 723         pcie3_rc: pcie@2930000 {
 724                 compatible = "ti,j721e-pcie-host";
 725                 reg = <0x00 0x02930000 0x00 0x1000>,
 726                       <0x00 0x02937000 0x00 0x400>,
 727                       <0x00 0x0e800000 0x00 0x00800000>,
 728                       <0x44 0x10000000 0x00 0x00001000>;
 729                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 730                 interrupt-names = "link_state";
 731                 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
 732                 device_type = "pci";
 733                 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
 734                 max-link-speed = <3>;
 735                 num-lanes = <2>;
 736                 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
 737                 clocks = <&k3_clks 242 1>;
 738                 clock-names = "fck";
 739                 #address-cells = <3>;
 740                 #size-cells = <2>;
 741                 bus-range = <0x0 0xf>;
 742                 vendor-id = <0x104c>;
 743                 device-id = <0xb00d>;
 744                 msi-map = <0x0 &gic_its 0x30000 0x10000>;
 745                 dma-coherent;
 746                 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
 747                          <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
 748                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 749         };
 750
 751         pcie3_ep: pcie-ep@2930000 {
 752                 compatible = "ti,j721e-pcie-ep";
 753                 reg = <0x00 0x02930000 0x00 0x1000>,
 754                       <0x00 0x02937000 0x00 0x400>,
 755                       <0x00 0x0e800000 0x00 0x00800000>,
 756                       <0x44 0x10000000 0x00 0x08000000>;
 757                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 758                 interrupt-names = "link_state";
 759                 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
 760                 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
 761                 max-link-speed = <3>;
 762                 num-lanes = <2>;
 763                 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
 764                 clocks = <&k3_clks 242 1>;
 765                 clock-names = "fck";
 766                 max-functions = /bits/ 8 <6>;
 767                 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
 768                 dma-coherent;
 769                 #address-cells = <2>;
 770                 #size-cells = <2>;
 771         };
 772
 773         main_uart0: serial@2800000 {
 774                 compatible = "ti,j721e-uart", "ti,am654-uart";
 775                 reg = <0x00 0x02800000 0x00 0x100>;
 776                 reg-shift = <2>;
 777                 reg-io-width = <4>;
 778                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 779                 clock-frequency = <48000000>;
 780                 current-speed = <115200>;
 781                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 782                 clocks = <&k3_clks 146 0>;
 783                 clock-names = "fclk";
 784         };
 785
 786         main_uart1: serial@2810000 {
 787                 compatible = "ti,j721e-uart", "ti,am654-uart";
 788                 reg = <0x00 0x02810000 0x00 0x100>;
 789                 reg-shift = <2>;
 790                 reg-io-width = <4>;
 791                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 792                 clock-frequency = <48000000>;
 793                 current-speed = <115200>;
 794                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 795                 clocks = <&k3_clks 278 0>;
 796                 clock-names = "fclk";
 797         };
 798
 799         main_uart2: serial@2820000 {
 800                 compatible = "ti,j721e-uart", "ti,am654-uart";
 801                 reg = <0x00 0x02820000 0x00 0x100>;
 802                 reg-shift = <2>;
 803                 reg-io-width = <4>;
 804                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 805                 clock-frequency = <48000000>;
 806                 current-speed = <115200>;
 807                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 808                 clocks = <&k3_clks 279 0>;
 809                 clock-names = "fclk";
 810         };
 811
 812         main_uart3: serial@2830000 {
 813                 compatible = "ti,j721e-uart", "ti,am654-uart";
 814                 reg = <0x00 0x02830000 0x00 0x100>;
 815                 reg-shift = <2>;
 816                 reg-io-width = <4>;
 817                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 818                 clock-frequency = <48000000>;
 819                 current-speed = <115200>;
 820                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 821                 clocks = <&k3_clks 280 0>;
 822                 clock-names = "fclk";
 823         };
 824
 825         main_uart4: serial@2840000 {
 826                 compatible = "ti,j721e-uart", "ti,am654-uart";
 827                 reg = <0x00 0x02840000 0x00 0x100>;
 828                 reg-shift = <2>;
 829                 reg-io-width = <4>;
 830                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 831                 clock-frequency = <48000000>;
 832                 current-speed = <115200>;
 833                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 834                 clocks = <&k3_clks 281 0>;
 835                 clock-names = "fclk";
 836         };
 837
 838         main_uart5: serial@2850000 {
 839                 compatible = "ti,j721e-uart", "ti,am654-uart";
 840                 reg = <0x00 0x02850000 0x00 0x100>;
 841                 reg-shift = <2>;
 842                 reg-io-width = <4>;
 843                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 844                 clock-frequency = <48000000>;
 845                 current-speed = <115200>;
 846                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 847                 clocks = <&k3_clks 282 0>;
 848                 clock-names = "fclk";
 849         };
 850
 851         main_uart6: serial@2860000 {
 852                 compatible = "ti,j721e-uart", "ti,am654-uart";
 853                 reg = <0x00 0x02860000 0x00 0x100>;
 854                 reg-shift = <2>;
 855                 reg-io-width = <4>;
 856                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 857                 clock-frequency = <48000000>;
 858                 current-speed = <115200>;
 859                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 860                 clocks = <&k3_clks 283 0>;
 861                 clock-names = "fclk";
 862         };
 863
 864         main_uart7: serial@2870000 {
 865                 compatible = "ti,j721e-uart", "ti,am654-uart";
 866                 reg = <0x00 0x02870000 0x00 0x100>;
 867                 reg-shift = <2>;
 868                 reg-io-width = <4>;
 869                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 870                 clock-frequency = <48000000>;
 871                 current-speed = <115200>;
 872                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 873                 clocks = <&k3_clks 284 0>;
 874                 clock-names = "fclk";
 875         };
 876
 877         main_uart8: serial@2880000 {
 878                 compatible = "ti,j721e-uart", "ti,am654-uart";
 879                 reg = <0x00 0x02880000 0x00 0x100>;
 880                 reg-shift = <2>;
 881                 reg-io-width = <4>;
 882                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 883                 clock-frequency = <48000000>;
 884                 current-speed = <115200>;
 885                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 886                 clocks = <&k3_clks 285 0>;
 887                 clock-names = "fclk";
 888         };
 889
 890         main_uart9: serial@2890000 {
 891                 compatible = "ti,j721e-uart", "ti,am654-uart";
 892                 reg = <0x00 0x02890000 0x00 0x100>;
 893                 reg-shift = <2>;
 894                 reg-io-width = <4>;
 895                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 896                 clock-frequency = <48000000>;
 897                 current-speed = <115200>;
 898                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 899                 clocks = <&k3_clks 286 0>;
 900                 clock-names = "fclk";
 901         };
 902
 903         main_gpio0: gpio@600000 {
 904                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 905                 reg = <0x0 0x00600000 0x0 0x100>;
 906                 gpio-controller;
 907                 #gpio-cells = <2>;
 908                 interrupt-parent = <&main_gpio_intr>;
 909                 interrupts = <256>, <257>, <258>, <259>,
 910                              <260>, <261>, <262>, <263>;
 911                 interrupt-controller;
 912                 #interrupt-cells = <2>;
 913                 ti,ngpio = <128>;
 914                 ti,davinci-gpio-unbanked = <0>;
 915                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 916                 clocks = <&k3_clks 105 0>;
 917                 clock-names = "gpio";
 918         };
 919
 920         main_gpio1: gpio@601000 {
 921                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 922                 reg = <0x0 0x00601000 0x0 0x100>;
 923                 gpio-controller;
 924                 #gpio-cells = <2>;
 925                 interrupt-parent = <&main_gpio_intr>;
 926                 interrupts = <288>, <289>, <290>;
 927                 interrupt-controller;
 928                 #interrupt-cells = <2>;
 929                 ti,ngpio = <36>;
 930                 ti,davinci-gpio-unbanked = <0>;
 931                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 932                 clocks = <&k3_clks 106 0>;
 933                 clock-names = "gpio";
 934         };
 935
 936         main_gpio2: gpio@610000 {
 937                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 938                 reg = <0x0 0x00610000 0x0 0x100>;
 939                 gpio-controller;
 940                 #gpio-cells = <2>;
 941                 interrupt-parent = <&main_gpio_intr>;
 942                 interrupts = <264>, <265>, <266>, <267>,
 943                              <268>, <269>, <270>, <271>;
 944                 interrupt-controller;
 945                 #interrupt-cells = <2>;
 946                 ti,ngpio = <128>;
 947                 ti,davinci-gpio-unbanked = <0>;
 948                 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 949                 clocks = <&k3_clks 107 0>;
 950                 clock-names = "gpio";
 951         };
 952
 953         main_gpio3: gpio@611000 {
 954                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 955                 reg = <0x0 0x00611000 0x0 0x100>;
 956                 gpio-controller;
 957                 #gpio-cells = <2>;
 958                 interrupt-parent = <&main_gpio_intr>;
 959                 interrupts = <292>, <293>, <294>;
 960                 interrupt-controller;
 961                 #interrupt-cells = <2>;
 962                 ti,ngpio = <36>;
 963                 ti,davinci-gpio-unbanked = <0>;
 964                 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
 965                 clocks = <&k3_clks 108 0>;
 966                 clock-names = "gpio";
 967         };
 968
 969         main_gpio4: gpio@620000 {
 970                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 971                 reg = <0x0 0x00620000 0x0 0x100>;
 972                 gpio-controller;
 973                 #gpio-cells = <2>;
 974                 interrupt-parent = <&main_gpio_intr>;
 975                 interrupts = <272>, <273>, <274>, <275>,
 976                              <276>, <277>, <278>, <279>;
 977                 interrupt-controller;
 978                 #interrupt-cells = <2>;
 979                 ti,ngpio = <128>;
 980                 ti,davinci-gpio-unbanked = <0>;
 981                 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 982                 clocks = <&k3_clks 109 0>;
 983                 clock-names = "gpio";
 984         };
 985
 986         main_gpio5: gpio@621000 {
 987                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 988                 reg = <0x0 0x00621000 0x0 0x100>;
 989                 gpio-controller;
 990                 #gpio-cells = <2>;
 991                 interrupt-parent = <&main_gpio_intr>;
 992                 interrupts = <296>, <297>, <298>;
 993                 interrupt-controller;
 994                 #interrupt-cells = <2>;
 995                 ti,ngpio = <36>;
 996                 ti,davinci-gpio-unbanked = <0>;
 997                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 998                 clocks = <&k3_clks 110 0>;
 999                 clock-names = "gpio";
1000         };
1001
1002         main_gpio6: gpio@630000 {
1003                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1004                 reg = <0x0 0x00630000 0x0 0x100>;
1005                 gpio-controller;
1006                 #gpio-cells = <2>;
1007                 interrupt-parent = <&main_gpio_intr>;
1008                 interrupts = <280>, <281>, <282>, <283>,
1009                              <284>, <285>, <286>, <287>;
1010                 interrupt-controller;
1011                 #interrupt-cells = <2>;
1012                 ti,ngpio = <128>;
1013                 ti,davinci-gpio-unbanked = <0>;
1014                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1015                 clocks = <&k3_clks 111 0>;
1016                 clock-names = "gpio";
1017         };
1018
1019         main_gpio7: gpio@631000 {
1020                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1021                 reg = <0x0 0x00631000 0x0 0x100>;
1022                 gpio-controller;
1023                 #gpio-cells = <2>;
1024                 interrupt-parent = <&main_gpio_intr>;
1025                 interrupts = <300>, <301>, <302>;
1026                 interrupt-controller;
1027                 #interrupt-cells = <2>;
1028                 ti,ngpio = <36>;
1029                 ti,davinci-gpio-unbanked = <0>;
1030                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1031                 clocks = <&k3_clks 112 0>;
1032                 clock-names = "gpio";
1033         };
1034
1035         main_sdhci0: mmc@4f80000 {
1036                 compatible = "ti,j721e-sdhci-8bit";
1037                 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1038                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1039                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1040                 clock-names = "clk_ahb", "clk_xin";
1041                 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1042                 assigned-clocks = <&k3_clks 91 1>;
1043                 assigned-clock-parents = <&k3_clks 91 2>;
1044                 bus-width = <8>;
1045                 mmc-hs200-1_8v;
1046                 mmc-ddr-1_8v;
1047                 ti,otap-del-sel-legacy = <0xf>;
1048                 ti,otap-del-sel-mmc-hs = <0xf>;
1049                 ti,otap-del-sel-ddr52 = <0x5>;
1050                 ti,otap-del-sel-hs200 = <0x6>;
1051                 ti,otap-del-sel-hs400 = <0x0>;
1052                 ti,itap-del-sel-legacy = <0x10>;
1053                 ti,itap-del-sel-mmc-hs = <0xa>;
1054                 ti,itap-del-sel-ddr52 = <0x3>;
1055                 ti,trm-icp = <0x8>;
1056                 ti,strobe-sel = <0x77>;
1057                 dma-coherent;
1058         };
1059
1060         main_sdhci1: mmc@4fb0000 {
1061                 compatible = "ti,j721e-sdhci-4bit";
1062                 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1063                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1064                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1065                 clock-names = "clk_ahb", "clk_xin";
1066                 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1067                 assigned-clocks = <&k3_clks 92 0>;
1068                 assigned-clock-parents = <&k3_clks 92 1>;
1069                 ti,otap-del-sel-legacy = <0x0>;
1070                 ti,otap-del-sel-sd-hs = <0xf>;
1071                 ti,otap-del-sel-sdr12 = <0xf>;
1072                 ti,otap-del-sel-sdr25 = <0xf>;
1073                 ti,otap-del-sel-sdr50 = <0xc>;
1074                 ti,otap-del-sel-ddr50 = <0xc>;
1075                 ti,itap-del-sel-legacy = <0x0>;
1076                 ti,itap-del-sel-sd-hs = <0x0>;
1077                 ti,itap-del-sel-sdr12 = <0x0>;
1078                 ti,itap-del-sel-sdr25 = <0x0>;
1079                 ti,itap-del-sel-ddr50 = <0x2>;
1080                 ti,trm-icp = <0x8>;
1081                 ti,clkbuf-sel = <0x7>;
1082                 dma-coherent;
1083                 sdhci-caps-mask = <0x2 0x0>;
1084         };
1085
1086         main_sdhci2: mmc@4f98000 {
1087                 compatible = "ti,j721e-sdhci-4bit";
1088                 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1089                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1090                 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1091                 clock-names = "clk_ahb", "clk_xin";
1092                 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1093                 assigned-clocks = <&k3_clks 93 0>;
1094                 assigned-clock-parents = <&k3_clks 93 1>;
1095                 ti,otap-del-sel-legacy = <0x0>;
1096                 ti,otap-del-sel-sd-hs = <0xf>;
1097                 ti,otap-del-sel-sdr12 = <0xf>;
1098                 ti,otap-del-sel-sdr25 = <0xf>;
1099                 ti,otap-del-sel-sdr50 = <0xc>;
1100                 ti,otap-del-sel-ddr50 = <0xc>;
1101                 ti,itap-del-sel-legacy = <0x0>;
1102                 ti,itap-del-sel-sd-hs = <0x0>;
1103                 ti,itap-del-sel-sdr12 = <0x0>;
1104                 ti,itap-del-sel-sdr25 = <0x0>;
1105                 ti,itap-del-sel-ddr50 = <0x2>;
1106                 ti,trm-icp = <0x8>;
1107                 ti,clkbuf-sel = <0x7>;
1108                 dma-coherent;
1109                 sdhci-caps-mask = <0x2 0x0>;
1110         };
1111
1112         usbss0: cdns-usb@4104000 {
1113                 compatible = "ti,j721e-usb";
1114                 reg = <0x00 0x4104000 0x00 0x100>;
1115                 dma-coherent;
1116                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1117                 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1118                 clock-names = "ref", "lpm";
1119                 assigned-clocks = <&k3_clks 288 15>;    /* USB2_REFCLK */
1120                 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1121                 #address-cells = <2>;
1122                 #size-cells = <2>;
1123                 ranges;
1124
1125                 usb0: usb@6000000 {
1126                         compatible = "cdns,usb3";
1127                         reg = <0x00 0x6000000 0x00 0x10000>,
1128                               <0x00 0x6010000 0x00 0x10000>,
1129                               <0x00 0x6020000 0x00 0x10000>;
1130                         reg-names = "otg", "xhci", "dev";
1131                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
1132                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1133                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1134                         interrupt-names = "host",
1135                                           "peripheral",
1136                                           "otg";
1137                         maximum-speed = "super-speed";
1138                         dr_mode = "otg";
1139                 };
1140         };
1141
1142         usbss1: cdns-usb@4114000 {
1143                 compatible = "ti,j721e-usb";
1144                 reg = <0x00 0x4114000 0x00 0x100>;
1145                 dma-coherent;
1146                 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1147                 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1148                 clock-names = "ref", "lpm";
1149                 assigned-clocks = <&k3_clks 289 15>;    /* USB2_REFCLK */
1150                 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1151                 #address-cells = <2>;
1152                 #size-cells = <2>;
1153                 ranges;
1154
1155                 usb1: usb@6400000 {
1156                         compatible = "cdns,usb3";
1157                         reg = <0x00 0x6400000 0x00 0x10000>,
1158                               <0x00 0x6410000 0x00 0x10000>,
1159                               <0x00 0x6420000 0x00 0x10000>;
1160                         reg-names = "otg", "xhci", "dev";
1161                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1162                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1163                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1164                         interrupt-names = "host",
1165                                           "peripheral",
1166                                           "otg";
1167                         maximum-speed = "super-speed";
1168                         dr_mode = "otg";
1169                 };
1170         };
1171
1172         main_i2c0: i2c@2000000 {
1173                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1174                 reg = <0x0 0x2000000 0x0 0x100>;
1175                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1176                 #address-cells = <1>;
1177                 #size-cells = <0>;
1178                 clock-names = "fck";
1179                 clocks = <&k3_clks 187 0>;
1180                 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1181         };
1182
1183         main_i2c1: i2c@2010000 {
1184                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1185                 reg = <0x0 0x2010000 0x0 0x100>;
1186                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1187                 #address-cells = <1>;
1188                 #size-cells = <0>;
1189                 clock-names = "fck";
1190                 clocks = <&k3_clks 188 0>;
1191                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1192         };
1193
1194         main_i2c2: i2c@2020000 {
1195                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1196                 reg = <0x0 0x2020000 0x0 0x100>;
1197                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1198                 #address-cells = <1>;
1199                 #size-cells = <0>;
1200                 clock-names = "fck";
1201                 clocks = <&k3_clks 189 0>;
1202                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1203         };
1204
1205         main_i2c3: i2c@2030000 {
1206                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1207                 reg = <0x0 0x2030000 0x0 0x100>;
1208                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1209                 #address-cells = <1>;
1210                 #size-cells = <0>;
1211                 clock-names = "fck";
1212                 clocks = <&k3_clks 190 0>;
1213                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1214         };
1215
1216         main_i2c4: i2c@2040000 {
1217                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1218                 reg = <0x0 0x2040000 0x0 0x100>;
1219                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1220                 #address-cells = <1>;
1221                 #size-cells = <0>;
1222                 clock-names = "fck";
1223                 clocks = <&k3_clks 191 0>;
1224                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1225         };
1226
1227         main_i2c5: i2c@2050000 {
1228                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1229                 reg = <0x0 0x2050000 0x0 0x100>;
1230                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1231                 #address-cells = <1>;
1232                 #size-cells = <0>;
1233                 clock-names = "fck";
1234                 clocks = <&k3_clks 192 0>;
1235                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1236         };
1237
1238         main_i2c6: i2c@2060000 {
1239                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1240                 reg = <0x0 0x2060000 0x0 0x100>;
1241                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1242                 #address-cells = <1>;
1243                 #size-cells = <0>;
1244                 clock-names = "fck";
1245                 clocks = <&k3_clks 193 0>;
1246                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1247         };
1248
1249         ufs_wrapper: ufs-wrapper@4e80000 {
1250                 compatible = "ti,j721e-ufs";
1251                 reg = <0x0 0x4e80000 0x0 0x100>;
1252                 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1253                 clocks = <&k3_clks 277 1>;
1254                 assigned-clocks = <&k3_clks 277 1>;
1255                 assigned-clock-parents = <&k3_clks 277 4>;
1256                 ranges;
1257                 #address-cells = <2>;
1258                 #size-cells = <2>;
1259
1260                 ufs@4e84000 {
1261                         compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1262                         reg = <0x0 0x4e84000 0x0 0x10000>;
1263                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1264                         freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1265                         clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1266                         clock-names = "core_clk", "phy_clk", "ref_clk";
1267                         dma-coherent;
1268                 };
1269         };
1270
1271         dss: dss@4a00000 {
1272                 compatible = "ti,j721e-dss";
1273                 reg =
1274                         <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1275                         <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1276                         <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1277                         <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1278
1279                         <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1280                         <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1281                         <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1282                         <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1283
1284                         <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1285                         <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1286                         <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1287                         <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1288
1289                         <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1290                         <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1291                         <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1292                         <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1293                         <0x00 0x04af0000 0x00 0x10000>; /* wb */
1294
1295                 reg-names = "common_m", "common_s0",
1296                         "common_s1", "common_s2",
1297                         "vidl1", "vidl2","vid1","vid2",
1298                         "ovr1", "ovr2", "ovr3", "ovr4",
1299                         "vp1", "vp2", "vp3", "vp4",
1300                         "wb";
1301
1302                 clocks =        <&k3_clks 152 0>,
1303                                 <&k3_clks 152 1>,
1304                                 <&k3_clks 152 4>,
1305                                 <&k3_clks 152 9>,
1306                                 <&k3_clks 152 13>;
1307                 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1308
1309                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1310
1311                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1312                              <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1313                              <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1314                              <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1315                 interrupt-names = "common_m",
1316                                   "common_s0",
1317                                   "common_s1",
1318                                   "common_s2";
1319
1320                 dss_ports: ports {
1321                         #address-cells = <1>;
1322                         #size-cells = <0>;
1323                 };
1324         };
1325
1326         mcasp0: mcasp@2b00000 {
1327                 compatible = "ti,am33xx-mcasp-audio";
1328                 reg = <0x0 0x02b00000 0x0 0x2000>,
1329                         <0x0 0x02b08000 0x0 0x1000>;
1330                 reg-names = "mpu","dat";
1331                 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1332                                 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1333                 interrupt-names = "tx", "rx";
1334
1335                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1336                 dma-names = "tx", "rx";
1337
1338                 clocks = <&k3_clks 174 1>;
1339                 clock-names = "fck";
1340                 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1341         };
1342
1343         mcasp1: mcasp@2b10000 {
1344                 compatible = "ti,am33xx-mcasp-audio";
1345                 reg = <0x0 0x02b10000 0x0 0x2000>,
1346                         <0x0 0x02b18000 0x0 0x1000>;
1347                 reg-names = "mpu","dat";
1348                 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1349                                 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1350                 interrupt-names = "tx", "rx";
1351
1352                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1353                 dma-names = "tx", "rx";
1354
1355                 clocks = <&k3_clks 175 1>;
1356                 clock-names = "fck";
1357                 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1358         };
1359
1360         mcasp2: mcasp@2b20000 {
1361                 compatible = "ti,am33xx-mcasp-audio";
1362                 reg = <0x0 0x02b20000 0x0 0x2000>,
1363                         <0x0 0x02b28000 0x0 0x1000>;
1364                 reg-names = "mpu","dat";
1365                 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1366                                 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1367                 interrupt-names = "tx", "rx";
1368
1369                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1370                 dma-names = "tx", "rx";
1371
1372                 clocks = <&k3_clks 176 1>;
1373                 clock-names = "fck";
1374                 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1375         };
1376
1377         mcasp3: mcasp@2b30000 {
1378                 compatible = "ti,am33xx-mcasp-audio";
1379                 reg = <0x0 0x02b30000 0x0 0x2000>,
1380                         <0x0 0x02b38000 0x0 0x1000>;
1381                 reg-names = "mpu","dat";
1382                 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1383                                 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1384                 interrupt-names = "tx", "rx";
1385
1386                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1387                 dma-names = "tx", "rx";
1388
1389                 clocks = <&k3_clks 177 1>;
1390                 clock-names = "fck";
1391                 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1392         };
1393
1394         mcasp4: mcasp@2b40000 {
1395                 compatible = "ti,am33xx-mcasp-audio";
1396                 reg = <0x0 0x02b40000 0x0 0x2000>,
1397                         <0x0 0x02b48000 0x0 0x1000>;
1398                 reg-names = "mpu","dat";
1399                 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1400                                 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1401                 interrupt-names = "tx", "rx";
1402
1403                 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1404                 dma-names = "tx", "rx";
1405
1406                 clocks = <&k3_clks 178 1>;
1407                 clock-names = "fck";
1408                 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1409         };
1410
1411         mcasp5: mcasp@2b50000 {
1412                 compatible = "ti,am33xx-mcasp-audio";
1413                 reg = <0x0 0x02b50000 0x0 0x2000>,
1414                         <0x0 0x02b58000 0x0 0x1000>;
1415                 reg-names = "mpu","dat";
1416                 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1417                                 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1418                 interrupt-names = "tx", "rx";
1419
1420                 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1421                 dma-names = "tx", "rx";
1422
1423                 clocks = <&k3_clks 179 1>;
1424                 clock-names = "fck";
1425                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1426         };
1427
1428         mcasp6: mcasp@2b60000 {
1429                 compatible = "ti,am33xx-mcasp-audio";
1430                 reg = <0x0 0x02b60000 0x0 0x2000>,
1431                         <0x0 0x02b68000 0x0 0x1000>;
1432                 reg-names = "mpu","dat";
1433                 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1434                                 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1435                 interrupt-names = "tx", "rx";
1436
1437                 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1438                 dma-names = "tx", "rx";
1439
1440                 clocks = <&k3_clks 180 1>;
1441                 clock-names = "fck";
1442                 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1443         };
1444
1445         mcasp7: mcasp@2b70000 {
1446                 compatible = "ti,am33xx-mcasp-audio";
1447                 reg = <0x0 0x02b70000 0x0 0x2000>,
1448                         <0x0 0x02b78000 0x0 0x1000>;
1449                 reg-names = "mpu","dat";
1450                 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1451                                 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1452                 interrupt-names = "tx", "rx";
1453
1454                 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1455                 dma-names = "tx", "rx";
1456
1457                 clocks = <&k3_clks 181 1>;
1458                 clock-names = "fck";
1459                 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1460         };
1461
1462         mcasp8: mcasp@2b80000 {
1463                 compatible = "ti,am33xx-mcasp-audio";
1464                 reg = <0x0 0x02b80000 0x0 0x2000>,
1465                         <0x0 0x02b88000 0x0 0x1000>;
1466                 reg-names = "mpu","dat";
1467                 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1468                                 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1469                 interrupt-names = "tx", "rx";
1470
1471                 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1472                 dma-names = "tx", "rx";
1473
1474                 clocks = <&k3_clks 182 1>;
1475                 clock-names = "fck";
1476                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1477         };
1478
1479         mcasp9: mcasp@2b90000 {
1480                 compatible = "ti,am33xx-mcasp-audio";
1481                 reg = <0x0 0x02b90000 0x0 0x2000>,
1482                         <0x0 0x02b98000 0x0 0x1000>;
1483                 reg-names = "mpu","dat";
1484                 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1485                                 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1486                 interrupt-names = "tx", "rx";
1487
1488                 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1489                 dma-names = "tx", "rx";
1490
1491                 clocks = <&k3_clks 183 1>;
1492                 clock-names = "fck";
1493                 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1494         };
1495
1496         mcasp10: mcasp@2ba0000 {
1497                 compatible = "ti,am33xx-mcasp-audio";
1498                 reg = <0x0 0x02ba0000 0x0 0x2000>,
1499                         <0x0 0x02ba8000 0x0 0x1000>;
1500                 reg-names = "mpu","dat";
1501                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1502                                 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1503                 interrupt-names = "tx", "rx";
1504
1505                 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1506                 dma-names = "tx", "rx";
1507
1508                 clocks = <&k3_clks 184 1>;
1509                 clock-names = "fck";
1510                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1511         };
1512
1513         mcasp11: mcasp@2bb0000 {
1514                 compatible = "ti,am33xx-mcasp-audio";
1515                 reg = <0x0 0x02bb0000 0x0 0x2000>,
1516                         <0x0 0x02bb8000 0x0 0x1000>;
1517                 reg-names = "mpu","dat";
1518                 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1519                                 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1520                 interrupt-names = "tx", "rx";
1521
1522                 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1523                 dma-names = "tx", "rx";
1524
1525                 clocks = <&k3_clks 185 1>;
1526                 clock-names = "fck";
1527                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1528         };
1529
1530         watchdog0: watchdog@2200000 {
1531                 compatible = "ti,j7-rti-wdt";
1532                 reg = <0x0 0x2200000 0x0 0x100>;
1533                 clocks = <&k3_clks 252 1>;
1534                 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1535                 assigned-clocks = <&k3_clks 252 1>;
1536                 assigned-clock-parents = <&k3_clks 252 5>;
1537         };
1538
1539         watchdog1: watchdog@2210000 {
1540                 compatible = "ti,j7-rti-wdt";
1541                 reg = <0x0 0x2210000 0x0 0x100>;
1542                 clocks = <&k3_clks 253 1>;
1543                 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1544                 assigned-clocks = <&k3_clks 253 1>;
1545                 assigned-clock-parents = <&k3_clks 253 5>;
1546         };
1547
1548         main_r5fss0: r5fss@5c00000 {
1549                 compatible = "ti,j721e-r5fss";
1550                 ti,cluster-mode = <1>;
1551                 #address-cells = <1>;
1552                 #size-cells = <1>;
1553                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1554                          <0x5d00000 0x00 0x5d00000 0x20000>;
1555                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1556
1557                 main_r5fss0_core0: r5f@5c00000 {
1558                         compatible = "ti,j721e-r5f";
1559                         reg = <0x5c00000 0x00008000>,
1560                               <0x5c10000 0x00008000>;
1561                         reg-names = "atcm", "btcm";
1562                         ti,sci = <&dmsc>;
1563                         ti,sci-dev-id = <245>;
1564                         ti,sci-proc-ids = <0x06 0xff>;
1565                         resets = <&k3_reset 245 1>;
1566                         firmware-name = "j7-main-r5f0_0-fw";
1567                         ti,atcm-enable = <1>;
1568                         ti,btcm-enable = <1>;
1569                         ti,loczrama = <1>;
1570                 };
1571
1572                 main_r5fss0_core1: r5f@5d00000 {
1573                         compatible = "ti,j721e-r5f";
1574                         reg = <0x5d00000 0x00008000>,
1575                               <0x5d10000 0x00008000>;
1576                         reg-names = "atcm", "btcm";
1577                         ti,sci = <&dmsc>;
1578                         ti,sci-dev-id = <246>;
1579                         ti,sci-proc-ids = <0x07 0xff>;
1580                         resets = <&k3_reset 246 1>;
1581                         firmware-name = "j7-main-r5f0_1-fw";
1582                         ti,atcm-enable = <1>;
1583                         ti,btcm-enable = <1>;
1584                         ti,loczrama = <1>;
1585                 };
1586         };
1587
1588         main_r5fss1: r5fss@5e00000 {
1589                 compatible = "ti,j721e-r5fss";
1590                 ti,cluster-mode = <1>;
1591                 #address-cells = <1>;
1592                 #size-cells = <1>;
1593                 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1594                          <0x5f00000 0x00 0x5f00000 0x20000>;
1595                 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1596
1597                 main_r5fss1_core0: r5f@5e00000 {
1598                         compatible = "ti,j721e-r5f";
1599                         reg = <0x5e00000 0x00008000>,
1600                               <0x5e10000 0x00008000>;
1601                         reg-names = "atcm", "btcm";
1602                         ti,sci = <&dmsc>;
1603                         ti,sci-dev-id = <247>;
1604                         ti,sci-proc-ids = <0x08 0xff>;
1605                         resets = <&k3_reset 247 1>;
1606                         firmware-name = "j7-main-r5f1_0-fw";
1607                         ti,atcm-enable = <1>;
1608                         ti,btcm-enable = <1>;
1609                         ti,loczrama = <1>;
1610                 };
1611
1612                 main_r5fss1_core1: r5f@5f00000 {
1613                         compatible = "ti,j721e-r5f";
1614                         reg = <0x5f00000 0x00008000>,
1615                               <0x5f10000 0x00008000>;
1616                         reg-names = "atcm", "btcm";
1617                         ti,sci = <&dmsc>;
1618                         ti,sci-dev-id = <248>;
1619                         ti,sci-proc-ids = <0x09 0xff>;
1620                         resets = <&k3_reset 248 1>;
1621                         firmware-name = "j7-main-r5f1_1-fw";
1622                         ti,atcm-enable = <1>;
1623                         ti,btcm-enable = <1>;
1624                         ti,loczrama = <1>;
1625                 };
1626         };
1627
1628         c66_0: dsp@4d80800000 {
1629                 compatible = "ti,j721e-c66-dsp";
1630                 reg = <0x4d 0x80800000 0x00 0x00048000>,
1631                       <0x4d 0x80e00000 0x00 0x00008000>,
1632                       <0x4d 0x80f00000 0x00 0x00008000>;
1633                 reg-names = "l2sram", "l1pram", "l1dram";
1634                 ti,sci = <&dmsc>;
1635                 ti,sci-dev-id = <142>;
1636                 ti,sci-proc-ids = <0x03 0xff>;
1637                 resets = <&k3_reset 142 1>;
1638                 firmware-name = "j7-c66_0-fw";
1639         };
1640
1641         c66_1: dsp@4d81800000 {
1642                 compatible = "ti,j721e-c66-dsp";
1643                 reg = <0x4d 0x81800000 0x00 0x00048000>,
1644                       <0x4d 0x81e00000 0x00 0x00008000>,
1645                       <0x4d 0x81f00000 0x00 0x00008000>;
1646                 reg-names = "l2sram", "l1pram", "l1dram";
1647                 ti,sci = <&dmsc>;
1648                 ti,sci-dev-id = <143>;
1649                 ti,sci-proc-ids = <0x04 0xff>;
1650                 resets = <&k3_reset 143 1>;
1651                 firmware-name = "j7-c66_1-fw";
1652         };
1653
1654         c71_0: dsp@64800000 {
1655                 compatible = "ti,j721e-c71-dsp";
1656                 reg = <0x00 0x64800000 0x00 0x00080000>,
1657                       <0x00 0x64e00000 0x00 0x0000c000>;
1658                 reg-names = "l2sram", "l1dram";
1659                 ti,sci = <&dmsc>;
1660                 ti,sci-dev-id = <15>;
1661                 ti,sci-proc-ids = <0x30 0xff>;
1662                 resets = <&k3_reset 15 1>;
1663                 firmware-name = "j7-c71_0-fw";
1664         };
1665
1666         icssg0: icssg@b000000 {
1667                 compatible = "ti,j721e-icssg";
1668                 reg = <0x00 0xb000000 0x00 0x80000>;
1669                 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1670                 #address-cells = <1>;
1671                 #size-cells = <1>;
1672                 ranges = <0x0 0x00 0x0b000000 0x100000>;
1673
1674                 icssg0_mem: memories@0 {
1675                         reg = <0x0 0x2000>,
1676                               <0x2000 0x2000>,
1677                               <0x10000 0x10000>;
1678                         reg-names = "dram0", "dram1",
1679                                     "shrdram2";
1680                 };
1681
1682                 icssg0_cfg: cfg@26000 {
1683                         compatible = "ti,pruss-cfg", "syscon";
1684                         reg = <0x26000 0x200>;
1685                         #address-cells = <1>;
1686                         #size-cells = <1>;
1687                         ranges = <0x0 0x26000 0x2000>;
1688
1689                         clocks {
1690                                 #address-cells = <1>;
1691                                 #size-cells = <0>;
1692
1693                                 icssg0_coreclk_mux: coreclk-mux@3c {
1694                                         reg = <0x3c>;
1695                                         #clock-cells = <0>;
1696                                         clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
1697                                                  <&k3_clks 119 1>;  /* icssg0_iclk */
1698                                         assigned-clocks = <&icssg0_coreclk_mux>;
1699                                         assigned-clock-parents = <&k3_clks 119 1>;
1700                                 };
1701
1702                                 icssg0_iepclk_mux: iepclk-mux@30 {
1703                                         reg = <0x30>;
1704                                         #clock-cells = <0>;
1705                                         clocks = <&k3_clks 119 3>,      /* icssg0_iep_clk */
1706                                                  <&icssg0_coreclk_mux>; /* core_clk */
1707                                         assigned-clocks = <&icssg0_iepclk_mux>;
1708                                         assigned-clock-parents = <&icssg0_coreclk_mux>;
1709                                 };
1710                         };
1711                 };
1712
1713                 icssg0_mii_rt: mii-rt@32000 {
1714                         compatible = "ti,pruss-mii", "syscon";
1715                         reg = <0x32000 0x100>;
1716                 };
1717
1718                 icssg0_mii_g_rt: mii-g-rt@33000 {
1719                         compatible = "ti,pruss-mii-g", "syscon";
1720                         reg = <0x33000 0x1000>;
1721                 };
1722
1723                 icssg0_intc: interrupt-controller@20000 {
1724                         compatible = "ti,icssg-intc";
1725                         reg = <0x20000 0x2000>;
1726                         interrupt-controller;
1727                         #interrupt-cells = <3>;
1728                         interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1729                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1730                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1731                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1732                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1733                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1734                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1736                         interrupt-names = "host_intr0", "host_intr1",
1737                                           "host_intr2", "host_intr3",
1738                                           "host_intr4", "host_intr5",
1739                                           "host_intr6", "host_intr7";
1740                 };
1741
1742                 pru0_0: pru@34000 {
1743                         compatible = "ti,j721e-pru";
1744                         reg = <0x34000 0x3000>,
1745                               <0x22000 0x100>,
1746                               <0x22400 0x100>;
1747                         reg-names = "iram", "control", "debug";
1748                         firmware-name = "j7-pru0_0-fw";
1749                 };
1750
1751                 rtu0_0: rtu@4000 {
1752                         compatible = "ti,j721e-rtu";
1753                         reg = <0x4000 0x2000>,
1754                               <0x23000 0x100>,
1755                               <0x23400 0x100>;
1756                         reg-names = "iram", "control", "debug";
1757                         firmware-name = "j7-rtu0_0-fw";
1758                 };
1759
1760                 tx_pru0_0: txpru@a000 {
1761                         compatible = "ti,j721e-tx-pru";
1762                         reg = <0xa000 0x1800>,
1763                               <0x25000 0x100>,
1764                               <0x25400 0x100>;
1765                         reg-names = "iram", "control", "debug";
1766                         firmware-name = "j7-txpru0_0-fw";
1767                 };
1768
1769                 pru0_1: pru@38000 {
1770                         compatible = "ti,j721e-pru";
1771                         reg = <0x38000 0x3000>,
1772                               <0x24000 0x100>,
1773                               <0x24400 0x100>;
1774                         reg-names = "iram", "control", "debug";
1775                         firmware-name = "j7-pru0_1-fw";
1776                 };
1777
1778                 rtu0_1: rtu@6000 {
1779                         compatible = "ti,j721e-rtu";
1780                         reg = <0x6000 0x2000>,
1781                               <0x23800 0x100>,
1782                               <0x23c00 0x100>;
1783                         reg-names = "iram", "control", "debug";
1784                         firmware-name = "j7-rtu0_1-fw";
1785                 };
1786
1787                 tx_pru0_1: txpru@c000 {
1788                         compatible = "ti,j721e-tx-pru";
1789                         reg = <0xc000 0x1800>,
1790                               <0x25800 0x100>,
1791                               <0x25c00 0x100>;
1792                         reg-names = "iram", "control", "debug";
1793                         firmware-name = "j7-txpru0_1-fw";
1794                 };
1795         };
1796
1797         icssg1: icssg@b100000 {
1798                 compatible = "ti,j721e-icssg";
1799                 reg = <0x00 0xb100000 0x00 0x80000>;
1800                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1801                 #address-cells = <1>;
1802                 #size-cells = <1>;
1803                 ranges = <0x0 0x00 0x0b100000 0x100000>;
1804
1805                 icssg1_mem: memories@b100000 {
1806                         reg = <0x0 0x2000>,
1807                               <0x2000 0x2000>,
1808                               <0x10000 0x10000>;
1809                         reg-names = "dram0", "dram1",
1810                                     "shrdram2";
1811                 };
1812
1813                 icssg1_cfg: cfg@26000 {
1814                         compatible = "ti,pruss-cfg", "syscon";
1815                         reg = <0x26000 0x200>;
1816                         #address-cells = <1>;
1817                         #size-cells = <1>;
1818                         ranges = <0x0 0x26000 0x2000>;
1819
1820                         clocks {
1821                                 #address-cells = <1>;
1822                                 #size-cells = <0>;
1823
1824                                 icssg1_coreclk_mux: coreclk-mux@3c {
1825                                         reg = <0x3c>;
1826                                         #clock-cells = <0>;
1827                                         clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
1828                                                  <&k3_clks 120 4>;  /* icssg1_iclk */
1829                                         assigned-clocks = <&icssg1_coreclk_mux>;
1830                                         assigned-clock-parents = <&k3_clks 120 4>;
1831                                 };
1832
1833                                 icssg1_iepclk_mux: iepclk-mux@30 {
1834                                         reg = <0x30>;
1835                                         #clock-cells = <0>;
1836                                         clocks = <&k3_clks 120 9>,      /* icssg1_iep_clk */
1837                                                  <&icssg1_coreclk_mux>; /* core_clk */
1838                                         assigned-clocks = <&icssg1_iepclk_mux>;
1839                                         assigned-clock-parents = <&icssg1_coreclk_mux>;
1840                                 };
1841                         };
1842                 };
1843
1844                 icssg1_mii_rt: mii-rt@32000 {
1845                         compatible = "ti,pruss-mii", "syscon";
1846                         reg = <0x32000 0x100>;
1847                 };
1848
1849                 icssg1_mii_g_rt: mii-g-rt@33000 {
1850                         compatible = "ti,pruss-mii-g", "syscon";
1851                         reg = <0x33000 0x1000>;
1852                 };
1853
1854                 icssg1_intc: interrupt-controller@20000 {
1855                         compatible = "ti,icssg-intc";
1856                         reg = <0x20000 0x2000>;
1857                         interrupt-controller;
1858                         #interrupt-cells = <3>;
1859                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1860                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1861                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1862                                      <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1863                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1864                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1865                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1867                         interrupt-names = "host_intr0", "host_intr1",
1868                                           "host_intr2", "host_intr3",
1869                                           "host_intr4", "host_intr5",
1870                                           "host_intr6", "host_intr7";
1871                 };
1872
1873                 pru1_0: pru@34000 {
1874                         compatible = "ti,j721e-pru";
1875                         reg = <0x34000 0x4000>,
1876                               <0x22000 0x100>,
1877                               <0x22400 0x100>;
1878                         reg-names = "iram", "control", "debug";
1879                         firmware-name = "j7-pru1_0-fw";
1880                 };
1881
1882                 rtu1_0: rtu@4000 {
1883                         compatible = "ti,j721e-rtu";
1884                         reg = <0x4000 0x2000>,
1885                               <0x23000 0x100>,
1886                               <0x23400 0x100>;
1887                         reg-names = "iram", "control", "debug";
1888                         firmware-name = "j7-rtu1_0-fw";
1889                 };
1890
1891                 tx_pru1_0: txpru@a000 {
1892                         compatible = "ti,j721e-tx-pru";
1893                         reg = <0xa000 0x1800>,
1894                               <0x25000 0x100>,
1895                               <0x25400 0x100>;
1896                         reg-names = "iram", "control", "debug";
1897                         firmware-name = "j7-txpru1_0-fw";
1898                 };
1899
1900                 pru1_1: pru@38000 {
1901                         compatible = "ti,j721e-pru";
1902                         reg = <0x38000 0x4000>,
1903                               <0x24000 0x100>,
1904                               <0x24400 0x100>;
1905                         reg-names = "iram", "control", "debug";
1906                         firmware-name = "j7-pru1_1-fw";
1907                 };
1908
1909                 rtu1_1: rtu@6000 {
1910                         compatible = "ti,j721e-rtu";
1911                         reg = <0x6000 0x2000>,
1912                               <0x23800 0x100>,
1913                               <0x23c00 0x100>;
1914                         reg-names = "iram", "control", "debug";
1915                         firmware-name = "j7-rtu1_1-fw";
1916                 };
1917
1918                 tx_pru1_1: txpru@c000 {
1919                         compatible = "ti,j721e-tx-pru";
1920                         reg = <0xc000 0x1800>,
1921                               <0x25800 0x100>,
1922                               <0x25c00 0x100>;
1923                         reg-names = "iram", "control", "debug";
1924                         firmware-name = "j7-txpru1_1-fw";
1925                 };
1926         };
1927 };