arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         dmsc: system-controller@44083000 {
  10                 compatible = "ti,k2g-sci";
  11                 ti,host-id = <12>;
  12
  13                 mbox-names = "rx", "tx";
  14
  15                 mboxes= <&secure_proxy_main 11>,
  16                         <&secure_proxy_main 13>;
  17
  18                 reg-names = "debug_messages";
  19                 reg = <0x00 0x44083000 0x00 0x1000>;
  20
  21                 k3_pds: power-controller {
  22                         compatible = "ti,sci-pm-domain";
  23                         #power-domain-cells = <2>;
  24                 };
  25
  26                 k3_clks: clock-controller {
  27                         compatible = "ti,k2g-sci-clk";
  28                         #clock-cells = <2>;
  29                 };
  30
  31                 k3_reset: reset-controller {
  32                         compatible = "ti,sci-reset";
  33                         #reset-cells = <2>;
  34                 };
  35         };
  36
  37         mcu_conf: syscon@40f00000 {
  38                 compatible = "syscon", "simple-mfd";
  39                 reg = <0x00 0x40f00000 0x00 0x20000>;
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 ranges = <0x00 0x00 0x40f00000 0x20000>;
  43
  44                 phy_gmii_sel: phy@4040 {
  45                         compatible = "ti,am654-phy-gmii-sel";
  46                         reg = <0x4040 0x4>;
  47                         #phy-cells = <1>;
  48                 };
  49         };
  50
  51         chipid@43000014 {
  52                 compatible = "ti,am654-chipid";
  53                 reg = <0x00 0x43000014 0x00 0x4>;
  54         };
  55
  56         wkup_pmx0: pinctrl@4301c000 {
  57                 compatible = "pinctrl-single";
  58                 /* Proxy 0 addressing */
  59                 reg = <0x00 0x4301c000 0x00 0x178>;
  60                 #pinctrl-cells = <1>;
  61                 pinctrl-single,register-width = <32>;
  62                 pinctrl-single,function-mask = <0xffffffff>;
  63         };
  64
  65         mcu_ram: sram@41c00000 {
  66                 compatible = "mmio-sram";
  67                 reg = <0x00 0x41c00000 0x00 0x100000>;
  68                 ranges = <0x00 0x00 0x41c00000 0x100000>;
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71         };
  72
  73         wkup_uart0: serial@42300000 {
  74                 compatible = "ti,j721e-uart", "ti,am654-uart";
  75                 reg = <0x00 0x42300000 0x00 0x100>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <4>;
  78                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  79                 clock-frequency = <48000000>;
  80                 current-speed = <115200>;
  81                 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  82                 clocks = <&k3_clks 287 2>;
  83                 clock-names = "fclk";
  84         };
  85
  86         mcu_uart0: serial@40a00000 {
  87                 compatible = "ti,j721e-uart", "ti,am654-uart";
  88                 reg = <0x00 0x40a00000 0x00 0x100>;
  89                 reg-shift = <2>;
  90                 reg-io-width = <4>;
  91                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  92                 clock-frequency = <96000000>;
  93                 current-speed = <115200>;
  94                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  95                 clocks = <&k3_clks 149 2>;
  96                 clock-names = "fclk";
  97         };
  98
  99         wkup_gpio_intr: interrupt-controller@42200000 {
 100                 compatible = "ti,sci-intr";
 101                 reg = <0x00 0x42200000 0x00 0x400>;
 102                 ti,intr-trigger-type = <1>;
 103                 interrupt-controller;
 104                 interrupt-parent = <&gic500>;
 105                 #interrupt-cells = <1>;
 106                 ti,sci = <&dmsc>;
 107                 ti,sci-dev-id = <137>;
 108                 ti,interrupt-ranges = <16 960 16>;
 109         };
 110
 111         wkup_gpio0: gpio@42110000 {
 112                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 113                 reg = <0x00 0x42110000 0x00 0x100>;
 114                 gpio-controller;
 115                 #gpio-cells = <2>;
 116                 interrupt-parent = <&wkup_gpio_intr>;
 117                 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
 118                 interrupt-controller;
 119                 #interrupt-cells = <2>;
 120                 #address-cells = <0>;
 121                 ti,ngpio = <85>;
 122                 ti,davinci-gpio-unbanked = <0>;
 123                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 124                 clocks = <&k3_clks 113 0>;
 125                 clock-names = "gpio";
 126         };
 127
 128         wkup_gpio1: gpio@42100000 {
 129                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 130                 reg = <0x00 0x42100000 0x00 0x100>;
 131                 gpio-controller;
 132                 #gpio-cells = <2>;
 133                 interrupt-parent = <&wkup_gpio_intr>;
 134                 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
 135                 interrupt-controller;
 136                 #interrupt-cells = <2>;
 137                 #address-cells = <0>;
 138                 ti,ngpio = <85>;
 139                 ti,davinci-gpio-unbanked = <0>;
 140                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 141                 clocks = <&k3_clks 114 0>;
 142                 clock-names = "gpio";
 143         };
 144
 145         mcu_navss: bus@28380000 {
 146                 compatible = "simple-mfd";
 147                 #address-cells = <2>;
 148                 #size-cells = <2>;
 149                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 150                 dma-coherent;
 151                 dma-ranges;
 152                 ti,sci-dev-id = <232>;
 153
 154                 mcu_ringacc: ringacc@2b800000 {
 155                         compatible = "ti,am654-navss-ringacc";
 156                         reg =   <0x00 0x2b800000 0x00 0x400000>,
 157                                 <0x00 0x2b000000 0x00 0x400000>,
 158                                 <0x00 0x28590000 0x00 0x100>,
 159                                 <0x00 0x2a500000 0x00 0x40000>;
 160                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 161                         ti,num-rings = <286>;
 162                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 163                         ti,sci = <&dmsc>;
 164                         ti,sci-dev-id = <235>;
 165                         msi-parent = <&main_udmass_inta>;
 166                 };
 167
 168                 mcu_udmap: dma-controller@285c0000 {
 169                         compatible = "ti,j721e-navss-mcu-udmap";
 170                         reg =   <0x00 0x285c0000 0x00 0x100>,
 171                                 <0x00 0x2a800000 0x00 0x40000>,
 172                                 <0x00 0x2aa00000 0x00 0x40000>;
 173                         reg-names = "gcfg", "rchanrt", "tchanrt";
 174                         msi-parent = <&main_udmass_inta>;
 175                         #dma-cells = <1>;
 176
 177                         ti,sci = <&dmsc>;
 178                         ti,sci-dev-id = <236>;
 179                         ti,ringacc = <&mcu_ringacc>;
 180
 181                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 182                                                 <0x0f>; /* TX_HCHAN */
 183                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 184                                                 <0x0b>; /* RX_HCHAN */
 185                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 186                 };
 187         };
 188
 189         mcu_cpsw: ethernet@46000000 {
 190                 compatible = "ti,j721e-cpsw-nuss";
 191                 #address-cells = <2>;
 192                 #size-cells = <2>;
 193                 reg = <0x00 0x46000000 0x00 0x200000>;
 194                 reg-names = "cpsw_nuss";
 195                 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
 196                 dma-coherent;
 197                 clocks = <&k3_clks 18 21>;
 198                 clock-names = "fck";
 199                 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
 200
 201                 dmas = <&mcu_udmap 0xf000>,
 202                        <&mcu_udmap 0xf001>,
 203                        <&mcu_udmap 0xf002>,
 204                        <&mcu_udmap 0xf003>,
 205                        <&mcu_udmap 0xf004>,
 206                        <&mcu_udmap 0xf005>,
 207                        <&mcu_udmap 0xf006>,
 208                        <&mcu_udmap 0xf007>,
 209                        <&mcu_udmap 0x7000>;
 210                 dma-names = "tx0", "tx1", "tx2", "tx3",
 211                             "tx4", "tx5", "tx6", "tx7",
 212                             "rx";
 213
 214                 ethernet-ports {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217
 218                         cpsw_port1: port@1 {
 219                                 reg = <1>;
 220                                 ti,mac-only;
 221                                 label = "port1";
 222                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 223                                 phys = <&phy_gmii_sel 1>;
 224                         };
 225                 };
 226
 227                 davinci_mdio: mdio@f00 {
 228                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 229                         reg = <0x00 0xf00 0x00 0x100>;
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         clocks = <&k3_clks 18 21>;
 233                         clock-names = "fck";
 234                         bus_freq = <1000000>;
 235                 };
 236
 237                 cpts@3d000 {
 238                         compatible = "ti,am65-cpts";
 239                         reg = <0x00 0x3d000 0x00 0x400>;
 240                         clocks = <&k3_clks 18 2>;
 241                         clock-names = "cpts";
 242                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 243                         interrupt-names = "cpts";
 244                         ti,cpts-ext-ts-inputs = <4>;
 245                         ti,cpts-periodic-outputs = <2>;
 246                 };
 247         };
 248
 249         mcu_i2c0: i2c@40b00000 {
 250                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 251                 reg = <0x00 0x40b00000 0x00 0x100>;
 252                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 clock-names = "fck";
 256                 clocks = <&k3_clks 194 1>;
 257                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 258         };
 259
 260         mcu_i2c1: i2c@40b10000 {
 261                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 262                 reg = <0x00 0x40b10000 0x00 0x100>;
 263                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 clock-names = "fck";
 267                 clocks = <&k3_clks 195 1>;
 268                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
 269         };
 270
 271         wkup_i2c0: i2c@42120000 {
 272                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 273                 reg = <0x00 0x42120000 0x00 0x100>;
 274                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clock-names = "fck";
 278                 clocks = <&k3_clks 197 1>;
 279                 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
 280         };
 281
 282         fss: syscon@47000000 {
 283                 compatible = "syscon", "simple-mfd";
 284                 reg = <0x00 0x47000000 0x00 0x100>;
 285                 #address-cells = <2>;
 286                 #size-cells = <2>;
 287                 ranges;
 288
 289                 hbmc_mux: hbmc-mux {
 290                         compatible = "mmio-mux";
 291                         #mux-control-cells = <1>;
 292                         mux-reg-masks = <0x4 0x2>; /* HBMC select */
 293                 };
 294
 295                 hbmc: hyperbus@47034000 {
 296                         compatible = "ti,am654-hbmc";
 297                         reg = <0x00 0x47034000 0x00 0x100>,
 298                                 <0x05 0x00000000 0x01 0x0000000>;
 299                         power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 300                         clocks = <&k3_clks 102 0>;
 301                         assigned-clocks = <&k3_clks 102 5>;
 302                         assigned-clock-rates = <333333333>;
 303                         #address-cells = <2>;
 304                         #size-cells = <1>;
 305                         mux-controls = <&hbmc_mux 0>;
 306                 };
 307
 308                 ospi0: spi@47040000 {
 309                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 310                         reg = <0x0 0x47040000 0x0 0x100>,
 311                               <0x5 0x00000000 0x1 0x0000000>;
 312                         interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 313                         cdns,fifo-depth = <256>;
 314                         cdns,fifo-width = <4>;
 315                         cdns,trigger-address = <0x0>;
 316                         clocks = <&k3_clks 103 0>;
 317                         assigned-clocks = <&k3_clks 103 0>;
 318                         assigned-clock-parents = <&k3_clks 103 2>;
 319                         assigned-clock-rates = <166666666>;
 320                         power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                 };
 324         };
 325
 326         tscadc0: tscadc@40200000 {
 327                 compatible = "ti,am3359-tscadc";
 328                 reg = <0x00 0x40200000 0x00 0x1000>;
 329                 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 330                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 331                 clocks = <&k3_clks 0 1>;
 332                 assigned-clocks = <&k3_clks 0 3>;
 333                 assigned-clock-rates = <60000000>;
 334                 clock-names = "adc_tsc_fck";
 335                 dmas = <&main_udmap 0x7400>,
 336                         <&main_udmap 0x7401>;
 337                 dma-names = "fifo0", "fifo1";
 338
 339                 adc {
 340                         #io-channel-cells = <1>;
 341                         compatible = "ti,am3359-adc";
 342                 };
 343         };
 344
 345         mcu_r5fss0: r5fss@41000000 {
 346                 compatible = "ti,j7200-r5fss";
 347                 ti,cluster-mode = <1>;
 348                 #address-cells = <1>;
 349                 #size-cells = <1>;
 350                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 351                          <0x41400000 0x00 0x41400000 0x20000>;
 352                 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 353
 354                 mcu_r5fss0_core0: r5f@41000000 {
 355                         compatible = "ti,j7200-r5f";
 356                         reg = <0x41000000 0x00010000>,
 357                               <0x41010000 0x00010000>;
 358                         reg-names = "atcm", "btcm";
 359                         ti,sci = <&dmsc>;
 360                         ti,sci-dev-id = <250>;
 361                         ti,sci-proc-ids = <0x01 0xff>;
 362                         resets = <&k3_reset 250 1>;
 363                         firmware-name = "j7200-mcu-r5f0_0-fw";
 364                         ti,atcm-enable = <1>;
 365                         ti,btcm-enable = <1>;
 366                         ti,loczrama = <1>;
 367                 };
 368
 369                 mcu_r5fss0_core1: r5f@41400000 {
 370                         compatible = "ti,j7200-r5f";
 371                         reg = <0x41400000 0x00008000>,
 372                               <0x41410000 0x00008000>;
 373                         reg-names = "atcm", "btcm";
 374                         ti,sci = <&dmsc>;
 375                         ti,sci-dev-id = <251>;
 376                         ti,sci-proc-ids = <0x02 0xff>;
 377                         resets = <&k3_reset 251 1>;
 378                         firmware-name = "j7200-mcu-r5f0_1-fw";
 379                         ti,atcm-enable = <1>;
 380                         ti,btcm-enable = <1>;
 381                         ti,loczrama = <1>;
 382                 };
 383         };
 384 };