1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/mux/ti-serdes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-am642.dtsi"
16 compatible = "ti,am642-evm", "ti,am642";
17 model = "Texas Instruments AM642 EVM";
20 stdout-path = "serial2:115200n8";
21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
25 device_type = "memory";
27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
36 secure_ddr: optee@9e800000 {
37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
43 compatible = "shared-dma-pool";
44 reg = <0x00 0xa0000000 0x00 0x100000>;
48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
49 compatible = "shared-dma-pool";
50 reg = <0x00 0xa0100000 0x00 0xf00000>;
54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
55 compatible = "shared-dma-pool";
56 reg = <0x00 0xa1000000 0x00 0x100000>;
60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
61 compatible = "shared-dma-pool";
62 reg = <0x00 0xa1100000 0x00 0xf00000>;
66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
67 compatible = "shared-dma-pool";
68 reg = <0x00 0xa2000000 0x00 0x100000>;
72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
73 compatible = "shared-dma-pool";
74 reg = <0x00 0xa2100000 0x00 0xf00000>;
78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
79 compatible = "shared-dma-pool";
80 reg = <0x00 0xa3000000 0x00 0x100000>;
84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
85 compatible = "shared-dma-pool";
86 reg = <0x00 0xa3100000 0x00 0xf00000>;
90 rtos_ipc_memory_region: ipc-memories@a5000000 {
91 reg = <0x00 0xa5000000 0x00 0x00800000>;
97 evm_12v0: fixedregulator-evm12v0 {
99 compatible = "regulator-fixed";
100 regulator-name = "evm_12v0";
101 regulator-min-microvolt = <12000000>;
102 regulator-max-microvolt = <12000000>;
107 vsys_5v0: fixedregulator-vsys5v0 {
108 /* output of LM5140 */
109 compatible = "regulator-fixed";
110 regulator-name = "vsys_5v0";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 vin-supply = <&evm_12v0>;
118 vsys_3v3: fixedregulator-vsys3v3 {
119 /* output of LM5140 */
120 compatible = "regulator-fixed";
121 regulator-name = "vsys_3v3";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 vin-supply = <&evm_12v0>;
129 vdd_mmc1: fixed-regulator-sd {
131 compatible = "regulator-fixed";
132 regulator-name = "vdd_mmc1";
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
137 vin-supply = <&vsys_3v3>;
138 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
141 vddb: fixedregulator-vddb {
142 compatible = "regulator-fixed";
143 regulator-name = "vddb_3v3_display";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 vin-supply = <&vsys_3v3>;
152 compatible = "gpio-leds";
155 label = "am64-evm:red:heartbeat";
156 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
157 linux,default-trigger = "heartbeat";
158 function = LED_FUNCTION_HEARTBEAT;
159 default-state = "off";
163 mdio_mux: mux-controller {
164 compatible = "gpio-mux";
165 #mux-control-cells = <0>;
167 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
171 compatible = "mdio-mux-multiplexer";
172 mux-controls = <&mdio_mux>;
173 mdio-parent-bus = <&cpsw3g_mdio>;
174 #address-cells = <1>;
179 #address-cells = <1>;
182 cpsw3g_phy3: ethernet-phy@3 {
190 main_mmc1_pins_default: main-mmc1-pins-default {
191 pinctrl-single,pins = <
192 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
193 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
194 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
195 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
196 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
197 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
198 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
199 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
200 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
204 main_uart0_pins_default: main-uart0-pins-default {
205 pinctrl-single,pins = <
206 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
207 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
208 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
209 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
213 main_spi0_pins_default: main-spi0-pins-default {
214 pinctrl-single,pins = <
215 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
216 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
217 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
218 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
222 main_i2c1_pins_default: main-i2c1-pins-default {
223 pinctrl-single,pins = <
224 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
225 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
229 mdio1_pins_default: mdio1-pins-default {
230 pinctrl-single,pins = <
231 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
232 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
236 rgmii1_pins_default: rgmii1-pins-default {
237 pinctrl-single,pins = <
238 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
239 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
240 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
241 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
242 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
243 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
244 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
245 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
246 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
247 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
248 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
249 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
253 rgmii2_pins_default: rgmii2-pins-default {
254 pinctrl-single,pins = <
255 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
256 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
257 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
258 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
259 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
260 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
261 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
262 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
263 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
264 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
265 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
266 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
270 main_usb0_pins_default: main-usb0-pins-default {
271 pinctrl-single,pins = <
272 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
276 ospi0_pins_default: ospi0-pins-default {
277 pinctrl-single,pins = <
278 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
279 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
280 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
281 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
282 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
283 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
284 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
285 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
286 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
287 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
288 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
292 main_ecap0_pins_default: main-ecap0-pins-default {
293 pinctrl-single,pins = <
294 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
300 pinctrl-names = "default";
301 pinctrl-0 = <&main_uart0_pins_default>;
304 /* main_uart1 is reserved for firmware usage */
338 pinctrl-names = "default";
339 pinctrl-0 = <&main_i2c1_pins_default>;
340 clock-frequency = <400000>;
343 compatible = "ti,tca6424";
347 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
348 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
349 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
350 "MMC1_SD_EN", "FSI_FET_SEL",
351 "MCAN0_STB_3V3", "MCAN1_STB_3V3",
352 "CPSW_FET_SEL", "CPSW_FET2_SEL",
353 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
354 "GPIO_OLED_RESETn", "VPP_LDO_EN",
355 "TEST_LED1", "TP92", "TP90", "TP88",
356 "TP87", "TP86", "TP89", "TP91";
359 /* osd9616p0899-10 */
361 compatible = "solomon,ssd1306fb-i2c";
363 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
364 vbat-supply = <&vddb>;
365 solomon,height = <16>;
366 solomon,width = <96>;
369 solomon,page-offset = <0>;
370 solomon,prechargep1 = <2>;
371 solomon,prechargep2 = <13>;
375 /* mcu_gpio0 is reserved for mcu firmware usage */
397 pinctrl-names = "default";
398 pinctrl-0 = <&main_spi0_pins_default>;
399 ti,pindir-d0-out-d1-in;
401 compatible = "microchip,93lc46b";
403 spi-max-frequency = <1000000>;
413 ti,driver-strength-ohm = <50>;
419 vmmc-supply = <&vdd_mmc1>;
420 pinctrl-names = "default";
422 pinctrl-0 = <&main_mmc1_pins_default>;
423 ti,driver-strength-ohm = <50>;
434 maximum-speed = "high-speed";
435 pinctrl-names = "default";
436 pinctrl-0 = <&main_usb0_pins_default>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&mdio1_pins_default
443 &rgmii2_pins_default>;
447 phy-mode = "rgmii-rxid";
448 phy-handle = <&cpsw3g_phy0>;
452 phy-mode = "rgmii-rxid";
453 phy-handle = <&cpsw3g_phy3>;
457 cpsw3g_phy0: ethernet-phy@0 {
459 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
460 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
465 /* ADC is reserved for R5 usage */
470 pinctrl-names = "default";
471 pinctrl-0 = <&ospi0_pins_default>;
474 compatible = "jedec,spi-nor";
476 spi-tx-bus-width = <8>;
477 spi-rx-bus-width = <8>;
478 spi-max-frequency = <25000000>;
479 cdns,tshsl-ns = <60>;
480 cdns,tsd2d-ns = <60>;
481 cdns,tchsh-ns = <60>;
482 cdns,tslch-ns = <60>;
483 cdns,read-delay = <4>;
484 #address-cells = <1>;
490 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
491 ti,mbox-rx = <0 0 2>;
492 ti,mbox-tx = <1 0 2>;
495 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
496 ti,mbox-rx = <2 0 2>;
497 ti,mbox-tx = <3 0 2>;
506 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
507 ti,mbox-rx = <0 0 2>;
508 ti,mbox-tx = <1 0 2>;
511 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
512 ti,mbox-rx = <2 0 2>;
513 ti,mbox-tx = <3 0 2>;
522 mbox_m4_0: mbox-m4-0 {
523 ti,mbox-rx = <0 0 2>;
524 ti,mbox-tx = <1 0 2>;
533 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
534 memory-region = <&main_r5fss0_core0_dma_memory_region>,
535 <&main_r5fss0_core0_memory_region>;
539 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
540 memory-region = <&main_r5fss0_core1_dma_memory_region>,
541 <&main_r5fss0_core1_memory_region>;
545 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
546 memory-region = <&main_r5fss1_core0_dma_memory_region>,
547 <&main_r5fss1_core0_memory_region>;
551 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
552 memory-region = <&main_r5fss1_core1_dma_memory_region>,
553 <&main_r5fss1_core1_memory_region>;
557 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
561 serdes0_pcie_link: phy@0 {
563 cdns,num-lanes = <1>;
565 cdns,phy-type = <PHY_TYPE_PCIE>;
566 resets = <&serdes_wiz0 1>;
571 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
572 phys = <&serdes0_pcie_link>;
573 phy-names = "pcie-phy";
578 phys = <&serdes0_pcie_link>;
579 phy-names = "pcie-phy";
585 /* PWM is available on Pin 1 of header J12 */
586 pinctrl-names = "default";
587 pinctrl-0 = <&main_ecap0_pins_default>;