arch/arm64/boot/dts/ti/k3-am64-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM642 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/phy/phy-cadence.h>
   9 #include <dt-bindings/phy/phy-ti.h>
  10
  11 / {
  12         serdes_refclk: clock-cmnrefclk {
  13                 #clock-cells = <0>;
  14                 compatible = "fixed-clock";
  15                 clock-frequency = <0>;
  16         };
  17 };
  18
  19 &cbass_main {
  20         oc_sram: sram@70000000 {
  21                 compatible = "mmio-sram";
  22                 reg = <0x00 0x70000000 0x00 0x200000>;
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges = <0x0 0x00 0x70000000 0x200000>;
  26
  27                 tfa-sram@1c0000 {
  28                         reg = <0x1c0000 0x20000>;
  29                 };
  30
  31                 dmsc-sram@1e0000 {
  32                         reg = <0x1e0000 0x1c000>;
  33                 };
  34
  35                 sproxy-sram@1fc000 {
  36                         reg = <0x1fc000 0x4000>;
  37                 };
  38         };
  39
  40         main_conf: syscon@43000000 {
  41                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  42                 reg = <0x0 0x43000000 0x0 0x20000>;
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 ranges = <0x0 0x0 0x43000000 0x20000>;
  46
  47                 serdes_ln_ctrl: mux-controller {
  48                         compatible = "mmio-mux";
  49                         #mux-control-cells = <1>;
  50                         mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
  51                 };
  52         };
  53
  54         gic500: interrupt-controller@1800000 {
  55                 compatible = "arm,gic-v3";
  56                 #address-cells = <2>;
  57                 #size-cells = <2>;
  58                 ranges;
  59                 #interrupt-cells = <3>;
  60                 interrupt-controller;
  61                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  62                       <0x00 0x01840000 0x00 0xC0000>;   /* GICR */
  63                 /*
  64                  * vcpumntirq:
  65                  * virtual CPU interface maintenance interrupt
  66                  */
  67                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  68
  69                 gic_its: msi-controller@1820000 {
  70                         compatible = "arm,gic-v3-its";
  71                         reg = <0x00 0x01820000 0x00 0x10000>;
  72                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  73                         msi-controller;
  74                         #msi-cells = <1>;
  75                 };
  76         };
  77
  78         dmss: bus@48000000 {
  79                 compatible = "simple-mfd";
  80                 #address-cells = <2>;
  81                 #size-cells = <2>;
  82                 dma-ranges;
  83                 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
  84
  85                 ti,sci-dev-id = <25>;
  86
  87                 secure_proxy_main: mailbox@4d000000 {
  88                         compatible = "ti,am654-secure-proxy";
  89                         #mbox-cells = <1>;
  90                         reg-names = "target_data", "rt", "scfg";
  91                         reg = <0x00 0x4d000000 0x00 0x80000>,
  92                               <0x00 0x4a600000 0x00 0x80000>,
  93                               <0x00 0x4a400000 0x00 0x80000>;
  94                         interrupt-names = "rx_012";
  95                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  96                 };
  97
  98                 inta_main_dmss: interrupt-controller@48000000 {
  99                         compatible = "ti,sci-inta";
 100                         reg = <0x00 0x48000000 0x00 0x100000>;
 101                         #interrupt-cells = <0>;
 102                         interrupt-controller;
 103                         interrupt-parent = <&gic500>;
 104                         msi-controller;
 105                         ti,sci = <&dmsc>;
 106                         ti,sci-dev-id = <28>;
 107                         ti,interrupt-ranges = <4 68 36>;
 108                         ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
 109                 };
 110
 111                 main_bcdma: dma-controller@485c0100 {
 112                         compatible = "ti,am64-dmss-bcdma";
 113                         reg = <0x00 0x485c0100 0x00 0x100>,
 114                               <0x00 0x4c000000 0x00 0x20000>,
 115                               <0x00 0x4a820000 0x00 0x20000>,
 116                               <0x00 0x4aa40000 0x00 0x20000>,
 117                               <0x00 0x4bc00000 0x00 0x100000>;
 118                         reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
 119                         msi-parent = <&inta_main_dmss>;
 120                         #dma-cells = <3>;
 121
 122                         ti,sci = <&dmsc>;
 123                         ti,sci-dev-id = <26>;
 124                         ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
 125                         ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
 126                         ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
 127                 };
 128
 129                 main_pktdma: dma-controller@485c0000 {
 130                         compatible = "ti,am64-dmss-pktdma";
 131                         reg = <0x00 0x485c0000 0x00 0x100>,
 132                               <0x00 0x4a800000 0x00 0x20000>,
 133                               <0x00 0x4aa00000 0x00 0x40000>,
 134                               <0x00 0x4b800000 0x00 0x400000>;
 135                         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
 136                         msi-parent = <&inta_main_dmss>;
 137                         #dma-cells = <2>;
 138
 139                         ti,sci = <&dmsc>;
 140                         ti,sci-dev-id = <30>;
 141                         ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 142                                                 <0x24>, /* CPSW_TX_CHAN */
 143                                                 <0x25>, /* SAUL_TX_0_CHAN */
 144                                                 <0x26>, /* SAUL_TX_1_CHAN */
 145                                                 <0x27>, /* ICSSG_0_TX_CHAN */
 146                                                 <0x28>; /* ICSSG_1_TX_CHAN */
 147                         ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 148                                                 <0x11>, /* RING_CPSW_TX_CHAN */
 149                                                 <0x12>, /* RING_SAUL_TX_0_CHAN */
 150                                                 <0x13>, /* RING_SAUL_TX_1_CHAN */
 151                                                 <0x14>, /* RING_ICSSG_0_TX_CHAN */
 152                                                 <0x15>; /* RING_ICSSG_1_TX_CHAN */
 153                         ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 154                                                 <0x2b>, /* CPSW_RX_CHAN */
 155                                                 <0x2d>, /* SAUL_RX_0_CHAN */
 156                                                 <0x2f>, /* SAUL_RX_1_CHAN */
 157                                                 <0x31>, /* SAUL_RX_2_CHAN */
 158                                                 <0x33>, /* SAUL_RX_3_CHAN */
 159                                                 <0x35>, /* ICSSG_0_RX_CHAN */
 160                                                 <0x37>; /* ICSSG_1_RX_CHAN */
 161                         ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 162                                                 <0x2c>, /* FLOW_CPSW_RX_CHAN */
 163                                                 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 164                                                 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
 165                                                 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
 166                                                 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
 167                 };
 168         };
 169
 170         dmsc: system-controller@44043000 {
 171                 compatible = "ti,k2g-sci";
 172                 ti,host-id = <12>;
 173                 mbox-names = "rx", "tx";
 174                 mboxes= <&secure_proxy_main 12>,
 175                         <&secure_proxy_main 13>;
 176                 reg-names = "debug_messages";
 177                 reg = <0x00 0x44043000 0x00 0xfe0>;
 178
 179                 k3_pds: power-controller {
 180                         compatible = "ti,sci-pm-domain";
 181                         #power-domain-cells = <2>;
 182                 };
 183
 184                 k3_clks: clock-controller {
 185                         compatible = "ti,k2g-sci-clk";
 186                         #clock-cells = <2>;
 187                 };
 188
 189                 k3_reset: reset-controller {
 190                         compatible = "ti,sci-reset";
 191                         #reset-cells = <2>;
 192                 };
 193         };
 194
 195         main_pmx0: pinctrl@f4000 {
 196                 compatible = "pinctrl-single";
 197                 reg = <0x00 0xf4000 0x00 0x2d0>;
 198                 #pinctrl-cells = <1>;
 199                 pinctrl-single,register-width = <32>;
 200                 pinctrl-single,function-mask = <0xffffffff>;
 201         };
 202
 203         main_conf: syscon@43000000 {
 204                 compatible = "syscon", "simple-mfd";
 205                 reg = <0x00 0x43000000 0x00 0x20000>;
 206                 #address-cells = <1>;
 207                 #size-cells = <1>;
 208                 ranges = <0x00 0x00 0x43000000 0x20000>;
 209
 210                 chipid@14 {
 211                         compatible = "ti,am654-chipid";
 212                         reg = <0x00000014 0x4>;
 213                 };
 214
 215                 phy_gmii_sel: phy@4044 {
 216                         compatible = "ti,am654-phy-gmii-sel";
 217                         reg = <0x4044 0x8>;
 218                         #phy-cells = <1>;
 219                 };
 220
 221                 epwm_tbclk: clock@4140 {
 222                         compatible = "ti,am64-epwm-tbclk", "syscon";
 223                         reg = <0x4130 0x4>;
 224                         #clock-cells = <1>;
 225                 };
 226         };
 227
 228         main_uart0: serial@2800000 {
 229                 compatible = "ti,am64-uart", "ti,am654-uart";
 230                 reg = <0x00 0x02800000 0x00 0x100>;
 231                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 232                 clock-frequency = <48000000>;
 233                 current-speed = <115200>;
 234                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 235                 clocks = <&k3_clks 146 0>;
 236                 clock-names = "fclk";
 237         };
 238
 239         main_uart1: serial@2810000 {
 240                 compatible = "ti,am64-uart", "ti,am654-uart";
 241                 reg = <0x00 0x02810000 0x00 0x100>;
 242                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 243                 clock-frequency = <48000000>;
 244                 current-speed = <115200>;
 245                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 246                 clocks = <&k3_clks 152 0>;
 247                 clock-names = "fclk";
 248         };
 249
 250         main_uart2: serial@2820000 {
 251                 compatible = "ti,am64-uart", "ti,am654-uart";
 252                 reg = <0x00 0x02820000 0x00 0x100>;
 253                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 254                 clock-frequency = <48000000>;
 255                 current-speed = <115200>;
 256                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
 257                 clocks = <&k3_clks 153 0>;
 258                 clock-names = "fclk";
 259         };
 260
 261         main_uart3: serial@2830000 {
 262                 compatible = "ti,am64-uart", "ti,am654-uart";
 263                 reg = <0x00 0x02830000 0x00 0x100>;
 264                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
 265                 clock-frequency = <48000000>;
 266                 current-speed = <115200>;
 267                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 268                 clocks = <&k3_clks 154 0>;
 269                 clock-names = "fclk";
 270         };
 271
 272         main_uart4: serial@2840000 {
 273                 compatible = "ti,am64-uart", "ti,am654-uart";
 274                 reg = <0x00 0x02840000 0x00 0x100>;
 275                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 276                 clock-frequency = <48000000>;
 277                 current-speed = <115200>;
 278                 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
 279                 clocks = <&k3_clks 155 0>;
 280                 clock-names = "fclk";
 281         };
 282
 283         main_uart5: serial@2850000 {
 284                 compatible = "ti,am64-uart", "ti,am654-uart";
 285                 reg = <0x00 0x02850000 0x00 0x100>;
 286                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 287                 clock-frequency = <48000000>;
 288                 current-speed = <115200>;
 289                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 290                 clocks = <&k3_clks 156 0>;
 291                 clock-names = "fclk";
 292         };
 293
 294         main_uart6: serial@2860000 {
 295                 compatible = "ti,am64-uart", "ti,am654-uart";
 296                 reg = <0x00 0x02860000 0x00 0x100>;
 297                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 298                 clock-frequency = <48000000>;
 299                 current-speed = <115200>;
 300                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 301                 clocks = <&k3_clks 158 0>;
 302                 clock-names = "fclk";
 303         };
 304
 305         main_i2c0: i2c@20000000 {
 306                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 307                 reg = <0x00 0x20000000 0x00 0x100>;
 308                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 312                 clocks = <&k3_clks 102 2>;
 313                 clock-names = "fck";
 314         };
 315
 316         main_i2c1: i2c@20010000 {
 317                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 318                 reg = <0x00 0x20010000 0x00 0x100>;
 319                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 323                 clocks = <&k3_clks 103 2>;
 324                 clock-names = "fck";
 325         };
 326
 327         main_i2c2: i2c@20020000 {
 328                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 329                 reg = <0x00 0x20020000 0x00 0x100>;
 330                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 334                 clocks = <&k3_clks 104 2>;
 335                 clock-names = "fck";
 336         };
 337
 338         main_i2c3: i2c@20030000 {
 339                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 340                 reg = <0x00 0x20030000 0x00 0x100>;
 341                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 345                 clocks = <&k3_clks 105 2>;
 346                 clock-names = "fck";
 347         };
 348
 349         main_spi0: spi@20100000 {
 350                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 351                 reg = <0x00 0x20100000 0x00 0x400>;
 352                 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 356                 clocks = <&k3_clks 141 0>;
 357                 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
 358                 dma-names = "tx0", "rx0";
 359         };
 360
 361         main_spi1: spi@20110000 {
 362                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 363                 reg = <0x00 0x20110000 0x00 0x400>;
 364                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
 368                 clocks = <&k3_clks 142 0>;
 369         };
 370
 371         main_spi2: spi@20120000 {
 372                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 373                 reg = <0x00 0x20120000 0x00 0x400>;
 374                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
 378                 clocks = <&k3_clks 143 0>;
 379         };
 380
 381         main_spi3: spi@20130000 {
 382                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 383                 reg = <0x00 0x20130000 0x00 0x400>;
 384                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
 388                 clocks = <&k3_clks 144 0>;
 389         };
 390
 391         main_spi4: spi@20140000 {
 392                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 393                 reg = <0x00 0x20140000 0x00 0x400>;
 394                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
 398                 clocks = <&k3_clks 145 0>;
 399         };
 400
 401         main_gpio_intr: interrupt-controller@a00000 {
 402                 compatible = "ti,sci-intr";
 403                 reg = <0x00 0x00a00000 0x00 0x800>;
 404                 ti,intr-trigger-type = <1>;
 405                 interrupt-controller;
 406                 interrupt-parent = <&gic500>;
 407                 #interrupt-cells = <1>;
 408                 ti,sci = <&dmsc>;
 409                 ti,sci-dev-id = <3>;
 410                 ti,interrupt-ranges = <0 32 16>;
 411         };
 412
 413         main_gpio0: gpio@600000 {
 414                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 415                 reg = <0x0 0x00600000 0x0 0x100>;
 416                 gpio-controller;
 417                 #gpio-cells = <2>;
 418                 interrupt-parent = <&main_gpio_intr>;
 419                 interrupts = <190>, <191>, <192>,
 420                              <193>, <194>, <195>;
 421                 interrupt-controller;
 422                 #interrupt-cells = <2>;
 423                 ti,ngpio = <87>;
 424                 ti,davinci-gpio-unbanked = <0>;
 425                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 426                 clocks = <&k3_clks 77 0>;
 427                 clock-names = "gpio";
 428         };
 429
 430         main_gpio1: gpio@601000 {
 431                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 432                 reg = <0x0 0x00601000 0x0 0x100>;
 433                 gpio-controller;
 434                 #gpio-cells = <2>;
 435                 interrupt-parent = <&main_gpio_intr>;
 436                 interrupts = <180>, <181>, <182>,
 437                              <183>, <184>, <185>;
 438                 interrupt-controller;
 439                 #interrupt-cells = <2>;
 440                 ti,ngpio = <88>;
 441                 ti,davinci-gpio-unbanked = <0>;
 442                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 443                 clocks = <&k3_clks 78 0>;
 444                 clock-names = "gpio";
 445         };
 446
 447         sdhci0: mmc@fa10000 {
 448                 compatible = "ti,am64-sdhci-8bit";
 449                 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
 450                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 451                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
 452                 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
 453                 clock-names = "clk_ahb", "clk_xin";
 454                 mmc-ddr-1_8v;
 455                 mmc-hs200-1_8v;
 456                 mmc-hs400-1_8v;
 457                 ti,trm-icp = <0x2>;
 458                 ti,otap-del-sel-legacy = <0x0>;
 459                 ti,otap-del-sel-mmc-hs = <0x0>;
 460                 ti,otap-del-sel-ddr52 = <0x6>;
 461                 ti,otap-del-sel-hs200 = <0x7>;
 462                 ti,otap-del-sel-hs400 = <0x4>;
 463         };
 464
 465         sdhci1: mmc@fa00000 {
 466                 compatible = "ti,am64-sdhci-4bit";
 467                 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
 468                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 469                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
 470                 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
 471                 clock-names = "clk_ahb", "clk_xin";
 472                 ti,trm-icp = <0x2>;
 473                 ti,otap-del-sel-legacy = <0x0>;
 474                 ti,otap-del-sel-sd-hs = <0xf>;
 475                 ti,otap-del-sel-sdr12 = <0xf>;
 476                 ti,otap-del-sel-sdr25 = <0xf>;
 477                 ti,otap-del-sel-sdr50 = <0xc>;
 478                 ti,otap-del-sel-sdr104 = <0x6>;
 479                 ti,otap-del-sel-ddr50 = <0x9>;
 480                 ti,clkbuf-sel = <0x7>;
 481         };
 482
 483         cpsw3g: ethernet@8000000 {
 484                 compatible = "ti,am642-cpsw-nuss";
 485                 #address-cells = <2>;
 486                 #size-cells = <2>;
 487                 reg = <0x0 0x8000000 0x0 0x200000>;
 488                 reg-names = "cpsw_nuss";
 489                 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
 490                 clocks = <&k3_clks 13 0>;
 491                 assigned-clocks = <&k3_clks 13 1>;
 492                 assigned-clock-parents = <&k3_clks 13 9>;
 493                 clock-names = "fck";
 494                 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
 495
 496                 dmas = <&main_pktdma 0xC500 15>,
 497                        <&main_pktdma 0xC501 15>,
 498                        <&main_pktdma 0xC502 15>,
 499                        <&main_pktdma 0xC503 15>,
 500                        <&main_pktdma 0xC504 15>,
 501                        <&main_pktdma 0xC505 15>,
 502                        <&main_pktdma 0xC506 15>,
 503                        <&main_pktdma 0xC507 15>,
 504                        <&main_pktdma 0x4500 15>;
 505                 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
 506                             "tx7", "rx";
 507
 508                 ethernet-ports {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511
 512                         cpsw_port1: port@1 {
 513                                 reg = <1>;
 514                                 ti,mac-only;
 515                                 label = "port1";
 516                                 phys = <&phy_gmii_sel 1>;
 517                                 mac-address = [00 00 00 00 00 00];
 518                                 ti,syscon-efuse = <&main_conf 0x200>;
 519                         };
 520
 521                         cpsw_port2: port@2 {
 522                                 reg = <2>;
 523                                 ti,mac-only;
 524                                 label = "port2";
 525                                 phys = <&phy_gmii_sel 2>;
 526                                 mac-address = [00 00 00 00 00 00];
 527                         };
 528                 };
 529
 530                 cpsw3g_mdio: mdio@f00 {
 531                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 532                         reg = <0x0 0xf00 0x0 0x100>;
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         clocks = <&k3_clks 13 0>;
 536                         clock-names = "fck";
 537                         bus_freq = <1000000>;
 538                 };
 539
 540                 cpts@3d000 {
 541                         compatible = "ti,j721e-cpts";
 542                         reg = <0x0 0x3d000 0x0 0x400>;
 543                         clocks = <&k3_clks 13 1>;
 544                         clock-names = "cpts";
 545                         interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 546                         interrupt-names = "cpts";
 547                         ti,cpts-ext-ts-inputs = <4>;
 548                         ti,cpts-periodic-outputs = <2>;
 549                 };
 550         };
 551
 552         cpts@39000000 {
 553                 compatible = "ti,j721e-cpts";
 554                 reg = <0x0 0x39000000 0x0 0x400>;
 555                 reg-names = "cpts";
 556                 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
 557                 clocks = <&k3_clks 84 0>;
 558                 clock-names = "cpts";
 559                 assigned-clocks = <&k3_clks 84 0>;
 560                 assigned-clock-parents = <&k3_clks 84 8>;
 561                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 562                 interrupt-names = "cpts";
 563                 ti,cpts-periodic-outputs = <6>;
 564                 ti,cpts-ext-ts-inputs = <8>;
 565         };
 566
 567         usbss0: cdns-usb@f900000{
 568                 compatible = "ti,am64-usb";
 569                 reg = <0x00 0xf900000 0x00 0x100>;
 570                 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
 571                 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
 572                 clock-names = "ref", "lpm";
 573                 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
 574                 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
 575                 #address-cells = <2>;
 576                 #size-cells = <2>;
 577                 ranges;
 578                 usb0: usb@f400000{
 579                         compatible = "cdns,usb3";
 580                         reg = <0x00 0xf400000 0x00 0x10000>,
 581                               <0x00 0xf410000 0x00 0x10000>,
 582                               <0x00 0xf420000 0x00 0x10000>;
 583                         reg-names = "otg",
 584                                     "xhci",
 585                                     "dev";
 586                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 587                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 588                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
 589                         interrupt-names = "host",
 590                                           "peripheral",
 591                                           "otg";
 592                         maximum-speed = "super-speed";
 593                         dr_mode = "otg";
 594                 };
 595         };
 596
 597         tscadc0: tscadc@28001000 {
 598                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
 599                 reg = <0x00 0x28001000 0x00 0x1000>;
 600                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 601                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 602                 clocks = <&k3_clks 0 0>;
 603                 assigned-clocks = <&k3_clks 0 0>;
 604                 assigned-clock-parents = <&k3_clks 0 3>;
 605                 assigned-clock-rates = <60000000>;
 606                 clock-names = "adc_tsc_fck";
 607
 608                 adc {
 609                         #io-channel-cells = <1>;
 610                         compatible = "ti,am654-adc", "ti,am3359-adc";
 611                 };
 612         };
 613
 614         fss: bus@fc00000 {
 615                 compatible = "simple-bus";
 616                 reg = <0x00 0x0fc00000 0x00 0x70000>;
 617                 #address-cells = <2>;
 618                 #size-cells = <2>;
 619                 ranges;
 620
 621                 ospi0: spi@fc40000 {
 622                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 623                         reg = <0x00 0x0fc40000 0x00 0x100>,
 624                               <0x05 0x00000000 0x01 0x00000000>;
 625                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 626                         cdns,fifo-depth = <256>;
 627                         cdns,fifo-width = <4>;
 628                         cdns,trigger-address = <0x0>;
 629                         #address-cells = <0x1>;
 630                         #size-cells = <0x0>;
 631                         clocks = <&k3_clks 75 6>;
 632                         assigned-clocks = <&k3_clks 75 6>;
 633                         assigned-clock-parents = <&k3_clks 75 7>;
 634                         assigned-clock-rates = <166666666>;
 635                         power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 636                 };
 637         };
 638
 639         hwspinlock: spinlock@2a000000 {
 640                 compatible = "ti,am64-hwspinlock";
 641                 reg = <0x00 0x2a000000 0x00 0x1000>;
 642                 #hwlock-cells = <1>;
 643         };
 644
 645         mailbox0_cluster2: mailbox@29020000 {
 646                 compatible = "ti,am64-mailbox";
 647                 reg = <0x00 0x29020000 0x00 0x200>;
 648                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 649                              <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 650                 #mbox-cells = <1>;
 651                 ti,mbox-num-users = <4>;
 652                 ti,mbox-num-fifos = <16>;
 653         };
 654
 655         mailbox0_cluster3: mailbox@29030000 {
 656                 compatible = "ti,am64-mailbox";
 657                 reg = <0x00 0x29030000 0x00 0x200>;
 658                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 659                              <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 660                 #mbox-cells = <1>;
 661                 ti,mbox-num-users = <4>;
 662                 ti,mbox-num-fifos = <16>;
 663         };
 664
 665         mailbox0_cluster4: mailbox@29040000 {
 666                 compatible = "ti,am64-mailbox";
 667                 reg = <0x00 0x29040000 0x00 0x200>;
 668                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 669                              <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 670                 #mbox-cells = <1>;
 671                 ti,mbox-num-users = <4>;
 672                 ti,mbox-num-fifos = <16>;
 673         };
 674
 675         mailbox0_cluster5: mailbox@29050000 {
 676                 compatible = "ti,am64-mailbox";
 677                 reg = <0x00 0x29050000 0x00 0x200>;
 678                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 679                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 680                 #mbox-cells = <1>;
 681                 ti,mbox-num-users = <4>;
 682                 ti,mbox-num-fifos = <16>;
 683         };
 684
 685         mailbox0_cluster6: mailbox@29060000 {
 686                 compatible = "ti,am64-mailbox";
 687                 reg = <0x00 0x29060000 0x00 0x200>;
 688                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 689                 #mbox-cells = <1>;
 690                 ti,mbox-num-users = <4>;
 691                 ti,mbox-num-fifos = <16>;
 692         };
 693
 694         mailbox0_cluster7: mailbox@29070000 {
 695                 compatible = "ti,am64-mailbox";
 696                 reg = <0x00 0x29070000 0x00 0x200>;
 697                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 698                 #mbox-cells = <1>;
 699                 ti,mbox-num-users = <4>;
 700                 ti,mbox-num-fifos = <16>;
 701         };
 702
 703         main_r5fss0: r5fss@78000000 {
 704                 compatible = "ti,am64-r5fss";
 705                 ti,cluster-mode = <0>;
 706                 #address-cells = <1>;
 707                 #size-cells = <1>;
 708                 ranges = <0x78000000 0x00 0x78000000 0x10000>,
 709                          <0x78100000 0x00 0x78100000 0x10000>,
 710                          <0x78200000 0x00 0x78200000 0x08000>,
 711                          <0x78300000 0x00 0x78300000 0x08000>;
 712                 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
 713
 714                 main_r5fss0_core0: r5f@78000000 {
 715                         compatible = "ti,am64-r5f";
 716                         reg = <0x78000000 0x00010000>,
 717                               <0x78100000 0x00010000>;
 718                         reg-names = "atcm", "btcm";
 719                         ti,sci = <&dmsc>;
 720                         ti,sci-dev-id = <121>;
 721                         ti,sci-proc-ids = <0x01 0xff>;
 722                         resets = <&k3_reset 121 1>;
 723                         firmware-name = "am64-main-r5f0_0-fw";
 724                         ti,atcm-enable = <1>;
 725                         ti,btcm-enable = <1>;
 726                         ti,loczrama = <1>;
 727                 };
 728
 729                 main_r5fss0_core1: r5f@78200000 {
 730                         compatible = "ti,am64-r5f";
 731                         reg = <0x78200000 0x00008000>,
 732                               <0x78300000 0x00008000>;
 733                         reg-names = "atcm", "btcm";
 734                         ti,sci = <&dmsc>;
 735                         ti,sci-dev-id = <122>;
 736                         ti,sci-proc-ids = <0x02 0xff>;
 737                         resets = <&k3_reset 122 1>;
 738                         firmware-name = "am64-main-r5f0_1-fw";
 739                         ti,atcm-enable = <1>;
 740                         ti,btcm-enable = <1>;
 741                         ti,loczrama = <1>;
 742                 };
 743         };
 744
 745         main_r5fss1: r5fss@78400000 {
 746                 compatible = "ti,am64-r5fss";
 747                 ti,cluster-mode = <0>;
 748                 #address-cells = <1>;
 749                 #size-cells = <1>;
 750                 ranges = <0x78400000 0x00 0x78400000 0x10000>,
 751                          <0x78500000 0x00 0x78500000 0x10000>,
 752                          <0x78600000 0x00 0x78600000 0x08000>,
 753                          <0x78700000 0x00 0x78700000 0x08000>;
 754                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 755
 756                 main_r5fss1_core0: r5f@78400000 {
 757                         compatible = "ti,am64-r5f";
 758                         reg = <0x78400000 0x00010000>,
 759                               <0x78500000 0x00010000>;
 760                         reg-names = "atcm", "btcm";
 761                         ti,sci = <&dmsc>;
 762                         ti,sci-dev-id = <123>;
 763                         ti,sci-proc-ids = <0x06 0xff>;
 764                         resets = <&k3_reset 123 1>;
 765                         firmware-name = "am64-main-r5f1_0-fw";
 766                         ti,atcm-enable = <1>;
 767                         ti,btcm-enable = <1>;
 768                         ti,loczrama = <1>;
 769                 };
 770
 771                 main_r5fss1_core1: r5f@78600000 {
 772                         compatible = "ti,am64-r5f";
 773                         reg = <0x78600000 0x00008000>,
 774                               <0x78700000 0x00008000>;
 775                         reg-names = "atcm", "btcm";
 776                         ti,sci = <&dmsc>;
 777                         ti,sci-dev-id = <124>;
 778                         ti,sci-proc-ids = <0x07 0xff>;
 779                         resets = <&k3_reset 124 1>;
 780                         firmware-name = "am64-main-r5f1_1-fw";
 781                         ti,atcm-enable = <1>;
 782                         ti,btcm-enable = <1>;
 783                         ti,loczrama = <1>;
 784                 };
 785         };
 786
 787         serdes_wiz0: wiz@f000000 {
 788                 compatible = "ti,am64-wiz-10g";
 789                 #address-cells = <1>;
 790                 #size-cells = <1>;
 791                 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
 792                 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
 793                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 794                 num-lanes = <1>;
 795                 #reset-cells = <1>;
 796                 #clock-cells = <1>;
 797                 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
 798
 799                 assigned-clocks = <&k3_clks 162 1>;
 800                 assigned-clock-parents = <&k3_clks 162 5>;
 801
 802                 serdes0: serdes@f000000 {
 803                         compatible = "ti,j721e-serdes-10g";
 804                         reg = <0x0f000000 0x00010000>;
 805                         reg-names = "torrent_phy";
 806                         resets = <&serdes_wiz0 0>;
 807                         reset-names = "torrent_reset";
 808                         clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
 809                                  <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
 810                         clock-names = "refclk", "phy_en_refclk";
 811                         assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
 812                                           <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
 813                                           <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
 814                         assigned-clock-parents = <&k3_clks 162 1>,
 815                                                  <&k3_clks 162 1>,
 816                                                  <&k3_clks 162 1>;
 817                         #address-cells = <1>;
 818                         #size-cells = <0>;
 819                         #clock-cells = <1>;
 820                 };
 821         };
 822
 823         pcie0_rc: pcie@f102000 {
 824                 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
 825                 reg = <0x00 0x0f102000 0x00 0x1000>,
 826                       <0x00 0x0f100000 0x00 0x400>,
 827                       <0x00 0x0d000000 0x00 0x00800000>,
 828                       <0x00 0x68000000 0x00 0x00001000>;
 829                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 830                 interrupt-names = "link_state";
 831                 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
 832                 device_type = "pci";
 833                 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
 834                 max-link-speed = <2>;
 835                 num-lanes = <1>;
 836                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 837                 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
 838                 clock-names = "fck", "pcie_refclk";
 839                 #address-cells = <3>;
 840                 #size-cells = <2>;
 841                 bus-range = <0x0 0xff>;
 842                 cdns,no-bar-match-nbits = <64>;
 843                 vendor-id = <0x104c>;
 844                 device-id = <0xb010>;
 845                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 846                 ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
 847                          <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
 848                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
 849         };
 850
 851         pcie0_ep: pcie-ep@f102000 {
 852                 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
 853                 reg = <0x00 0x0f102000 0x00 0x1000>,
 854                       <0x00 0x0f100000 0x00 0x400>,
 855                       <0x00 0x0d000000 0x00 0x00800000>,
 856                       <0x00 0x68000000 0x00 0x08000000>;
 857                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 858                 interrupt-names = "link_state";
 859                 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
 860                 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
 861                 max-link-speed = <2>;
 862                 num-lanes = <1>;
 863                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 864                 clocks = <&k3_clks 114 0>;
 865                 clock-names = "fck";
 866                 max-functions = /bits/ 8 <1>;
 867         };
 868
 869         epwm0: pwm@23000000 {
 870                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 871                 #pwm-cells = <3>;
 872                 reg = <0x0 0x23000000 0x0 0x100>;
 873                 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
 874                 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
 875                 clock-names = "tbclk", "fck";
 876         };
 877
 878         epwm1: pwm@23010000 {
 879                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 880                 #pwm-cells = <3>;
 881                 reg = <0x0 0x23010000 0x0 0x100>;
 882                 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
 883                 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
 884                 clock-names = "tbclk", "fck";
 885         };
 886
 887         epwm2: pwm@23020000 {
 888                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 889                 #pwm-cells = <3>;
 890                 reg = <0x0 0x23020000 0x0 0x100>;
 891                 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
 892                 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
 893                 clock-names = "tbclk", "fck";
 894         };
 895
 896         epwm3: pwm@23030000 {
 897                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 898                 #pwm-cells = <3>;
 899                 reg = <0x0 0x23030000 0x0 0x100>;
 900                 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
 901                 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
 902                 clock-names = "tbclk", "fck";
 903         };
 904
 905         epwm4: pwm@23040000 {
 906                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 907                 #pwm-cells = <3>;
 908                 reg = <0x0 0x23040000 0x0 0x100>;
 909                 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
 910                 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
 911                 clock-names = "tbclk", "fck";
 912         };
 913
 914         epwm5: pwm@23050000 {
 915                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 916                 #pwm-cells = <3>;
 917                 reg = <0x0 0x23050000 0x0 0x100>;
 918                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 919                 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
 920                 clock-names = "tbclk", "fck";
 921         };
 922
 923         epwm6: pwm@23060000 {
 924                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 925                 #pwm-cells = <3>;
 926                 reg = <0x0 0x23060000 0x0 0x100>;
 927                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 928                 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
 929                 clock-names = "tbclk", "fck";
 930         };
 931
 932         epwm7: pwm@23070000 {
 933                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 934                 #pwm-cells = <3>;
 935                 reg = <0x0 0x23070000 0x0 0x100>;
 936                 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
 937                 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
 938                 clock-names = "tbclk", "fck";
 939         };
 940
 941         epwm8: pwm@23080000 {
 942                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 943                 #pwm-cells = <3>;
 944                 reg = <0x0 0x23080000 0x0 0x100>;
 945                 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
 946                 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
 947                 clock-names = "tbclk", "fck";
 948         };
 949
 950         ecap0: pwm@23100000 {
 951                 compatible = "ti,am64-ecap", "ti,am3352-ecap";
 952                 #pwm-cells = <3>;
 953                 reg = <0x0 0x23100000 0x0 0x60>;
 954                 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
 955                 clocks = <&k3_clks 51 0>;
 956                 clock-names = "fck";
 957         };
 958
 959         ecap1: pwm@23110000 {
 960                 compatible = "ti,am64-ecap", "ti,am3352-ecap";
 961                 #pwm-cells = <3>;
 962                 reg = <0x0 0x23110000 0x0 0x60>;
 963                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
 964                 clocks = <&k3_clks 52 0>;
 965                 clock-names = "fck";
 966         };
 967
 968         ecap2: pwm@23120000 {
 969                 compatible = "ti,am64-ecap", "ti,am3352-ecap";
 970                 #pwm-cells = <3>;
 971                 reg = <0x0 0x23120000 0x0 0x60>;
 972                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
 973                 clocks = <&k3_clks 53 0>;
 974                 clock-names = "fck";
 975         };
 976 };