arch/arm64/boot/dts/renesas/r8a77980-condor.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Condor board with R-Car V3H
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a77980.dtsi"
  11
  12 / {
  13         model = "Renesas Condor board based on r8a77980";
  14         compatible = "renesas,condor", "renesas,r8a77980";
  15
  16         aliases {
  17                 serial0 = &scif0;
  18                 ethernet0 = &gether;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial0:115200n8";
  23         };
  24
  25         d1_8v: regulator-2 {
  26                 compatible = "regulator-fixed";
  27                 regulator-name = "D1.8V";
  28                 regulator-min-microvolt = <1800000>;
  29                 regulator-max-microvolt = <1800000>;
  30                 regulator-boot-on;
  31                 regulator-always-on;
  32         };
  33
  34         d3_3v: regulator-0 {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "D3.3V";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 regulator-boot-on;
  40                 regulator-always-on;
  41         };
  42
  43         hdmi-out {
  44                 compatible = "hdmi-connector";
  45                 type = "a";
  46
  47                 port {
  48                         hdmi_con: endpoint {
  49                                 remote-endpoint = <&adv7511_out>;
  50                         };
  51                 };
  52         };
  53
  54         lvds-decoder {
  55                 compatible = "thine,thc63lvd1024";
  56                 vcc-supply = <&d3_3v>;
  57
  58                 ports {
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61
  62                         port@0 {
  63                                 reg = <0>;
  64                                 thc63lvd1024_in: endpoint {
  65                                         remote-endpoint = <&lvds0_out>;
  66                                 };
  67                         };
  68
  69                         port@2 {
  70                                 reg = <2>;
  71                                 thc63lvd1024_out: endpoint {
  72                                         remote-endpoint = <&adv7511_in>;
  73                                 };
  74                         };
  75                 };
  76         };
  77
  78         memory@48000000 {
  79                 device_type = "memory";
  80                 /* first 128MB is reserved for secure area. */
  81                 reg = <0 0x48000000 0 0x78000000>;
  82         };
  83
  84         vddq_vin01: regulator-1 {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "VDDQ_VIN01";
  87                 regulator-min-microvolt = <1800000>;
  88                 regulator-max-microvolt = <1800000>;
  89                 regulator-boot-on;
  90                 regulator-always-on;
  91         };
  92
  93         x1_clk: x1-clock {
  94                 compatible = "fixed-clock";
  95                 #clock-cells = <0>;
  96                 clock-frequency = <148500000>;
  97         };
  98 };
  99
 100 &canfd {
 101         pinctrl-0 = <&canfd0_pins>;
 102         pinctrl-names = "default";
 103         status = "okay";
 104
 105         channel0 {
 106                 status = "okay";
 107         };
 108 };
 109
 110 &du {
 111         clocks = <&cpg CPG_MOD 724>,
 112                  <&x1_clk>;
 113         clock-names = "du.0", "dclkin.0";
 114         status = "okay";
 115 };
 116
 117 &extal_clk {
 118         clock-frequency = <16666666>;
 119 };
 120
 121 &extalr_clk {
 122         clock-frequency = <32768>;
 123 };
 124
 125 &gether {
 126         pinctrl-0 = <&gether_pins>;
 127         pinctrl-names = "default";
 128
 129         phy-mode = "rgmii-id";
 130         phy-handle = <&phy0>;
 131         renesas,no-ether-link;
 132         status = "okay";
 133
 134         phy0: ethernet-phy@0 {
 135                 rxc-skew-ps = <1500>;
 136                 reg = <0>;
 137                 interrupt-parent = <&gpio4>;
 138                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 139         };
 140 };
 141
 142 &i2c0 {
 143         pinctrl-0 = <&i2c0_pins>;
 144         pinctrl-names = "default";
 145
 146         status = "okay";
 147         clock-frequency = <400000>;
 148
 149         io_expander0: gpio@20 {
 150                 compatible = "onnn,pca9654";
 151                 reg = <0x20>;
 152                 gpio-controller;
 153                 #gpio-cells = <2>;
 154         };
 155
 156         io_expander1: gpio@21 {
 157                 compatible = "onnn,pca9654";
 158                 reg = <0x21>;
 159                 gpio-controller;
 160                 #gpio-cells = <2>;
 161         };
 162
 163         hdmi@39 {
 164                 compatible = "adi,adv7511w";
 165                 reg = <0x39>;
 166                 interrupt-parent = <&gpio1>;
 167                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 168                 avdd-supply = <&d1_8v>;
 169                 dvdd-supply = <&d1_8v>;
 170                 pvdd-supply = <&d1_8v>;
 171                 bgvdd-supply = <&d1_8v>;
 172                 dvdd-3v-supply = <&d3_3v>;
 173
 174                 adi,input-depth = <8>;
 175                 adi,input-colorspace = "rgb";
 176                 adi,input-clock = "1x";
 177
 178                 ports {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181
 182                         port@0 {
 183                                 reg = <0>;
 184                                 adv7511_in: endpoint {
 185                                         remote-endpoint = <&thc63lvd1024_out>;
 186                                 };
 187                         };
 188
 189                         port@1 {
 190                                 reg = <1>;
 191                                 adv7511_out: endpoint {
 192                                         remote-endpoint = <&hdmi_con>;
 193                                 };
 194                         };
 195                 };
 196         };
 197 };
 198
 199 &lvds0 {
 200         status = "okay";
 201
 202         ports {
 203                 port@1 {
 204                         lvds0_out: endpoint {
 205                                 remote-endpoint = <&thc63lvd1024_in>;
 206                         };
 207                 };
 208         };
 209 };
 210
 211 &mmc0 {
 212         pinctrl-0 = <&mmc_pins>;
 213         pinctrl-1 = <&mmc_pins>;
 214         pinctrl-names = "default", "state_uhs";
 215
 216         vmmc-supply = <&d3_3v>;
 217         vqmmc-supply = <&vddq_vin01>;
 218         mmc-hs200-1_8v;
 219         bus-width = <8>;
 220         no-sd;
 221         no-sdio;
 222         non-removable;
 223         status = "okay";
 224 };
 225
 226 &pciec {
 227         status = "okay";
 228 };
 229
 230 &pcie_bus_clk {
 231         clock-frequency = <100000000>;
 232 };
 233
 234 &pcie_phy {
 235         status = "okay";
 236 };
 237
 238 &pfc {
 239         canfd0_pins: canfd0 {
 240                 groups = "canfd0_data_a";
 241                 function = "canfd0";
 242         };
 243
 244         gether_pins: gether {
 245                 groups = "gether_mdio_a", "gether_rgmii",
 246                          "gether_txcrefclk", "gether_txcrefclk_mega";
 247                 function = "gether";
 248         };
 249
 250         i2c0_pins: i2c0 {
 251                 groups = "i2c0";
 252                 function = "i2c0";
 253         };
 254
 255         mmc_pins: mmc {
 256                 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
 257                 function = "mmc";
 258                 power-source = <1800>;
 259         };
 260
 261         qspi0_pins: qspi0 {
 262                 groups = "qspi0_ctrl", "qspi0_data4";
 263                 function = "qspi0";
 264         };
 265
 266         scif0_pins: scif0 {
 267                 groups = "scif0_data";
 268                 function = "scif0";
 269         };
 270
 271         scif_clk_pins: scif_clk {
 272                 groups = "scif_clk_b";
 273                 function = "scif_clk";
 274         };
 275 };
 276
 277 &rpc {
 278         pinctrl-0 = <&qspi0_pins>;
 279         pinctrl-names = "default";
 280
 281         status = "okay";
 282
 283         flash@0 {
 284                 compatible = "spansion,s25fs512s", "jedec,spi-nor";
 285                 reg = <0>;
 286                 spi-max-frequency = <50000000>;
 287                 spi-rx-bus-width = <4>;
 288
 289                 partitions {
 290                         compatible = "fixed-partitions";
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293
 294                         bootparam@0 {
 295                                 reg = <0x00000000 0x040000>;
 296                                 read-only;
 297                         };
 298                         cr7@40000 {
 299                                 reg = <0x00040000 0x080000>;
 300                                 read-only;
 301                         };
 302                         cert_header_sa3@c0000 {
 303                                 reg = <0x000c0000 0x080000>;
 304                                 read-only;
 305                         };
 306                         bl2@140000 {
 307                                 reg = <0x00140000 0x040000>;
 308                                 read-only;
 309                         };
 310                         cert_header_sa6@180000 {
 311                                 reg = <0x00180000 0x040000>;
 312                                 read-only;
 313                         };
 314                         bl31@1c0000 {
 315                                 reg = <0x001c0000 0x460000>;
 316                                 read-only;
 317                         };
 318                         uboot@640000 {
 319                                 reg = <0x00640000 0x0c0000>;
 320                                 read-only;
 321                         };
 322                         uboot-env@700000 {
 323                                 reg = <0x00700000 0x040000>;
 324                                 read-only;
 325                         };
 326                         dtb@740000 {
 327                                 reg = <0x00740000 0x080000>;
 328                         };
 329                         kernel@7c0000 {
 330                                 reg = <0x007c0000 0x1400000>;
 331                         };
 332                         user@1bc0000 {
 333                                 reg = <0x01bc0000 0x2440000>;
 334                         };
 335                 };
 336         };
 337 };
 338
 339 &rwdt {
 340         timeout-sec = <60>;
 341         status = "okay";
 342 };
 343
 344 &scif0 {
 345         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
 346         pinctrl-names = "default";
 347
 348         status = "okay";
 349 };
 350
 351 &scif_clk {
 352         clock-frequency = <14745600>;
 353 };