arch/arm64/boot/dts/renesas/r8a77970-eagle.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Eagle board with R-Car V3M
   4  *
   5  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Cogent Embedded, Inc.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a77970.dtsi"
  11
  12 / {
  13         model = "Renesas Eagle board based on r8a77970";
  14         compatible = "renesas,eagle", "renesas,r8a77970";
  15
  16         aliases {
  17                 serial0 = &scif0;
  18                 ethernet0 = &avb;
  19         };
  20
  21         chosen {
  22                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         d3p3: regulator-fixed {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "fixed-3.3V";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 regulator-boot-on;
  32                 regulator-always-on;
  33         };
  34
  35         hdmi-out {
  36                 compatible = "hdmi-connector";
  37                 type = "a";
  38
  39                 port {
  40                         hdmi_con_out: endpoint {
  41                                 remote-endpoint = <&adv7511_out>;
  42                         };
  43                 };
  44         };
  45
  46         lvds-decoder {
  47                 compatible = "thine,thc63lvd1024";
  48
  49                 vcc-supply = <&d3p3>;
  50
  51                 ports {
  52                         #address-cells = <1>;
  53                         #size-cells = <0>;
  54
  55                         port@0 {
  56                                 reg = <0>;
  57                                 thc63lvd1024_in: endpoint {
  58                                         remote-endpoint = <&lvds0_out>;
  59                                 };
  60                         };
  61
  62                         port@2 {
  63                                 reg = <2>;
  64                                 thc63lvd1024_out: endpoint {
  65                                         remote-endpoint = <&adv7511_in>;
  66                                 };
  67                         };
  68                 };
  69         };
  70
  71         memory@48000000 {
  72                 device_type = "memory";
  73                 /* first 128MB is reserved for secure area. */
  74                 reg = <0x0 0x48000000 0x0 0x38000000>;
  75         };
  76
  77         x1_clk: x1-clock {
  78                 compatible = "fixed-clock";
  79                 #clock-cells = <0>;
  80                 clock-frequency = <148500000>;
  81         };
  82 };
  83
  84 &avb {
  85         pinctrl-0 = <&avb_pins>;
  86         pinctrl-names = "default";
  87
  88         renesas,no-ether-link;
  89         phy-handle = <&phy0>;
  90         rx-internal-delay-ps = <1800>;
  91         tx-internal-delay-ps = <2000>;
  92         status = "okay";
  93
  94         phy0: ethernet-phy@0 {
  95                 rxc-skew-ps = <1500>;
  96                 reg = <0>;
  97                 interrupt-parent = <&gpio1>;
  98                 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
  99         };
 100 };
 101
 102 &canfd {
 103         pinctrl-0 = <&canfd0_pins>;
 104         pinctrl-names = "default";
 105         status = "okay";
 106
 107         channel0 {
 108                 status = "okay";
 109         };
 110 };
 111
 112 &du {
 113         clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
 114         clock-names = "du.0", "dclkin.0";
 115         status = "okay";
 116 };
 117
 118 &extal_clk {
 119         clock-frequency = <16666666>;
 120 };
 121
 122 &extalr_clk {
 123         clock-frequency = <32768>;
 124 };
 125
 126 &i2c0 {
 127         pinctrl-0 = <&i2c0_pins>;
 128         pinctrl-names = "default";
 129
 130         status = "okay";
 131         clock-frequency = <400000>;
 132
 133         io_expander: gpio@20 {
 134                 compatible = "onnn,pca9654";
 135                 reg = <0x20>;
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138         };
 139
 140         hdmi@39 {
 141                 compatible = "adi,adv7511w";
 142                 reg = <0x39>;
 143                 interrupt-parent = <&gpio1>;
 144                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 145
 146                 adi,input-depth = <8>;
 147                 adi,input-colorspace = "rgb";
 148                 adi,input-clock = "1x";
 149
 150                 ports {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153
 154                         port@0 {
 155                                 reg = <0>;
 156                                 adv7511_in: endpoint {
 157                                         remote-endpoint = <&thc63lvd1024_out>;
 158                                 };
 159                         };
 160
 161                         port@1 {
 162                                 reg = <1>;
 163                                 adv7511_out: endpoint {
 164                                         remote-endpoint = <&hdmi_con_out>;
 165                                 };
 166                         };
 167                 };
 168         };
 169 };
 170
 171 &lvds0 {
 172         status = "okay";
 173
 174         ports {
 175                 port@1 {
 176                         lvds0_out: endpoint {
 177                                 remote-endpoint = <&thc63lvd1024_in>;
 178                         };
 179                 };
 180         };
 181 };
 182
 183 &pfc {
 184         avb_pins: avb0 {
 185                 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
 186                 function = "avb0";
 187         };
 188
 189         canfd0_pins: canfd0 {
 190                 groups = "canfd0_data_a";
 191                 function = "canfd0";
 192         };
 193
 194         i2c0_pins: i2c0 {
 195                 groups = "i2c0";
 196                 function = "i2c0";
 197         };
 198
 199         qspi0_pins: qspi0 {
 200                 groups = "qspi0_ctrl", "qspi0_data4";
 201                 function = "qspi0";
 202         };
 203
 204         scif0_pins: scif0 {
 205                 groups = "scif0_data";
 206                 function = "scif0";
 207         };
 208 };
 209
 210 &rpc {
 211         pinctrl-0 = <&qspi0_pins>;
 212         pinctrl-names = "default";
 213
 214         status = "okay";
 215
 216         flash@0 {
 217                 compatible = "spansion,s25fs512s", "jedec,spi-nor";
 218                 reg = <0>;
 219                 spi-max-frequency = <50000000>;
 220                 spi-rx-bus-width = <4>;
 221
 222                 partitions {
 223                         compatible = "fixed-partitions";
 224                         #address-cells = <1>;
 225                         #size-cells = <1>;
 226
 227                         bootparam@0 {
 228                                 reg = <0x00000000 0x040000>;
 229                                 read-only;
 230                         };
 231                         cr7@40000 {
 232                                 reg = <0x00040000 0x080000>;
 233                                 read-only;
 234                         };
 235                         cert_header_sa3@c0000 {
 236                                 reg = <0x000c0000 0x080000>;
 237                                 read-only;
 238                         };
 239                         bl2@140000 {
 240                                 reg = <0x00140000 0x040000>;
 241                                 read-only;
 242                         };
 243                         cert_header_sa6@180000 {
 244                                 reg = <0x00180000 0x040000>;
 245                                 read-only;
 246                         };
 247                         bl31@1c0000 {
 248                                 reg = <0x001c0000 0x460000>;
 249                                 read-only;
 250                         };
 251                         uboot@640000 {
 252                                 reg = <0x00640000 0x0c0000>;
 253                                 read-only;
 254                         };
 255                         uboot-env@700000 {
 256                                 reg = <0x00700000 0x040000>;
 257                                 read-only;
 258                         };
 259                         dtb@740000 {
 260                                 reg = <0x00740000 0x080000>;
 261                         };
 262                         kernel@7c0000 {
 263                                 reg = <0x007c0000 0x1400000>;
 264                         };
 265                         user@1bc0000 {
 266                                 reg = <0x01bc0000 0x2440000>;
 267                         };
 268                 };
 269         };
 270 };
 271
 272 &rwdt {
 273         timeout-sec = <60>;
 274         status = "okay";
 275 };
 276
 277 &scif0 {
 278         pinctrl-0 = <&scif0_pins>;
 279         pinctrl-names = "default";
 280
 281         status = "okay";
 282 };