arch/arm64/boot/dts/qcom/sm6125.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
   4  */
   5
   6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/qcom-rpmpd.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         clocks {
  20                 xo_board: xo-board {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <19200000>;
  24                         clock-output-names = "xo_board";
  25                 };
  26
  27                 sleep_clk: sleep-clk {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <32000>;
  31                         clock-output-names = "sleep_clk";
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <2>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "qcom,kryo260";
  42                         reg = <0x0 0x0>;
  43                         enable-method = "psci";
  44                         capacity-dmips-mhz = <1024>;
  45                         next-level-cache = <&L2_0>;
  46                         L2_0: l2-cache {
  47                                 compatible = "cache";
  48                         };
  49                 };
  50
  51                 CPU1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "qcom,kryo260";
  54                         reg = <0x0 0x1>;
  55                         enable-method = "psci";
  56                         capacity-dmips-mhz = <1024>;
  57                         next-level-cache = <&L2_0>;
  58                 };
  59
  60                 CPU2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "qcom,kryo260";
  63                         reg = <0x0 0x2>;
  64                         enable-method = "psci";
  65                         capacity-dmips-mhz = <1024>;
  66                         next-level-cache = <&L2_0>;
  67                 };
  68
  69                 CPU3: cpu@3 {
  70                         device_type = "cpu";
  71                         compatible = "qcom,kryo260";
  72                         reg = <0x0 0x3>;
  73                         enable-method = "psci";
  74                         capacity-dmips-mhz = <1024>;
  75                         next-level-cache = <&L2_0>;
  76                 };
  77
  78                 CPU4: cpu@100 {
  79                         device_type = "cpu";
  80                         compatible = "qcom,kryo260";
  81                         reg = <0x0 0x100>;
  82                         enable-method = "psci";
  83                         capacity-dmips-mhz = <1638>;
  84                         next-level-cache = <&L2_1>;
  85                         L2_1: l2-cache {
  86                                 compatible = "cache";
  87                         };
  88                 };
  89
  90                 CPU5: cpu@101 {
  91                         device_type = "cpu";
  92                         compatible = "qcom,kryo260";
  93                         reg = <0x0 0x101>;
  94                         enable-method = "psci";
  95                         capacity-dmips-mhz = <1638>;
  96                         next-level-cache = <&L2_1>;
  97                 };
  98
  99                 CPU6: cpu@102 {
 100                         device_type = "cpu";
 101                         compatible = "qcom,kryo260";
 102                         reg = <0x0 0x102>;
 103                         enable-method = "psci";
 104                         capacity-dmips-mhz = <1638>;
 105                         next-level-cache = <&L2_1>;
 106                 };
 107
 108                 CPU7: cpu@103 {
 109                         device_type = "cpu";
 110                         compatible = "qcom,kryo260";
 111                         reg = <0x0 0x103>;
 112                         enable-method = "psci";
 113                         capacity-dmips-mhz = <1638>;
 114                         next-level-cache = <&L2_1>;
 115                 };
 116
 117                 cpu-map {
 118                         cluster0 {
 119                                 core0 {
 120                                         cpu = <&CPU0>;
 121                                 };
 122
 123                                 core1 {
 124                                         cpu = <&CPU1>;
 125                                 };
 126
 127                                 core2 {
 128                                         cpu = <&CPU2>;
 129                                 };
 130
 131                                 core3 {
 132                                         cpu = <&CPU3>;
 133                                 };
 134                         };
 135
 136                         cluster1 {
 137                                 core0 {
 138                                         cpu = <&CPU4>;
 139                                 };
 140
 141                                 core1 {
 142                                         cpu = <&CPU5>;
 143                                 };
 144
 145                                 core2 {
 146                                         cpu = <&CPU6>;
 147                                 };
 148
 149                                 core3 {
 150                                         cpu = <&CPU7>;
 151                                 };
 152                         };
 153                 };
 154         };
 155
 156         firmware {
 157                 scm: scm {
 158                         compatible = "qcom,scm-sm6125", "qcom,scm";
 159                         #reset-cells = <1>;
 160                 };
 161         };
 162
 163         memory@40000000 {
 164                 /* We expect the bootloader to fill in the size */
 165                 reg = <0x0 0x40000000 0x0 0x0>;
 166                 device_type = "memory";
 167         };
 168
 169         pmu {
 170                 compatible = "arm,armv8-pmuv3";
 171                 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         psci {
 175                 compatible = "arm,psci-1.0";
 176                 method = "smc";
 177         };
 178
 179         reserved_memory: reserved-memory {
 180                 #address-cells = <2>;
 181                 #size-cells = <2>;
 182                 ranges;
 183
 184                 hyp_mem: memory@45700000 {
 185                         reg = <0x0 0x45700000 0x0 0x600000>;
 186                         no-map;
 187                 };
 188
 189                 xbl_aop_mem: memory@45e00000 {
 190                         reg = <0x0 0x45e00000 0x0 0x140000>;
 191                         no-map;
 192                 };
 193
 194                 sec_apps_mem: memory@45fff000 {
 195                         reg = <0x0 0x45fff000 0x0 0x1000>;
 196                         no-map;
 197                 };
 198
 199                 smem_mem: memory@46000000 {
 200                         reg = <0x0 0x46000000 0x0 0x200000>;
 201                         no-map;
 202                 };
 203
 204                 reserved_mem1: memory@46200000 {
 205                         reg = <0x0 0x46200000 0x0 0x2d00000>;
 206                         no-map;
 207                 };
 208
 209                 camera_mem: memory@4ab00000 {
 210                         reg = <0x0 0x4ab00000 0x0 0x500000>;
 211                         no-map;
 212                 };
 213
 214                 modem_mem: memory@4b000000 {
 215                         reg = <0x0 0x4b000000 0x0 0x7e00000>;
 216                         no-map;
 217                 };
 218
 219                 venus_mem: memory@52e00000 {
 220                         reg = <0x0 0x52e00000 0x0 0x500000>;
 221                         no-map;
 222                 };
 223
 224                 wlan_msa_mem: memory@53300000 {
 225                         reg = <0x0 0x53300000 0x0 0x200000>;
 226                         no-map;
 227                 };
 228
 229                 cdsp_mem: memory@53500000 {
 230                         reg = <0x0 0x53500000 0x0 0x1e00000>;
 231                         no-map;
 232                 };
 233
 234                 adsp_pil_mem: memory@55300000 {
 235                         reg = <0x0 0x55300000 0x0 0x1e00000>;
 236                         no-map;
 237                 };
 238
 239                 ipa_fw_mem: memory@57100000 {
 240                         reg = <0x0 0x57100000 0x0 0x10000>;
 241                         no-map;
 242                 };
 243
 244                 ipa_gsi_mem: memory@57110000 {
 245                         reg = <0x0 0x57110000 0x0 0x5000>;
 246                         no-map;
 247                 };
 248
 249                 gpu_mem: memory@57115000 {
 250                         reg = <0x0 0x57115000 0x0 0x2000>;
 251                         no-map;
 252                 };
 253
 254                 cont_splash_mem: memory@5c000000 {
 255                         reg = <0x0 0x5c000000 0x0 0x00f00000>;
 256                         no-map;
 257                 };
 258
 259                 dfps_data_mem: memory@5cf00000 {
 260                         reg = <0x0 0x5cf00000 0x0 0x0100000>;
 261                         no-map;
 262                 };
 263
 264                 cdsp_sec_mem: memory@5f800000 {
 265                         reg = <0x0 0x5f800000 0x0 0x1e00000>;
 266                         no-map;
 267                 };
 268
 269                 qseecom_mem: memory@5e400000 {
 270                         reg = <0x0 0x5e400000 0x0 0x1400000>;
 271                         no-map;
 272                 };
 273
 274                 sdsp_mem: memory@f3000000 {
 275                         reg = <0x0 0xf3000000 0x0 0x400000>;
 276                         no-map;
 277                 };
 278
 279                 adsp_mem: memory@f3400000 {
 280                         reg = <0x0 0xf3400000 0x0 0x800000>;
 281                         no-map;
 282                 };
 283
 284                 qseecom_ta_mem: memory@13fc00000 {
 285                         reg = <0x1 0x3fc00000 0x0 0x400000>;
 286                         no-map;
 287                 };
 288         };
 289
 290         rpm-glink {
 291                 compatible = "qcom,glink-rpm";
 292
 293                 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
 294                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 295                 mboxes = <&apcs_glb 0>;
 296
 297                 rpm_requests: rpm-requests {
 298                         compatible = "qcom,rpm-sm6125";
 299                         qcom,glink-channels = "rpm_requests";
 300
 301                         rpmcc: clock-controller {
 302                                 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
 303                                 #clock-cells = <1>;
 304                         };
 305                 };
 306         };
 307
 308         smem: smem {
 309                 compatible = "qcom,smem";
 310                 memory-region = <&smem_mem>;
 311                 hwlocks = <&tcsr_mutex 3>;
 312         };
 313
 314         soc {
 315                 #address-cells = <1>;
 316                 #size-cells = <1>;
 317                 ranges = <0x00 0x00 0x00 0xffffffff>;
 318                 compatible = "simple-bus";
 319
 320                 tcsr_mutex: hwlock@340000 {
 321                         compatible = "qcom,tcsr-mutex";
 322                         reg = <0x00340000 0x20000>;
 323                         #hwlock-cells = <1>;
 324                 };
 325
 326                 tlmm: pinctrl@500000 {
 327                         compatible = "qcom,sm6125-tlmm";
 328                         reg = <0x00500000 0x400000>,
 329                                 <0x00900000 0x400000>,
 330                                 <0x00d00000 0x400000>;
 331                         reg-names = "west", "south", "east";
 332                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 333                         gpio-controller;
 334                         gpio-ranges = <&tlmm 0 0 134>;
 335                         #gpio-cells = <2>;
 336                         interrupt-controller;
 337                         #interrupt-cells = <2>;
 338
 339                         sdc2_state_off: sdc2-off {
 340                                 clk {
 341                                         pins = "sdc2_clk";
 342                                         bias-disable;
 343                                         drive-strength = <2>;
 344                                 };
 345
 346                                 cmd {
 347                                         pins = "sdc2_cmd";
 348                                         bias-pull-up;
 349                                         drive-strength = <2>;
 350                                 };
 351
 352                                 data {
 353                                         pins = "sdc2_data";
 354                                         bias-pull-up;
 355                                         drive-strength = <2>;
 356                                 };
 357                         };
 358                 };
 359
 360                 gcc: clock-controller@1400000 {
 361                         compatible = "qcom,gcc-sm6125";
 362                         reg = <0x01400000 0x1f0000>;
 363                         #clock-cells = <1>;
 364                         #reset-cells = <1>;
 365                         #power-domain-cells = <1>;
 366                         clock-names = "bi_tcxo", "sleep_clk";
 367                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
 368                 };
 369
 370                 hsusb_phy1: phy@1613000 {
 371                         compatible = "qcom,msm8996-qusb2-phy";
 372                         reg = <0x01613000 0x180>;
 373                         #phy-cells = <0>;
 374
 375                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 376                                  <&gcc GCC_AHB2PHY_USB_CLK>;
 377                         clock-names = "ref", "cfg_ahb";
 378
 379                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 380                         status = "disabled";
 381                 };
 382
 383                 rpm_msg_ram: memory@45f0000 {
 384                         compatible = "qcom,rpm-msg-ram";
 385                         reg = <0x045f0000 0x7000>;
 386                 };
 387
 388                 sdhc_1: sdhci@4744000 {
 389                         compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 390                         reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
 391                         reg-names = "hc", "core";
 392
 393                         interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 394                                 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
 395                         interrupt-names = "hc_irq", "pwr_irq";
 396
 397                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 398                                 <&gcc GCC_SDCC1_APPS_CLK>,
 399                                 <&xo_board>;
 400                         clock-names = "iface", "core", "xo";
 401                         bus-width = <8>;
 402                         non-removable;
 403                         status = "disabled";
 404                 };
 405
 406                 sdhc_2: sdhci@4784000 {
 407                         compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 408                         reg = <0x04784000 0x1000>;
 409                         reg-names = "hc";
 410
 411                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 412                                 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 413                         interrupt-names = "hc_irq", "pwr_irq";
 414
 415                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 416                                 <&gcc GCC_SDCC2_APPS_CLK>,
 417                                 <&xo_board>;
 418                         clock-names = "iface", "core", "xo";
 419
 420                         pinctrl-0 = <&sdc2_state_on>;
 421                         pinctrl-1 = <&sdc2_state_off>;
 422                         pinctrl-names = "default", "sleep";
 423
 424                         bus-width = <4>;
 425                         status = "disabled";
 426                 };
 427
 428                 usb3: usb@4ef8800 {
 429                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 430                         reg = <0x04ef8800 0x400>;
 431                         #address-cells = <1>;
 432                         #size-cells = <1>;
 433                         ranges;
 434
 435                         clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 436                                 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
 437                                 <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
 438                                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 439                                 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
 440                                 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
 441
 442                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 443                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 444                         assigned-clock-rates = <19200000>, <66666667>;
 445
 446                         power-domains = <&gcc USB30_PRIM_GDSC>;
 447                         qcom,select-utmi-as-pipe-clk;
 448                         status = "disabled";
 449
 450                         usb3_dwc3: usb@4e00000 {
 451                                 compatible = "snps,dwc3";
 452                                 reg = <0x04e00000 0xcd00>;
 453                                 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 454                                 phys = <&hsusb_phy1>;
 455                                 phy-names = "usb2-phy";
 456                                 snps,dis_u2_susphy_quirk;
 457                                 snps,dis_enblslpm_quirk;
 458                                 maximum-speed = "high-speed";
 459                                 dr_mode = "peripheral";
 460                         };
 461                 };
 462
 463                 spmi_bus: spmi@1c40000 {
 464                         compatible = "qcom,spmi-pmic-arb";
 465                         reg =   <0x01c40000 0x1100>,
 466                                 <0x01e00000 0x2000000>,
 467                                 <0x03e00000 0x100000>,
 468                                 <0x03f00000 0xa0000>,
 469                                 <0x01c0a000 0x26000>;
 470                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 471                         interrupt-names = "periph_irq";
 472                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 473                         qcom,ee = <0>;
 474                         qcom,channel = <0>;
 475                         #address-cells = <2>;
 476                         #size-cells = <0>;
 477                         interrupt-controller;
 478                         #interrupt-cells = <4>;
 479                         cell-index = <0>;
 480                 };
 481
 482                 apcs_glb: mailbox@f111000 {
 483                         compatible = "qcom,sm6125-apcs-hmss-global";
 484                         reg = <0x0f111000 0x1000>;
 485
 486                         #mbox-cells = <1>;
 487                 };
 488
 489                 timer@f120000 {
 490                         compatible = "arm,armv7-timer-mem";
 491                         #address-cells = <1>;
 492                         #size-cells = <1>;
 493                         ranges;
 494                         reg = <0x0f120000 0x1000>;
 495                         clock-frequency = <19200000>;
 496
 497                         frame@0f121000 {
 498                                 frame-number = <0>;
 499                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 500                                                 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 501                                 reg = <0x0f121000 0x1000>,
 502                                       <0x0f122000 0x1000>;
 503                         };
 504
 505                         frame@0f123000 {
 506                                 frame-number = <1>;
 507                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 508                                 reg = <0x0f123000 0x1000>;
 509                                 status = "disabled";
 510                         };
 511
 512                         frame@0f124000 {
 513                                 frame-number = <2>;
 514                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 515                                 reg = <0x0f124000 0x1000>;
 516                                 status = "disabled";
 517                         };
 518
 519                         frame@f125000 {
 520                                 frame-number = <3>;
 521                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 522                                 reg = <0x0f125000 0x1000>;
 523                                 status = "disabled";
 524                         };
 525
 526                         frame@f126000 {
 527                                 frame-number = <4>;
 528                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 529                                 reg = <0x0f126000 0x1000>;
 530                                 status = "disabled";
 531                         };
 532
 533                         frame@f127000 {
 534                                 frame-number = <5>;
 535                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 536                                 reg = <0x0f127000 0x1000>;
 537                                 status = "disabled";
 538                         };
 539
 540                         frame@f128000 {
 541                                 frame-number = <6>;
 542                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 543                                 reg = <0x0f128000 0x1000>;
 544                                 status = "disabled";
 545                         };
 546                 };
 547
 548                 intc: interrupt-controller@f200000 {
 549                         compatible = "arm,gic-v3";
 550                         reg = <0x0f200000 0x20000>,
 551                                 <0x0f300000 0x100000>;
 552                         #interrupt-cells = <3>;
 553                         interrupt-controller;
 554                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 555                 };
 556         };
 557
 558         timer {
 559                 compatible = "arm,armv8-timer";
 560                 interrupts = <GIC_PPI 1 0xf08
 561                                 GIC_PPI 2 0xf08
 562                                 GIC_PPI 3 0xf08
 563                                 GIC_PPI 0 0xf08>;
 564                 clock-frequency = <19200000>;
 565         };
 566 };