arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-aoss-qmp.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  15 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         clocks {
  28                 xo_board: xo-board {
  29                         compatible = "fixed-clock";
  30                         clock-frequency = <76800000>;
  31                         #clock-cells = <0>;
  32                 };
  33
  34                 sleep_clk: sleep-clk {
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <32000>;
  37                         #clock-cells = <0>;
  38                 };
  39         };
  40
  41         reserved-memory {
  42                 #address-cells = <2>;
  43                 #size-cells = <2>;
  44                 ranges;
  45
  46                 aop_mem: memory@80800000 {
  47                         reg = <0x0 0x80800000 0x0 0x60000>;
  48                         no-map;
  49                 };
  50
  51                 aop_cmd_db_mem: memory@80860000 {
  52                         reg = <0x0 0x80860000 0x0 0x20000>;
  53                         compatible = "qcom,cmd-db";
  54                         no-map;
  55                 };
  56
  57                 smem_mem: memory@80900000 {
  58                         reg = <0x0 0x80900000 0x0 0x200000>;
  59                         no-map;
  60                 };
  61
  62                 cpucp_mem: memory@80b00000 {
  63                         no-map;
  64                         reg = <0x0 0x80b00000 0x0 0x100000>;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 CPU0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,kryo";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  78                                            &LITTLE_CPU_SLEEP_1
  79                                            &CLUSTER_SLEEP_0>;
  80                         next-level-cache = <&L2_0>;
  81                         qcom,freq-domain = <&cpufreq_hw 0>;
  82                         #cooling-cells = <2>;
  83                         L2_0: l2-cache {
  84                                 compatible = "cache";
  85                                 next-level-cache = <&L3_0>;
  86                                 L3_0: l3-cache {
  87                                         compatible = "cache";
  88                                 };
  89                         };
  90                 };
  91
  92                 CPU1: cpu@100 {
  93                         device_type = "cpu";
  94                         compatible = "arm,kryo";
  95                         reg = <0x0 0x100>;
  96                         enable-method = "psci";
  97                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  98                                            &LITTLE_CPU_SLEEP_1
  99                                            &CLUSTER_SLEEP_0>;
 100                         next-level-cache = <&L2_100>;
 101                         qcom,freq-domain = <&cpufreq_hw 0>;
 102                         #cooling-cells = <2>;
 103                         L2_100: l2-cache {
 104                                 compatible = "cache";
 105                                 next-level-cache = <&L3_0>;
 106                         };
 107                 };
 108
 109                 CPU2: cpu@200 {
 110                         device_type = "cpu";
 111                         compatible = "arm,kryo";
 112                         reg = <0x0 0x200>;
 113                         enable-method = "psci";
 114                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 115                                            &LITTLE_CPU_SLEEP_1
 116                                            &CLUSTER_SLEEP_0>;
 117                         next-level-cache = <&L2_200>;
 118                         qcom,freq-domain = <&cpufreq_hw 0>;
 119                         #cooling-cells = <2>;
 120                         L2_200: l2-cache {
 121                                 compatible = "cache";
 122                                 next-level-cache = <&L3_0>;
 123                         };
 124                 };
 125
 126                 CPU3: cpu@300 {
 127                         device_type = "cpu";
 128                         compatible = "arm,kryo";
 129                         reg = <0x0 0x300>;
 130                         enable-method = "psci";
 131                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 132                                            &LITTLE_CPU_SLEEP_1
 133                                            &CLUSTER_SLEEP_0>;
 134                         next-level-cache = <&L2_300>;
 135                         qcom,freq-domain = <&cpufreq_hw 0>;
 136                         #cooling-cells = <2>;
 137                         L2_300: l2-cache {
 138                                 compatible = "cache";
 139                                 next-level-cache = <&L3_0>;
 140                         };
 141                 };
 142
 143                 CPU4: cpu@400 {
 144                         device_type = "cpu";
 145                         compatible = "arm,kryo";
 146                         reg = <0x0 0x400>;
 147                         enable-method = "psci";
 148                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 149                                            &BIG_CPU_SLEEP_1
 150                                            &CLUSTER_SLEEP_0>;
 151                         next-level-cache = <&L2_400>;
 152                         qcom,freq-domain = <&cpufreq_hw 1>;
 153                         #cooling-cells = <2>;
 154                         L2_400: l2-cache {
 155                                 compatible = "cache";
 156                                 next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159
 160                 CPU5: cpu@500 {
 161                         device_type = "cpu";
 162                         compatible = "arm,kryo";
 163                         reg = <0x0 0x500>;
 164                         enable-method = "psci";
 165                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 166                                            &BIG_CPU_SLEEP_1
 167                                            &CLUSTER_SLEEP_0>;
 168                         next-level-cache = <&L2_500>;
 169                         qcom,freq-domain = <&cpufreq_hw 1>;
 170                         #cooling-cells = <2>;
 171                         L2_500: l2-cache {
 172                                 compatible = "cache";
 173                                 next-level-cache = <&L3_0>;
 174                         };
 175                 };
 176
 177                 CPU6: cpu@600 {
 178                         device_type = "cpu";
 179                         compatible = "arm,kryo";
 180                         reg = <0x0 0x600>;
 181                         enable-method = "psci";
 182                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 183                                            &BIG_CPU_SLEEP_1
 184                                            &CLUSTER_SLEEP_0>;
 185                         next-level-cache = <&L2_600>;
 186                         qcom,freq-domain = <&cpufreq_hw 1>;
 187                         #cooling-cells = <2>;
 188                         L2_600: l2-cache {
 189                                 compatible = "cache";
 190                                 next-level-cache = <&L3_0>;
 191                         };
 192                 };
 193
 194                 CPU7: cpu@700 {
 195                         device_type = "cpu";
 196                         compatible = "arm,kryo";
 197                         reg = <0x0 0x700>;
 198                         enable-method = "psci";
 199                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 200                                            &BIG_CPU_SLEEP_1
 201                                            &CLUSTER_SLEEP_0>;
 202                         next-level-cache = <&L2_700>;
 203                         qcom,freq-domain = <&cpufreq_hw 2>;
 204                         #cooling-cells = <2>;
 205                         L2_700: l2-cache {
 206                                 compatible = "cache";
 207                                 next-level-cache = <&L3_0>;
 208                         };
 209                 };
 210
 211                 idle-states {
 212                         entry-method = "psci";
 213
 214                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 215                                 compatible = "arm,idle-state";
 216                                 idle-state-name = "little-power-down";
 217                                 arm,psci-suspend-param = <0x40000003>;
 218                                 entry-latency-us = <549>;
 219                                 exit-latency-us = <901>;
 220                                 min-residency-us = <1774>;
 221                                 local-timer-stop;
 222                         };
 223
 224                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 225                                 compatible = "arm,idle-state";
 226                                 idle-state-name = "little-rail-power-down";
 227                                 arm,psci-suspend-param = <0x40000004>;
 228                                 entry-latency-us = <702>;
 229                                 exit-latency-us = <915>;
 230                                 min-residency-us = <4001>;
 231                                 local-timer-stop;
 232                         };
 233
 234                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 235                                 compatible = "arm,idle-state";
 236                                 idle-state-name = "big-power-down";
 237                                 arm,psci-suspend-param = <0x40000003>;
 238                                 entry-latency-us = <523>;
 239                                 exit-latency-us = <1244>;
 240                                 min-residency-us = <2207>;
 241                                 local-timer-stop;
 242                         };
 243
 244                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 245                                 compatible = "arm,idle-state";
 246                                 idle-state-name = "big-rail-power-down";
 247                                 arm,psci-suspend-param = <0x40000004>;
 248                                 entry-latency-us = <526>;
 249                                 exit-latency-us = <1854>;
 250                                 min-residency-us = <5555>;
 251                                 local-timer-stop;
 252                         };
 253
 254                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 255                                 compatible = "arm,idle-state";
 256                                 idle-state-name = "cluster-power-down";
 257                                 arm,psci-suspend-param = <0x40003444>;
 258                                 entry-latency-us = <3263>;
 259                                 exit-latency-us = <6562>;
 260                                 min-residency-us = <9926>;
 261                                 local-timer-stop;
 262                         };
 263                 };
 264         };
 265
 266         memory@80000000 {
 267                 device_type = "memory";
 268                 /* We expect the bootloader to fill in the size */
 269                 reg = <0 0x80000000 0 0>;
 270         };
 271
 272         firmware {
 273                 scm {
 274                         compatible = "qcom,scm-sc7280", "qcom,scm";
 275                 };
 276         };
 277
 278         clk_virt: interconnect {
 279                 compatible = "qcom,sc7280-clk-virt";
 280                 #interconnect-cells = <2>;
 281                 qcom,bcm-voters = <&apps_bcm_voter>;
 282         };
 283
 284         smem {
 285                 compatible = "qcom,smem";
 286                 memory-region = <&smem_mem>;
 287                 hwlocks = <&tcsr_mutex 3>;
 288         };
 289
 290         smp2p-adsp {
 291                 compatible = "qcom,smp2p";
 292                 qcom,smem = <443>, <429>;
 293                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 294                                              IPCC_MPROC_SIGNAL_SMP2P
 295                                              IRQ_TYPE_EDGE_RISING>;
 296                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 297                                 IPCC_MPROC_SIGNAL_SMP2P>;
 298
 299                 qcom,local-pid = <0>;
 300                 qcom,remote-pid = <2>;
 301
 302                 adsp_smp2p_out: master-kernel {
 303                         qcom,entry-name = "master-kernel";
 304                         #qcom,smem-state-cells = <1>;
 305                 };
 306
 307                 adsp_smp2p_in: slave-kernel {
 308                         qcom,entry-name = "slave-kernel";
 309                         interrupt-controller;
 310                         #interrupt-cells = <2>;
 311                 };
 312         };
 313
 314         smp2p-cdsp {
 315                 compatible = "qcom,smp2p";
 316                 qcom,smem = <94>, <432>;
 317                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 318                                              IPCC_MPROC_SIGNAL_SMP2P
 319                                              IRQ_TYPE_EDGE_RISING>;
 320                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 321                                 IPCC_MPROC_SIGNAL_SMP2P>;
 322
 323                 qcom,local-pid = <0>;
 324                 qcom,remote-pid = <5>;
 325
 326                 cdsp_smp2p_out: master-kernel {
 327                         qcom,entry-name = "master-kernel";
 328                         #qcom,smem-state-cells = <1>;
 329                 };
 330
 331                 cdsp_smp2p_in: slave-kernel {
 332                         qcom,entry-name = "slave-kernel";
 333                         interrupt-controller;
 334                         #interrupt-cells = <2>;
 335                 };
 336         };
 337
 338         smp2p-mpss {
 339                 compatible = "qcom,smp2p";
 340                 qcom,smem = <435>, <428>;
 341                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 342                                              IPCC_MPROC_SIGNAL_SMP2P
 343                                              IRQ_TYPE_EDGE_RISING>;
 344                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 345                                 IPCC_MPROC_SIGNAL_SMP2P>;
 346
 347                 qcom,local-pid = <0>;
 348                 qcom,remote-pid = <1>;
 349
 350                 modem_smp2p_out: master-kernel {
 351                         qcom,entry-name = "master-kernel";
 352                         #qcom,smem-state-cells = <1>;
 353                 };
 354
 355                 modem_smp2p_in: slave-kernel {
 356                         qcom,entry-name = "slave-kernel";
 357                         interrupt-controller;
 358                         #interrupt-cells = <2>;
 359                 };
 360
 361                 ipa_smp2p_out: ipa-ap-to-modem {
 362                         qcom,entry-name = "ipa";
 363                         #qcom,smem-state-cells = <1>;
 364                 };
 365
 366                 ipa_smp2p_in: ipa-modem-to-ap {
 367                         qcom,entry-name = "ipa";
 368                         interrupt-controller;
 369                         #interrupt-cells = <2>;
 370                 };
 371         };
 372
 373         smp2p-wpss {
 374                 compatible = "qcom,smp2p";
 375                 qcom,smem = <617>, <616>;
 376                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 377                                              IPCC_MPROC_SIGNAL_SMP2P
 378                                              IRQ_TYPE_EDGE_RISING>;
 379                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 380                                 IPCC_MPROC_SIGNAL_SMP2P>;
 381
 382                 qcom,local-pid = <0>;
 383                 qcom,remote-pid = <13>;
 384
 385                 wpss_smp2p_out: master-kernel {
 386                         qcom,entry-name = "master-kernel";
 387                         #qcom,smem-state-cells = <1>;
 388                 };
 389
 390                 wpss_smp2p_in: slave-kernel {
 391                         qcom,entry-name = "slave-kernel";
 392                         interrupt-controller;
 393                         #interrupt-cells = <2>;
 394                 };
 395         };
 396
 397         pmu {
 398                 compatible = "arm,armv8-pmuv3";
 399                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 400         };
 401
 402         psci {
 403                 compatible = "arm,psci-1.0";
 404                 method = "smc";
 405         };
 406
 407         soc: soc@0 {
 408                 #address-cells = <2>;
 409                 #size-cells = <2>;
 410                 ranges = <0 0 0 0 0x10 0>;
 411                 dma-ranges = <0 0 0 0 0x10 0>;
 412                 compatible = "simple-bus";
 413
 414                 gcc: clock-controller@100000 {
 415                         compatible = "qcom,gcc-sc7280";
 416                         reg = <0 0x00100000 0 0x1f0000>;
 417                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 418                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 419                                  <0>, <0>, <0>, <0>, <0>, <0>;
 420                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 421                                       "pcie_0_pipe_clk", "pcie_1_pipe-clk",
 422                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 423                                       "ufs_phy_tx_symbol_0_clk",
 424                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 425                         #clock-cells = <1>;
 426                         #reset-cells = <1>;
 427                         #power-domain-cells = <1>;
 428                 };
 429
 430                 ipcc: mailbox@408000 {
 431                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 432                         reg = <0 0x00408000 0 0x1000>;
 433                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 434                         interrupt-controller;
 435                         #interrupt-cells = <3>;
 436                         #mbox-cells = <2>;
 437                 };
 438
 439                 qupv3_id_0: geniqup@9c0000 {
 440                         compatible = "qcom,geni-se-qup";
 441                         reg = <0 0x009c0000 0 0x2000>;
 442                         clock-names = "m-ahb", "s-ahb";
 443                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 444                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 445                         #address-cells = <2>;
 446                         #size-cells = <2>;
 447                         ranges;
 448                         status = "disabled";
 449
 450                         uart5: serial@994000 {
 451                                 compatible = "qcom,geni-debug-uart";
 452                                 reg = <0 0x00994000 0 0x4000>;
 453                                 clock-names = "se";
 454                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 455                                 pinctrl-names = "default";
 456                                 pinctrl-0 = <&qup_uart5_default>;
 457                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 458                                 status = "disabled";
 459                         };
 460                 };
 461
 462                 cnoc2: interconnect@1500000 {
 463                         reg = <0 0x01500000 0 0x1000>;
 464                         compatible = "qcom,sc7280-cnoc2";
 465                         #interconnect-cells = <2>;
 466                         qcom,bcm-voters = <&apps_bcm_voter>;
 467                 };
 468
 469                 cnoc3: interconnect@1502000 {
 470                         reg = <0 0x01502000 0 0x1000>;
 471                         compatible = "qcom,sc7280-cnoc3";
 472                         #interconnect-cells = <2>;
 473                         qcom,bcm-voters = <&apps_bcm_voter>;
 474                 };
 475
 476                 mc_virt: interconnect@1580000 {
 477                         reg = <0 0x01580000 0 0x4>;
 478                         compatible = "qcom,sc7280-mc-virt";
 479                         #interconnect-cells = <2>;
 480                         qcom,bcm-voters = <&apps_bcm_voter>;
 481                 };
 482
 483                 system_noc: interconnect@1680000 {
 484                         reg = <0 0x01680000 0 0x15480>;
 485                         compatible = "qcom,sc7280-system-noc";
 486                         #interconnect-cells = <2>;
 487                         qcom,bcm-voters = <&apps_bcm_voter>;
 488                 };
 489
 490                 aggre1_noc: interconnect@16e0000 {
 491                         compatible = "qcom,sc7280-aggre1-noc";
 492                         reg = <0 0x016e0000 0 0x1c080>;
 493                         #interconnect-cells = <2>;
 494                         qcom,bcm-voters = <&apps_bcm_voter>;
 495                 };
 496
 497                 aggre2_noc: interconnect@1700000 {
 498                         reg = <0 0x01700000 0 0x2b080>;
 499                         compatible = "qcom,sc7280-aggre2-noc";
 500                         #interconnect-cells = <2>;
 501                         qcom,bcm-voters = <&apps_bcm_voter>;
 502                 };
 503
 504                 mmss_noc: interconnect@1740000 {
 505                         reg = <0 0x01740000 0 0x1e080>;
 506                         compatible = "qcom,sc7280-mmss-noc";
 507                         #interconnect-cells = <2>;
 508                         qcom,bcm-voters = <&apps_bcm_voter>;
 509                 };
 510
 511                 tcsr_mutex: hwlock@1f40000 {
 512                         compatible = "qcom,tcsr-mutex", "syscon";
 513                         reg = <0 0x01f40000 0 0x40000>;
 514                         #hwlock-cells = <1>;
 515                 };
 516
 517                 lpasscc: lpasscc@3000000 {
 518                         compatible = "qcom,sc7280-lpasscc";
 519                         reg = <0 0x03000000 0 0x40>,
 520                               <0 0x03c04000 0 0x4>,
 521                               <0 0x03389000 0 0x24>;
 522                         reg-names = "qdsp6ss", "top_cc", "cc";
 523                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
 524                         clock-names = "iface";
 525                         #clock-cells = <1>;
 526                 };
 527
 528                 lpass_ag_noc: interconnect@3c40000 {
 529                         reg = <0 0x03c40000 0 0xf080>;
 530                         compatible = "qcom,sc7280-lpass-ag-noc";
 531                         #interconnect-cells = <2>;
 532                         qcom,bcm-voters = <&apps_bcm_voter>;
 533                 };
 534
 535                 gpucc: clock-controller@3d90000 {
 536                         compatible = "qcom,sc7280-gpucc";
 537                         reg = <0 0x03d90000 0 0x9000>;
 538                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 539                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
 540                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
 541                         clock-names = "bi_tcxo",
 542                                       "gcc_gpu_gpll0_clk_src",
 543                                       "gcc_gpu_gpll0_div_clk_src";
 544                         #clock-cells = <1>;
 545                         #reset-cells = <1>;
 546                         #power-domain-cells = <1>;
 547                 };
 548
 549                 stm@6002000 {
 550                         compatible = "arm,coresight-stm", "arm,primecell";
 551                         reg = <0 0x06002000 0 0x1000>,
 552                               <0 0x16280000 0 0x180000>;
 553                         reg-names = "stm-base", "stm-stimulus-base";
 554
 555                         clocks = <&aoss_qmp>;
 556                         clock-names = "apb_pclk";
 557
 558                         out-ports {
 559                                 port {
 560                                         stm_out: endpoint {
 561                                                 remote-endpoint = <&funnel0_in7>;
 562                                         };
 563                                 };
 564                         };
 565                 };
 566
 567                 funnel@6041000 {
 568                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 569                         reg = <0 0x06041000 0 0x1000>;
 570
 571                         clocks = <&aoss_qmp>;
 572                         clock-names = "apb_pclk";
 573
 574                         out-ports {
 575                                 port {
 576                                         funnel0_out: endpoint {
 577                                                 remote-endpoint = <&merge_funnel_in0>;
 578                                         };
 579                                 };
 580                         };
 581
 582                         in-ports {
 583                                 #address-cells = <1>;
 584                                 #size-cells = <0>;
 585
 586                                 port@7 {
 587                                         reg = <7>;
 588                                         funnel0_in7: endpoint {
 589                                                 remote-endpoint = <&stm_out>;
 590                                         };
 591                                 };
 592                         };
 593                 };
 594
 595                 funnel@6042000 {
 596                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 597                         reg = <0 0x06042000 0 0x1000>;
 598
 599                         clocks = <&aoss_qmp>;
 600                         clock-names = "apb_pclk";
 601
 602                         out-ports {
 603                                 port {
 604                                         funnel1_out: endpoint {
 605                                                 remote-endpoint = <&merge_funnel_in1>;
 606                                         };
 607                                 };
 608                         };
 609
 610                         in-ports {
 611                                 #address-cells = <1>;
 612                                 #size-cells = <0>;
 613
 614                                 port@4 {
 615                                         reg = <4>;
 616                                         funnel1_in4: endpoint {
 617                                                 remote-endpoint = <&apss_merge_funnel_out>;
 618                                         };
 619                                 };
 620                         };
 621                 };
 622
 623                 funnel@6045000 {
 624                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 625                         reg = <0 0x06045000 0 0x1000>;
 626
 627                         clocks = <&aoss_qmp>;
 628                         clock-names = "apb_pclk";
 629
 630                         out-ports {
 631                                 port {
 632                                         merge_funnel_out: endpoint {
 633                                                 remote-endpoint = <&swao_funnel_in>;
 634                                         };
 635                                 };
 636                         };
 637
 638                         in-ports {
 639                                 #address-cells = <1>;
 640                                 #size-cells = <0>;
 641
 642                                 port@0 {
 643                                         reg = <0>;
 644                                         merge_funnel_in0: endpoint {
 645                                                 remote-endpoint = <&funnel0_out>;
 646                                         };
 647                                 };
 648
 649                                 port@1 {
 650                                         reg = <1>;
 651                                         merge_funnel_in1: endpoint {
 652                                                 remote-endpoint = <&funnel1_out>;
 653                                         };
 654                                 };
 655                         };
 656                 };
 657
 658                 replicator@6046000 {
 659                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 660                         reg = <0 0x06046000 0 0x1000>;
 661
 662                         clocks = <&aoss_qmp>;
 663                         clock-names = "apb_pclk";
 664
 665                         out-ports {
 666                                 port {
 667                                         replicator_out: endpoint {
 668                                                 remote-endpoint = <&etr_in>;
 669                                         };
 670                                 };
 671                         };
 672
 673                         in-ports {
 674                                 port {
 675                                         replicator_in: endpoint {
 676                                                 remote-endpoint = <&swao_replicator_out>;
 677                                         };
 678                                 };
 679                         };
 680                 };
 681
 682                 etr@6048000 {
 683                         compatible = "arm,coresight-tmc", "arm,primecell";
 684                         reg = <0 0x06048000 0 0x1000>;
 685                         iommus = <&apps_smmu 0x04c0 0>;
 686
 687                         clocks = <&aoss_qmp>;
 688                         clock-names = "apb_pclk";
 689                         arm,scatter-gather;
 690
 691                         in-ports {
 692                                 port {
 693                                         etr_in: endpoint {
 694                                                 remote-endpoint = <&replicator_out>;
 695                                         };
 696                                 };
 697                         };
 698                 };
 699
 700                 funnel@6b04000 {
 701                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 702                         reg = <0 0x06b04000 0 0x1000>;
 703
 704                         clocks = <&aoss_qmp>;
 705                         clock-names = "apb_pclk";
 706
 707                         out-ports {
 708                                 port {
 709                                         swao_funnel_out: endpoint {
 710                                                 remote-endpoint = <&etf_in>;
 711                                         };
 712                                 };
 713                         };
 714
 715                         in-ports {
 716                                 #address-cells = <1>;
 717                                 #size-cells = <0>;
 718
 719                                 port@7 {
 720                                         reg = <7>;
 721                                         swao_funnel_in: endpoint {
 722                                                 remote-endpoint = <&merge_funnel_out>;
 723                                         };
 724                                 };
 725                         };
 726                 };
 727
 728                 etf@6b05000 {
 729                         compatible = "arm,coresight-tmc", "arm,primecell";
 730                         reg = <0 0x06b05000 0 0x1000>;
 731
 732                         clocks = <&aoss_qmp>;
 733                         clock-names = "apb_pclk";
 734
 735                         out-ports {
 736                                 port {
 737                                         etf_out: endpoint {
 738                                                 remote-endpoint = <&swao_replicator_in>;
 739                                         };
 740                                 };
 741                         };
 742
 743                         in-ports {
 744                                 port {
 745                                         etf_in: endpoint {
 746                                                 remote-endpoint = <&swao_funnel_out>;
 747                                         };
 748                                 };
 749                         };
 750                 };
 751
 752                 replicator@6b06000 {
 753                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 754                         reg = <0 0x06b06000 0 0x1000>;
 755
 756                         clocks = <&aoss_qmp>;
 757                         clock-names = "apb_pclk";
 758                         qcom,replicator-loses-context;
 759
 760                         out-ports {
 761                                 port {
 762                                         swao_replicator_out: endpoint {
 763                                                 remote-endpoint = <&replicator_in>;
 764                                         };
 765                                 };
 766                         };
 767
 768                         in-ports {
 769                                 port {
 770                                         swao_replicator_in: endpoint {
 771                                                 remote-endpoint = <&etf_out>;
 772                                         };
 773                                 };
 774                         };
 775                 };
 776
 777                 etm@7040000 {
 778                         compatible = "arm,coresight-etm4x", "arm,primecell";
 779                         reg = <0 0x07040000 0 0x1000>;
 780
 781                         cpu = <&CPU0>;
 782
 783                         clocks = <&aoss_qmp>;
 784                         clock-names = "apb_pclk";
 785                         arm,coresight-loses-context-with-cpu;
 786                         qcom,skip-power-up;
 787
 788                         out-ports {
 789                                 port {
 790                                         etm0_out: endpoint {
 791                                                 remote-endpoint = <&apss_funnel_in0>;
 792                                         };
 793                                 };
 794                         };
 795                 };
 796
 797                 etm@7140000 {
 798                         compatible = "arm,coresight-etm4x", "arm,primecell";
 799                         reg = <0 0x07140000 0 0x1000>;
 800
 801                         cpu = <&CPU1>;
 802
 803                         clocks = <&aoss_qmp>;
 804                         clock-names = "apb_pclk";
 805                         arm,coresight-loses-context-with-cpu;
 806                         qcom,skip-power-up;
 807
 808                         out-ports {
 809                                 port {
 810                                         etm1_out: endpoint {
 811                                                 remote-endpoint = <&apss_funnel_in1>;
 812                                         };
 813                                 };
 814                         };
 815                 };
 816
 817                 etm@7240000 {
 818                         compatible = "arm,coresight-etm4x", "arm,primecell";
 819                         reg = <0 0x07240000 0 0x1000>;
 820
 821                         cpu = <&CPU2>;
 822
 823                         clocks = <&aoss_qmp>;
 824                         clock-names = "apb_pclk";
 825                         arm,coresight-loses-context-with-cpu;
 826                         qcom,skip-power-up;
 827
 828                         out-ports {
 829                                 port {
 830                                         etm2_out: endpoint {
 831                                                 remote-endpoint = <&apss_funnel_in2>;
 832                                         };
 833                                 };
 834                         };
 835                 };
 836
 837                 etm@7340000 {
 838                         compatible = "arm,coresight-etm4x", "arm,primecell";
 839                         reg = <0 0x07340000 0 0x1000>;
 840
 841                         cpu = <&CPU3>;
 842
 843                         clocks = <&aoss_qmp>;
 844                         clock-names = "apb_pclk";
 845                         arm,coresight-loses-context-with-cpu;
 846                         qcom,skip-power-up;
 847
 848                         out-ports {
 849                                 port {
 850                                         etm3_out: endpoint {
 851                                                 remote-endpoint = <&apss_funnel_in3>;
 852                                         };
 853                                 };
 854                         };
 855                 };
 856
 857                 etm@7440000 {
 858                         compatible = "arm,coresight-etm4x", "arm,primecell";
 859                         reg = <0 0x07440000 0 0x1000>;
 860
 861                         cpu = <&CPU4>;
 862
 863                         clocks = <&aoss_qmp>;
 864                         clock-names = "apb_pclk";
 865                         arm,coresight-loses-context-with-cpu;
 866                         qcom,skip-power-up;
 867
 868                         out-ports {
 869                                 port {
 870                                         etm4_out: endpoint {
 871                                                 remote-endpoint = <&apss_funnel_in4>;
 872                                         };
 873                                 };
 874                         };
 875                 };
 876
 877                 etm@7540000 {
 878                         compatible = "arm,coresight-etm4x", "arm,primecell";
 879                         reg = <0 0x07540000 0 0x1000>;
 880
 881                         cpu = <&CPU5>;
 882
 883                         clocks = <&aoss_qmp>;
 884                         clock-names = "apb_pclk";
 885                         arm,coresight-loses-context-with-cpu;
 886                         qcom,skip-power-up;
 887
 888                         out-ports {
 889                                 port {
 890                                         etm5_out: endpoint {
 891                                                 remote-endpoint = <&apss_funnel_in5>;
 892                                         };
 893                                 };
 894                         };
 895                 };
 896
 897                 etm@7640000 {
 898                         compatible = "arm,coresight-etm4x", "arm,primecell";
 899                         reg = <0 0x07640000 0 0x1000>;
 900
 901                         cpu = <&CPU6>;
 902
 903                         clocks = <&aoss_qmp>;
 904                         clock-names = "apb_pclk";
 905                         arm,coresight-loses-context-with-cpu;
 906                         qcom,skip-power-up;
 907
 908                         out-ports {
 909                                 port {
 910                                         etm6_out: endpoint {
 911                                                 remote-endpoint = <&apss_funnel_in6>;
 912                                         };
 913                                 };
 914                         };
 915                 };
 916
 917                 etm@7740000 {
 918                         compatible = "arm,coresight-etm4x", "arm,primecell";
 919                         reg = <0 0x07740000 0 0x1000>;
 920
 921                         cpu = <&CPU7>;
 922
 923                         clocks = <&aoss_qmp>;
 924                         clock-names = "apb_pclk";
 925                         arm,coresight-loses-context-with-cpu;
 926                         qcom,skip-power-up;
 927
 928                         out-ports {
 929                                 port {
 930                                         etm7_out: endpoint {
 931                                                 remote-endpoint = <&apss_funnel_in7>;
 932                                         };
 933                                 };
 934                         };
 935                 };
 936
 937                 funnel@7800000 { /* APSS Funnel */
 938                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 939                         reg = <0 0x07800000 0 0x1000>;
 940
 941                         clocks = <&aoss_qmp>;
 942                         clock-names = "apb_pclk";
 943
 944                         out-ports {
 945                                 port {
 946                                         apss_funnel_out: endpoint {
 947                                                 remote-endpoint = <&apss_merge_funnel_in>;
 948                                         };
 949                                 };
 950                         };
 951
 952                         in-ports {
 953                                 #address-cells = <1>;
 954                                 #size-cells = <0>;
 955
 956                                 port@0 {
 957                                         reg = <0>;
 958                                         apss_funnel_in0: endpoint {
 959                                                 remote-endpoint = <&etm0_out>;
 960                                         };
 961                                 };
 962
 963                                 port@1 {
 964                                         reg = <1>;
 965                                         apss_funnel_in1: endpoint {
 966                                                 remote-endpoint = <&etm1_out>;
 967                                         };
 968                                 };
 969
 970                                 port@2 {
 971                                         reg = <2>;
 972                                         apss_funnel_in2: endpoint {
 973                                                 remote-endpoint = <&etm2_out>;
 974                                         };
 975                                 };
 976
 977                                 port@3 {
 978                                         reg = <3>;
 979                                         apss_funnel_in3: endpoint {
 980                                                 remote-endpoint = <&etm3_out>;
 981                                         };
 982                                 };
 983
 984                                 port@4 {
 985                                         reg = <4>;
 986                                         apss_funnel_in4: endpoint {
 987                                                 remote-endpoint = <&etm4_out>;
 988                                         };
 989                                 };
 990
 991                                 port@5 {
 992                                         reg = <5>;
 993                                         apss_funnel_in5: endpoint {
 994                                                 remote-endpoint = <&etm5_out>;
 995                                         };
 996                                 };
 997
 998                                 port@6 {
 999                                         reg = <6>;
1000                                         apss_funnel_in6: endpoint {
1001                                                 remote-endpoint = <&etm6_out>;
1002                                         };
1003                                 };
1004
1005                                 port@7 {
1006                                         reg = <7>;
1007                                         apss_funnel_in7: endpoint {
1008                                                 remote-endpoint = <&etm7_out>;
1009                                         };
1010                                 };
1011                         };
1012                 };
1013
1014                 funnel@7810000 {
1015                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1016                         reg = <0 0x07810000 0 0x1000>;
1017
1018                         clocks = <&aoss_qmp>;
1019                         clock-names = "apb_pclk";
1020
1021                         out-ports {
1022                                 port {
1023                                         apss_merge_funnel_out: endpoint {
1024                                                 remote-endpoint = <&funnel1_in4>;
1025                                         };
1026                                 };
1027                         };
1028
1029                         in-ports {
1030                                 port {
1031                                         apss_merge_funnel_in: endpoint {
1032                                                 remote-endpoint = <&apss_funnel_out>;
1033                                         };
1034                                 };
1035                         };
1036                 };
1037
1038                 usb_1_hsphy: phy@88e3000 {
1039                         compatible = "qcom,sc7280-usb-hs-phy",
1040                                      "qcom,usb-snps-hs-7nm-phy";
1041                         reg = <0 0x088e3000 0 0x400>;
1042                         status = "disabled";
1043                         #phy-cells = <0>;
1044
1045                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1046                         clock-names = "ref";
1047
1048                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1049                 };
1050
1051                 usb_2_hsphy: phy@88e4000 {
1052                         compatible = "qcom,sc7280-usb-hs-phy",
1053                                      "qcom,usb-snps-hs-7nm-phy";
1054                         reg = <0 0x088e4000 0 0x400>;
1055                         status = "disabled";
1056                         #phy-cells = <0>;
1057
1058                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1059                         clock-names = "ref";
1060
1061                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1062                 };
1063
1064                 usb_1_qmpphy: phy-wrapper@88e9000 {
1065                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
1066                                      "qcom,sm8250-qmp-usb3-dp-phy";
1067                         reg = <0 0x088e9000 0 0x200>,
1068                               <0 0x088e8000 0 0x40>,
1069                               <0 0x088ea000 0 0x200>;
1070                         status = "disabled";
1071                         #address-cells = <2>;
1072                         #size-cells = <2>;
1073                         ranges;
1074
1075                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1076                                  <&rpmhcc RPMH_CXO_CLK>,
1077                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1078                         clock-names = "aux", "ref_clk_src", "com_aux";
1079
1080                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1081                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1082                         reset-names = "phy", "common";
1083
1084                         usb_1_ssphy: usb3-phy@88e9200 {
1085                                 reg = <0 0x088e9200 0 0x200>,
1086                                       <0 0x088e9400 0 0x200>,
1087                                       <0 0x088e9c00 0 0x400>,
1088                                       <0 0x088e9600 0 0x200>,
1089                                       <0 0x088e9800 0 0x200>,
1090                                       <0 0x088e9a00 0 0x100>;
1091                                 #clock-cells = <0>;
1092                                 #phy-cells = <0>;
1093                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1094                                 clock-names = "pipe0";
1095                                 clock-output-names = "usb3_phy_pipe_clk_src";
1096                         };
1097
1098                         dp_phy: dp-phy@88ea200 {
1099                                 reg = <0 0x088ea200 0 0x200>,
1100                                       <0 0x088ea400 0 0x200>,
1101                                       <0 0x088eac00 0 0x400>,
1102                                       <0 0x088ea600 0 0x200>,
1103                                       <0 0x088ea800 0 0x200>,
1104                                       <0 0x088eaa00 0 0x100>;
1105                                 #phy-cells = <0>;
1106                                 #clock-cells = <1>;
1107                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1108                                 clock-names = "pipe0";
1109                                 clock-output-names = "usb3_phy_pipe_clk_src";
1110                         };
1111                 };
1112
1113                 usb_2: usb@8cf8800 {
1114                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1115                         reg = <0 0x08cf8800 0 0x400>;
1116                         status = "disabled";
1117                         #address-cells = <2>;
1118                         #size-cells = <2>;
1119                         ranges;
1120                         dma-ranges;
1121
1122                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1123                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1124                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1125                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1126                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
1127                         clock-names = "cfg_noc", "core", "iface","mock_utmi",
1128                                       "sleep";
1129
1130                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1131                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1132                         assigned-clock-rates = <19200000>, <200000000>;
1133
1134                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1135                                      <&pdc 13 IRQ_TYPE_EDGE_RISING>,
1136                                      <&pdc 12 IRQ_TYPE_EDGE_RISING>;
1137                         interrupt-names = "hs_phy_irq",
1138                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
1139
1140                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
1141
1142                         resets = <&gcc GCC_USB30_SEC_BCR>;
1143
1144                         usb_2_dwc3: usb@8c00000 {
1145                                 compatible = "snps,dwc3";
1146                                 reg = <0 0x08c00000 0 0xe000>;
1147                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1148                                 iommus = <&apps_smmu 0xa0 0x0>;
1149                                 snps,dis_u2_susphy_quirk;
1150                                 snps,dis_enblslpm_quirk;
1151                                 phys = <&usb_2_hsphy>;
1152                                 phy-names = "usb2-phy";
1153                                 maximum-speed = "high-speed";
1154                         };
1155                 };
1156
1157                 dc_noc: interconnect@90e0000 {
1158                         reg = <0 0x090e0000 0 0x5080>;
1159                         compatible = "qcom,sc7280-dc-noc";
1160                         #interconnect-cells = <2>;
1161                         qcom,bcm-voters = <&apps_bcm_voter>;
1162                 };
1163
1164                 gem_noc: interconnect@9100000 {
1165                         reg = <0 0x9100000 0 0xe2200>;
1166                         compatible = "qcom,sc7280-gem-noc";
1167                         #interconnect-cells = <2>;
1168                         qcom,bcm-voters = <&apps_bcm_voter>;
1169                 };
1170
1171                 system-cache-controller@9200000 {
1172                         compatible = "qcom,sc7280-llcc";
1173                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
1174                         reg-names = "llcc_base", "llcc_broadcast_base";
1175                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1176                 };
1177
1178                 nsp_noc: interconnect@a0c0000 {
1179                         reg = <0 0x0a0c0000 0 0x10000>;
1180                         compatible = "qcom,sc7280-nsp-noc";
1181                         #interconnect-cells = <2>;
1182                         qcom,bcm-voters = <&apps_bcm_voter>;
1183                 };
1184
1185                 usb_1: usb@a6f8800 {
1186                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1187                         reg = <0 0x0a6f8800 0 0x400>;
1188                         status = "disabled";
1189                         #address-cells = <2>;
1190                         #size-cells = <2>;
1191                         ranges;
1192                         dma-ranges;
1193
1194                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1195                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1196                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1197                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1198                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1199                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1200                                       "sleep";
1201
1202                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1203                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1204                         assigned-clock-rates = <19200000>, <200000000>;
1205
1206                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1207                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1208                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1209                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1210                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1211                                           "dm_hs_phy_irq", "ss_phy_irq";
1212
1213                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1214
1215                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1216
1217                         usb_1_dwc3: usb@a600000 {
1218                                 compatible = "snps,dwc3";
1219                                 reg = <0 0x0a600000 0 0xe000>;
1220                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1221                                 iommus = <&apps_smmu 0xe0 0x0>;
1222                                 snps,dis_u2_susphy_quirk;
1223                                 snps,dis_enblslpm_quirk;
1224                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1225                                 phy-names = "usb2-phy", "usb3-phy";
1226                                 maximum-speed = "super-speed";
1227                         };
1228                 };
1229
1230                 videocc: clock-controller@aaf0000 {
1231                         compatible = "qcom,sc7280-videocc";
1232                         reg = <0 0xaaf0000 0 0x10000>;
1233                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1234                                 <&rpmhcc RPMH_CXO_CLK_A>;
1235                         clock-names = "bi_tcxo", "bi_tcxo_ao";
1236                         #clock-cells = <1>;
1237                         #reset-cells = <1>;
1238                         #power-domain-cells = <1>;
1239                 };
1240
1241                 dispcc: clock-controller@af00000 {
1242                         compatible = "qcom,sc7280-dispcc";
1243                         reg = <0 0xaf00000 0 0x20000>;
1244                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1245                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1246                                  <0>, <0>, <0>, <0>, <0>, <0>;
1247                         clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
1248                                       "dsi0_phy_pll_out_byteclk",
1249                                       "dsi0_phy_pll_out_dsiclk",
1250                                       "dp_phy_pll_link_clk",
1251                                       "dp_phy_pll_vco_div_clk",
1252                                       "edp_phy_pll_link_clk",
1253                                       "edp_phy_pll_vco_div_clk";
1254                         #clock-cells = <1>;
1255                         #reset-cells = <1>;
1256                         #power-domain-cells = <1>;
1257                 };
1258
1259                 pdc: interrupt-controller@b220000 {
1260                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
1261                         reg = <0 0x0b220000 0 0x30000>;
1262                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
1263                                           <55 306 4>, <59 312 3>, <62 374 2>,
1264                                           <64 434 2>, <66 438 3>, <69 86 1>,
1265                                           <70 520 54>, <124 609 31>, <155 63 1>,
1266                                           <156 716 12>;
1267                         #interrupt-cells = <2>;
1268                         interrupt-parent = <&intc>;
1269                         interrupt-controller;
1270                 };
1271
1272                 pdc_reset: reset-controller@b5e0000 {
1273                         compatible = "qcom,sc7280-pdc-global";
1274                         reg = <0 0x0b5e0000 0 0x20000>;
1275                         #reset-cells = <1>;
1276                 };
1277
1278                 tsens0: thermal-sensor@c263000 {
1279                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1280                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1281                                 <0 0x0c222000 0 0x1ff>; /* SROT */
1282                         #qcom,sensors = <15>;
1283                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1284                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1285                         interrupt-names = "uplow","critical";
1286                         #thermal-sensor-cells = <1>;
1287                 };
1288
1289                 tsens1: thermal-sensor@c265000 {
1290                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1291                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1292                                 <0 0x0c223000 0 0x1ff>; /* SROT */
1293                         #qcom,sensors = <12>;
1294                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1295                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1296                         interrupt-names = "uplow","critical";
1297                         #thermal-sensor-cells = <1>;
1298                 };
1299
1300                 aoss_reset: reset-controller@c2a0000 {
1301                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
1302                         reg = <0 0x0c2a0000 0 0x31000>;
1303                         #reset-cells = <1>;
1304                 };
1305
1306                 aoss_qmp: power-controller@c300000 {
1307                         compatible = "qcom,sc7280-aoss-qmp";
1308                         reg = <0 0x0c300000 0 0x100000>;
1309                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1310                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
1311                                                      IRQ_TYPE_EDGE_RISING>;
1312                         mboxes = <&ipcc IPCC_CLIENT_AOP
1313                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
1314
1315                         #clock-cells = <0>;
1316                         #power-domain-cells = <1>;
1317                 };
1318
1319                 spmi_bus: spmi@c440000 {
1320                         compatible = "qcom,spmi-pmic-arb";
1321                         reg = <0 0x0c440000 0 0x1100>,
1322                               <0 0x0c600000 0 0x2000000>,
1323                               <0 0x0e600000 0 0x100000>,
1324                               <0 0x0e700000 0 0xa0000>,
1325                               <0 0x0c40a000 0 0x26000>;
1326                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1327                         interrupt-names = "periph_irq";
1328                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1329                         qcom,ee = <0>;
1330                         qcom,channel = <0>;
1331                         #address-cells = <1>;
1332                         #size-cells = <1>;
1333                         interrupt-controller;
1334                         #interrupt-cells = <4>;
1335                 };
1336
1337                 tlmm: pinctrl@f100000 {
1338                         compatible = "qcom,sc7280-pinctrl";
1339                         reg = <0 0x0f100000 0 0x300000>;
1340                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1341                         gpio-controller;
1342                         #gpio-cells = <2>;
1343                         interrupt-controller;
1344                         #interrupt-cells = <2>;
1345                         gpio-ranges = <&tlmm 0 0 175>;
1346                         wakeup-parent = <&pdc>;
1347
1348                         qup_uart5_default: qup-uart5-default {
1349                                 pins = "gpio46", "gpio47";
1350                                 function = "qup13";
1351                         };
1352                 };
1353
1354                 apps_smmu: iommu@15000000 {
1355                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
1356                         reg = <0 0x15000000 0 0x100000>;
1357                         #iommu-cells = <2>;
1358                         #global-interrupts = <1>;
1359                         dma-coherent;
1360                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1361                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1362                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1363                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1364                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1365                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1366                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1367                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1368                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1369                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1370                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1371                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1372                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1373                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1374                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1375                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1376                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1377                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1378                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1379                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1380                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1381                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1382                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1383                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1384                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1385                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1386                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1387                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1388                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1389                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1390                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1391                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1392                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1393                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1394                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1395                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1396                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1397                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1398                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1399                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1400                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1401                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1402                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1403                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1404                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1405                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1406                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1407                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1408                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1409                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1410                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1411                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1412                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1413                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1414                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1415                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1416                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1417                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1418                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1419                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1420                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1421                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1422                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1423                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1424                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1425                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1426                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1427                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1428                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1429                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1430                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1431                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1432                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1433                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1434                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1435                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1436                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1437                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1438                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1439                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1440                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1441                 };
1442
1443                 intc: interrupt-controller@17a00000 {
1444                         compatible = "arm,gic-v3";
1445                         #address-cells = <2>;
1446                         #size-cells = <2>;
1447                         ranges;
1448                         #interrupt-cells = <3>;
1449                         interrupt-controller;
1450                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
1451                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
1452                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1453
1454                         gic-its@17a40000 {
1455                                 compatible = "arm,gic-v3-its";
1456                                 msi-controller;
1457                                 #msi-cells = <1>;
1458                                 reg = <0 0x17a40000 0 0x20000>;
1459                                 status = "disabled";
1460                         };
1461                 };
1462
1463                 watchdog@17c10000 {
1464                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
1465                         reg = <0 0x17c10000 0 0x1000>;
1466                         clocks = <&sleep_clk>;
1467                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1468                 };
1469
1470                 timer@17c20000 {
1471                         #address-cells = <2>;
1472                         #size-cells = <2>;
1473                         ranges;
1474                         compatible = "arm,armv7-timer-mem";
1475                         reg = <0 0x17c20000 0 0x1000>;
1476
1477                         frame@17c21000 {
1478                                 frame-number = <0>;
1479                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1480                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1481                                 reg = <0 0x17c21000 0 0x1000>,
1482                                       <0 0x17c22000 0 0x1000>;
1483                         };
1484
1485                         frame@17c23000 {
1486                                 frame-number = <1>;
1487                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1488                                 reg = <0 0x17c23000 0 0x1000>;
1489                                 status = "disabled";
1490                         };
1491
1492                         frame@17c25000 {
1493                                 frame-number = <2>;
1494                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1495                                 reg = <0 0x17c25000 0 0x1000>;
1496                                 status = "disabled";
1497                         };
1498
1499                         frame@17c27000 {
1500                                 frame-number = <3>;
1501                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1502                                 reg = <0 0x17c27000 0 0x1000>;
1503                                 status = "disabled";
1504                         };
1505
1506                         frame@17c29000 {
1507                                 frame-number = <4>;
1508                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1509                                 reg = <0 0x17c29000 0 0x1000>;
1510                                 status = "disabled";
1511                         };
1512
1513                         frame@17c2b000 {
1514                                 frame-number = <5>;
1515                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1516                                 reg = <0 0x17c2b000 0 0x1000>;
1517                                 status = "disabled";
1518                         };
1519
1520                         frame@17c2d000 {
1521                                 frame-number = <6>;
1522                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1523                                 reg = <0 0x17c2d000 0 0x1000>;
1524                                 status = "disabled";
1525                         };
1526                 };
1527
1528                 apps_rsc: rsc@18200000 {
1529                         compatible = "qcom,rpmh-rsc";
1530                         reg = <0 0x18200000 0 0x10000>,
1531                               <0 0x18210000 0 0x10000>,
1532                               <0 0x18220000 0 0x10000>;
1533                         reg-names = "drv-0", "drv-1", "drv-2";
1534                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1535                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1536                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1537                         qcom,tcs-offset = <0xd00>;
1538                         qcom,drv-id = <2>;
1539                         qcom,tcs-config = <ACTIVE_TCS  2>,
1540                                           <SLEEP_TCS   3>,
1541                                           <WAKE_TCS    3>,
1542                                           <CONTROL_TCS 1>;
1543
1544                         apps_bcm_voter: bcm-voter {
1545                                 compatible = "qcom,bcm-voter";
1546                         };
1547
1548                         rpmhpd: power-controller {
1549                                 compatible = "qcom,sc7280-rpmhpd";
1550                                 #power-domain-cells = <1>;
1551                                 operating-points-v2 = <&rpmhpd_opp_table>;
1552
1553                                 rpmhpd_opp_table: opp-table {
1554                                         compatible = "operating-points-v2";
1555
1556                                         rpmhpd_opp_ret: opp1 {
1557                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1558                                         };
1559
1560                                         rpmhpd_opp_low_svs: opp2 {
1561                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1562                                         };
1563
1564                                         rpmhpd_opp_svs: opp3 {
1565                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1566                                         };
1567
1568                                         rpmhpd_opp_svs_l1: opp4 {
1569                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1570                                         };
1571
1572                                         rpmhpd_opp_svs_l2: opp5 {
1573                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1574                                         };
1575
1576                                         rpmhpd_opp_nom: opp6 {
1577                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1578                                         };
1579
1580                                         rpmhpd_opp_nom_l1: opp7 {
1581                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1582                                         };
1583
1584                                         rpmhpd_opp_turbo: opp8 {
1585                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1586                                         };
1587
1588                                         rpmhpd_opp_turbo_l1: opp9 {
1589                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1590                                         };
1591                                 };
1592                         };
1593
1594                         rpmhcc: clock-controller {
1595                                 compatible = "qcom,sc7280-rpmh-clk";
1596                                 clocks = <&xo_board>;
1597                                 clock-names = "xo";
1598                                 #clock-cells = <1>;
1599                         };
1600                 };
1601
1602                 cpufreq_hw: cpufreq@18591000 {
1603                         compatible = "qcom,cpufreq-epss";
1604                         reg = <0 0x18591000 0 0x1000>,
1605                               <0 0x18592000 0 0x1000>,
1606                               <0 0x18593000 0 0x1000>;
1607                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1608                         clock-names = "xo", "alternate";
1609                         #freq-domain-cells = <1>;
1610                 };
1611         };
1612
1613         thermal_zones: thermal-zones {
1614                 cpu0-thermal {
1615                         polling-delay-passive = <250>;
1616                         polling-delay = <0>;
1617
1618                         thermal-sensors = <&tsens0 1>;
1619
1620                         trips {
1621                                 cpu0_alert0: trip-point0 {
1622                                         temperature = <90000>;
1623                                         hysteresis = <2000>;
1624                                         type = "passive";
1625                                 };
1626
1627                                 cpu0_alert1: trip-point1 {
1628                                         temperature = <95000>;
1629                                         hysteresis = <2000>;
1630                                         type = "passive";
1631                                 };
1632
1633                                 cpu0_crit: cpu-crit {
1634                                         temperature = <110000>;
1635                                         hysteresis = <0>;
1636                                         type = "critical";
1637                                 };
1638                         };
1639
1640                         cooling-maps {
1641                                 map0 {
1642                                         trip = <&cpu0_alert0>;
1643                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1644                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1645                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1646                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1647                                 };
1648                                 map1 {
1649                                         trip = <&cpu0_alert1>;
1650                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1651                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1652                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1653                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1654                                 };
1655                         };
1656                 };
1657
1658                 cpu1-thermal {
1659                         polling-delay-passive = <250>;
1660                         polling-delay = <0>;
1661
1662                         thermal-sensors = <&tsens0 2>;
1663
1664                         trips {
1665                                 cpu1_alert0: trip-point0 {
1666                                         temperature = <90000>;
1667                                         hysteresis = <2000>;
1668                                         type = "passive";
1669                                 };
1670
1671                                 cpu1_alert1: trip-point1 {
1672                                         temperature = <95000>;
1673                                         hysteresis = <2000>;
1674                                         type = "passive";
1675                                 };
1676
1677                                 cpu1_crit: cpu-crit {
1678                                         temperature = <110000>;
1679                                         hysteresis = <0>;
1680                                         type = "critical";
1681                                 };
1682                         };
1683
1684                         cooling-maps {
1685                                 map0 {
1686                                         trip = <&cpu1_alert0>;
1687                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1688                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1689                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1690                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1691                                 };
1692                                 map1 {
1693                                         trip = <&cpu1_alert1>;
1694                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1695                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1696                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1697                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1698                                 };
1699                         };
1700                 };
1701
1702                 cpu2-thermal {
1703                         polling-delay-passive = <250>;
1704                         polling-delay = <0>;
1705
1706                         thermal-sensors = <&tsens0 3>;
1707
1708                         trips {
1709                                 cpu2_alert0: trip-point0 {
1710                                         temperature = <90000>;
1711                                         hysteresis = <2000>;
1712                                         type = "passive";
1713                                 };
1714
1715                                 cpu2_alert1: trip-point1 {
1716                                         temperature = <95000>;
1717                                         hysteresis = <2000>;
1718                                         type = "passive";
1719                                 };
1720
1721                                 cpu2_crit: cpu-crit {
1722                                         temperature = <110000>;
1723                                         hysteresis = <0>;
1724                                         type = "critical";
1725                                 };
1726                         };
1727
1728                         cooling-maps {
1729                                 map0 {
1730                                         trip = <&cpu2_alert0>;
1731                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1732                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1733                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1734                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1735                                 };
1736                                 map1 {
1737                                         trip = <&cpu2_alert1>;
1738                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1739                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1740                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1741                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1742                                 };
1743                         };
1744                 };
1745
1746                 cpu3-thermal {
1747                         polling-delay-passive = <250>;
1748                         polling-delay = <0>;
1749
1750                         thermal-sensors = <&tsens0 4>;
1751
1752                         trips {
1753                                 cpu3_alert0: trip-point0 {
1754                                         temperature = <90000>;
1755                                         hysteresis = <2000>;
1756                                         type = "passive";
1757                                 };
1758
1759                                 cpu3_alert1: trip-point1 {
1760                                         temperature = <95000>;
1761                                         hysteresis = <2000>;
1762                                         type = "passive";
1763                                 };
1764
1765                                 cpu3_crit: cpu-crit {
1766                                         temperature = <110000>;
1767                                         hysteresis = <0>;
1768                                         type = "critical";
1769                                 };
1770                         };
1771
1772                         cooling-maps {
1773                                 map0 {
1774                                         trip = <&cpu3_alert0>;
1775                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1776                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1777                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1778                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1779                                 };
1780                                 map1 {
1781                                         trip = <&cpu3_alert1>;
1782                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1783                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1784                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1785                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1786                                 };
1787                         };
1788                 };
1789
1790                 cpu4-thermal {
1791                         polling-delay-passive = <250>;
1792                         polling-delay = <0>;
1793
1794                         thermal-sensors = <&tsens0 7>;
1795
1796                         trips {
1797                                 cpu4_alert0: trip-point0 {
1798                                         temperature = <90000>;
1799                                         hysteresis = <2000>;
1800                                         type = "passive";
1801                                 };
1802
1803                                 cpu4_alert1: trip-point1 {
1804                                         temperature = <95000>;
1805                                         hysteresis = <2000>;
1806                                         type = "passive";
1807                                 };
1808
1809                                 cpu4_crit: cpu-crit {
1810                                         temperature = <110000>;
1811                                         hysteresis = <0>;
1812                                         type = "critical";
1813                                 };
1814                         };
1815
1816                         cooling-maps {
1817                                 map0 {
1818                                         trip = <&cpu4_alert0>;
1819                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1820                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1821                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1822                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1823                                 };
1824                                 map1 {
1825                                         trip = <&cpu4_alert1>;
1826                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1827                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1828                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1829                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1830                                 };
1831                         };
1832                 };
1833
1834                 cpu5-thermal {
1835                         polling-delay-passive = <250>;
1836                         polling-delay = <0>;
1837
1838                         thermal-sensors = <&tsens0 8>;
1839
1840                         trips {
1841                                 cpu5_alert0: trip-point0 {
1842                                         temperature = <90000>;
1843                                         hysteresis = <2000>;
1844                                         type = "passive";
1845                                 };
1846
1847                                 cpu5_alert1: trip-point1 {
1848                                         temperature = <95000>;
1849                                         hysteresis = <2000>;
1850                                         type = "passive";
1851                                 };
1852
1853                                 cpu5_crit: cpu-crit {
1854                                         temperature = <110000>;
1855                                         hysteresis = <0>;
1856                                         type = "critical";
1857                                 };
1858                         };
1859
1860                         cooling-maps {
1861                                 map0 {
1862                                         trip = <&cpu5_alert0>;
1863                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1864                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1865                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1866                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1867                                 };
1868                                 map1 {
1869                                         trip = <&cpu5_alert1>;
1870                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1871                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1872                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1873                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1874                                 };
1875                         };
1876                 };
1877
1878                 cpu6-thermal {
1879                         polling-delay-passive = <250>;
1880                         polling-delay = <0>;
1881
1882                         thermal-sensors = <&tsens0 9>;
1883
1884                         trips {
1885                                 cpu6_alert0: trip-point0 {
1886                                         temperature = <90000>;
1887                                         hysteresis = <2000>;
1888                                         type = "passive";
1889                                 };
1890
1891                                 cpu6_alert1: trip-point1 {
1892                                         temperature = <95000>;
1893                                         hysteresis = <2000>;
1894                                         type = "passive";
1895                                 };
1896
1897                                 cpu6_crit: cpu-crit {
1898                                         temperature = <110000>;
1899                                         hysteresis = <0>;
1900                                         type = "critical";
1901                                 };
1902                         };
1903
1904                         cooling-maps {
1905                                 map0 {
1906                                         trip = <&cpu6_alert0>;
1907                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1908                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1909                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1910                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1911                                 };
1912                                 map1 {
1913                                         trip = <&cpu6_alert1>;
1914                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1915                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1916                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1917                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1918                                 };
1919                         };
1920                 };
1921
1922                 cpu7-thermal {
1923                         polling-delay-passive = <250>;
1924                         polling-delay = <0>;
1925
1926                         thermal-sensors = <&tsens0 10>;
1927
1928                         trips {
1929                                 cpu7_alert0: trip-point0 {
1930                                         temperature = <90000>;
1931                                         hysteresis = <2000>;
1932                                         type = "passive";
1933                                 };
1934
1935                                 cpu7_alert1: trip-point1 {
1936                                         temperature = <95000>;
1937                                         hysteresis = <2000>;
1938                                         type = "passive";
1939                                 };
1940
1941                                 cpu7_crit: cpu-crit {
1942                                         temperature = <110000>;
1943                                         hysteresis = <0>;
1944                                         type = "critical";
1945                                 };
1946                         };
1947
1948                         cooling-maps {
1949                                 map0 {
1950                                         trip = <&cpu7_alert0>;
1951                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1952                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1953                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1954                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1955                                 };
1956                                 map1 {
1957                                         trip = <&cpu7_alert1>;
1958                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1959                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1960                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1961                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1962                                 };
1963                         };
1964                 };
1965
1966                 cpu8-thermal {
1967                         polling-delay-passive = <250>;
1968                         polling-delay = <0>;
1969
1970                         thermal-sensors = <&tsens0 11>;
1971
1972                         trips {
1973                                 cpu8_alert0: trip-point0 {
1974                                         temperature = <90000>;
1975                                         hysteresis = <2000>;
1976                                         type = "passive";
1977                                 };
1978
1979                                 cpu8_alert1: trip-point1 {
1980                                         temperature = <95000>;
1981                                         hysteresis = <2000>;
1982                                         type = "passive";
1983                                 };
1984
1985                                 cpu8_crit: cpu-crit {
1986                                         temperature = <110000>;
1987                                         hysteresis = <0>;
1988                                         type = "critical";
1989                                 };
1990                         };
1991
1992                         cooling-maps {
1993                                 map0 {
1994                                         trip = <&cpu8_alert0>;
1995                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1996                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1997                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1998                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1999                                 };
2000                                 map1 {
2001                                         trip = <&cpu8_alert1>;
2002                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2003                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2004                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2005                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2006                                 };
2007                         };
2008                 };
2009
2010                 cpu9-thermal {
2011                         polling-delay-passive = <250>;
2012                         polling-delay = <0>;
2013
2014                         thermal-sensors = <&tsens0 12>;
2015
2016                         trips {
2017                                 cpu9_alert0: trip-point0 {
2018                                         temperature = <90000>;
2019                                         hysteresis = <2000>;
2020                                         type = "passive";
2021                                 };
2022
2023                                 cpu9_alert1: trip-point1 {
2024                                         temperature = <95000>;
2025                                         hysteresis = <2000>;
2026                                         type = "passive";
2027                                 };
2028
2029                                 cpu9_crit: cpu-crit {
2030                                         temperature = <110000>;
2031                                         hysteresis = <0>;
2032                                         type = "critical";
2033                                 };
2034                         };
2035
2036                         cooling-maps {
2037                                 map0 {
2038                                         trip = <&cpu9_alert0>;
2039                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2040                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2041                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2042                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2043                                 };
2044                                 map1 {
2045                                         trip = <&cpu9_alert1>;
2046                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2047                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2048                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2049                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2050                                 };
2051                         };
2052                 };
2053
2054                 cpu10-thermal {
2055                         polling-delay-passive = <250>;
2056                         polling-delay = <0>;
2057
2058                         thermal-sensors = <&tsens0 13>;
2059
2060                         trips {
2061                                 cpu10_alert0: trip-point0 {
2062                                         temperature = <90000>;
2063                                         hysteresis = <2000>;
2064                                         type = "passive";
2065                                 };
2066
2067                                 cpu10_alert1: trip-point1 {
2068                                         temperature = <95000>;
2069                                         hysteresis = <2000>;
2070                                         type = "passive";
2071                                 };
2072
2073                                 cpu10_crit: cpu-crit {
2074                                         temperature = <110000>;
2075                                         hysteresis = <0>;
2076                                         type = "critical";
2077                                 };
2078                         };
2079
2080                         cooling-maps {
2081                                 map0 {
2082                                         trip = <&cpu10_alert0>;
2083                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2084                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2085                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2086                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2087                                 };
2088                                 map1 {
2089                                         trip = <&cpu10_alert1>;
2090                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2091                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2092                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2093                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2094                                 };
2095                         };
2096                 };
2097
2098                 cpu11-thermal {
2099                         polling-delay-passive = <250>;
2100                         polling-delay = <0>;
2101
2102                         thermal-sensors = <&tsens0 14>;
2103
2104                         trips {
2105                                 cpu11_alert0: trip-point0 {
2106                                         temperature = <90000>;
2107                                         hysteresis = <2000>;
2108                                         type = "passive";
2109                                 };
2110
2111                                 cpu11_alert1: trip-point1 {
2112                                         temperature = <95000>;
2113                                         hysteresis = <2000>;
2114                                         type = "passive";
2115                                 };
2116
2117                                 cpu11_crit: cpu-crit {
2118                                         temperature = <110000>;
2119                                         hysteresis = <0>;
2120                                         type = "critical";
2121                                 };
2122                         };
2123
2124                         cooling-maps {
2125                                 map0 {
2126                                         trip = <&cpu11_alert0>;
2127                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2128                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2129                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2130                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2131                                 };
2132                                 map1 {
2133                                         trip = <&cpu11_alert1>;
2134                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2135                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2136                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2137                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2138                                 };
2139                         };
2140                 };
2141
2142                 aoss0-thermal {
2143                         polling-delay-passive = <0>;
2144                         polling-delay = <0>;
2145
2146                         thermal-sensors = <&tsens0 0>;
2147
2148                         trips {
2149                                 aoss0_alert0: trip-point0 {
2150                                         temperature = <90000>;
2151                                         hysteresis = <2000>;
2152                                         type = "hot";
2153                                 };
2154
2155                                 aoss0_crit: aoss0-crit {
2156                                         temperature = <110000>;
2157                                         hysteresis = <0>;
2158                                         type = "critical";
2159                                 };
2160                         };
2161                 };
2162
2163                 aoss1-thermal {
2164                         polling-delay-passive = <0>;
2165                         polling-delay = <0>;
2166
2167                         thermal-sensors = <&tsens1 0>;
2168
2169                         trips {
2170                                 aoss1_alert0: trip-point0 {
2171                                         temperature = <90000>;
2172                                         hysteresis = <2000>;
2173                                         type = "hot";
2174                                 };
2175
2176                                 aoss1_crit: aoss1-crit {
2177                                         temperature = <110000>;
2178                                         hysteresis = <0>;
2179                                         type = "critical";
2180                                 };
2181                         };
2182                 };
2183
2184                 cpuss0-thermal {
2185                         polling-delay-passive = <0>;
2186                         polling-delay = <0>;
2187
2188                         thermal-sensors = <&tsens0 5>;
2189
2190                         trips {
2191                                 cpuss0_alert0: trip-point0 {
2192                                         temperature = <90000>;
2193                                         hysteresis = <2000>;
2194                                         type = "hot";
2195                                 };
2196                                 cpuss0_crit: cluster0-crit {
2197                                         temperature = <110000>;
2198                                         hysteresis = <0>;
2199                                         type = "critical";
2200                                 };
2201                         };
2202                 };
2203
2204                 cpuss1-thermal {
2205                         polling-delay-passive = <0>;
2206                         polling-delay = <0>;
2207
2208                         thermal-sensors = <&tsens0 6>;
2209
2210                         trips {
2211                                 cpuss1_alert0: trip-point0 {
2212                                         temperature = <90000>;
2213                                         hysteresis = <2000>;
2214                                         type = "hot";
2215                                 };
2216                                 cpuss1_crit: cluster0-crit {
2217                                         temperature = <110000>;
2218                                         hysteresis = <0>;
2219                                         type = "critical";
2220                                 };
2221                         };
2222                 };
2223
2224                 gpuss0-thermal {
2225                         polling-delay-passive = <0>;
2226                         polling-delay = <0>;
2227
2228                         thermal-sensors = <&tsens1 1>;
2229
2230                         trips {
2231                                 gpuss0_alert0: trip-point0 {
2232                                         temperature = <90000>;
2233                                         hysteresis = <2000>;
2234                                         type = "hot";
2235                                 };
2236
2237                                 gpuss0_crit: gpuss0-crit {
2238                                         temperature = <110000>;
2239                                         hysteresis = <0>;
2240                                         type = "critical";
2241                                 };
2242                         };
2243                 };
2244
2245                 gpuss1-thermal {
2246                         polling-delay-passive = <0>;
2247                         polling-delay = <0>;
2248
2249                         thermal-sensors = <&tsens1 2>;
2250
2251                         trips {
2252                                 gpuss1_alert0: trip-point0 {
2253                                         temperature = <90000>;
2254                                         hysteresis = <2000>;
2255                                         type = "hot";
2256                                 };
2257
2258                                 gpuss1_crit: gpuss1-crit {
2259                                         temperature = <110000>;
2260                                         hysteresis = <0>;
2261                                         type = "critical";
2262                                 };
2263                         };
2264                 };
2265
2266                 nspss0-thermal {
2267                         polling-delay-passive = <0>;
2268                         polling-delay = <0>;
2269
2270                         thermal-sensors = <&tsens1 3>;
2271
2272                         trips {
2273                                 nspss0_alert0: trip-point0 {
2274                                         temperature = <90000>;
2275                                         hysteresis = <2000>;
2276                                         type = "hot";
2277                                 };
2278
2279                                 nspss0_crit: nspss0-crit {
2280                                         temperature = <110000>;
2281                                         hysteresis = <0>;
2282                                         type = "critical";
2283                                 };
2284                         };
2285                 };
2286
2287                 nspss1-thermal {
2288                         polling-delay-passive = <0>;
2289                         polling-delay = <0>;
2290
2291                         thermal-sensors = <&tsens1 4>;
2292
2293                         trips {
2294                                 nspss1_alert0: trip-point0 {
2295                                         temperature = <90000>;
2296                                         hysteresis = <2000>;
2297                                         type = "hot";
2298                                 };
2299
2300                                 nspss1_crit: nspss1-crit {
2301                                         temperature = <110000>;
2302                                         hysteresis = <0>;
2303                                         type = "critical";
2304                                 };
2305                         };
2306                 };
2307
2308                 video-thermal {
2309                         polling-delay-passive = <0>;
2310                         polling-delay = <0>;
2311
2312                         thermal-sensors = <&tsens1 5>;
2313
2314                         trips {
2315                                 video_alert0: trip-point0 {
2316                                         temperature = <90000>;
2317                                         hysteresis = <2000>;
2318                                         type = "hot";
2319                                 };
2320
2321                                 video_crit: video-crit {
2322                                         temperature = <110000>;
2323                                         hysteresis = <0>;
2324                                         type = "critical";
2325                                 };
2326                         };
2327                 };
2328
2329                 ddr-thermal {
2330                         polling-delay-passive = <0>;
2331                         polling-delay = <0>;
2332
2333                         thermal-sensors = <&tsens1 6>;
2334
2335                         trips {
2336                                 ddr_alert0: trip-point0 {
2337                                         temperature = <90000>;
2338                                         hysteresis = <2000>;
2339                                         type = "hot";
2340                                 };
2341
2342                                 ddr_crit: ddr-crit {
2343                                         temperature = <110000>;
2344                                         hysteresis = <0>;
2345                                         type = "critical";
2346                                 };
2347                         };
2348                 };
2349
2350                 mdmss0-thermal {
2351                         polling-delay-passive = <0>;
2352                         polling-delay = <0>;
2353
2354                         thermal-sensors = <&tsens1 7>;
2355
2356                         trips {
2357                                 mdmss0_alert0: trip-point0 {
2358                                         temperature = <90000>;
2359                                         hysteresis = <2000>;
2360                                         type = "hot";
2361                                 };
2362
2363                                 mdmss0_crit: mdmss0-crit {
2364                                         temperature = <110000>;
2365                                         hysteresis = <0>;
2366                                         type = "critical";
2367                                 };
2368                         };
2369                 };
2370
2371                 mdmss1-thermal {
2372                         polling-delay-passive = <0>;
2373                         polling-delay = <0>;
2374
2375                         thermal-sensors = <&tsens1 8>;
2376
2377                         trips {
2378                                 mdmss1_alert0: trip-point0 {
2379                                         temperature = <90000>;
2380                                         hysteresis = <2000>;
2381                                         type = "hot";
2382                                 };
2383
2384                                 mdmss1_crit: mdmss1-crit {
2385                                         temperature = <110000>;
2386                                         hysteresis = <0>;
2387                                         type = "critical";
2388                                 };
2389                         };
2390                 };
2391
2392                 mdmss2-thermal {
2393                         polling-delay-passive = <0>;
2394                         polling-delay = <0>;
2395
2396                         thermal-sensors = <&tsens1 9>;
2397
2398                         trips {
2399                                 mdmss2_alert0: trip-point0 {
2400                                         temperature = <90000>;
2401                                         hysteresis = <2000>;
2402                                         type = "hot";
2403                                 };
2404
2405                                 mdmss2_crit: mdmss2-crit {
2406                                         temperature = <110000>;
2407                                         hysteresis = <0>;
2408                                         type = "critical";
2409                                 };
2410                         };
2411                 };
2412
2413                 mdmss3-thermal {
2414                         polling-delay-passive = <0>;
2415                         polling-delay = <0>;
2416
2417                         thermal-sensors = <&tsens1 10>;
2418
2419                         trips {
2420                                 mdmss3_alert0: trip-point0 {
2421                                         temperature = <90000>;
2422                                         hysteresis = <2000>;
2423                                         type = "hot";
2424                                 };
2425
2426                                 mdmss3_crit: mdmss3-crit {
2427                                         temperature = <110000>;
2428                                         hysteresis = <0>;
2429                                         type = "critical";
2430                                 };
2431                         };
2432                 };
2433
2434                 camera0-thermal {
2435                         polling-delay-passive = <0>;
2436                         polling-delay = <0>;
2437
2438                         thermal-sensors = <&tsens1 11>;
2439
2440                         trips {
2441                                 camera0_alert0: trip-point0 {
2442                                         temperature = <90000>;
2443                                         hysteresis = <2000>;
2444                                         type = "hot";
2445                                 };
2446
2447                                 camera0_crit: camera0-crit {
2448                                         temperature = <110000>;
2449                                         hysteresis = <0>;
2450                                         type = "critical";
2451                                 };
2452                         };
2453                 };
2454         };
2455
2456         timer {
2457                 compatible = "arm,armv8-timer";
2458                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2459                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2460                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2461                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2462         };
2463 };