1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
15 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
29 compatible = "fixed-clock";
30 clock-frequency = <76800000>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 clock-frequency = <32000>;
46 aop_mem: memory@80800000 {
47 reg = <0x0 0x80800000 0x0 0x60000>;
51 aop_cmd_db_mem: memory@80860000 {
52 reg = <0x0 0x80860000 0x0 0x20000>;
53 compatible = "qcom,cmd-db";
57 smem_mem: memory@80900000 {
58 reg = <0x0 0x80900000 0x0 0x200000>;
62 cpucp_mem: memory@80b00000 {
64 reg = <0x0 0x80b00000 0x0 0x100000>;
74 compatible = "arm,kryo";
76 enable-method = "psci";
77 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
80 next-level-cache = <&L2_0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L3_0>;
94 compatible = "arm,kryo";
96 enable-method = "psci";
97 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
100 next-level-cache = <&L2_100>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 #cooling-cells = <2>;
104 compatible = "cache";
105 next-level-cache = <&L3_0>;
111 compatible = "arm,kryo";
113 enable-method = "psci";
114 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
117 next-level-cache = <&L2_200>;
118 qcom,freq-domain = <&cpufreq_hw 0>;
119 #cooling-cells = <2>;
121 compatible = "cache";
122 next-level-cache = <&L3_0>;
128 compatible = "arm,kryo";
130 enable-method = "psci";
131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
134 next-level-cache = <&L2_300>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
136 #cooling-cells = <2>;
138 compatible = "cache";
139 next-level-cache = <&L3_0>;
145 compatible = "arm,kryo";
147 enable-method = "psci";
148 cpu-idle-states = <&BIG_CPU_SLEEP_0
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 #cooling-cells = <2>;
155 compatible = "cache";
156 next-level-cache = <&L3_0>;
162 compatible = "arm,kryo";
164 enable-method = "psci";
165 cpu-idle-states = <&BIG_CPU_SLEEP_0
168 next-level-cache = <&L2_500>;
169 qcom,freq-domain = <&cpufreq_hw 1>;
170 #cooling-cells = <2>;
172 compatible = "cache";
173 next-level-cache = <&L3_0>;
179 compatible = "arm,kryo";
181 enable-method = "psci";
182 cpu-idle-states = <&BIG_CPU_SLEEP_0
185 next-level-cache = <&L2_600>;
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 #cooling-cells = <2>;
189 compatible = "cache";
190 next-level-cache = <&L3_0>;
196 compatible = "arm,kryo";
198 enable-method = "psci";
199 cpu-idle-states = <&BIG_CPU_SLEEP_0
202 next-level-cache = <&L2_700>;
203 qcom,freq-domain = <&cpufreq_hw 2>;
204 #cooling-cells = <2>;
206 compatible = "cache";
207 next-level-cache = <&L3_0>;
212 entry-method = "psci";
214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
215 compatible = "arm,idle-state";
216 idle-state-name = "little-power-down";
217 arm,psci-suspend-param = <0x40000003>;
218 entry-latency-us = <549>;
219 exit-latency-us = <901>;
220 min-residency-us = <1774>;
224 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
225 compatible = "arm,idle-state";
226 idle-state-name = "little-rail-power-down";
227 arm,psci-suspend-param = <0x40000004>;
228 entry-latency-us = <702>;
229 exit-latency-us = <915>;
230 min-residency-us = <4001>;
234 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
235 compatible = "arm,idle-state";
236 idle-state-name = "big-power-down";
237 arm,psci-suspend-param = <0x40000003>;
238 entry-latency-us = <523>;
239 exit-latency-us = <1244>;
240 min-residency-us = <2207>;
244 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
245 compatible = "arm,idle-state";
246 idle-state-name = "big-rail-power-down";
247 arm,psci-suspend-param = <0x40000004>;
248 entry-latency-us = <526>;
249 exit-latency-us = <1854>;
250 min-residency-us = <5555>;
254 CLUSTER_SLEEP_0: cluster-sleep-0 {
255 compatible = "arm,idle-state";
256 idle-state-name = "cluster-power-down";
257 arm,psci-suspend-param = <0x40003444>;
258 entry-latency-us = <3263>;
259 exit-latency-us = <6562>;
260 min-residency-us = <9926>;
267 device_type = "memory";
268 /* We expect the bootloader to fill in the size */
269 reg = <0 0x80000000 0 0>;
274 compatible = "qcom,scm-sc7280", "qcom,scm";
278 clk_virt: interconnect {
279 compatible = "qcom,sc7280-clk-virt";
280 #interconnect-cells = <2>;
281 qcom,bcm-voters = <&apps_bcm_voter>;
285 compatible = "qcom,smem";
286 memory-region = <&smem_mem>;
287 hwlocks = <&tcsr_mutex 3>;
291 compatible = "qcom,smp2p";
292 qcom,smem = <443>, <429>;
293 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
294 IPCC_MPROC_SIGNAL_SMP2P
295 IRQ_TYPE_EDGE_RISING>;
296 mboxes = <&ipcc IPCC_CLIENT_LPASS
297 IPCC_MPROC_SIGNAL_SMP2P>;
299 qcom,local-pid = <0>;
300 qcom,remote-pid = <2>;
302 adsp_smp2p_out: master-kernel {
303 qcom,entry-name = "master-kernel";
304 #qcom,smem-state-cells = <1>;
307 adsp_smp2p_in: slave-kernel {
308 qcom,entry-name = "slave-kernel";
309 interrupt-controller;
310 #interrupt-cells = <2>;
315 compatible = "qcom,smp2p";
316 qcom,smem = <94>, <432>;
317 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
318 IPCC_MPROC_SIGNAL_SMP2P
319 IRQ_TYPE_EDGE_RISING>;
320 mboxes = <&ipcc IPCC_CLIENT_CDSP
321 IPCC_MPROC_SIGNAL_SMP2P>;
323 qcom,local-pid = <0>;
324 qcom,remote-pid = <5>;
326 cdsp_smp2p_out: master-kernel {
327 qcom,entry-name = "master-kernel";
328 #qcom,smem-state-cells = <1>;
331 cdsp_smp2p_in: slave-kernel {
332 qcom,entry-name = "slave-kernel";
333 interrupt-controller;
334 #interrupt-cells = <2>;
339 compatible = "qcom,smp2p";
340 qcom,smem = <435>, <428>;
341 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
342 IPCC_MPROC_SIGNAL_SMP2P
343 IRQ_TYPE_EDGE_RISING>;
344 mboxes = <&ipcc IPCC_CLIENT_MPSS
345 IPCC_MPROC_SIGNAL_SMP2P>;
347 qcom,local-pid = <0>;
348 qcom,remote-pid = <1>;
350 modem_smp2p_out: master-kernel {
351 qcom,entry-name = "master-kernel";
352 #qcom,smem-state-cells = <1>;
355 modem_smp2p_in: slave-kernel {
356 qcom,entry-name = "slave-kernel";
357 interrupt-controller;
358 #interrupt-cells = <2>;
361 ipa_smp2p_out: ipa-ap-to-modem {
362 qcom,entry-name = "ipa";
363 #qcom,smem-state-cells = <1>;
366 ipa_smp2p_in: ipa-modem-to-ap {
367 qcom,entry-name = "ipa";
368 interrupt-controller;
369 #interrupt-cells = <2>;
374 compatible = "qcom,smp2p";
375 qcom,smem = <617>, <616>;
376 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
377 IPCC_MPROC_SIGNAL_SMP2P
378 IRQ_TYPE_EDGE_RISING>;
379 mboxes = <&ipcc IPCC_CLIENT_WPSS
380 IPCC_MPROC_SIGNAL_SMP2P>;
382 qcom,local-pid = <0>;
383 qcom,remote-pid = <13>;
385 wpss_smp2p_out: master-kernel {
386 qcom,entry-name = "master-kernel";
387 #qcom,smem-state-cells = <1>;
390 wpss_smp2p_in: slave-kernel {
391 qcom,entry-name = "slave-kernel";
392 interrupt-controller;
393 #interrupt-cells = <2>;
398 compatible = "arm,armv8-pmuv3";
399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
403 compatible = "arm,psci-1.0";
408 #address-cells = <2>;
410 ranges = <0 0 0 0 0x10 0>;
411 dma-ranges = <0 0 0 0 0x10 0>;
412 compatible = "simple-bus";
414 gcc: clock-controller@100000 {
415 compatible = "qcom,gcc-sc7280";
416 reg = <0 0x00100000 0 0x1f0000>;
417 clocks = <&rpmhcc RPMH_CXO_CLK>,
418 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
419 <0>, <0>, <0>, <0>, <0>, <0>;
420 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
421 "pcie_0_pipe_clk", "pcie_1_pipe-clk",
422 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
423 "ufs_phy_tx_symbol_0_clk",
424 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
427 #power-domain-cells = <1>;
430 ipcc: mailbox@408000 {
431 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
432 reg = <0 0x00408000 0 0x1000>;
433 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
434 interrupt-controller;
435 #interrupt-cells = <3>;
439 qupv3_id_0: geniqup@9c0000 {
440 compatible = "qcom,geni-se-qup";
441 reg = <0 0x009c0000 0 0x2000>;
442 clock-names = "m-ahb", "s-ahb";
443 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
444 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
445 #address-cells = <2>;
450 uart5: serial@994000 {
451 compatible = "qcom,geni-debug-uart";
452 reg = <0 0x00994000 0 0x4000>;
454 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&qup_uart5_default>;
457 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
462 cnoc2: interconnect@1500000 {
463 reg = <0 0x01500000 0 0x1000>;
464 compatible = "qcom,sc7280-cnoc2";
465 #interconnect-cells = <2>;
466 qcom,bcm-voters = <&apps_bcm_voter>;
469 cnoc3: interconnect@1502000 {
470 reg = <0 0x01502000 0 0x1000>;
471 compatible = "qcom,sc7280-cnoc3";
472 #interconnect-cells = <2>;
473 qcom,bcm-voters = <&apps_bcm_voter>;
476 mc_virt: interconnect@1580000 {
477 reg = <0 0x01580000 0 0x4>;
478 compatible = "qcom,sc7280-mc-virt";
479 #interconnect-cells = <2>;
480 qcom,bcm-voters = <&apps_bcm_voter>;
483 system_noc: interconnect@1680000 {
484 reg = <0 0x01680000 0 0x15480>;
485 compatible = "qcom,sc7280-system-noc";
486 #interconnect-cells = <2>;
487 qcom,bcm-voters = <&apps_bcm_voter>;
490 aggre1_noc: interconnect@16e0000 {
491 compatible = "qcom,sc7280-aggre1-noc";
492 reg = <0 0x016e0000 0 0x1c080>;
493 #interconnect-cells = <2>;
494 qcom,bcm-voters = <&apps_bcm_voter>;
497 aggre2_noc: interconnect@1700000 {
498 reg = <0 0x01700000 0 0x2b080>;
499 compatible = "qcom,sc7280-aggre2-noc";
500 #interconnect-cells = <2>;
501 qcom,bcm-voters = <&apps_bcm_voter>;
504 mmss_noc: interconnect@1740000 {
505 reg = <0 0x01740000 0 0x1e080>;
506 compatible = "qcom,sc7280-mmss-noc";
507 #interconnect-cells = <2>;
508 qcom,bcm-voters = <&apps_bcm_voter>;
511 tcsr_mutex: hwlock@1f40000 {
512 compatible = "qcom,tcsr-mutex", "syscon";
513 reg = <0 0x01f40000 0 0x40000>;
517 lpasscc: lpasscc@3000000 {
518 compatible = "qcom,sc7280-lpasscc";
519 reg = <0 0x03000000 0 0x40>,
520 <0 0x03c04000 0 0x4>,
521 <0 0x03389000 0 0x24>;
522 reg-names = "qdsp6ss", "top_cc", "cc";
523 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
524 clock-names = "iface";
528 lpass_ag_noc: interconnect@3c40000 {
529 reg = <0 0x03c40000 0 0xf080>;
530 compatible = "qcom,sc7280-lpass-ag-noc";
531 #interconnect-cells = <2>;
532 qcom,bcm-voters = <&apps_bcm_voter>;
535 gpucc: clock-controller@3d90000 {
536 compatible = "qcom,sc7280-gpucc";
537 reg = <0 0x03d90000 0 0x9000>;
538 clocks = <&rpmhcc RPMH_CXO_CLK>,
539 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
540 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
541 clock-names = "bi_tcxo",
542 "gcc_gpu_gpll0_clk_src",
543 "gcc_gpu_gpll0_div_clk_src";
546 #power-domain-cells = <1>;
550 compatible = "arm,coresight-stm", "arm,primecell";
551 reg = <0 0x06002000 0 0x1000>,
552 <0 0x16280000 0 0x180000>;
553 reg-names = "stm-base", "stm-stimulus-base";
555 clocks = <&aoss_qmp>;
556 clock-names = "apb_pclk";
561 remote-endpoint = <&funnel0_in7>;
568 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
569 reg = <0 0x06041000 0 0x1000>;
571 clocks = <&aoss_qmp>;
572 clock-names = "apb_pclk";
576 funnel0_out: endpoint {
577 remote-endpoint = <&merge_funnel_in0>;
583 #address-cells = <1>;
588 funnel0_in7: endpoint {
589 remote-endpoint = <&stm_out>;
596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
597 reg = <0 0x06042000 0 0x1000>;
599 clocks = <&aoss_qmp>;
600 clock-names = "apb_pclk";
604 funnel1_out: endpoint {
605 remote-endpoint = <&merge_funnel_in1>;
611 #address-cells = <1>;
616 funnel1_in4: endpoint {
617 remote-endpoint = <&apss_merge_funnel_out>;
624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
625 reg = <0 0x06045000 0 0x1000>;
627 clocks = <&aoss_qmp>;
628 clock-names = "apb_pclk";
632 merge_funnel_out: endpoint {
633 remote-endpoint = <&swao_funnel_in>;
639 #address-cells = <1>;
644 merge_funnel_in0: endpoint {
645 remote-endpoint = <&funnel0_out>;
651 merge_funnel_in1: endpoint {
652 remote-endpoint = <&funnel1_out>;
659 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
660 reg = <0 0x06046000 0 0x1000>;
662 clocks = <&aoss_qmp>;
663 clock-names = "apb_pclk";
667 replicator_out: endpoint {
668 remote-endpoint = <&etr_in>;
675 replicator_in: endpoint {
676 remote-endpoint = <&swao_replicator_out>;
683 compatible = "arm,coresight-tmc", "arm,primecell";
684 reg = <0 0x06048000 0 0x1000>;
685 iommus = <&apps_smmu 0x04c0 0>;
687 clocks = <&aoss_qmp>;
688 clock-names = "apb_pclk";
694 remote-endpoint = <&replicator_out>;
701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
702 reg = <0 0x06b04000 0 0x1000>;
704 clocks = <&aoss_qmp>;
705 clock-names = "apb_pclk";
709 swao_funnel_out: endpoint {
710 remote-endpoint = <&etf_in>;
716 #address-cells = <1>;
721 swao_funnel_in: endpoint {
722 remote-endpoint = <&merge_funnel_out>;
729 compatible = "arm,coresight-tmc", "arm,primecell";
730 reg = <0 0x06b05000 0 0x1000>;
732 clocks = <&aoss_qmp>;
733 clock-names = "apb_pclk";
738 remote-endpoint = <&swao_replicator_in>;
746 remote-endpoint = <&swao_funnel_out>;
753 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
754 reg = <0 0x06b06000 0 0x1000>;
756 clocks = <&aoss_qmp>;
757 clock-names = "apb_pclk";
758 qcom,replicator-loses-context;
762 swao_replicator_out: endpoint {
763 remote-endpoint = <&replicator_in>;
770 swao_replicator_in: endpoint {
771 remote-endpoint = <&etf_out>;
778 compatible = "arm,coresight-etm4x", "arm,primecell";
779 reg = <0 0x07040000 0 0x1000>;
783 clocks = <&aoss_qmp>;
784 clock-names = "apb_pclk";
785 arm,coresight-loses-context-with-cpu;
791 remote-endpoint = <&apss_funnel_in0>;
798 compatible = "arm,coresight-etm4x", "arm,primecell";
799 reg = <0 0x07140000 0 0x1000>;
803 clocks = <&aoss_qmp>;
804 clock-names = "apb_pclk";
805 arm,coresight-loses-context-with-cpu;
811 remote-endpoint = <&apss_funnel_in1>;
818 compatible = "arm,coresight-etm4x", "arm,primecell";
819 reg = <0 0x07240000 0 0x1000>;
823 clocks = <&aoss_qmp>;
824 clock-names = "apb_pclk";
825 arm,coresight-loses-context-with-cpu;
831 remote-endpoint = <&apss_funnel_in2>;
838 compatible = "arm,coresight-etm4x", "arm,primecell";
839 reg = <0 0x07340000 0 0x1000>;
843 clocks = <&aoss_qmp>;
844 clock-names = "apb_pclk";
845 arm,coresight-loses-context-with-cpu;
851 remote-endpoint = <&apss_funnel_in3>;
858 compatible = "arm,coresight-etm4x", "arm,primecell";
859 reg = <0 0x07440000 0 0x1000>;
863 clocks = <&aoss_qmp>;
864 clock-names = "apb_pclk";
865 arm,coresight-loses-context-with-cpu;
871 remote-endpoint = <&apss_funnel_in4>;
878 compatible = "arm,coresight-etm4x", "arm,primecell";
879 reg = <0 0x07540000 0 0x1000>;
883 clocks = <&aoss_qmp>;
884 clock-names = "apb_pclk";
885 arm,coresight-loses-context-with-cpu;
891 remote-endpoint = <&apss_funnel_in5>;
898 compatible = "arm,coresight-etm4x", "arm,primecell";
899 reg = <0 0x07640000 0 0x1000>;
903 clocks = <&aoss_qmp>;
904 clock-names = "apb_pclk";
905 arm,coresight-loses-context-with-cpu;
911 remote-endpoint = <&apss_funnel_in6>;
918 compatible = "arm,coresight-etm4x", "arm,primecell";
919 reg = <0 0x07740000 0 0x1000>;
923 clocks = <&aoss_qmp>;
924 clock-names = "apb_pclk";
925 arm,coresight-loses-context-with-cpu;
931 remote-endpoint = <&apss_funnel_in7>;
937 funnel@7800000 { /* APSS Funnel */
938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
939 reg = <0 0x07800000 0 0x1000>;
941 clocks = <&aoss_qmp>;
942 clock-names = "apb_pclk";
946 apss_funnel_out: endpoint {
947 remote-endpoint = <&apss_merge_funnel_in>;
953 #address-cells = <1>;
958 apss_funnel_in0: endpoint {
959 remote-endpoint = <&etm0_out>;
965 apss_funnel_in1: endpoint {
966 remote-endpoint = <&etm1_out>;
972 apss_funnel_in2: endpoint {
973 remote-endpoint = <&etm2_out>;
979 apss_funnel_in3: endpoint {
980 remote-endpoint = <&etm3_out>;
986 apss_funnel_in4: endpoint {
987 remote-endpoint = <&etm4_out>;
993 apss_funnel_in5: endpoint {
994 remote-endpoint = <&etm5_out>;
1000 apss_funnel_in6: endpoint {
1001 remote-endpoint = <&etm6_out>;
1007 apss_funnel_in7: endpoint {
1008 remote-endpoint = <&etm7_out>;
1015 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1016 reg = <0 0x07810000 0 0x1000>;
1018 clocks = <&aoss_qmp>;
1019 clock-names = "apb_pclk";
1023 apss_merge_funnel_out: endpoint {
1024 remote-endpoint = <&funnel1_in4>;
1031 apss_merge_funnel_in: endpoint {
1032 remote-endpoint = <&apss_funnel_out>;
1038 dc_noc: interconnect@90e0000 {
1039 reg = <0 0x090e0000 0 0x5080>;
1040 compatible = "qcom,sc7280-dc-noc";
1041 #interconnect-cells = <2>;
1042 qcom,bcm-voters = <&apps_bcm_voter>;
1045 gem_noc: interconnect@9100000 {
1046 reg = <0 0x9100000 0 0xe2200>;
1047 compatible = "qcom,sc7280-gem-noc";
1048 #interconnect-cells = <2>;
1049 qcom,bcm-voters = <&apps_bcm_voter>;
1052 system-cache-controller@9200000 {
1053 compatible = "qcom,sc7280-llcc";
1054 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
1055 reg-names = "llcc_base", "llcc_broadcast_base";
1056 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1059 nsp_noc: interconnect@a0c0000 {
1060 reg = <0 0x0a0c0000 0 0x10000>;
1061 compatible = "qcom,sc7280-nsp-noc";
1062 #interconnect-cells = <2>;
1063 qcom,bcm-voters = <&apps_bcm_voter>;
1066 videocc: clock-controller@aaf0000 {
1067 compatible = "qcom,sc7280-videocc";
1068 reg = <0 0xaaf0000 0 0x10000>;
1069 clocks = <&rpmhcc RPMH_CXO_CLK>,
1070 <&rpmhcc RPMH_CXO_CLK_A>;
1071 clock-names = "bi_tcxo", "bi_tcxo_ao";
1074 #power-domain-cells = <1>;
1077 dispcc: clock-controller@af00000 {
1078 compatible = "qcom,sc7280-dispcc";
1079 reg = <0 0xaf00000 0 0x20000>;
1080 clocks = <&rpmhcc RPMH_CXO_CLK>,
1081 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1082 <0>, <0>, <0>, <0>, <0>, <0>;
1083 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
1084 "dsi0_phy_pll_out_byteclk",
1085 "dsi0_phy_pll_out_dsiclk",
1086 "dp_phy_pll_link_clk",
1087 "dp_phy_pll_vco_div_clk",
1088 "edp_phy_pll_link_clk",
1089 "edp_phy_pll_vco_div_clk";
1092 #power-domain-cells = <1>;
1095 pdc: interrupt-controller@b220000 {
1096 compatible = "qcom,sc7280-pdc", "qcom,pdc";
1097 reg = <0 0x0b220000 0 0x30000>;
1098 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
1099 <55 306 4>, <59 312 3>, <62 374 2>,
1100 <64 434 2>, <66 438 3>, <69 86 1>,
1101 <70 520 54>, <124 609 31>, <155 63 1>,
1103 #interrupt-cells = <2>;
1104 interrupt-parent = <&intc>;
1105 interrupt-controller;
1108 pdc_reset: reset-controller@b5e0000 {
1109 compatible = "qcom,sc7280-pdc-global";
1110 reg = <0 0x0b5e0000 0 0x20000>;
1114 tsens0: thermal-sensor@c263000 {
1115 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1116 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1117 <0 0x0c222000 0 0x1ff>; /* SROT */
1118 #qcom,sensors = <15>;
1119 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1120 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1121 interrupt-names = "uplow","critical";
1122 #thermal-sensor-cells = <1>;
1125 tsens1: thermal-sensor@c265000 {
1126 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1127 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1128 <0 0x0c223000 0 0x1ff>; /* SROT */
1129 #qcom,sensors = <12>;
1130 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1132 interrupt-names = "uplow","critical";
1133 #thermal-sensor-cells = <1>;
1136 aoss_reset: reset-controller@c2a0000 {
1137 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
1138 reg = <0 0x0c2a0000 0 0x31000>;
1142 aoss_qmp: power-controller@c300000 {
1143 compatible = "qcom,sc7280-aoss-qmp";
1144 reg = <0 0x0c300000 0 0x100000>;
1145 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1146 IPCC_MPROC_SIGNAL_GLINK_QMP
1147 IRQ_TYPE_EDGE_RISING>;
1148 mboxes = <&ipcc IPCC_CLIENT_AOP
1149 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1152 #power-domain-cells = <1>;
1155 spmi_bus: spmi@c440000 {
1156 compatible = "qcom,spmi-pmic-arb";
1157 reg = <0 0x0c440000 0 0x1100>,
1158 <0 0x0c600000 0 0x2000000>,
1159 <0 0x0e600000 0 0x100000>,
1160 <0 0x0e700000 0 0xa0000>,
1161 <0 0x0c40a000 0 0x26000>;
1162 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1163 interrupt-names = "periph_irq";
1164 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1167 #address-cells = <1>;
1169 interrupt-controller;
1170 #interrupt-cells = <4>;
1173 tlmm: pinctrl@f100000 {
1174 compatible = "qcom,sc7280-pinctrl";
1175 reg = <0 0x0f100000 0 0x300000>;
1176 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1179 interrupt-controller;
1180 #interrupt-cells = <2>;
1181 gpio-ranges = <&tlmm 0 0 175>;
1182 wakeup-parent = <&pdc>;
1184 qup_uart5_default: qup-uart5-default {
1185 pins = "gpio46", "gpio47";
1190 apps_smmu: iommu@15000000 {
1191 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
1192 reg = <0 0x15000000 0 0x100000>;
1194 #global-interrupts = <1>;
1196 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1279 intc: interrupt-controller@17a00000 {
1280 compatible = "arm,gic-v3";
1281 #address-cells = <2>;
1284 #interrupt-cells = <3>;
1285 interrupt-controller;
1286 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1287 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1288 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1291 compatible = "arm,gic-v3-its";
1294 reg = <0 0x17a40000 0 0x20000>;
1295 status = "disabled";
1300 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
1301 reg = <0 0x17c10000 0 0x1000>;
1302 clocks = <&sleep_clk>;
1303 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1307 #address-cells = <2>;
1310 compatible = "arm,armv7-timer-mem";
1311 reg = <0 0x17c20000 0 0x1000>;
1315 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1317 reg = <0 0x17c21000 0 0x1000>,
1318 <0 0x17c22000 0 0x1000>;
1323 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1324 reg = <0 0x17c23000 0 0x1000>;
1325 status = "disabled";
1330 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1331 reg = <0 0x17c25000 0 0x1000>;
1332 status = "disabled";
1337 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1338 reg = <0 0x17c27000 0 0x1000>;
1339 status = "disabled";
1344 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1345 reg = <0 0x17c29000 0 0x1000>;
1346 status = "disabled";
1351 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1352 reg = <0 0x17c2b000 0 0x1000>;
1353 status = "disabled";
1358 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1359 reg = <0 0x17c2d000 0 0x1000>;
1360 status = "disabled";
1364 apps_rsc: rsc@18200000 {
1365 compatible = "qcom,rpmh-rsc";
1366 reg = <0 0x18200000 0 0x10000>,
1367 <0 0x18210000 0 0x10000>,
1368 <0 0x18220000 0 0x10000>;
1369 reg-names = "drv-0", "drv-1", "drv-2";
1370 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1373 qcom,tcs-offset = <0xd00>;
1375 qcom,tcs-config = <ACTIVE_TCS 2>,
1380 apps_bcm_voter: bcm-voter {
1381 compatible = "qcom,bcm-voter";
1384 rpmhpd: power-controller {
1385 compatible = "qcom,sc7280-rpmhpd";
1386 #power-domain-cells = <1>;
1387 operating-points-v2 = <&rpmhpd_opp_table>;
1389 rpmhpd_opp_table: opp-table {
1390 compatible = "operating-points-v2";
1392 rpmhpd_opp_ret: opp1 {
1393 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1396 rpmhpd_opp_low_svs: opp2 {
1397 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1400 rpmhpd_opp_svs: opp3 {
1401 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1404 rpmhpd_opp_svs_l1: opp4 {
1405 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1408 rpmhpd_opp_svs_l2: opp5 {
1409 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1412 rpmhpd_opp_nom: opp6 {
1413 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1416 rpmhpd_opp_nom_l1: opp7 {
1417 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1420 rpmhpd_opp_turbo: opp8 {
1421 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1424 rpmhpd_opp_turbo_l1: opp9 {
1425 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1430 rpmhcc: clock-controller {
1431 compatible = "qcom,sc7280-rpmh-clk";
1432 clocks = <&xo_board>;
1438 cpufreq_hw: cpufreq@18591000 {
1439 compatible = "qcom,cpufreq-epss";
1440 reg = <0 0x18591000 0 0x1000>,
1441 <0 0x18592000 0 0x1000>,
1442 <0 0x18593000 0 0x1000>;
1443 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1444 clock-names = "xo", "alternate";
1445 #freq-domain-cells = <1>;
1449 thermal_zones: thermal-zones {
1451 polling-delay-passive = <250>;
1452 polling-delay = <0>;
1454 thermal-sensors = <&tsens0 1>;
1457 cpu0_alert0: trip-point0 {
1458 temperature = <90000>;
1459 hysteresis = <2000>;
1463 cpu0_alert1: trip-point1 {
1464 temperature = <95000>;
1465 hysteresis = <2000>;
1469 cpu0_crit: cpu-crit {
1470 temperature = <110000>;
1478 trip = <&cpu0_alert0>;
1479 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1480 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1481 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1482 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1485 trip = <&cpu0_alert1>;
1486 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1487 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1488 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1489 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1495 polling-delay-passive = <250>;
1496 polling-delay = <0>;
1498 thermal-sensors = <&tsens0 2>;
1501 cpu1_alert0: trip-point0 {
1502 temperature = <90000>;
1503 hysteresis = <2000>;
1507 cpu1_alert1: trip-point1 {
1508 temperature = <95000>;
1509 hysteresis = <2000>;
1513 cpu1_crit: cpu-crit {
1514 temperature = <110000>;
1522 trip = <&cpu1_alert0>;
1523 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1524 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1525 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1526 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1529 trip = <&cpu1_alert1>;
1530 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1531 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1532 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1533 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1539 polling-delay-passive = <250>;
1540 polling-delay = <0>;
1542 thermal-sensors = <&tsens0 3>;
1545 cpu2_alert0: trip-point0 {
1546 temperature = <90000>;
1547 hysteresis = <2000>;
1551 cpu2_alert1: trip-point1 {
1552 temperature = <95000>;
1553 hysteresis = <2000>;
1557 cpu2_crit: cpu-crit {
1558 temperature = <110000>;
1566 trip = <&cpu2_alert0>;
1567 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1568 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1569 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1570 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1573 trip = <&cpu2_alert1>;
1574 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1575 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1576 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1577 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1583 polling-delay-passive = <250>;
1584 polling-delay = <0>;
1586 thermal-sensors = <&tsens0 4>;
1589 cpu3_alert0: trip-point0 {
1590 temperature = <90000>;
1591 hysteresis = <2000>;
1595 cpu3_alert1: trip-point1 {
1596 temperature = <95000>;
1597 hysteresis = <2000>;
1601 cpu3_crit: cpu-crit {
1602 temperature = <110000>;
1610 trip = <&cpu3_alert0>;
1611 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1612 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1613 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1614 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1617 trip = <&cpu3_alert1>;
1618 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1619 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1620 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1621 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1627 polling-delay-passive = <250>;
1628 polling-delay = <0>;
1630 thermal-sensors = <&tsens0 7>;
1633 cpu4_alert0: trip-point0 {
1634 temperature = <90000>;
1635 hysteresis = <2000>;
1639 cpu4_alert1: trip-point1 {
1640 temperature = <95000>;
1641 hysteresis = <2000>;
1645 cpu4_crit: cpu-crit {
1646 temperature = <110000>;
1654 trip = <&cpu4_alert0>;
1655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1661 trip = <&cpu4_alert1>;
1662 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1663 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1664 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1665 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1671 polling-delay-passive = <250>;
1672 polling-delay = <0>;
1674 thermal-sensors = <&tsens0 8>;
1677 cpu5_alert0: trip-point0 {
1678 temperature = <90000>;
1679 hysteresis = <2000>;
1683 cpu5_alert1: trip-point1 {
1684 temperature = <95000>;
1685 hysteresis = <2000>;
1689 cpu5_crit: cpu-crit {
1690 temperature = <110000>;
1698 trip = <&cpu5_alert0>;
1699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1705 trip = <&cpu5_alert1>;
1706 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1707 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1708 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1709 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1715 polling-delay-passive = <250>;
1716 polling-delay = <0>;
1718 thermal-sensors = <&tsens0 9>;
1721 cpu6_alert0: trip-point0 {
1722 temperature = <90000>;
1723 hysteresis = <2000>;
1727 cpu6_alert1: trip-point1 {
1728 temperature = <95000>;
1729 hysteresis = <2000>;
1733 cpu6_crit: cpu-crit {
1734 temperature = <110000>;
1742 trip = <&cpu6_alert0>;
1743 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1745 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1746 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1749 trip = <&cpu6_alert1>;
1750 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1751 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1752 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1753 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1759 polling-delay-passive = <250>;
1760 polling-delay = <0>;
1762 thermal-sensors = <&tsens0 10>;
1765 cpu7_alert0: trip-point0 {
1766 temperature = <90000>;
1767 hysteresis = <2000>;
1771 cpu7_alert1: trip-point1 {
1772 temperature = <95000>;
1773 hysteresis = <2000>;
1777 cpu7_crit: cpu-crit {
1778 temperature = <110000>;
1786 trip = <&cpu7_alert0>;
1787 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1789 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1790 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1793 trip = <&cpu7_alert1>;
1794 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1795 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1796 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1797 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1803 polling-delay-passive = <250>;
1804 polling-delay = <0>;
1806 thermal-sensors = <&tsens0 11>;
1809 cpu8_alert0: trip-point0 {
1810 temperature = <90000>;
1811 hysteresis = <2000>;
1815 cpu8_alert1: trip-point1 {
1816 temperature = <95000>;
1817 hysteresis = <2000>;
1821 cpu8_crit: cpu-crit {
1822 temperature = <110000>;
1830 trip = <&cpu8_alert0>;
1831 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1832 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1833 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1834 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1837 trip = <&cpu8_alert1>;
1838 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1839 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1840 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1841 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1847 polling-delay-passive = <250>;
1848 polling-delay = <0>;
1850 thermal-sensors = <&tsens0 12>;
1853 cpu9_alert0: trip-point0 {
1854 temperature = <90000>;
1855 hysteresis = <2000>;
1859 cpu9_alert1: trip-point1 {
1860 temperature = <95000>;
1861 hysteresis = <2000>;
1865 cpu9_crit: cpu-crit {
1866 temperature = <110000>;
1874 trip = <&cpu9_alert0>;
1875 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1877 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1878 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1881 trip = <&cpu9_alert1>;
1882 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1883 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1884 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1885 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1891 polling-delay-passive = <250>;
1892 polling-delay = <0>;
1894 thermal-sensors = <&tsens0 13>;
1897 cpu10_alert0: trip-point0 {
1898 temperature = <90000>;
1899 hysteresis = <2000>;
1903 cpu10_alert1: trip-point1 {
1904 temperature = <95000>;
1905 hysteresis = <2000>;
1909 cpu10_crit: cpu-crit {
1910 temperature = <110000>;
1918 trip = <&cpu10_alert0>;
1919 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1920 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1921 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1922 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1925 trip = <&cpu10_alert1>;
1926 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1927 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1928 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1929 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1935 polling-delay-passive = <250>;
1936 polling-delay = <0>;
1938 thermal-sensors = <&tsens0 14>;
1941 cpu11_alert0: trip-point0 {
1942 temperature = <90000>;
1943 hysteresis = <2000>;
1947 cpu11_alert1: trip-point1 {
1948 temperature = <95000>;
1949 hysteresis = <2000>;
1953 cpu11_crit: cpu-crit {
1954 temperature = <110000>;
1962 trip = <&cpu11_alert0>;
1963 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1964 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1965 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1966 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1969 trip = <&cpu11_alert1>;
1970 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1971 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1972 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1973 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1979 polling-delay-passive = <0>;
1980 polling-delay = <0>;
1982 thermal-sensors = <&tsens0 0>;
1985 aoss0_alert0: trip-point0 {
1986 temperature = <90000>;
1987 hysteresis = <2000>;
1991 aoss0_crit: aoss0-crit {
1992 temperature = <110000>;
2000 polling-delay-passive = <0>;
2001 polling-delay = <0>;
2003 thermal-sensors = <&tsens1 0>;
2006 aoss1_alert0: trip-point0 {
2007 temperature = <90000>;
2008 hysteresis = <2000>;
2012 aoss1_crit: aoss1-crit {
2013 temperature = <110000>;
2021 polling-delay-passive = <0>;
2022 polling-delay = <0>;
2024 thermal-sensors = <&tsens0 5>;
2027 cpuss0_alert0: trip-point0 {
2028 temperature = <90000>;
2029 hysteresis = <2000>;
2032 cpuss0_crit: cluster0-crit {
2033 temperature = <110000>;
2041 polling-delay-passive = <0>;
2042 polling-delay = <0>;
2044 thermal-sensors = <&tsens0 6>;
2047 cpuss1_alert0: trip-point0 {
2048 temperature = <90000>;
2049 hysteresis = <2000>;
2052 cpuss1_crit: cluster0-crit {
2053 temperature = <110000>;
2061 polling-delay-passive = <0>;
2062 polling-delay = <0>;
2064 thermal-sensors = <&tsens1 1>;
2067 gpuss0_alert0: trip-point0 {
2068 temperature = <90000>;
2069 hysteresis = <2000>;
2073 gpuss0_crit: gpuss0-crit {
2074 temperature = <110000>;
2082 polling-delay-passive = <0>;
2083 polling-delay = <0>;
2085 thermal-sensors = <&tsens1 2>;
2088 gpuss1_alert0: trip-point0 {
2089 temperature = <90000>;
2090 hysteresis = <2000>;
2094 gpuss1_crit: gpuss1-crit {
2095 temperature = <110000>;
2103 polling-delay-passive = <0>;
2104 polling-delay = <0>;
2106 thermal-sensors = <&tsens1 3>;
2109 nspss0_alert0: trip-point0 {
2110 temperature = <90000>;
2111 hysteresis = <2000>;
2115 nspss0_crit: nspss0-crit {
2116 temperature = <110000>;
2124 polling-delay-passive = <0>;
2125 polling-delay = <0>;
2127 thermal-sensors = <&tsens1 4>;
2130 nspss1_alert0: trip-point0 {
2131 temperature = <90000>;
2132 hysteresis = <2000>;
2136 nspss1_crit: nspss1-crit {
2137 temperature = <110000>;
2145 polling-delay-passive = <0>;
2146 polling-delay = <0>;
2148 thermal-sensors = <&tsens1 5>;
2151 video_alert0: trip-point0 {
2152 temperature = <90000>;
2153 hysteresis = <2000>;
2157 video_crit: video-crit {
2158 temperature = <110000>;
2166 polling-delay-passive = <0>;
2167 polling-delay = <0>;
2169 thermal-sensors = <&tsens1 6>;
2172 ddr_alert0: trip-point0 {
2173 temperature = <90000>;
2174 hysteresis = <2000>;
2178 ddr_crit: ddr-crit {
2179 temperature = <110000>;
2187 polling-delay-passive = <0>;
2188 polling-delay = <0>;
2190 thermal-sensors = <&tsens1 7>;
2193 mdmss0_alert0: trip-point0 {
2194 temperature = <90000>;
2195 hysteresis = <2000>;
2199 mdmss0_crit: mdmss0-crit {
2200 temperature = <110000>;
2208 polling-delay-passive = <0>;
2209 polling-delay = <0>;
2211 thermal-sensors = <&tsens1 8>;
2214 mdmss1_alert0: trip-point0 {
2215 temperature = <90000>;
2216 hysteresis = <2000>;
2220 mdmss1_crit: mdmss1-crit {
2221 temperature = <110000>;
2229 polling-delay-passive = <0>;
2230 polling-delay = <0>;
2232 thermal-sensors = <&tsens1 9>;
2235 mdmss2_alert0: trip-point0 {
2236 temperature = <90000>;
2237 hysteresis = <2000>;
2241 mdmss2_crit: mdmss2-crit {
2242 temperature = <110000>;
2250 polling-delay-passive = <0>;
2251 polling-delay = <0>;
2253 thermal-sensors = <&tsens1 10>;
2256 mdmss3_alert0: trip-point0 {
2257 temperature = <90000>;
2258 hysteresis = <2000>;
2262 mdmss3_crit: mdmss3-crit {
2263 temperature = <110000>;
2271 polling-delay-passive = <0>;
2272 polling-delay = <0>;
2274 thermal-sensors = <&tsens1 11>;
2277 camera0_alert0: trip-point0 {
2278 temperature = <90000>;
2279 hysteresis = <2000>;
2283 camera0_crit: camera0-crit {
2284 temperature = <110000>;
2293 compatible = "arm,armv8-timer";
2294 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2295 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2296 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2297 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;