1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
15 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
29 compatible = "fixed-clock";
30 clock-frequency = <76800000>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 clock-frequency = <32000>;
46 aop_mem: memory@80800000 {
47 reg = <0x0 0x80800000 0x0 0x60000>;
51 aop_cmd_db_mem: memory@80860000 {
52 reg = <0x0 0x80860000 0x0 0x20000>;
53 compatible = "qcom,cmd-db";
57 smem_mem: memory@80900000 {
58 reg = <0x0 0x80900000 0x0 0x200000>;
62 cpucp_mem: memory@80b00000 {
64 reg = <0x0 0x80b00000 0x0 0x100000>;
74 compatible = "arm,kryo";
76 enable-method = "psci";
77 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
80 next-level-cache = <&L2_0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L3_0>;
94 compatible = "arm,kryo";
96 enable-method = "psci";
97 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
100 next-level-cache = <&L2_100>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 #cooling-cells = <2>;
104 compatible = "cache";
105 next-level-cache = <&L3_0>;
111 compatible = "arm,kryo";
113 enable-method = "psci";
114 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
117 next-level-cache = <&L2_200>;
118 qcom,freq-domain = <&cpufreq_hw 0>;
119 #cooling-cells = <2>;
121 compatible = "cache";
122 next-level-cache = <&L3_0>;
128 compatible = "arm,kryo";
130 enable-method = "psci";
131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
134 next-level-cache = <&L2_300>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
136 #cooling-cells = <2>;
138 compatible = "cache";
139 next-level-cache = <&L3_0>;
145 compatible = "arm,kryo";
147 enable-method = "psci";
148 cpu-idle-states = <&BIG_CPU_SLEEP_0
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 #cooling-cells = <2>;
155 compatible = "cache";
156 next-level-cache = <&L3_0>;
162 compatible = "arm,kryo";
164 enable-method = "psci";
165 cpu-idle-states = <&BIG_CPU_SLEEP_0
168 next-level-cache = <&L2_500>;
169 qcom,freq-domain = <&cpufreq_hw 1>;
170 #cooling-cells = <2>;
172 compatible = "cache";
173 next-level-cache = <&L3_0>;
179 compatible = "arm,kryo";
181 enable-method = "psci";
182 cpu-idle-states = <&BIG_CPU_SLEEP_0
185 next-level-cache = <&L2_600>;
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 #cooling-cells = <2>;
189 compatible = "cache";
190 next-level-cache = <&L3_0>;
196 compatible = "arm,kryo";
198 enable-method = "psci";
199 cpu-idle-states = <&BIG_CPU_SLEEP_0
202 next-level-cache = <&L2_700>;
203 qcom,freq-domain = <&cpufreq_hw 2>;
204 #cooling-cells = <2>;
206 compatible = "cache";
207 next-level-cache = <&L3_0>;
212 entry-method = "psci";
214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
215 compatible = "arm,idle-state";
216 idle-state-name = "little-power-down";
217 arm,psci-suspend-param = <0x40000003>;
218 entry-latency-us = <549>;
219 exit-latency-us = <901>;
220 min-residency-us = <1774>;
224 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
225 compatible = "arm,idle-state";
226 idle-state-name = "little-rail-power-down";
227 arm,psci-suspend-param = <0x40000004>;
228 entry-latency-us = <702>;
229 exit-latency-us = <915>;
230 min-residency-us = <4001>;
234 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
235 compatible = "arm,idle-state";
236 idle-state-name = "big-power-down";
237 arm,psci-suspend-param = <0x40000003>;
238 entry-latency-us = <523>;
239 exit-latency-us = <1244>;
240 min-residency-us = <2207>;
244 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
245 compatible = "arm,idle-state";
246 idle-state-name = "big-rail-power-down";
247 arm,psci-suspend-param = <0x40000004>;
248 entry-latency-us = <526>;
249 exit-latency-us = <1854>;
250 min-residency-us = <5555>;
254 CLUSTER_SLEEP_0: cluster-sleep-0 {
255 compatible = "arm,idle-state";
256 idle-state-name = "cluster-power-down";
257 arm,psci-suspend-param = <0x40003444>;
258 entry-latency-us = <3263>;
259 exit-latency-us = <6562>;
260 min-residency-us = <9926>;
267 device_type = "memory";
268 /* We expect the bootloader to fill in the size */
269 reg = <0 0x80000000 0 0>;
274 compatible = "qcom,scm-sc7280", "qcom,scm";
278 clk_virt: interconnect {
279 compatible = "qcom,sc7280-clk-virt";
280 #interconnect-cells = <2>;
281 qcom,bcm-voters = <&apps_bcm_voter>;
285 compatible = "qcom,smem";
286 memory-region = <&smem_mem>;
287 hwlocks = <&tcsr_mutex 3>;
291 compatible = "qcom,smp2p";
292 qcom,smem = <443>, <429>;
293 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
294 IPCC_MPROC_SIGNAL_SMP2P
295 IRQ_TYPE_EDGE_RISING>;
296 mboxes = <&ipcc IPCC_CLIENT_LPASS
297 IPCC_MPROC_SIGNAL_SMP2P>;
299 qcom,local-pid = <0>;
300 qcom,remote-pid = <2>;
302 adsp_smp2p_out: master-kernel {
303 qcom,entry-name = "master-kernel";
304 #qcom,smem-state-cells = <1>;
307 adsp_smp2p_in: slave-kernel {
308 qcom,entry-name = "slave-kernel";
309 interrupt-controller;
310 #interrupt-cells = <2>;
315 compatible = "qcom,smp2p";
316 qcom,smem = <94>, <432>;
317 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
318 IPCC_MPROC_SIGNAL_SMP2P
319 IRQ_TYPE_EDGE_RISING>;
320 mboxes = <&ipcc IPCC_CLIENT_CDSP
321 IPCC_MPROC_SIGNAL_SMP2P>;
323 qcom,local-pid = <0>;
324 qcom,remote-pid = <5>;
326 cdsp_smp2p_out: master-kernel {
327 qcom,entry-name = "master-kernel";
328 #qcom,smem-state-cells = <1>;
331 cdsp_smp2p_in: slave-kernel {
332 qcom,entry-name = "slave-kernel";
333 interrupt-controller;
334 #interrupt-cells = <2>;
339 compatible = "qcom,smp2p";
340 qcom,smem = <435>, <428>;
341 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
342 IPCC_MPROC_SIGNAL_SMP2P
343 IRQ_TYPE_EDGE_RISING>;
344 mboxes = <&ipcc IPCC_CLIENT_MPSS
345 IPCC_MPROC_SIGNAL_SMP2P>;
347 qcom,local-pid = <0>;
348 qcom,remote-pid = <1>;
350 modem_smp2p_out: master-kernel {
351 qcom,entry-name = "master-kernel";
352 #qcom,smem-state-cells = <1>;
355 modem_smp2p_in: slave-kernel {
356 qcom,entry-name = "slave-kernel";
357 interrupt-controller;
358 #interrupt-cells = <2>;
361 ipa_smp2p_out: ipa-ap-to-modem {
362 qcom,entry-name = "ipa";
363 #qcom,smem-state-cells = <1>;
366 ipa_smp2p_in: ipa-modem-to-ap {
367 qcom,entry-name = "ipa";
368 interrupt-controller;
369 #interrupt-cells = <2>;
374 compatible = "qcom,smp2p";
375 qcom,smem = <617>, <616>;
376 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
377 IPCC_MPROC_SIGNAL_SMP2P
378 IRQ_TYPE_EDGE_RISING>;
379 mboxes = <&ipcc IPCC_CLIENT_WPSS
380 IPCC_MPROC_SIGNAL_SMP2P>;
382 qcom,local-pid = <0>;
383 qcom,remote-pid = <13>;
385 wpss_smp2p_out: master-kernel {
386 qcom,entry-name = "master-kernel";
387 #qcom,smem-state-cells = <1>;
390 wpss_smp2p_in: slave-kernel {
391 qcom,entry-name = "slave-kernel";
392 interrupt-controller;
393 #interrupt-cells = <2>;
398 compatible = "arm,armv8-pmuv3";
399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
403 compatible = "arm,psci-1.0";
408 #address-cells = <2>;
410 ranges = <0 0 0 0 0x10 0>;
411 dma-ranges = <0 0 0 0 0x10 0>;
412 compatible = "simple-bus";
414 gcc: clock-controller@100000 {
415 compatible = "qcom,gcc-sc7280";
416 reg = <0 0x00100000 0 0x1f0000>;
417 clocks = <&rpmhcc RPMH_CXO_CLK>,
418 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
419 <0>, <0>, <0>, <0>, <0>, <0>;
420 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
421 "pcie_0_pipe_clk", "pcie_1_pipe-clk",
422 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
423 "ufs_phy_tx_symbol_0_clk",
424 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
427 #power-domain-cells = <1>;
430 ipcc: mailbox@408000 {
431 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
432 reg = <0 0x00408000 0 0x1000>;
433 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
434 interrupt-controller;
435 #interrupt-cells = <3>;
439 qupv3_id_0: geniqup@9c0000 {
440 compatible = "qcom,geni-se-qup";
441 reg = <0 0x009c0000 0 0x2000>;
442 clock-names = "m-ahb", "s-ahb";
443 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
444 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
445 #address-cells = <2>;
450 uart5: serial@994000 {
451 compatible = "qcom,geni-debug-uart";
452 reg = <0 0x00994000 0 0x4000>;
454 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&qup_uart5_default>;
457 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
462 cnoc2: interconnect@1500000 {
463 reg = <0 0x01500000 0 0x1000>;
464 compatible = "qcom,sc7280-cnoc2";
465 #interconnect-cells = <2>;
466 qcom,bcm-voters = <&apps_bcm_voter>;
469 cnoc3: interconnect@1502000 {
470 reg = <0 0x01502000 0 0x1000>;
471 compatible = "qcom,sc7280-cnoc3";
472 #interconnect-cells = <2>;
473 qcom,bcm-voters = <&apps_bcm_voter>;
476 mc_virt: interconnect@1580000 {
477 reg = <0 0x01580000 0 0x4>;
478 compatible = "qcom,sc7280-mc-virt";
479 #interconnect-cells = <2>;
480 qcom,bcm-voters = <&apps_bcm_voter>;
483 system_noc: interconnect@1680000 {
484 reg = <0 0x01680000 0 0x15480>;
485 compatible = "qcom,sc7280-system-noc";
486 #interconnect-cells = <2>;
487 qcom,bcm-voters = <&apps_bcm_voter>;
490 aggre1_noc: interconnect@16e0000 {
491 compatible = "qcom,sc7280-aggre1-noc";
492 reg = <0 0x016e0000 0 0x1c080>;
493 #interconnect-cells = <2>;
494 qcom,bcm-voters = <&apps_bcm_voter>;
497 aggre2_noc: interconnect@1700000 {
498 reg = <0 0x01700000 0 0x2b080>;
499 compatible = "qcom,sc7280-aggre2-noc";
500 #interconnect-cells = <2>;
501 qcom,bcm-voters = <&apps_bcm_voter>;
504 mmss_noc: interconnect@1740000 {
505 reg = <0 0x01740000 0 0x1e080>;
506 compatible = "qcom,sc7280-mmss-noc";
507 #interconnect-cells = <2>;
508 qcom,bcm-voters = <&apps_bcm_voter>;
511 tcsr_mutex: hwlock@1f40000 {
512 compatible = "qcom,tcsr-mutex", "syscon";
513 reg = <0 0x01f40000 0 0x40000>;
517 lpasscc: lpasscc@3000000 {
518 compatible = "qcom,sc7280-lpasscc";
519 reg = <0 0x03000000 0 0x40>,
520 <0 0x03c04000 0 0x4>,
521 <0 0x03389000 0 0x24>;
522 reg-names = "qdsp6ss", "top_cc", "cc";
523 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
524 clock-names = "iface";
528 lpass_ag_noc: interconnect@3c40000 {
529 reg = <0 0x03c40000 0 0xf080>;
530 compatible = "qcom,sc7280-lpass-ag-noc";
531 #interconnect-cells = <2>;
532 qcom,bcm-voters = <&apps_bcm_voter>;
535 gpucc: clock-controller@3d90000 {
536 compatible = "qcom,sc7280-gpucc";
537 reg = <0 0x03d90000 0 0x9000>;
538 clocks = <&rpmhcc RPMH_CXO_CLK>,
539 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
540 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
541 clock-names = "bi_tcxo",
542 "gcc_gpu_gpll0_clk_src",
543 "gcc_gpu_gpll0_div_clk_src";
546 #power-domain-cells = <1>;
550 compatible = "arm,coresight-stm", "arm,primecell";
551 reg = <0 0x06002000 0 0x1000>,
552 <0 0x16280000 0 0x180000>;
553 reg-names = "stm-base", "stm-stimulus-base";
555 clocks = <&aoss_qmp>;
556 clock-names = "apb_pclk";
561 remote-endpoint = <&funnel0_in7>;
568 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
569 reg = <0 0x06041000 0 0x1000>;
571 clocks = <&aoss_qmp>;
572 clock-names = "apb_pclk";
576 funnel0_out: endpoint {
577 remote-endpoint = <&merge_funnel_in0>;
583 #address-cells = <1>;
588 funnel0_in7: endpoint {
589 remote-endpoint = <&stm_out>;
596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
597 reg = <0 0x06042000 0 0x1000>;
599 clocks = <&aoss_qmp>;
600 clock-names = "apb_pclk";
604 funnel1_out: endpoint {
605 remote-endpoint = <&merge_funnel_in1>;
611 #address-cells = <1>;
616 funnel1_in4: endpoint {
617 remote-endpoint = <&apss_merge_funnel_out>;
624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
625 reg = <0 0x06045000 0 0x1000>;
627 clocks = <&aoss_qmp>;
628 clock-names = "apb_pclk";
632 merge_funnel_out: endpoint {
633 remote-endpoint = <&swao_funnel_in>;
639 #address-cells = <1>;
644 merge_funnel_in0: endpoint {
645 remote-endpoint = <&funnel0_out>;
651 merge_funnel_in1: endpoint {
652 remote-endpoint = <&funnel1_out>;
659 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
660 reg = <0 0x06046000 0 0x1000>;
662 clocks = <&aoss_qmp>;
663 clock-names = "apb_pclk";
667 replicator_out: endpoint {
668 remote-endpoint = <&etr_in>;
675 replicator_in: endpoint {
676 remote-endpoint = <&swao_replicator_out>;
683 compatible = "arm,coresight-tmc", "arm,primecell";
684 reg = <0 0x06048000 0 0x1000>;
685 iommus = <&apps_smmu 0x04c0 0>;
687 clocks = <&aoss_qmp>;
688 clock-names = "apb_pclk";
694 remote-endpoint = <&replicator_out>;
701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
702 reg = <0 0x06b04000 0 0x1000>;
704 clocks = <&aoss_qmp>;
705 clock-names = "apb_pclk";
709 swao_funnel_out: endpoint {
710 remote-endpoint = <&etf_in>;
716 #address-cells = <1>;
721 swao_funnel_in: endpoint {
722 remote-endpoint = <&merge_funnel_out>;
729 compatible = "arm,coresight-tmc", "arm,primecell";
730 reg = <0 0x06b05000 0 0x1000>;
732 clocks = <&aoss_qmp>;
733 clock-names = "apb_pclk";
738 remote-endpoint = <&swao_replicator_in>;
746 remote-endpoint = <&swao_funnel_out>;
753 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
754 reg = <0 0x06b06000 0 0x1000>;
756 clocks = <&aoss_qmp>;
757 clock-names = "apb_pclk";
758 qcom,replicator-loses-context;
762 swao_replicator_out: endpoint {
763 remote-endpoint = <&replicator_in>;
770 swao_replicator_in: endpoint {
771 remote-endpoint = <&etf_out>;
778 compatible = "arm,coresight-etm4x", "arm,primecell";
779 reg = <0 0x07040000 0 0x1000>;
783 clocks = <&aoss_qmp>;
784 clock-names = "apb_pclk";
785 arm,coresight-loses-context-with-cpu;
791 remote-endpoint = <&apss_funnel_in0>;
798 compatible = "arm,coresight-etm4x", "arm,primecell";
799 reg = <0 0x07140000 0 0x1000>;
803 clocks = <&aoss_qmp>;
804 clock-names = "apb_pclk";
805 arm,coresight-loses-context-with-cpu;
811 remote-endpoint = <&apss_funnel_in1>;
818 compatible = "arm,coresight-etm4x", "arm,primecell";
819 reg = <0 0x07240000 0 0x1000>;
823 clocks = <&aoss_qmp>;
824 clock-names = "apb_pclk";
825 arm,coresight-loses-context-with-cpu;
831 remote-endpoint = <&apss_funnel_in2>;
838 compatible = "arm,coresight-etm4x", "arm,primecell";
839 reg = <0 0x07340000 0 0x1000>;
843 clocks = <&aoss_qmp>;
844 clock-names = "apb_pclk";
845 arm,coresight-loses-context-with-cpu;
851 remote-endpoint = <&apss_funnel_in3>;
858 compatible = "arm,coresight-etm4x", "arm,primecell";
859 reg = <0 0x07440000 0 0x1000>;
863 clocks = <&aoss_qmp>;
864 clock-names = "apb_pclk";
865 arm,coresight-loses-context-with-cpu;
871 remote-endpoint = <&apss_funnel_in4>;
878 compatible = "arm,coresight-etm4x", "arm,primecell";
879 reg = <0 0x07540000 0 0x1000>;
883 clocks = <&aoss_qmp>;
884 clock-names = "apb_pclk";
885 arm,coresight-loses-context-with-cpu;
891 remote-endpoint = <&apss_funnel_in5>;
898 compatible = "arm,coresight-etm4x", "arm,primecell";
899 reg = <0 0x07640000 0 0x1000>;
903 clocks = <&aoss_qmp>;
904 clock-names = "apb_pclk";
905 arm,coresight-loses-context-with-cpu;
911 remote-endpoint = <&apss_funnel_in6>;
918 compatible = "arm,coresight-etm4x", "arm,primecell";
919 reg = <0 0x07740000 0 0x1000>;
923 clocks = <&aoss_qmp>;
924 clock-names = "apb_pclk";
925 arm,coresight-loses-context-with-cpu;
931 remote-endpoint = <&apss_funnel_in7>;
937 funnel@7800000 { /* APSS Funnel */
938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
939 reg = <0 0x07800000 0 0x1000>;
941 clocks = <&aoss_qmp>;
942 clock-names = "apb_pclk";
946 apss_funnel_out: endpoint {
947 remote-endpoint = <&apss_merge_funnel_in>;
953 #address-cells = <1>;
958 apss_funnel_in0: endpoint {
959 remote-endpoint = <&etm0_out>;
965 apss_funnel_in1: endpoint {
966 remote-endpoint = <&etm1_out>;
972 apss_funnel_in2: endpoint {
973 remote-endpoint = <&etm2_out>;
979 apss_funnel_in3: endpoint {
980 remote-endpoint = <&etm3_out>;
986 apss_funnel_in4: endpoint {
987 remote-endpoint = <&etm4_out>;
993 apss_funnel_in5: endpoint {
994 remote-endpoint = <&etm5_out>;
1000 apss_funnel_in6: endpoint {
1001 remote-endpoint = <&etm6_out>;
1007 apss_funnel_in7: endpoint {
1008 remote-endpoint = <&etm7_out>;
1015 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1016 reg = <0 0x07810000 0 0x1000>;
1018 clocks = <&aoss_qmp>;
1019 clock-names = "apb_pclk";
1023 apss_merge_funnel_out: endpoint {
1024 remote-endpoint = <&funnel1_in4>;
1031 apss_merge_funnel_in: endpoint {
1032 remote-endpoint = <&apss_funnel_out>;
1038 usb_1_hsphy: phy@88e3000 {
1039 compatible = "qcom,sc7280-usb-hs-phy",
1040 "qcom,usb-snps-hs-7nm-phy";
1041 reg = <0 0x088e3000 0 0x400>;
1042 status = "disabled";
1045 clocks = <&rpmhcc RPMH_CXO_CLK>;
1046 clock-names = "ref";
1048 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1051 usb_2_hsphy: phy@88e4000 {
1052 compatible = "qcom,sc7280-usb-hs-phy",
1053 "qcom,usb-snps-hs-7nm-phy";
1054 reg = <0 0x088e4000 0 0x400>;
1055 status = "disabled";
1058 clocks = <&rpmhcc RPMH_CXO_CLK>;
1059 clock-names = "ref";
1061 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1064 usb_1_qmpphy: phy-wrapper@88e9000 {
1065 compatible = "qcom,sc7280-qmp-usb3-dp-phy",
1066 "qcom,sm8250-qmp-usb3-dp-phy";
1067 reg = <0 0x088e9000 0 0x200>,
1068 <0 0x088e8000 0 0x40>,
1069 <0 0x088ea000 0 0x200>;
1070 status = "disabled";
1071 #address-cells = <2>;
1075 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1076 <&rpmhcc RPMH_CXO_CLK>,
1077 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1078 clock-names = "aux", "ref_clk_src", "com_aux";
1080 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1081 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1082 reset-names = "phy", "common";
1084 usb_1_ssphy: usb3-phy@88e9200 {
1085 reg = <0 0x088e9200 0 0x200>,
1086 <0 0x088e9400 0 0x200>,
1087 <0 0x088e9c00 0 0x400>,
1088 <0 0x088e9600 0 0x200>,
1089 <0 0x088e9800 0 0x200>,
1090 <0 0x088e9a00 0 0x100>;
1093 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1094 clock-names = "pipe0";
1095 clock-output-names = "usb3_phy_pipe_clk_src";
1098 dp_phy: dp-phy@88ea200 {
1099 reg = <0 0x088ea200 0 0x200>,
1100 <0 0x088ea400 0 0x200>,
1101 <0 0x088eac00 0 0x400>,
1102 <0 0x088ea600 0 0x200>,
1103 <0 0x088ea800 0 0x200>,
1104 <0 0x088eaa00 0 0x100>;
1107 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1108 clock-names = "pipe0";
1109 clock-output-names = "usb3_phy_pipe_clk_src";
1113 usb_2: usb@8cf8800 {
1114 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1115 reg = <0 0x08cf8800 0 0x400>;
1116 status = "disabled";
1117 #address-cells = <2>;
1122 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1123 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1124 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1125 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1126 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
1127 clock-names = "cfg_noc", "core", "iface","mock_utmi",
1130 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1131 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1132 assigned-clock-rates = <19200000>, <200000000>;
1134 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1135 <&pdc 13 IRQ_TYPE_EDGE_RISING>,
1136 <&pdc 12 IRQ_TYPE_EDGE_RISING>;
1137 interrupt-names = "hs_phy_irq",
1138 "dm_hs_phy_irq", "dp_hs_phy_irq";
1140 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
1142 resets = <&gcc GCC_USB30_SEC_BCR>;
1144 usb_2_dwc3: usb@8c00000 {
1145 compatible = "snps,dwc3";
1146 reg = <0 0x08c00000 0 0xe000>;
1147 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1148 iommus = <&apps_smmu 0xa0 0x0>;
1149 snps,dis_u2_susphy_quirk;
1150 snps,dis_enblslpm_quirk;
1151 phys = <&usb_2_hsphy>;
1152 phy-names = "usb2-phy";
1153 maximum-speed = "high-speed";
1157 dc_noc: interconnect@90e0000 {
1158 reg = <0 0x090e0000 0 0x5080>;
1159 compatible = "qcom,sc7280-dc-noc";
1160 #interconnect-cells = <2>;
1161 qcom,bcm-voters = <&apps_bcm_voter>;
1164 gem_noc: interconnect@9100000 {
1165 reg = <0 0x9100000 0 0xe2200>;
1166 compatible = "qcom,sc7280-gem-noc";
1167 #interconnect-cells = <2>;
1168 qcom,bcm-voters = <&apps_bcm_voter>;
1171 system-cache-controller@9200000 {
1172 compatible = "qcom,sc7280-llcc";
1173 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
1174 reg-names = "llcc_base", "llcc_broadcast_base";
1175 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1178 nsp_noc: interconnect@a0c0000 {
1179 reg = <0 0x0a0c0000 0 0x10000>;
1180 compatible = "qcom,sc7280-nsp-noc";
1181 #interconnect-cells = <2>;
1182 qcom,bcm-voters = <&apps_bcm_voter>;
1185 usb_1: usb@a6f8800 {
1186 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1187 reg = <0 0x0a6f8800 0 0x400>;
1188 status = "disabled";
1189 #address-cells = <2>;
1194 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1195 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1196 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1197 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1198 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1199 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1202 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1203 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1204 assigned-clock-rates = <19200000>, <200000000>;
1206 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1207 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1208 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1209 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1211 "dm_hs_phy_irq", "ss_phy_irq";
1213 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1215 resets = <&gcc GCC_USB30_PRIM_BCR>;
1217 usb_1_dwc3: usb@a600000 {
1218 compatible = "snps,dwc3";
1219 reg = <0 0x0a600000 0 0xe000>;
1220 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1221 iommus = <&apps_smmu 0xe0 0x0>;
1222 snps,dis_u2_susphy_quirk;
1223 snps,dis_enblslpm_quirk;
1224 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1225 phy-names = "usb2-phy", "usb3-phy";
1226 maximum-speed = "super-speed";
1230 videocc: clock-controller@aaf0000 {
1231 compatible = "qcom,sc7280-videocc";
1232 reg = <0 0xaaf0000 0 0x10000>;
1233 clocks = <&rpmhcc RPMH_CXO_CLK>,
1234 <&rpmhcc RPMH_CXO_CLK_A>;
1235 clock-names = "bi_tcxo", "bi_tcxo_ao";
1238 #power-domain-cells = <1>;
1241 dispcc: clock-controller@af00000 {
1242 compatible = "qcom,sc7280-dispcc";
1243 reg = <0 0xaf00000 0 0x20000>;
1244 clocks = <&rpmhcc RPMH_CXO_CLK>,
1245 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1246 <0>, <0>, <0>, <0>, <0>, <0>;
1247 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
1248 "dsi0_phy_pll_out_byteclk",
1249 "dsi0_phy_pll_out_dsiclk",
1250 "dp_phy_pll_link_clk",
1251 "dp_phy_pll_vco_div_clk",
1252 "edp_phy_pll_link_clk",
1253 "edp_phy_pll_vco_div_clk";
1256 #power-domain-cells = <1>;
1259 pdc: interrupt-controller@b220000 {
1260 compatible = "qcom,sc7280-pdc", "qcom,pdc";
1261 reg = <0 0x0b220000 0 0x30000>;
1262 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
1263 <55 306 4>, <59 312 3>, <62 374 2>,
1264 <64 434 2>, <66 438 3>, <69 86 1>,
1265 <70 520 54>, <124 609 31>, <155 63 1>,
1267 #interrupt-cells = <2>;
1268 interrupt-parent = <&intc>;
1269 interrupt-controller;
1272 pdc_reset: reset-controller@b5e0000 {
1273 compatible = "qcom,sc7280-pdc-global";
1274 reg = <0 0x0b5e0000 0 0x20000>;
1278 tsens0: thermal-sensor@c263000 {
1279 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1280 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1281 <0 0x0c222000 0 0x1ff>; /* SROT */
1282 #qcom,sensors = <15>;
1283 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1285 interrupt-names = "uplow","critical";
1286 #thermal-sensor-cells = <1>;
1289 tsens1: thermal-sensor@c265000 {
1290 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1291 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1292 <0 0x0c223000 0 0x1ff>; /* SROT */
1293 #qcom,sensors = <12>;
1294 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1295 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1296 interrupt-names = "uplow","critical";
1297 #thermal-sensor-cells = <1>;
1300 aoss_reset: reset-controller@c2a0000 {
1301 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
1302 reg = <0 0x0c2a0000 0 0x31000>;
1306 aoss_qmp: power-controller@c300000 {
1307 compatible = "qcom,sc7280-aoss-qmp";
1308 reg = <0 0x0c300000 0 0x100000>;
1309 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1310 IPCC_MPROC_SIGNAL_GLINK_QMP
1311 IRQ_TYPE_EDGE_RISING>;
1312 mboxes = <&ipcc IPCC_CLIENT_AOP
1313 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1316 #power-domain-cells = <1>;
1319 spmi_bus: spmi@c440000 {
1320 compatible = "qcom,spmi-pmic-arb";
1321 reg = <0 0x0c440000 0 0x1100>,
1322 <0 0x0c600000 0 0x2000000>,
1323 <0 0x0e600000 0 0x100000>,
1324 <0 0x0e700000 0 0xa0000>,
1325 <0 0x0c40a000 0 0x26000>;
1326 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1327 interrupt-names = "periph_irq";
1328 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1331 #address-cells = <1>;
1333 interrupt-controller;
1334 #interrupt-cells = <4>;
1337 tlmm: pinctrl@f100000 {
1338 compatible = "qcom,sc7280-pinctrl";
1339 reg = <0 0x0f100000 0 0x300000>;
1340 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1343 interrupt-controller;
1344 #interrupt-cells = <2>;
1345 gpio-ranges = <&tlmm 0 0 175>;
1346 wakeup-parent = <&pdc>;
1348 qup_uart5_default: qup-uart5-default {
1349 pins = "gpio46", "gpio47";
1354 apps_smmu: iommu@15000000 {
1355 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
1356 reg = <0 0x15000000 0 0x100000>;
1358 #global-interrupts = <1>;
1360 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1443 intc: interrupt-controller@17a00000 {
1444 compatible = "arm,gic-v3";
1445 #address-cells = <2>;
1448 #interrupt-cells = <3>;
1449 interrupt-controller;
1450 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1451 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1452 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1455 compatible = "arm,gic-v3-its";
1458 reg = <0 0x17a40000 0 0x20000>;
1459 status = "disabled";
1464 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
1465 reg = <0 0x17c10000 0 0x1000>;
1466 clocks = <&sleep_clk>;
1467 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1471 #address-cells = <2>;
1474 compatible = "arm,armv7-timer-mem";
1475 reg = <0 0x17c20000 0 0x1000>;
1479 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1481 reg = <0 0x17c21000 0 0x1000>,
1482 <0 0x17c22000 0 0x1000>;
1487 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1488 reg = <0 0x17c23000 0 0x1000>;
1489 status = "disabled";
1494 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1495 reg = <0 0x17c25000 0 0x1000>;
1496 status = "disabled";
1501 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1502 reg = <0 0x17c27000 0 0x1000>;
1503 status = "disabled";
1508 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1509 reg = <0 0x17c29000 0 0x1000>;
1510 status = "disabled";
1515 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1516 reg = <0 0x17c2b000 0 0x1000>;
1517 status = "disabled";
1522 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1523 reg = <0 0x17c2d000 0 0x1000>;
1524 status = "disabled";
1528 apps_rsc: rsc@18200000 {
1529 compatible = "qcom,rpmh-rsc";
1530 reg = <0 0x18200000 0 0x10000>,
1531 <0 0x18210000 0 0x10000>,
1532 <0 0x18220000 0 0x10000>;
1533 reg-names = "drv-0", "drv-1", "drv-2";
1534 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1537 qcom,tcs-offset = <0xd00>;
1539 qcom,tcs-config = <ACTIVE_TCS 2>,
1544 apps_bcm_voter: bcm-voter {
1545 compatible = "qcom,bcm-voter";
1548 rpmhpd: power-controller {
1549 compatible = "qcom,sc7280-rpmhpd";
1550 #power-domain-cells = <1>;
1551 operating-points-v2 = <&rpmhpd_opp_table>;
1553 rpmhpd_opp_table: opp-table {
1554 compatible = "operating-points-v2";
1556 rpmhpd_opp_ret: opp1 {
1557 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1560 rpmhpd_opp_low_svs: opp2 {
1561 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1564 rpmhpd_opp_svs: opp3 {
1565 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1568 rpmhpd_opp_svs_l1: opp4 {
1569 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1572 rpmhpd_opp_svs_l2: opp5 {
1573 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1576 rpmhpd_opp_nom: opp6 {
1577 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1580 rpmhpd_opp_nom_l1: opp7 {
1581 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1584 rpmhpd_opp_turbo: opp8 {
1585 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1588 rpmhpd_opp_turbo_l1: opp9 {
1589 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1594 rpmhcc: clock-controller {
1595 compatible = "qcom,sc7280-rpmh-clk";
1596 clocks = <&xo_board>;
1602 cpufreq_hw: cpufreq@18591000 {
1603 compatible = "qcom,cpufreq-epss";
1604 reg = <0 0x18591000 0 0x1000>,
1605 <0 0x18592000 0 0x1000>,
1606 <0 0x18593000 0 0x1000>;
1607 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1608 clock-names = "xo", "alternate";
1609 #freq-domain-cells = <1>;
1613 thermal_zones: thermal-zones {
1615 polling-delay-passive = <250>;
1616 polling-delay = <0>;
1618 thermal-sensors = <&tsens0 1>;
1621 cpu0_alert0: trip-point0 {
1622 temperature = <90000>;
1623 hysteresis = <2000>;
1627 cpu0_alert1: trip-point1 {
1628 temperature = <95000>;
1629 hysteresis = <2000>;
1633 cpu0_crit: cpu-crit {
1634 temperature = <110000>;
1642 trip = <&cpu0_alert0>;
1643 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1644 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1645 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1646 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1649 trip = <&cpu0_alert1>;
1650 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1651 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1652 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1653 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1659 polling-delay-passive = <250>;
1660 polling-delay = <0>;
1662 thermal-sensors = <&tsens0 2>;
1665 cpu1_alert0: trip-point0 {
1666 temperature = <90000>;
1667 hysteresis = <2000>;
1671 cpu1_alert1: trip-point1 {
1672 temperature = <95000>;
1673 hysteresis = <2000>;
1677 cpu1_crit: cpu-crit {
1678 temperature = <110000>;
1686 trip = <&cpu1_alert0>;
1687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1693 trip = <&cpu1_alert1>;
1694 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1695 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1696 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1697 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1703 polling-delay-passive = <250>;
1704 polling-delay = <0>;
1706 thermal-sensors = <&tsens0 3>;
1709 cpu2_alert0: trip-point0 {
1710 temperature = <90000>;
1711 hysteresis = <2000>;
1715 cpu2_alert1: trip-point1 {
1716 temperature = <95000>;
1717 hysteresis = <2000>;
1721 cpu2_crit: cpu-crit {
1722 temperature = <110000>;
1730 trip = <&cpu2_alert0>;
1731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1732 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1733 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1734 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1737 trip = <&cpu2_alert1>;
1738 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1739 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1740 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1741 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1747 polling-delay-passive = <250>;
1748 polling-delay = <0>;
1750 thermal-sensors = <&tsens0 4>;
1753 cpu3_alert0: trip-point0 {
1754 temperature = <90000>;
1755 hysteresis = <2000>;
1759 cpu3_alert1: trip-point1 {
1760 temperature = <95000>;
1761 hysteresis = <2000>;
1765 cpu3_crit: cpu-crit {
1766 temperature = <110000>;
1774 trip = <&cpu3_alert0>;
1775 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1776 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1777 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1778 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1781 trip = <&cpu3_alert1>;
1782 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1783 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1784 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1785 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1791 polling-delay-passive = <250>;
1792 polling-delay = <0>;
1794 thermal-sensors = <&tsens0 7>;
1797 cpu4_alert0: trip-point0 {
1798 temperature = <90000>;
1799 hysteresis = <2000>;
1803 cpu4_alert1: trip-point1 {
1804 temperature = <95000>;
1805 hysteresis = <2000>;
1809 cpu4_crit: cpu-crit {
1810 temperature = <110000>;
1818 trip = <&cpu4_alert0>;
1819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1820 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1821 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1822 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1825 trip = <&cpu4_alert1>;
1826 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1828 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1829 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1835 polling-delay-passive = <250>;
1836 polling-delay = <0>;
1838 thermal-sensors = <&tsens0 8>;
1841 cpu5_alert0: trip-point0 {
1842 temperature = <90000>;
1843 hysteresis = <2000>;
1847 cpu5_alert1: trip-point1 {
1848 temperature = <95000>;
1849 hysteresis = <2000>;
1853 cpu5_crit: cpu-crit {
1854 temperature = <110000>;
1862 trip = <&cpu5_alert0>;
1863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1865 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1866 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1869 trip = <&cpu5_alert1>;
1870 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1871 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1872 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1873 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1879 polling-delay-passive = <250>;
1880 polling-delay = <0>;
1882 thermal-sensors = <&tsens0 9>;
1885 cpu6_alert0: trip-point0 {
1886 temperature = <90000>;
1887 hysteresis = <2000>;
1891 cpu6_alert1: trip-point1 {
1892 temperature = <95000>;
1893 hysteresis = <2000>;
1897 cpu6_crit: cpu-crit {
1898 temperature = <110000>;
1906 trip = <&cpu6_alert0>;
1907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1909 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1910 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1913 trip = <&cpu6_alert1>;
1914 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1915 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1916 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1917 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1923 polling-delay-passive = <250>;
1924 polling-delay = <0>;
1926 thermal-sensors = <&tsens0 10>;
1929 cpu7_alert0: trip-point0 {
1930 temperature = <90000>;
1931 hysteresis = <2000>;
1935 cpu7_alert1: trip-point1 {
1936 temperature = <95000>;
1937 hysteresis = <2000>;
1941 cpu7_crit: cpu-crit {
1942 temperature = <110000>;
1950 trip = <&cpu7_alert0>;
1951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1957 trip = <&cpu7_alert1>;
1958 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1959 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1960 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1961 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1967 polling-delay-passive = <250>;
1968 polling-delay = <0>;
1970 thermal-sensors = <&tsens0 11>;
1973 cpu8_alert0: trip-point0 {
1974 temperature = <90000>;
1975 hysteresis = <2000>;
1979 cpu8_alert1: trip-point1 {
1980 temperature = <95000>;
1981 hysteresis = <2000>;
1985 cpu8_crit: cpu-crit {
1986 temperature = <110000>;
1994 trip = <&cpu8_alert0>;
1995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1996 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1997 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1998 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2001 trip = <&cpu8_alert1>;
2002 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2003 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2004 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2005 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2011 polling-delay-passive = <250>;
2012 polling-delay = <0>;
2014 thermal-sensors = <&tsens0 12>;
2017 cpu9_alert0: trip-point0 {
2018 temperature = <90000>;
2019 hysteresis = <2000>;
2023 cpu9_alert1: trip-point1 {
2024 temperature = <95000>;
2025 hysteresis = <2000>;
2029 cpu9_crit: cpu-crit {
2030 temperature = <110000>;
2038 trip = <&cpu9_alert0>;
2039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2045 trip = <&cpu9_alert1>;
2046 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2047 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2048 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2049 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2055 polling-delay-passive = <250>;
2056 polling-delay = <0>;
2058 thermal-sensors = <&tsens0 13>;
2061 cpu10_alert0: trip-point0 {
2062 temperature = <90000>;
2063 hysteresis = <2000>;
2067 cpu10_alert1: trip-point1 {
2068 temperature = <95000>;
2069 hysteresis = <2000>;
2073 cpu10_crit: cpu-crit {
2074 temperature = <110000>;
2082 trip = <&cpu10_alert0>;
2083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2089 trip = <&cpu10_alert1>;
2090 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2091 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2092 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2093 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2099 polling-delay-passive = <250>;
2100 polling-delay = <0>;
2102 thermal-sensors = <&tsens0 14>;
2105 cpu11_alert0: trip-point0 {
2106 temperature = <90000>;
2107 hysteresis = <2000>;
2111 cpu11_alert1: trip-point1 {
2112 temperature = <95000>;
2113 hysteresis = <2000>;
2117 cpu11_crit: cpu-crit {
2118 temperature = <110000>;
2126 trip = <&cpu11_alert0>;
2127 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2128 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2129 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2130 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2133 trip = <&cpu11_alert1>;
2134 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2135 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2136 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2137 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2143 polling-delay-passive = <0>;
2144 polling-delay = <0>;
2146 thermal-sensors = <&tsens0 0>;
2149 aoss0_alert0: trip-point0 {
2150 temperature = <90000>;
2151 hysteresis = <2000>;
2155 aoss0_crit: aoss0-crit {
2156 temperature = <110000>;
2164 polling-delay-passive = <0>;
2165 polling-delay = <0>;
2167 thermal-sensors = <&tsens1 0>;
2170 aoss1_alert0: trip-point0 {
2171 temperature = <90000>;
2172 hysteresis = <2000>;
2176 aoss1_crit: aoss1-crit {
2177 temperature = <110000>;
2185 polling-delay-passive = <0>;
2186 polling-delay = <0>;
2188 thermal-sensors = <&tsens0 5>;
2191 cpuss0_alert0: trip-point0 {
2192 temperature = <90000>;
2193 hysteresis = <2000>;
2196 cpuss0_crit: cluster0-crit {
2197 temperature = <110000>;
2205 polling-delay-passive = <0>;
2206 polling-delay = <0>;
2208 thermal-sensors = <&tsens0 6>;
2211 cpuss1_alert0: trip-point0 {
2212 temperature = <90000>;
2213 hysteresis = <2000>;
2216 cpuss1_crit: cluster0-crit {
2217 temperature = <110000>;
2225 polling-delay-passive = <0>;
2226 polling-delay = <0>;
2228 thermal-sensors = <&tsens1 1>;
2231 gpuss0_alert0: trip-point0 {
2232 temperature = <90000>;
2233 hysteresis = <2000>;
2237 gpuss0_crit: gpuss0-crit {
2238 temperature = <110000>;
2246 polling-delay-passive = <0>;
2247 polling-delay = <0>;
2249 thermal-sensors = <&tsens1 2>;
2252 gpuss1_alert0: trip-point0 {
2253 temperature = <90000>;
2254 hysteresis = <2000>;
2258 gpuss1_crit: gpuss1-crit {
2259 temperature = <110000>;
2267 polling-delay-passive = <0>;
2268 polling-delay = <0>;
2270 thermal-sensors = <&tsens1 3>;
2273 nspss0_alert0: trip-point0 {
2274 temperature = <90000>;
2275 hysteresis = <2000>;
2279 nspss0_crit: nspss0-crit {
2280 temperature = <110000>;
2288 polling-delay-passive = <0>;
2289 polling-delay = <0>;
2291 thermal-sensors = <&tsens1 4>;
2294 nspss1_alert0: trip-point0 {
2295 temperature = <90000>;
2296 hysteresis = <2000>;
2300 nspss1_crit: nspss1-crit {
2301 temperature = <110000>;
2309 polling-delay-passive = <0>;
2310 polling-delay = <0>;
2312 thermal-sensors = <&tsens1 5>;
2315 video_alert0: trip-point0 {
2316 temperature = <90000>;
2317 hysteresis = <2000>;
2321 video_crit: video-crit {
2322 temperature = <110000>;
2330 polling-delay-passive = <0>;
2331 polling-delay = <0>;
2333 thermal-sensors = <&tsens1 6>;
2336 ddr_alert0: trip-point0 {
2337 temperature = <90000>;
2338 hysteresis = <2000>;
2342 ddr_crit: ddr-crit {
2343 temperature = <110000>;
2351 polling-delay-passive = <0>;
2352 polling-delay = <0>;
2354 thermal-sensors = <&tsens1 7>;
2357 mdmss0_alert0: trip-point0 {
2358 temperature = <90000>;
2359 hysteresis = <2000>;
2363 mdmss0_crit: mdmss0-crit {
2364 temperature = <110000>;
2372 polling-delay-passive = <0>;
2373 polling-delay = <0>;
2375 thermal-sensors = <&tsens1 8>;
2378 mdmss1_alert0: trip-point0 {
2379 temperature = <90000>;
2380 hysteresis = <2000>;
2384 mdmss1_crit: mdmss1-crit {
2385 temperature = <110000>;
2393 polling-delay-passive = <0>;
2394 polling-delay = <0>;
2396 thermal-sensors = <&tsens1 9>;
2399 mdmss2_alert0: trip-point0 {
2400 temperature = <90000>;
2401 hysteresis = <2000>;
2405 mdmss2_crit: mdmss2-crit {
2406 temperature = <110000>;
2414 polling-delay-passive = <0>;
2415 polling-delay = <0>;
2417 thermal-sensors = <&tsens1 10>;
2420 mdmss3_alert0: trip-point0 {
2421 temperature = <90000>;
2422 hysteresis = <2000>;
2426 mdmss3_crit: mdmss3-crit {
2427 temperature = <110000>;
2435 polling-delay-passive = <0>;
2436 polling-delay = <0>;
2438 thermal-sensors = <&tsens1 11>;
2441 camera0_alert0: trip-point0 {
2442 temperature = <90000>;
2443 hysteresis = <2000>;
2447 camera0_crit: camera0-crit {
2448 temperature = <110000>;
2457 compatible = "arm,armv8-timer";
2458 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2459 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2460 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2461 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;