arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interconnect/qcom,sc7280.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/mailbox/qcom-ipcc.h>
  13 #include <dt-bindings/power/qcom-aoss-qmp.h>
  14 #include <dt-bindings/power/qcom-rpmpd.h>
  15 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  16 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19
  20 / {
  21         interrupt-parent = <&intc>;
  22
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         chosen { };
  27
  28         aliases {
  29                 mmc1 = &sdhc_1;
  30                 mmc2 = &sdhc_2;
  31         };
  32
  33         clocks {
  34                 xo_board: xo-board {
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <76800000>;
  37                         #clock-cells = <0>;
  38                 };
  39
  40                 sleep_clk: sleep-clk {
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <32000>;
  43                         #clock-cells = <0>;
  44                 };
  45         };
  46
  47         reserved-memory {
  48                 #address-cells = <2>;
  49                 #size-cells = <2>;
  50                 ranges;
  51
  52                 aop_mem: memory@80800000 {
  53                         reg = <0x0 0x80800000 0x0 0x60000>;
  54                         no-map;
  55                 };
  56
  57                 aop_cmd_db_mem: memory@80860000 {
  58                         reg = <0x0 0x80860000 0x0 0x20000>;
  59                         compatible = "qcom,cmd-db";
  60                         no-map;
  61                 };
  62
  63                 smem_mem: memory@80900000 {
  64                         reg = <0x0 0x80900000 0x0 0x200000>;
  65                         no-map;
  66                 };
  67
  68                 cpucp_mem: memory@80b00000 {
  69                         no-map;
  70                         reg = <0x0 0x80b00000 0x0 0x100000>;
  71                 };
  72
  73                 ipa_fw_mem: memory@8b700000 {
  74                         reg = <0 0x8b700000 0 0x10000>;
  75                         no-map;
  76                 };
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 CPU0: cpu@0 {
  84                         device_type = "cpu";
  85                         compatible = "arm,kryo";
  86                         reg = <0x0 0x0>;
  87                         enable-method = "psci";
  88                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  89                                            &LITTLE_CPU_SLEEP_1
  90                                            &CLUSTER_SLEEP_0>;
  91                         next-level-cache = <&L2_0>;
  92                         qcom,freq-domain = <&cpufreq_hw 0>;
  93                         #cooling-cells = <2>;
  94                         L2_0: l2-cache {
  95                                 compatible = "cache";
  96                                 next-level-cache = <&L3_0>;
  97                                 L3_0: l3-cache {
  98                                         compatible = "cache";
  99                                 };
 100                         };
 101                 };
 102
 103                 CPU1: cpu@100 {
 104                         device_type = "cpu";
 105                         compatible = "arm,kryo";
 106                         reg = <0x0 0x100>;
 107                         enable-method = "psci";
 108                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 109                                            &LITTLE_CPU_SLEEP_1
 110                                            &CLUSTER_SLEEP_0>;
 111                         next-level-cache = <&L2_100>;
 112                         qcom,freq-domain = <&cpufreq_hw 0>;
 113                         #cooling-cells = <2>;
 114                         L2_100: l2-cache {
 115                                 compatible = "cache";
 116                                 next-level-cache = <&L3_0>;
 117                         };
 118                 };
 119
 120                 CPU2: cpu@200 {
 121                         device_type = "cpu";
 122                         compatible = "arm,kryo";
 123                         reg = <0x0 0x200>;
 124                         enable-method = "psci";
 125                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 126                                            &LITTLE_CPU_SLEEP_1
 127                                            &CLUSTER_SLEEP_0>;
 128                         next-level-cache = <&L2_200>;
 129                         qcom,freq-domain = <&cpufreq_hw 0>;
 130                         #cooling-cells = <2>;
 131                         L2_200: l2-cache {
 132                                 compatible = "cache";
 133                                 next-level-cache = <&L3_0>;
 134                         };
 135                 };
 136
 137                 CPU3: cpu@300 {
 138                         device_type = "cpu";
 139                         compatible = "arm,kryo";
 140                         reg = <0x0 0x300>;
 141                         enable-method = "psci";
 142                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 143                                            &LITTLE_CPU_SLEEP_1
 144                                            &CLUSTER_SLEEP_0>;
 145                         next-level-cache = <&L2_300>;
 146                         qcom,freq-domain = <&cpufreq_hw 0>;
 147                         #cooling-cells = <2>;
 148                         L2_300: l2-cache {
 149                                 compatible = "cache";
 150                                 next-level-cache = <&L3_0>;
 151                         };
 152                 };
 153
 154                 CPU4: cpu@400 {
 155                         device_type = "cpu";
 156                         compatible = "arm,kryo";
 157                         reg = <0x0 0x400>;
 158                         enable-method = "psci";
 159                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 160                                            &BIG_CPU_SLEEP_1
 161                                            &CLUSTER_SLEEP_0>;
 162                         next-level-cache = <&L2_400>;
 163                         qcom,freq-domain = <&cpufreq_hw 1>;
 164                         #cooling-cells = <2>;
 165                         L2_400: l2-cache {
 166                                 compatible = "cache";
 167                                 next-level-cache = <&L3_0>;
 168                         };
 169                 };
 170
 171                 CPU5: cpu@500 {
 172                         device_type = "cpu";
 173                         compatible = "arm,kryo";
 174                         reg = <0x0 0x500>;
 175                         enable-method = "psci";
 176                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 177                                            &BIG_CPU_SLEEP_1
 178                                            &CLUSTER_SLEEP_0>;
 179                         next-level-cache = <&L2_500>;
 180                         qcom,freq-domain = <&cpufreq_hw 1>;
 181                         #cooling-cells = <2>;
 182                         L2_500: l2-cache {
 183                                 compatible = "cache";
 184                                 next-level-cache = <&L3_0>;
 185                         };
 186                 };
 187
 188                 CPU6: cpu@600 {
 189                         device_type = "cpu";
 190                         compatible = "arm,kryo";
 191                         reg = <0x0 0x600>;
 192                         enable-method = "psci";
 193                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 194                                            &BIG_CPU_SLEEP_1
 195                                            &CLUSTER_SLEEP_0>;
 196                         next-level-cache = <&L2_600>;
 197                         qcom,freq-domain = <&cpufreq_hw 1>;
 198                         #cooling-cells = <2>;
 199                         L2_600: l2-cache {
 200                                 compatible = "cache";
 201                                 next-level-cache = <&L3_0>;
 202                         };
 203                 };
 204
 205                 CPU7: cpu@700 {
 206                         device_type = "cpu";
 207                         compatible = "arm,kryo";
 208                         reg = <0x0 0x700>;
 209                         enable-method = "psci";
 210                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 211                                            &BIG_CPU_SLEEP_1
 212                                            &CLUSTER_SLEEP_0>;
 213                         next-level-cache = <&L2_700>;
 214                         qcom,freq-domain = <&cpufreq_hw 2>;
 215                         #cooling-cells = <2>;
 216                         L2_700: l2-cache {
 217                                 compatible = "cache";
 218                                 next-level-cache = <&L3_0>;
 219                         };
 220                 };
 221
 222                 idle-states {
 223                         entry-method = "psci";
 224
 225                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 226                                 compatible = "arm,idle-state";
 227                                 idle-state-name = "little-power-down";
 228                                 arm,psci-suspend-param = <0x40000003>;
 229                                 entry-latency-us = <549>;
 230                                 exit-latency-us = <901>;
 231                                 min-residency-us = <1774>;
 232                                 local-timer-stop;
 233                         };
 234
 235                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 236                                 compatible = "arm,idle-state";
 237                                 idle-state-name = "little-rail-power-down";
 238                                 arm,psci-suspend-param = <0x40000004>;
 239                                 entry-latency-us = <702>;
 240                                 exit-latency-us = <915>;
 241                                 min-residency-us = <4001>;
 242                                 local-timer-stop;
 243                         };
 244
 245                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 246                                 compatible = "arm,idle-state";
 247                                 idle-state-name = "big-power-down";
 248                                 arm,psci-suspend-param = <0x40000003>;
 249                                 entry-latency-us = <523>;
 250                                 exit-latency-us = <1244>;
 251                                 min-residency-us = <2207>;
 252                                 local-timer-stop;
 253                         };
 254
 255                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 256                                 compatible = "arm,idle-state";
 257                                 idle-state-name = "big-rail-power-down";
 258                                 arm,psci-suspend-param = <0x40000004>;
 259                                 entry-latency-us = <526>;
 260                                 exit-latency-us = <1854>;
 261                                 min-residency-us = <5555>;
 262                                 local-timer-stop;
 263                         };
 264
 265                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 266                                 compatible = "arm,idle-state";
 267                                 idle-state-name = "cluster-power-down";
 268                                 arm,psci-suspend-param = <0x40003444>;
 269                                 entry-latency-us = <3263>;
 270                                 exit-latency-us = <6562>;
 271                                 min-residency-us = <9926>;
 272                                 local-timer-stop;
 273                         };
 274                 };
 275         };
 276
 277         memory@80000000 {
 278                 device_type = "memory";
 279                 /* We expect the bootloader to fill in the size */
 280                 reg = <0 0x80000000 0 0>;
 281         };
 282
 283         firmware {
 284                 scm {
 285                         compatible = "qcom,scm-sc7280", "qcom,scm";
 286                 };
 287         };
 288
 289         clk_virt: interconnect {
 290                 compatible = "qcom,sc7280-clk-virt";
 291                 #interconnect-cells = <2>;
 292                 qcom,bcm-voters = <&apps_bcm_voter>;
 293         };
 294
 295         smem {
 296                 compatible = "qcom,smem";
 297                 memory-region = <&smem_mem>;
 298                 hwlocks = <&tcsr_mutex 3>;
 299         };
 300
 301         smp2p-adsp {
 302                 compatible = "qcom,smp2p";
 303                 qcom,smem = <443>, <429>;
 304                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 305                                              IPCC_MPROC_SIGNAL_SMP2P
 306                                              IRQ_TYPE_EDGE_RISING>;
 307                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 308                                 IPCC_MPROC_SIGNAL_SMP2P>;
 309
 310                 qcom,local-pid = <0>;
 311                 qcom,remote-pid = <2>;
 312
 313                 adsp_smp2p_out: master-kernel {
 314                         qcom,entry-name = "master-kernel";
 315                         #qcom,smem-state-cells = <1>;
 316                 };
 317
 318                 adsp_smp2p_in: slave-kernel {
 319                         qcom,entry-name = "slave-kernel";
 320                         interrupt-controller;
 321                         #interrupt-cells = <2>;
 322                 };
 323         };
 324
 325         smp2p-cdsp {
 326                 compatible = "qcom,smp2p";
 327                 qcom,smem = <94>, <432>;
 328                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 329                                              IPCC_MPROC_SIGNAL_SMP2P
 330                                              IRQ_TYPE_EDGE_RISING>;
 331                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 332                                 IPCC_MPROC_SIGNAL_SMP2P>;
 333
 334                 qcom,local-pid = <0>;
 335                 qcom,remote-pid = <5>;
 336
 337                 cdsp_smp2p_out: master-kernel {
 338                         qcom,entry-name = "master-kernel";
 339                         #qcom,smem-state-cells = <1>;
 340                 };
 341
 342                 cdsp_smp2p_in: slave-kernel {
 343                         qcom,entry-name = "slave-kernel";
 344                         interrupt-controller;
 345                         #interrupt-cells = <2>;
 346                 };
 347         };
 348
 349         smp2p-mpss {
 350                 compatible = "qcom,smp2p";
 351                 qcom,smem = <435>, <428>;
 352                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 353                                              IPCC_MPROC_SIGNAL_SMP2P
 354                                              IRQ_TYPE_EDGE_RISING>;
 355                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 356                                 IPCC_MPROC_SIGNAL_SMP2P>;
 357
 358                 qcom,local-pid = <0>;
 359                 qcom,remote-pid = <1>;
 360
 361                 modem_smp2p_out: master-kernel {
 362                         qcom,entry-name = "master-kernel";
 363                         #qcom,smem-state-cells = <1>;
 364                 };
 365
 366                 modem_smp2p_in: slave-kernel {
 367                         qcom,entry-name = "slave-kernel";
 368                         interrupt-controller;
 369                         #interrupt-cells = <2>;
 370                 };
 371
 372                 ipa_smp2p_out: ipa-ap-to-modem {
 373                         qcom,entry-name = "ipa";
 374                         #qcom,smem-state-cells = <1>;
 375                 };
 376
 377                 ipa_smp2p_in: ipa-modem-to-ap {
 378                         qcom,entry-name = "ipa";
 379                         interrupt-controller;
 380                         #interrupt-cells = <2>;
 381                 };
 382         };
 383
 384         smp2p-wpss {
 385                 compatible = "qcom,smp2p";
 386                 qcom,smem = <617>, <616>;
 387                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 388                                              IPCC_MPROC_SIGNAL_SMP2P
 389                                              IRQ_TYPE_EDGE_RISING>;
 390                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 391                                 IPCC_MPROC_SIGNAL_SMP2P>;
 392
 393                 qcom,local-pid = <0>;
 394                 qcom,remote-pid = <13>;
 395
 396                 wpss_smp2p_out: master-kernel {
 397                         qcom,entry-name = "master-kernel";
 398                         #qcom,smem-state-cells = <1>;
 399                 };
 400
 401                 wpss_smp2p_in: slave-kernel {
 402                         qcom,entry-name = "slave-kernel";
 403                         interrupt-controller;
 404                         #interrupt-cells = <2>;
 405                 };
 406         };
 407
 408         pmu {
 409                 compatible = "arm,armv8-pmuv3";
 410                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 411         };
 412
 413         psci {
 414                 compatible = "arm,psci-1.0";
 415                 method = "smc";
 416         };
 417
 418         soc: soc@0 {
 419                 #address-cells = <2>;
 420                 #size-cells = <2>;
 421                 ranges = <0 0 0 0 0x10 0>;
 422                 dma-ranges = <0 0 0 0 0x10 0>;
 423                 compatible = "simple-bus";
 424
 425                 gcc: clock-controller@100000 {
 426                         compatible = "qcom,gcc-sc7280";
 427                         reg = <0 0x00100000 0 0x1f0000>;
 428                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 429                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 430                                  <0>, <0>, <0>, <0>, <0>, <0>;
 431                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 432                                       "pcie_0_pipe_clk", "pcie_1_pipe-clk",
 433                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 434                                       "ufs_phy_tx_symbol_0_clk",
 435                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 436                         #clock-cells = <1>;
 437                         #reset-cells = <1>;
 438                         #power-domain-cells = <1>;
 439                 };
 440
 441                 ipcc: mailbox@408000 {
 442                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 443                         reg = <0 0x00408000 0 0x1000>;
 444                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 445                         interrupt-controller;
 446                         #interrupt-cells = <3>;
 447                         #mbox-cells = <2>;
 448                 };
 449
 450                 qfprom: efuse@784000 {
 451                         compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
 452                         reg = <0 0x00784000 0 0xa20>,
 453                               <0 0x00780000 0 0xa20>,
 454                               <0 0x00782000 0 0x120>,
 455                               <0 0x00786000 0 0x1fff>;
 456                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 457                         clock-names = "core";
 458                         power-domains = <&rpmhpd SC7280_MX>;
 459                         #address-cells = <1>;
 460                         #size-cells = <1>;
 461                 };
 462
 463                 sdhc_1: sdhci@7c4000 {
 464                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 465                         status = "disabled";
 466
 467                         reg = <0 0x007c4000 0 0x1000>,
 468                               <0 0x007c5000 0 0x1000>;
 469                         reg-names = "hc", "cqhci";
 470
 471                         iommus = <&apps_smmu 0xc0 0x0>;
 472                         interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
 473                                      <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 474                         interrupt-names = "hc_irq", "pwr_irq";
 475
 476                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 477                                  <&gcc GCC_SDCC1_AHB_CLK>,
 478                                  <&rpmhcc RPMH_CXO_CLK>;
 479                         clock-names = "core", "iface", "xo";
 480                         interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
 481                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
 482                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 483                         power-domains = <&rpmhpd SC7280_CX>;
 484                         operating-points-v2 = <&sdhc1_opp_table>;
 485
 486                         bus-width = <8>;
 487                         supports-cqe;
 488
 489                         qcom,dll-config = <0x0007642c>;
 490                         qcom,ddr-config = <0x80040868>;
 491
 492                         mmc-ddr-1_8v;
 493                         mmc-hs200-1_8v;
 494                         mmc-hs400-1_8v;
 495                         mmc-hs400-enhanced-strobe;
 496
 497                         sdhc1_opp_table: opp-table {
 498                                 compatible = "operating-points-v2";
 499
 500                                 opp-100000000 {
 501                                         opp-hz = /bits/ 64 <100000000>;
 502                                         required-opps = <&rpmhpd_opp_low_svs>;
 503                                         opp-peak-kBps = <1800000 400000>;
 504                                         opp-avg-kBps = <100000 0>;
 505                                 };
 506
 507                                 opp-384000000 {
 508                                         opp-hz = /bits/ 64 <384000000>;
 509                                         required-opps = <&rpmhpd_opp_nom>;
 510                                         opp-peak-kBps = <5400000 1600000>;
 511                                         opp-avg-kBps = <390000 0>;
 512                                 };
 513                         };
 514
 515                 };
 516
 517                 qupv3_id_0: geniqup@9c0000 {
 518                         compatible = "qcom,geni-se-qup";
 519                         reg = <0 0x009c0000 0 0x2000>;
 520                         clock-names = "m-ahb", "s-ahb";
 521                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 522                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 523                         #address-cells = <2>;
 524                         #size-cells = <2>;
 525                         ranges;
 526                         status = "disabled";
 527
 528                         uart5: serial@994000 {
 529                                 compatible = "qcom,geni-debug-uart";
 530                                 reg = <0 0x00994000 0 0x4000>;
 531                                 clock-names = "se";
 532                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 533                                 pinctrl-names = "default";
 534                                 pinctrl-0 = <&qup_uart5_default>;
 535                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 536                                 status = "disabled";
 537                         };
 538                 };
 539
 540                 cnoc2: interconnect@1500000 {
 541                         reg = <0 0x01500000 0 0x1000>;
 542                         compatible = "qcom,sc7280-cnoc2";
 543                         #interconnect-cells = <2>;
 544                         qcom,bcm-voters = <&apps_bcm_voter>;
 545                 };
 546
 547                 cnoc3: interconnect@1502000 {
 548                         reg = <0 0x01502000 0 0x1000>;
 549                         compatible = "qcom,sc7280-cnoc3";
 550                         #interconnect-cells = <2>;
 551                         qcom,bcm-voters = <&apps_bcm_voter>;
 552                 };
 553
 554                 mc_virt: interconnect@1580000 {
 555                         reg = <0 0x01580000 0 0x4>;
 556                         compatible = "qcom,sc7280-mc-virt";
 557                         #interconnect-cells = <2>;
 558                         qcom,bcm-voters = <&apps_bcm_voter>;
 559                 };
 560
 561                 system_noc: interconnect@1680000 {
 562                         reg = <0 0x01680000 0 0x15480>;
 563                         compatible = "qcom,sc7280-system-noc";
 564                         #interconnect-cells = <2>;
 565                         qcom,bcm-voters = <&apps_bcm_voter>;
 566                 };
 567
 568                 aggre1_noc: interconnect@16e0000 {
 569                         compatible = "qcom,sc7280-aggre1-noc";
 570                         reg = <0 0x016e0000 0 0x1c080>;
 571                         #interconnect-cells = <2>;
 572                         qcom,bcm-voters = <&apps_bcm_voter>;
 573                 };
 574
 575                 aggre2_noc: interconnect@1700000 {
 576                         reg = <0 0x01700000 0 0x2b080>;
 577                         compatible = "qcom,sc7280-aggre2-noc";
 578                         #interconnect-cells = <2>;
 579                         qcom,bcm-voters = <&apps_bcm_voter>;
 580                 };
 581
 582                 mmss_noc: interconnect@1740000 {
 583                         reg = <0 0x01740000 0 0x1e080>;
 584                         compatible = "qcom,sc7280-mmss-noc";
 585                         #interconnect-cells = <2>;
 586                         qcom,bcm-voters = <&apps_bcm_voter>;
 587                 };
 588
 589                 ipa: ipa@1e40000 {
 590                         compatible = "qcom,sc7280-ipa";
 591
 592                         iommus = <&apps_smmu 0x480 0x0>,
 593                                  <&apps_smmu 0x482 0x0>;
 594                         reg = <0 0x1e40000 0 0x8000>,
 595                               <0 0x1e50000 0 0x4ad0>,
 596                               <0 0x1e04000 0 0x23000>;
 597                         reg-names = "ipa-reg",
 598                                     "ipa-shared",
 599                                     "gsi";
 600
 601                         interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
 602                                               <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
 603                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 604                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
 605                         interrupt-names = "ipa",
 606                                           "gsi",
 607                                           "ipa-clock-query",
 608                                           "ipa-setup-ready";
 609
 610                         clocks = <&rpmhcc RPMH_IPA_CLK>;
 611                         clock-names = "core";
 612
 613                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
 614                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
 615                         interconnect-names = "memory",
 616                                              "config";
 617
 618                         qcom,smem-states = <&ipa_smp2p_out 0>,
 619                                            <&ipa_smp2p_out 1>;
 620                         qcom,smem-state-names = "ipa-clock-enabled-valid",
 621                                                 "ipa-clock-enabled";
 622
 623                         status = "disabled";
 624                 };
 625
 626                 tcsr_mutex: hwlock@1f40000 {
 627                         compatible = "qcom,tcsr-mutex", "syscon";
 628                         reg = <0 0x01f40000 0 0x40000>;
 629                         #hwlock-cells = <1>;
 630                 };
 631
 632                 lpasscc: lpasscc@3000000 {
 633                         compatible = "qcom,sc7280-lpasscc";
 634                         reg = <0 0x03000000 0 0x40>,
 635                               <0 0x03c04000 0 0x4>,
 636                               <0 0x03389000 0 0x24>;
 637                         reg-names = "qdsp6ss", "top_cc", "cc";
 638                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
 639                         clock-names = "iface";
 640                         #clock-cells = <1>;
 641                 };
 642
 643                 lpass_ag_noc: interconnect@3c40000 {
 644                         reg = <0 0x03c40000 0 0xf080>;
 645                         compatible = "qcom,sc7280-lpass-ag-noc";
 646                         #interconnect-cells = <2>;
 647                         qcom,bcm-voters = <&apps_bcm_voter>;
 648                 };
 649
 650                 gpucc: clock-controller@3d90000 {
 651                         compatible = "qcom,sc7280-gpucc";
 652                         reg = <0 0x03d90000 0 0x9000>;
 653                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 654                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
 655                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
 656                         clock-names = "bi_tcxo",
 657                                       "gcc_gpu_gpll0_clk_src",
 658                                       "gcc_gpu_gpll0_div_clk_src";
 659                         #clock-cells = <1>;
 660                         #reset-cells = <1>;
 661                         #power-domain-cells = <1>;
 662                 };
 663
 664                 stm@6002000 {
 665                         compatible = "arm,coresight-stm", "arm,primecell";
 666                         reg = <0 0x06002000 0 0x1000>,
 667                               <0 0x16280000 0 0x180000>;
 668                         reg-names = "stm-base", "stm-stimulus-base";
 669
 670                         clocks = <&aoss_qmp>;
 671                         clock-names = "apb_pclk";
 672
 673                         out-ports {
 674                                 port {
 675                                         stm_out: endpoint {
 676                                                 remote-endpoint = <&funnel0_in7>;
 677                                         };
 678                                 };
 679                         };
 680                 };
 681
 682                 funnel@6041000 {
 683                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 684                         reg = <0 0x06041000 0 0x1000>;
 685
 686                         clocks = <&aoss_qmp>;
 687                         clock-names = "apb_pclk";
 688
 689                         out-ports {
 690                                 port {
 691                                         funnel0_out: endpoint {
 692                                                 remote-endpoint = <&merge_funnel_in0>;
 693                                         };
 694                                 };
 695                         };
 696
 697                         in-ports {
 698                                 #address-cells = <1>;
 699                                 #size-cells = <0>;
 700
 701                                 port@7 {
 702                                         reg = <7>;
 703                                         funnel0_in7: endpoint {
 704                                                 remote-endpoint = <&stm_out>;
 705                                         };
 706                                 };
 707                         };
 708                 };
 709
 710                 funnel@6042000 {
 711                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 712                         reg = <0 0x06042000 0 0x1000>;
 713
 714                         clocks = <&aoss_qmp>;
 715                         clock-names = "apb_pclk";
 716
 717                         out-ports {
 718                                 port {
 719                                         funnel1_out: endpoint {
 720                                                 remote-endpoint = <&merge_funnel_in1>;
 721                                         };
 722                                 };
 723                         };
 724
 725                         in-ports {
 726                                 #address-cells = <1>;
 727                                 #size-cells = <0>;
 728
 729                                 port@4 {
 730                                         reg = <4>;
 731                                         funnel1_in4: endpoint {
 732                                                 remote-endpoint = <&apss_merge_funnel_out>;
 733                                         };
 734                                 };
 735                         };
 736                 };
 737
 738                 funnel@6045000 {
 739                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 740                         reg = <0 0x06045000 0 0x1000>;
 741
 742                         clocks = <&aoss_qmp>;
 743                         clock-names = "apb_pclk";
 744
 745                         out-ports {
 746                                 port {
 747                                         merge_funnel_out: endpoint {
 748                                                 remote-endpoint = <&swao_funnel_in>;
 749                                         };
 750                                 };
 751                         };
 752
 753                         in-ports {
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756
 757                                 port@0 {
 758                                         reg = <0>;
 759                                         merge_funnel_in0: endpoint {
 760                                                 remote-endpoint = <&funnel0_out>;
 761                                         };
 762                                 };
 763
 764                                 port@1 {
 765                                         reg = <1>;
 766                                         merge_funnel_in1: endpoint {
 767                                                 remote-endpoint = <&funnel1_out>;
 768                                         };
 769                                 };
 770                         };
 771                 };
 772
 773                 replicator@6046000 {
 774                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 775                         reg = <0 0x06046000 0 0x1000>;
 776
 777                         clocks = <&aoss_qmp>;
 778                         clock-names = "apb_pclk";
 779
 780                         out-ports {
 781                                 port {
 782                                         replicator_out: endpoint {
 783                                                 remote-endpoint = <&etr_in>;
 784                                         };
 785                                 };
 786                         };
 787
 788                         in-ports {
 789                                 port {
 790                                         replicator_in: endpoint {
 791                                                 remote-endpoint = <&swao_replicator_out>;
 792                                         };
 793                                 };
 794                         };
 795                 };
 796
 797                 etr@6048000 {
 798                         compatible = "arm,coresight-tmc", "arm,primecell";
 799                         reg = <0 0x06048000 0 0x1000>;
 800                         iommus = <&apps_smmu 0x04c0 0>;
 801
 802                         clocks = <&aoss_qmp>;
 803                         clock-names = "apb_pclk";
 804                         arm,scatter-gather;
 805
 806                         in-ports {
 807                                 port {
 808                                         etr_in: endpoint {
 809                                                 remote-endpoint = <&replicator_out>;
 810                                         };
 811                                 };
 812                         };
 813                 };
 814
 815                 funnel@6b04000 {
 816                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 817                         reg = <0 0x06b04000 0 0x1000>;
 818
 819                         clocks = <&aoss_qmp>;
 820                         clock-names = "apb_pclk";
 821
 822                         out-ports {
 823                                 port {
 824                                         swao_funnel_out: endpoint {
 825                                                 remote-endpoint = <&etf_in>;
 826                                         };
 827                                 };
 828                         };
 829
 830                         in-ports {
 831                                 #address-cells = <1>;
 832                                 #size-cells = <0>;
 833
 834                                 port@7 {
 835                                         reg = <7>;
 836                                         swao_funnel_in: endpoint {
 837                                                 remote-endpoint = <&merge_funnel_out>;
 838                                         };
 839                                 };
 840                         };
 841                 };
 842
 843                 etf@6b05000 {
 844                         compatible = "arm,coresight-tmc", "arm,primecell";
 845                         reg = <0 0x06b05000 0 0x1000>;
 846
 847                         clocks = <&aoss_qmp>;
 848                         clock-names = "apb_pclk";
 849
 850                         out-ports {
 851                                 port {
 852                                         etf_out: endpoint {
 853                                                 remote-endpoint = <&swao_replicator_in>;
 854                                         };
 855                                 };
 856                         };
 857
 858                         in-ports {
 859                                 port {
 860                                         etf_in: endpoint {
 861                                                 remote-endpoint = <&swao_funnel_out>;
 862                                         };
 863                                 };
 864                         };
 865                 };
 866
 867                 replicator@6b06000 {
 868                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 869                         reg = <0 0x06b06000 0 0x1000>;
 870
 871                         clocks = <&aoss_qmp>;
 872                         clock-names = "apb_pclk";
 873                         qcom,replicator-loses-context;
 874
 875                         out-ports {
 876                                 port {
 877                                         swao_replicator_out: endpoint {
 878                                                 remote-endpoint = <&replicator_in>;
 879                                         };
 880                                 };
 881                         };
 882
 883                         in-ports {
 884                                 port {
 885                                         swao_replicator_in: endpoint {
 886                                                 remote-endpoint = <&etf_out>;
 887                                         };
 888                                 };
 889                         };
 890                 };
 891
 892                 etm@7040000 {
 893                         compatible = "arm,coresight-etm4x", "arm,primecell";
 894                         reg = <0 0x07040000 0 0x1000>;
 895
 896                         cpu = <&CPU0>;
 897
 898                         clocks = <&aoss_qmp>;
 899                         clock-names = "apb_pclk";
 900                         arm,coresight-loses-context-with-cpu;
 901                         qcom,skip-power-up;
 902
 903                         out-ports {
 904                                 port {
 905                                         etm0_out: endpoint {
 906                                                 remote-endpoint = <&apss_funnel_in0>;
 907                                         };
 908                                 };
 909                         };
 910                 };
 911
 912                 etm@7140000 {
 913                         compatible = "arm,coresight-etm4x", "arm,primecell";
 914                         reg = <0 0x07140000 0 0x1000>;
 915
 916                         cpu = <&CPU1>;
 917
 918                         clocks = <&aoss_qmp>;
 919                         clock-names = "apb_pclk";
 920                         arm,coresight-loses-context-with-cpu;
 921                         qcom,skip-power-up;
 922
 923                         out-ports {
 924                                 port {
 925                                         etm1_out: endpoint {
 926                                                 remote-endpoint = <&apss_funnel_in1>;
 927                                         };
 928                                 };
 929                         };
 930                 };
 931
 932                 etm@7240000 {
 933                         compatible = "arm,coresight-etm4x", "arm,primecell";
 934                         reg = <0 0x07240000 0 0x1000>;
 935
 936                         cpu = <&CPU2>;
 937
 938                         clocks = <&aoss_qmp>;
 939                         clock-names = "apb_pclk";
 940                         arm,coresight-loses-context-with-cpu;
 941                         qcom,skip-power-up;
 942
 943                         out-ports {
 944                                 port {
 945                                         etm2_out: endpoint {
 946                                                 remote-endpoint = <&apss_funnel_in2>;
 947                                         };
 948                                 };
 949                         };
 950                 };
 951
 952                 etm@7340000 {
 953                         compatible = "arm,coresight-etm4x", "arm,primecell";
 954                         reg = <0 0x07340000 0 0x1000>;
 955
 956                         cpu = <&CPU3>;
 957
 958                         clocks = <&aoss_qmp>;
 959                         clock-names = "apb_pclk";
 960                         arm,coresight-loses-context-with-cpu;
 961                         qcom,skip-power-up;
 962
 963                         out-ports {
 964                                 port {
 965                                         etm3_out: endpoint {
 966                                                 remote-endpoint = <&apss_funnel_in3>;
 967                                         };
 968                                 };
 969                         };
 970                 };
 971
 972                 etm@7440000 {
 973                         compatible = "arm,coresight-etm4x", "arm,primecell";
 974                         reg = <0 0x07440000 0 0x1000>;
 975
 976                         cpu = <&CPU4>;
 977
 978                         clocks = <&aoss_qmp>;
 979                         clock-names = "apb_pclk";
 980                         arm,coresight-loses-context-with-cpu;
 981                         qcom,skip-power-up;
 982
 983                         out-ports {
 984                                 port {
 985                                         etm4_out: endpoint {
 986                                                 remote-endpoint = <&apss_funnel_in4>;
 987                                         };
 988                                 };
 989                         };
 990                 };
 991
 992                 etm@7540000 {
 993                         compatible = "arm,coresight-etm4x", "arm,primecell";
 994                         reg = <0 0x07540000 0 0x1000>;
 995
 996                         cpu = <&CPU5>;
 997
 998                         clocks = <&aoss_qmp>;
 999                         clock-names = "apb_pclk";
1000                         arm,coresight-loses-context-with-cpu;
1001                         qcom,skip-power-up;
1002
1003                         out-ports {
1004                                 port {
1005                                         etm5_out: endpoint {
1006                                                 remote-endpoint = <&apss_funnel_in5>;
1007                                         };
1008                                 };
1009                         };
1010                 };
1011
1012                 etm@7640000 {
1013                         compatible = "arm,coresight-etm4x", "arm,primecell";
1014                         reg = <0 0x07640000 0 0x1000>;
1015
1016                         cpu = <&CPU6>;
1017
1018                         clocks = <&aoss_qmp>;
1019                         clock-names = "apb_pclk";
1020                         arm,coresight-loses-context-with-cpu;
1021                         qcom,skip-power-up;
1022
1023                         out-ports {
1024                                 port {
1025                                         etm6_out: endpoint {
1026                                                 remote-endpoint = <&apss_funnel_in6>;
1027                                         };
1028                                 };
1029                         };
1030                 };
1031
1032                 etm@7740000 {
1033                         compatible = "arm,coresight-etm4x", "arm,primecell";
1034                         reg = <0 0x07740000 0 0x1000>;
1035
1036                         cpu = <&CPU7>;
1037
1038                         clocks = <&aoss_qmp>;
1039                         clock-names = "apb_pclk";
1040                         arm,coresight-loses-context-with-cpu;
1041                         qcom,skip-power-up;
1042
1043                         out-ports {
1044                                 port {
1045                                         etm7_out: endpoint {
1046                                                 remote-endpoint = <&apss_funnel_in7>;
1047                                         };
1048                                 };
1049                         };
1050                 };
1051
1052                 funnel@7800000 { /* APSS Funnel */
1053                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1054                         reg = <0 0x07800000 0 0x1000>;
1055
1056                         clocks = <&aoss_qmp>;
1057                         clock-names = "apb_pclk";
1058
1059                         out-ports {
1060                                 port {
1061                                         apss_funnel_out: endpoint {
1062                                                 remote-endpoint = <&apss_merge_funnel_in>;
1063                                         };
1064                                 };
1065                         };
1066
1067                         in-ports {
1068                                 #address-cells = <1>;
1069                                 #size-cells = <0>;
1070
1071                                 port@0 {
1072                                         reg = <0>;
1073                                         apss_funnel_in0: endpoint {
1074                                                 remote-endpoint = <&etm0_out>;
1075                                         };
1076                                 };
1077
1078                                 port@1 {
1079                                         reg = <1>;
1080                                         apss_funnel_in1: endpoint {
1081                                                 remote-endpoint = <&etm1_out>;
1082                                         };
1083                                 };
1084
1085                                 port@2 {
1086                                         reg = <2>;
1087                                         apss_funnel_in2: endpoint {
1088                                                 remote-endpoint = <&etm2_out>;
1089                                         };
1090                                 };
1091
1092                                 port@3 {
1093                                         reg = <3>;
1094                                         apss_funnel_in3: endpoint {
1095                                                 remote-endpoint = <&etm3_out>;
1096                                         };
1097                                 };
1098
1099                                 port@4 {
1100                                         reg = <4>;
1101                                         apss_funnel_in4: endpoint {
1102                                                 remote-endpoint = <&etm4_out>;
1103                                         };
1104                                 };
1105
1106                                 port@5 {
1107                                         reg = <5>;
1108                                         apss_funnel_in5: endpoint {
1109                                                 remote-endpoint = <&etm5_out>;
1110                                         };
1111                                 };
1112
1113                                 port@6 {
1114                                         reg = <6>;
1115                                         apss_funnel_in6: endpoint {
1116                                                 remote-endpoint = <&etm6_out>;
1117                                         };
1118                                 };
1119
1120                                 port@7 {
1121                                         reg = <7>;
1122                                         apss_funnel_in7: endpoint {
1123                                                 remote-endpoint = <&etm7_out>;
1124                                         };
1125                                 };
1126                         };
1127                 };
1128
1129                 funnel@7810000 {
1130                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1131                         reg = <0 0x07810000 0 0x1000>;
1132
1133                         clocks = <&aoss_qmp>;
1134                         clock-names = "apb_pclk";
1135
1136                         out-ports {
1137                                 port {
1138                                         apss_merge_funnel_out: endpoint {
1139                                                 remote-endpoint = <&funnel1_in4>;
1140                                         };
1141                                 };
1142                         };
1143
1144                         in-ports {
1145                                 port {
1146                                         apss_merge_funnel_in: endpoint {
1147                                                 remote-endpoint = <&apss_funnel_out>;
1148                                         };
1149                                 };
1150                         };
1151                 };
1152
1153                 sdhc_2: sdhci@8804000 {
1154                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1155                         status = "disabled";
1156
1157                         reg = <0 0x08804000 0 0x1000>;
1158
1159                         iommus = <&apps_smmu 0x100 0x0>;
1160                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1162                         interrupt-names = "hc_irq", "pwr_irq";
1163
1164                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1165                                  <&gcc GCC_SDCC2_AHB_CLK>,
1166                                  <&rpmhcc RPMH_CXO_CLK>;
1167                         clock-names = "core", "iface", "xo";
1168                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
1169                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
1170                         interconnect-names = "sdhc-ddr","cpu-sdhc";
1171                         power-domains = <&rpmhpd SC7280_CX>;
1172                         operating-points-v2 = <&sdhc2_opp_table>;
1173
1174                         bus-width = <4>;
1175
1176                         qcom,dll-config = <0x0007642c>;
1177
1178                         sdhc2_opp_table: opp-table {
1179                                 compatible = "operating-points-v2";
1180
1181                                 opp-100000000 {
1182                                         opp-hz = /bits/ 64 <100000000>;
1183                                         required-opps = <&rpmhpd_opp_low_svs>;
1184                                         opp-peak-kBps = <1800000 400000>;
1185                                         opp-avg-kBps = <100000 0>;
1186                                 };
1187
1188                                 opp-202000000 {
1189                                         opp-hz = /bits/ 64 <202000000>;
1190                                         required-opps = <&rpmhpd_opp_nom>;
1191                                         opp-peak-kBps = <5400000 1600000>;
1192                                         opp-avg-kBps = <200000 0>;
1193                                 };
1194                         };
1195
1196                 };
1197
1198                 usb_1_hsphy: phy@88e3000 {
1199                         compatible = "qcom,sc7280-usb-hs-phy",
1200                                      "qcom,usb-snps-hs-7nm-phy";
1201                         reg = <0 0x088e3000 0 0x400>;
1202                         status = "disabled";
1203                         #phy-cells = <0>;
1204
1205                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1206                         clock-names = "ref";
1207
1208                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1209                 };
1210
1211                 usb_2_hsphy: phy@88e4000 {
1212                         compatible = "qcom,sc7280-usb-hs-phy",
1213                                      "qcom,usb-snps-hs-7nm-phy";
1214                         reg = <0 0x088e4000 0 0x400>;
1215                         status = "disabled";
1216                         #phy-cells = <0>;
1217
1218                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1219                         clock-names = "ref";
1220
1221                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1222                 };
1223
1224                 usb_1_qmpphy: phy-wrapper@88e9000 {
1225                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
1226                                      "qcom,sm8250-qmp-usb3-dp-phy";
1227                         reg = <0 0x088e9000 0 0x200>,
1228                               <0 0x088e8000 0 0x40>,
1229                               <0 0x088ea000 0 0x200>;
1230                         status = "disabled";
1231                         #address-cells = <2>;
1232                         #size-cells = <2>;
1233                         ranges;
1234
1235                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1236                                  <&rpmhcc RPMH_CXO_CLK>,
1237                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1238                         clock-names = "aux", "ref_clk_src", "com_aux";
1239
1240                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1241                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1242                         reset-names = "phy", "common";
1243
1244                         usb_1_ssphy: usb3-phy@88e9200 {
1245                                 reg = <0 0x088e9200 0 0x200>,
1246                                       <0 0x088e9400 0 0x200>,
1247                                       <0 0x088e9c00 0 0x400>,
1248                                       <0 0x088e9600 0 0x200>,
1249                                       <0 0x088e9800 0 0x200>,
1250                                       <0 0x088e9a00 0 0x100>;
1251                                 #clock-cells = <0>;
1252                                 #phy-cells = <0>;
1253                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1254                                 clock-names = "pipe0";
1255                                 clock-output-names = "usb3_phy_pipe_clk_src";
1256                         };
1257
1258                         dp_phy: dp-phy@88ea200 {
1259                                 reg = <0 0x088ea200 0 0x200>,
1260                                       <0 0x088ea400 0 0x200>,
1261                                       <0 0x088eac00 0 0x400>,
1262                                       <0 0x088ea600 0 0x200>,
1263                                       <0 0x088ea800 0 0x200>,
1264                                       <0 0x088eaa00 0 0x100>;
1265                                 #phy-cells = <0>;
1266                                 #clock-cells = <1>;
1267                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1268                                 clock-names = "pipe0";
1269                                 clock-output-names = "usb3_phy_pipe_clk_src";
1270                         };
1271                 };
1272
1273                 usb_2: usb@8cf8800 {
1274                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1275                         reg = <0 0x08cf8800 0 0x400>;
1276                         status = "disabled";
1277                         #address-cells = <2>;
1278                         #size-cells = <2>;
1279                         ranges;
1280                         dma-ranges;
1281
1282                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1283                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1284                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1285                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1286                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
1287                         clock-names = "cfg_noc", "core", "iface","mock_utmi",
1288                                       "sleep";
1289
1290                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1291                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1292                         assigned-clock-rates = <19200000>, <200000000>;
1293
1294                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1295                                      <&pdc 13 IRQ_TYPE_EDGE_RISING>,
1296                                      <&pdc 12 IRQ_TYPE_EDGE_RISING>;
1297                         interrupt-names = "hs_phy_irq",
1298                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
1299
1300                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
1301
1302                         resets = <&gcc GCC_USB30_SEC_BCR>;
1303
1304                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
1305                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
1306                         interconnect-names = "usb-ddr", "apps-usb";
1307
1308                         usb_2_dwc3: usb@8c00000 {
1309                                 compatible = "snps,dwc3";
1310                                 reg = <0 0x08c00000 0 0xe000>;
1311                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1312                                 iommus = <&apps_smmu 0xa0 0x0>;
1313                                 snps,dis_u2_susphy_quirk;
1314                                 snps,dis_enblslpm_quirk;
1315                                 phys = <&usb_2_hsphy>;
1316                                 phy-names = "usb2-phy";
1317                                 maximum-speed = "high-speed";
1318                         };
1319                 };
1320
1321                 dc_noc: interconnect@90e0000 {
1322                         reg = <0 0x090e0000 0 0x5080>;
1323                         compatible = "qcom,sc7280-dc-noc";
1324                         #interconnect-cells = <2>;
1325                         qcom,bcm-voters = <&apps_bcm_voter>;
1326                 };
1327
1328                 gem_noc: interconnect@9100000 {
1329                         reg = <0 0x9100000 0 0xe2200>;
1330                         compatible = "qcom,sc7280-gem-noc";
1331                         #interconnect-cells = <2>;
1332                         qcom,bcm-voters = <&apps_bcm_voter>;
1333                 };
1334
1335                 system-cache-controller@9200000 {
1336                         compatible = "qcom,sc7280-llcc";
1337                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
1338                         reg-names = "llcc_base", "llcc_broadcast_base";
1339                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1340                 };
1341
1342                 nsp_noc: interconnect@a0c0000 {
1343                         reg = <0 0x0a0c0000 0 0x10000>;
1344                         compatible = "qcom,sc7280-nsp-noc";
1345                         #interconnect-cells = <2>;
1346                         qcom,bcm-voters = <&apps_bcm_voter>;
1347                 };
1348
1349                 usb_1: usb@a6f8800 {
1350                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1351                         reg = <0 0x0a6f8800 0 0x400>;
1352                         status = "disabled";
1353                         #address-cells = <2>;
1354                         #size-cells = <2>;
1355                         ranges;
1356                         dma-ranges;
1357
1358                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1359                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1360                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1361                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1362                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1363                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1364                                       "sleep";
1365
1366                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1367                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1368                         assigned-clock-rates = <19200000>, <200000000>;
1369
1370                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1371                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1372                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1373                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1374                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1375                                           "dm_hs_phy_irq", "ss_phy_irq";
1376
1377                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1378
1379                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1380
1381                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1382                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
1383                         interconnect-names = "usb-ddr", "apps-usb";
1384
1385                         usb_1_dwc3: usb@a600000 {
1386                                 compatible = "snps,dwc3";
1387                                 reg = <0 0x0a600000 0 0xe000>;
1388                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1389                                 iommus = <&apps_smmu 0xe0 0x0>;
1390                                 snps,dis_u2_susphy_quirk;
1391                                 snps,dis_enblslpm_quirk;
1392                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1393                                 phy-names = "usb2-phy", "usb3-phy";
1394                                 maximum-speed = "super-speed";
1395                         };
1396                 };
1397
1398                 videocc: clock-controller@aaf0000 {
1399                         compatible = "qcom,sc7280-videocc";
1400                         reg = <0 0xaaf0000 0 0x10000>;
1401                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1402                                 <&rpmhcc RPMH_CXO_CLK_A>;
1403                         clock-names = "bi_tcxo", "bi_tcxo_ao";
1404                         #clock-cells = <1>;
1405                         #reset-cells = <1>;
1406                         #power-domain-cells = <1>;
1407                 };
1408
1409                 dispcc: clock-controller@af00000 {
1410                         compatible = "qcom,sc7280-dispcc";
1411                         reg = <0 0xaf00000 0 0x20000>;
1412                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1413                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1414                                  <0>, <0>, <0>, <0>, <0>, <0>;
1415                         clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
1416                                       "dsi0_phy_pll_out_byteclk",
1417                                       "dsi0_phy_pll_out_dsiclk",
1418                                       "dp_phy_pll_link_clk",
1419                                       "dp_phy_pll_vco_div_clk",
1420                                       "edp_phy_pll_link_clk",
1421                                       "edp_phy_pll_vco_div_clk";
1422                         #clock-cells = <1>;
1423                         #reset-cells = <1>;
1424                         #power-domain-cells = <1>;
1425                 };
1426
1427                 pdc: interrupt-controller@b220000 {
1428                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
1429                         reg = <0 0x0b220000 0 0x30000>;
1430                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
1431                                           <55 306 4>, <59 312 3>, <62 374 2>,
1432                                           <64 434 2>, <66 438 3>, <69 86 1>,
1433                                           <70 520 54>, <124 609 31>, <155 63 1>,
1434                                           <156 716 12>;
1435                         #interrupt-cells = <2>;
1436                         interrupt-parent = <&intc>;
1437                         interrupt-controller;
1438                 };
1439
1440                 pdc_reset: reset-controller@b5e0000 {
1441                         compatible = "qcom,sc7280-pdc-global";
1442                         reg = <0 0x0b5e0000 0 0x20000>;
1443                         #reset-cells = <1>;
1444                 };
1445
1446                 tsens0: thermal-sensor@c263000 {
1447                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1448                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1449                                 <0 0x0c222000 0 0x1ff>; /* SROT */
1450                         #qcom,sensors = <15>;
1451                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1452                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1453                         interrupt-names = "uplow","critical";
1454                         #thermal-sensor-cells = <1>;
1455                 };
1456
1457                 tsens1: thermal-sensor@c265000 {
1458                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1459                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1460                                 <0 0x0c223000 0 0x1ff>; /* SROT */
1461                         #qcom,sensors = <12>;
1462                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1463                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1464                         interrupt-names = "uplow","critical";
1465                         #thermal-sensor-cells = <1>;
1466                 };
1467
1468                 aoss_reset: reset-controller@c2a0000 {
1469                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
1470                         reg = <0 0x0c2a0000 0 0x31000>;
1471                         #reset-cells = <1>;
1472                 };
1473
1474                 aoss_qmp: power-controller@c300000 {
1475                         compatible = "qcom,sc7280-aoss-qmp";
1476                         reg = <0 0x0c300000 0 0x100000>;
1477                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1478                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
1479                                                      IRQ_TYPE_EDGE_RISING>;
1480                         mboxes = <&ipcc IPCC_CLIENT_AOP
1481                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
1482
1483                         #clock-cells = <0>;
1484                         #power-domain-cells = <1>;
1485                 };
1486
1487                 spmi_bus: spmi@c440000 {
1488                         compatible = "qcom,spmi-pmic-arb";
1489                         reg = <0 0x0c440000 0 0x1100>,
1490                               <0 0x0c600000 0 0x2000000>,
1491                               <0 0x0e600000 0 0x100000>,
1492                               <0 0x0e700000 0 0xa0000>,
1493                               <0 0x0c40a000 0 0x26000>;
1494                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1495                         interrupt-names = "periph_irq";
1496                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1497                         qcom,ee = <0>;
1498                         qcom,channel = <0>;
1499                         #address-cells = <1>;
1500                         #size-cells = <1>;
1501                         interrupt-controller;
1502                         #interrupt-cells = <4>;
1503                 };
1504
1505                 tlmm: pinctrl@f100000 {
1506                         compatible = "qcom,sc7280-pinctrl";
1507                         reg = <0 0x0f100000 0 0x300000>;
1508                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1509                         gpio-controller;
1510                         #gpio-cells = <2>;
1511                         interrupt-controller;
1512                         #interrupt-cells = <2>;
1513                         gpio-ranges = <&tlmm 0 0 175>;
1514                         wakeup-parent = <&pdc>;
1515
1516                         qup_uart5_default: qup-uart5-default {
1517                                 pins = "gpio46", "gpio47";
1518                                 function = "qup13";
1519                         };
1520
1521                         sdc1_on: sdc1-on {
1522                                 clk {
1523                                         pins = "sdc1_clk";
1524                                 };
1525
1526                                 cmd {
1527                                         pins = "sdc1_cmd";
1528                                 };
1529
1530                                 data {
1531                                         pins = "sdc1_data";
1532                                 };
1533
1534                                 rclk {
1535                                         pins = "sdc1_rclk";
1536                                 };
1537                         };
1538
1539                         sdc1_off: sdc1-off {
1540                                 clk {
1541                                         pins = "sdc1_clk";
1542                                         drive-strength = <2>;
1543                                         bias-bus-hold;
1544                                 };
1545
1546                                 cmd {
1547                                         pins = "sdc1_cmd";
1548                                         drive-strength = <2>;
1549                                         bias-bus-hold;
1550                                 };
1551
1552                                 data {
1553                                         pins = "sdc1_data";
1554                                         drive-strength = <2>;
1555                                         bias-bus-hold;
1556                                 };
1557
1558                                 rclk {
1559                                         pins = "sdc1_rclk";
1560                                         bias-bus-hold;
1561                                 };
1562                         };
1563
1564                         sdc2_on: sdc2-on {
1565                                 clk {
1566                                         pins = "sdc2_clk";
1567                                 };
1568
1569                                 cmd {
1570                                         pins = "sdc2_cmd";
1571                                 };
1572
1573                                 data {
1574                                         pins = "sdc2_data";
1575                                 };
1576
1577                                 sd-cd {
1578                                         pins = "gpio91";
1579                                 };
1580                         };
1581
1582                         sdc2_off: sdc2-off {
1583                                 clk {
1584                                         pins = "sdc2_clk";
1585                                         drive-strength = <2>;
1586                                         bias-bus-hold;
1587                                 };
1588
1589                                 cmd {
1590                                         pins ="sdc2_cmd";
1591                                         drive-strength = <2>;
1592                                         bias-bus-hold;
1593                                 };
1594
1595                                 data {
1596                                         pins ="sdc2_data";
1597                                         drive-strength = <2>;
1598                                         bias-bus-hold;
1599                                 };
1600                         };
1601                 };
1602
1603                 apps_smmu: iommu@15000000 {
1604                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
1605                         reg = <0 0x15000000 0 0x100000>;
1606                         #iommu-cells = <2>;
1607                         #global-interrupts = <1>;
1608                         dma-coherent;
1609                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1610                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1611                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1612                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1613                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1614                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1615                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1616                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1617                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1618                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1619                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1620                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1621                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1622                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1623                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1624                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1625                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1626                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1627                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1628                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1629                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1630                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1631                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1632                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1633                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1634                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1635                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1636                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1637                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1638                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1639                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1640                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1641                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1642                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1643                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1644                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1645                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1646                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1647                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1648                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1649                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1650                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1651                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1652                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1653                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1654                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1655                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1656                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1657                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1658                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1659                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1660                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1661                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1662                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1663                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1664                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1665                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1666                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1667                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1668                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1669                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1670                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1671                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1672                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1673                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1674                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1675                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1676                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1677                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1678                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1679                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1680                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1681                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1682                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1683                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1684                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1685                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1686                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1687                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1688                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1689                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1690                 };
1691
1692                 intc: interrupt-controller@17a00000 {
1693                         compatible = "arm,gic-v3";
1694                         #address-cells = <2>;
1695                         #size-cells = <2>;
1696                         ranges;
1697                         #interrupt-cells = <3>;
1698                         interrupt-controller;
1699                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
1700                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
1701                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1702
1703                         gic-its@17a40000 {
1704                                 compatible = "arm,gic-v3-its";
1705                                 msi-controller;
1706                                 #msi-cells = <1>;
1707                                 reg = <0 0x17a40000 0 0x20000>;
1708                                 status = "disabled";
1709                         };
1710                 };
1711
1712                 watchdog@17c10000 {
1713                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
1714                         reg = <0 0x17c10000 0 0x1000>;
1715                         clocks = <&sleep_clk>;
1716                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1717                 };
1718
1719                 timer@17c20000 {
1720                         #address-cells = <2>;
1721                         #size-cells = <2>;
1722                         ranges;
1723                         compatible = "arm,armv7-timer-mem";
1724                         reg = <0 0x17c20000 0 0x1000>;
1725
1726                         frame@17c21000 {
1727                                 frame-number = <0>;
1728                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1729                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1730                                 reg = <0 0x17c21000 0 0x1000>,
1731                                       <0 0x17c22000 0 0x1000>;
1732                         };
1733
1734                         frame@17c23000 {
1735                                 frame-number = <1>;
1736                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1737                                 reg = <0 0x17c23000 0 0x1000>;
1738                                 status = "disabled";
1739                         };
1740
1741                         frame@17c25000 {
1742                                 frame-number = <2>;
1743                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1744                                 reg = <0 0x17c25000 0 0x1000>;
1745                                 status = "disabled";
1746                         };
1747
1748                         frame@17c27000 {
1749                                 frame-number = <3>;
1750                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1751                                 reg = <0 0x17c27000 0 0x1000>;
1752                                 status = "disabled";
1753                         };
1754
1755                         frame@17c29000 {
1756                                 frame-number = <4>;
1757                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1758                                 reg = <0 0x17c29000 0 0x1000>;
1759                                 status = "disabled";
1760                         };
1761
1762                         frame@17c2b000 {
1763                                 frame-number = <5>;
1764                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1765                                 reg = <0 0x17c2b000 0 0x1000>;
1766                                 status = "disabled";
1767                         };
1768
1769                         frame@17c2d000 {
1770                                 frame-number = <6>;
1771                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1772                                 reg = <0 0x17c2d000 0 0x1000>;
1773                                 status = "disabled";
1774                         };
1775                 };
1776
1777                 apps_rsc: rsc@18200000 {
1778                         compatible = "qcom,rpmh-rsc";
1779                         reg = <0 0x18200000 0 0x10000>,
1780                               <0 0x18210000 0 0x10000>,
1781                               <0 0x18220000 0 0x10000>;
1782                         reg-names = "drv-0", "drv-1", "drv-2";
1783                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1784                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1785                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1786                         qcom,tcs-offset = <0xd00>;
1787                         qcom,drv-id = <2>;
1788                         qcom,tcs-config = <ACTIVE_TCS  2>,
1789                                           <SLEEP_TCS   3>,
1790                                           <WAKE_TCS    3>,
1791                                           <CONTROL_TCS 1>;
1792
1793                         apps_bcm_voter: bcm-voter {
1794                                 compatible = "qcom,bcm-voter";
1795                         };
1796
1797                         rpmhpd: power-controller {
1798                                 compatible = "qcom,sc7280-rpmhpd";
1799                                 #power-domain-cells = <1>;
1800                                 operating-points-v2 = <&rpmhpd_opp_table>;
1801
1802                                 rpmhpd_opp_table: opp-table {
1803                                         compatible = "operating-points-v2";
1804
1805                                         rpmhpd_opp_ret: opp1 {
1806                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1807                                         };
1808
1809                                         rpmhpd_opp_low_svs: opp2 {
1810                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1811                                         };
1812
1813                                         rpmhpd_opp_svs: opp3 {
1814                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1815                                         };
1816
1817                                         rpmhpd_opp_svs_l1: opp4 {
1818                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1819                                         };
1820
1821                                         rpmhpd_opp_svs_l2: opp5 {
1822                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1823                                         };
1824
1825                                         rpmhpd_opp_nom: opp6 {
1826                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1827                                         };
1828
1829                                         rpmhpd_opp_nom_l1: opp7 {
1830                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1831                                         };
1832
1833                                         rpmhpd_opp_turbo: opp8 {
1834                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1835                                         };
1836
1837                                         rpmhpd_opp_turbo_l1: opp9 {
1838                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1839                                         };
1840                                 };
1841                         };
1842
1843                         rpmhcc: clock-controller {
1844                                 compatible = "qcom,sc7280-rpmh-clk";
1845                                 clocks = <&xo_board>;
1846                                 clock-names = "xo";
1847                                 #clock-cells = <1>;
1848                         };
1849                 };
1850
1851                 cpufreq_hw: cpufreq@18591000 {
1852                         compatible = "qcom,cpufreq-epss";
1853                         reg = <0 0x18591100 0 0x900>,
1854                               <0 0x18592100 0 0x900>,
1855                               <0 0x18593100 0 0x900>;
1856                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1857                         clock-names = "xo", "alternate";
1858                         #freq-domain-cells = <1>;
1859                 };
1860         };
1861
1862         thermal_zones: thermal-zones {
1863                 cpu0-thermal {
1864                         polling-delay-passive = <250>;
1865                         polling-delay = <0>;
1866
1867                         thermal-sensors = <&tsens0 1>;
1868
1869                         trips {
1870                                 cpu0_alert0: trip-point0 {
1871                                         temperature = <90000>;
1872                                         hysteresis = <2000>;
1873                                         type = "passive";
1874                                 };
1875
1876                                 cpu0_alert1: trip-point1 {
1877                                         temperature = <95000>;
1878                                         hysteresis = <2000>;
1879                                         type = "passive";
1880                                 };
1881
1882                                 cpu0_crit: cpu-crit {
1883                                         temperature = <110000>;
1884                                         hysteresis = <0>;
1885                                         type = "critical";
1886                                 };
1887                         };
1888
1889                         cooling-maps {
1890                                 map0 {
1891                                         trip = <&cpu0_alert0>;
1892                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1893                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1894                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1895                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1896                                 };
1897                                 map1 {
1898                                         trip = <&cpu0_alert1>;
1899                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1900                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1901                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1902                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1903                                 };
1904                         };
1905                 };
1906
1907                 cpu1-thermal {
1908                         polling-delay-passive = <250>;
1909                         polling-delay = <0>;
1910
1911                         thermal-sensors = <&tsens0 2>;
1912
1913                         trips {
1914                                 cpu1_alert0: trip-point0 {
1915                                         temperature = <90000>;
1916                                         hysteresis = <2000>;
1917                                         type = "passive";
1918                                 };
1919
1920                                 cpu1_alert1: trip-point1 {
1921                                         temperature = <95000>;
1922                                         hysteresis = <2000>;
1923                                         type = "passive";
1924                                 };
1925
1926                                 cpu1_crit: cpu-crit {
1927                                         temperature = <110000>;
1928                                         hysteresis = <0>;
1929                                         type = "critical";
1930                                 };
1931                         };
1932
1933                         cooling-maps {
1934                                 map0 {
1935                                         trip = <&cpu1_alert0>;
1936                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1937                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1938                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1939                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1940                                 };
1941                                 map1 {
1942                                         trip = <&cpu1_alert1>;
1943                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1944                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1945                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1946                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1947                                 };
1948                         };
1949                 };
1950
1951                 cpu2-thermal {
1952                         polling-delay-passive = <250>;
1953                         polling-delay = <0>;
1954
1955                         thermal-sensors = <&tsens0 3>;
1956
1957                         trips {
1958                                 cpu2_alert0: trip-point0 {
1959                                         temperature = <90000>;
1960                                         hysteresis = <2000>;
1961                                         type = "passive";
1962                                 };
1963
1964                                 cpu2_alert1: trip-point1 {
1965                                         temperature = <95000>;
1966                                         hysteresis = <2000>;
1967                                         type = "passive";
1968                                 };
1969
1970                                 cpu2_crit: cpu-crit {
1971                                         temperature = <110000>;
1972                                         hysteresis = <0>;
1973                                         type = "critical";
1974                                 };
1975                         };
1976
1977                         cooling-maps {
1978                                 map0 {
1979                                         trip = <&cpu2_alert0>;
1980                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1981                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1982                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1983                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1984                                 };
1985                                 map1 {
1986                                         trip = <&cpu2_alert1>;
1987                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1988                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1989                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1990                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1991                                 };
1992                         };
1993                 };
1994
1995                 cpu3-thermal {
1996                         polling-delay-passive = <250>;
1997                         polling-delay = <0>;
1998
1999                         thermal-sensors = <&tsens0 4>;
2000
2001                         trips {
2002                                 cpu3_alert0: trip-point0 {
2003                                         temperature = <90000>;
2004                                         hysteresis = <2000>;
2005                                         type = "passive";
2006                                 };
2007
2008                                 cpu3_alert1: trip-point1 {
2009                                         temperature = <95000>;
2010                                         hysteresis = <2000>;
2011                                         type = "passive";
2012                                 };
2013
2014                                 cpu3_crit: cpu-crit {
2015                                         temperature = <110000>;
2016                                         hysteresis = <0>;
2017                                         type = "critical";
2018                                 };
2019                         };
2020
2021                         cooling-maps {
2022                                 map0 {
2023                                         trip = <&cpu3_alert0>;
2024                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2025                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2026                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2027                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2028                                 };
2029                                 map1 {
2030                                         trip = <&cpu3_alert1>;
2031                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2032                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2033                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2034                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2035                                 };
2036                         };
2037                 };
2038
2039                 cpu4-thermal {
2040                         polling-delay-passive = <250>;
2041                         polling-delay = <0>;
2042
2043                         thermal-sensors = <&tsens0 7>;
2044
2045                         trips {
2046                                 cpu4_alert0: trip-point0 {
2047                                         temperature = <90000>;
2048                                         hysteresis = <2000>;
2049                                         type = "passive";
2050                                 };
2051
2052                                 cpu4_alert1: trip-point1 {
2053                                         temperature = <95000>;
2054                                         hysteresis = <2000>;
2055                                         type = "passive";
2056                                 };
2057
2058                                 cpu4_crit: cpu-crit {
2059                                         temperature = <110000>;
2060                                         hysteresis = <0>;
2061                                         type = "critical";
2062                                 };
2063                         };
2064
2065                         cooling-maps {
2066                                 map0 {
2067                                         trip = <&cpu4_alert0>;
2068                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2069                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2070                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2071                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2072                                 };
2073                                 map1 {
2074                                         trip = <&cpu4_alert1>;
2075                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2076                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2077                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2078                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2079                                 };
2080                         };
2081                 };
2082
2083                 cpu5-thermal {
2084                         polling-delay-passive = <250>;
2085                         polling-delay = <0>;
2086
2087                         thermal-sensors = <&tsens0 8>;
2088
2089                         trips {
2090                                 cpu5_alert0: trip-point0 {
2091                                         temperature = <90000>;
2092                                         hysteresis = <2000>;
2093                                         type = "passive";
2094                                 };
2095
2096                                 cpu5_alert1: trip-point1 {
2097                                         temperature = <95000>;
2098                                         hysteresis = <2000>;
2099                                         type = "passive";
2100                                 };
2101
2102                                 cpu5_crit: cpu-crit {
2103                                         temperature = <110000>;
2104                                         hysteresis = <0>;
2105                                         type = "critical";
2106                                 };
2107                         };
2108
2109                         cooling-maps {
2110                                 map0 {
2111                                         trip = <&cpu5_alert0>;
2112                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2113                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2114                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2115                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2116                                 };
2117                                 map1 {
2118                                         trip = <&cpu5_alert1>;
2119                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2120                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2121                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2122                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2123                                 };
2124                         };
2125                 };
2126
2127                 cpu6-thermal {
2128                         polling-delay-passive = <250>;
2129                         polling-delay = <0>;
2130
2131                         thermal-sensors = <&tsens0 9>;
2132
2133                         trips {
2134                                 cpu6_alert0: trip-point0 {
2135                                         temperature = <90000>;
2136                                         hysteresis = <2000>;
2137                                         type = "passive";
2138                                 };
2139
2140                                 cpu6_alert1: trip-point1 {
2141                                         temperature = <95000>;
2142                                         hysteresis = <2000>;
2143                                         type = "passive";
2144                                 };
2145
2146                                 cpu6_crit: cpu-crit {
2147                                         temperature = <110000>;
2148                                         hysteresis = <0>;
2149                                         type = "critical";
2150                                 };
2151                         };
2152
2153                         cooling-maps {
2154                                 map0 {
2155                                         trip = <&cpu6_alert0>;
2156                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2157                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2158                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2159                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2160                                 };
2161                                 map1 {
2162                                         trip = <&cpu6_alert1>;
2163                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2164                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2165                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2166                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2167                                 };
2168                         };
2169                 };
2170
2171                 cpu7-thermal {
2172                         polling-delay-passive = <250>;
2173                         polling-delay = <0>;
2174
2175                         thermal-sensors = <&tsens0 10>;
2176
2177                         trips {
2178                                 cpu7_alert0: trip-point0 {
2179                                         temperature = <90000>;
2180                                         hysteresis = <2000>;
2181                                         type = "passive";
2182                                 };
2183
2184                                 cpu7_alert1: trip-point1 {
2185                                         temperature = <95000>;
2186                                         hysteresis = <2000>;
2187                                         type = "passive";
2188                                 };
2189
2190                                 cpu7_crit: cpu-crit {
2191                                         temperature = <110000>;
2192                                         hysteresis = <0>;
2193                                         type = "critical";
2194                                 };
2195                         };
2196
2197                         cooling-maps {
2198                                 map0 {
2199                                         trip = <&cpu7_alert0>;
2200                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2201                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2202                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2203                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2204                                 };
2205                                 map1 {
2206                                         trip = <&cpu7_alert1>;
2207                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2208                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2209                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2210                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2211                                 };
2212                         };
2213                 };
2214
2215                 cpu8-thermal {
2216                         polling-delay-passive = <250>;
2217                         polling-delay = <0>;
2218
2219                         thermal-sensors = <&tsens0 11>;
2220
2221                         trips {
2222                                 cpu8_alert0: trip-point0 {
2223                                         temperature = <90000>;
2224                                         hysteresis = <2000>;
2225                                         type = "passive";
2226                                 };
2227
2228                                 cpu8_alert1: trip-point1 {
2229                                         temperature = <95000>;
2230                                         hysteresis = <2000>;
2231                                         type = "passive";
2232                                 };
2233
2234                                 cpu8_crit: cpu-crit {
2235                                         temperature = <110000>;
2236                                         hysteresis = <0>;
2237                                         type = "critical";
2238                                 };
2239                         };
2240
2241                         cooling-maps {
2242                                 map0 {
2243                                         trip = <&cpu8_alert0>;
2244                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2245                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2246                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2247                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2248                                 };
2249                                 map1 {
2250                                         trip = <&cpu8_alert1>;
2251                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2252                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2253                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2254                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2255                                 };
2256                         };
2257                 };
2258
2259                 cpu9-thermal {
2260                         polling-delay-passive = <250>;
2261                         polling-delay = <0>;
2262
2263                         thermal-sensors = <&tsens0 12>;
2264
2265                         trips {
2266                                 cpu9_alert0: trip-point0 {
2267                                         temperature = <90000>;
2268                                         hysteresis = <2000>;
2269                                         type = "passive";
2270                                 };
2271
2272                                 cpu9_alert1: trip-point1 {
2273                                         temperature = <95000>;
2274                                         hysteresis = <2000>;
2275                                         type = "passive";
2276                                 };
2277
2278                                 cpu9_crit: cpu-crit {
2279                                         temperature = <110000>;
2280                                         hysteresis = <0>;
2281                                         type = "critical";
2282                                 };
2283                         };
2284
2285                         cooling-maps {
2286                                 map0 {
2287                                         trip = <&cpu9_alert0>;
2288                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2289                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2290                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2291                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2292                                 };
2293                                 map1 {
2294                                         trip = <&cpu9_alert1>;
2295                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2296                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2297                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2298                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2299                                 };
2300                         };
2301                 };
2302
2303                 cpu10-thermal {
2304                         polling-delay-passive = <250>;
2305                         polling-delay = <0>;
2306
2307                         thermal-sensors = <&tsens0 13>;
2308
2309                         trips {
2310                                 cpu10_alert0: trip-point0 {
2311                                         temperature = <90000>;
2312                                         hysteresis = <2000>;
2313                                         type = "passive";
2314                                 };
2315
2316                                 cpu10_alert1: trip-point1 {
2317                                         temperature = <95000>;
2318                                         hysteresis = <2000>;
2319                                         type = "passive";
2320                                 };
2321
2322                                 cpu10_crit: cpu-crit {
2323                                         temperature = <110000>;
2324                                         hysteresis = <0>;
2325                                         type = "critical";
2326                                 };
2327                         };
2328
2329                         cooling-maps {
2330                                 map0 {
2331                                         trip = <&cpu10_alert0>;
2332                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2333                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2334                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2335                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2336                                 };
2337                                 map1 {
2338                                         trip = <&cpu10_alert1>;
2339                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2340                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2341                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2342                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2343                                 };
2344                         };
2345                 };
2346
2347                 cpu11-thermal {
2348                         polling-delay-passive = <250>;
2349                         polling-delay = <0>;
2350
2351                         thermal-sensors = <&tsens0 14>;
2352
2353                         trips {
2354                                 cpu11_alert0: trip-point0 {
2355                                         temperature = <90000>;
2356                                         hysteresis = <2000>;
2357                                         type = "passive";
2358                                 };
2359
2360                                 cpu11_alert1: trip-point1 {
2361                                         temperature = <95000>;
2362                                         hysteresis = <2000>;
2363                                         type = "passive";
2364                                 };
2365
2366                                 cpu11_crit: cpu-crit {
2367                                         temperature = <110000>;
2368                                         hysteresis = <0>;
2369                                         type = "critical";
2370                                 };
2371                         };
2372
2373                         cooling-maps {
2374                                 map0 {
2375                                         trip = <&cpu11_alert0>;
2376                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2377                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2378                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2379                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2380                                 };
2381                                 map1 {
2382                                         trip = <&cpu11_alert1>;
2383                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2385                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2386                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2387                                 };
2388                         };
2389                 };
2390
2391                 aoss0-thermal {
2392                         polling-delay-passive = <0>;
2393                         polling-delay = <0>;
2394
2395                         thermal-sensors = <&tsens0 0>;
2396
2397                         trips {
2398                                 aoss0_alert0: trip-point0 {
2399                                         temperature = <90000>;
2400                                         hysteresis = <2000>;
2401                                         type = "hot";
2402                                 };
2403
2404                                 aoss0_crit: aoss0-crit {
2405                                         temperature = <110000>;
2406                                         hysteresis = <0>;
2407                                         type = "critical";
2408                                 };
2409                         };
2410                 };
2411
2412                 aoss1-thermal {
2413                         polling-delay-passive = <0>;
2414                         polling-delay = <0>;
2415
2416                         thermal-sensors = <&tsens1 0>;
2417
2418                         trips {
2419                                 aoss1_alert0: trip-point0 {
2420                                         temperature = <90000>;
2421                                         hysteresis = <2000>;
2422                                         type = "hot";
2423                                 };
2424
2425                                 aoss1_crit: aoss1-crit {
2426                                         temperature = <110000>;
2427                                         hysteresis = <0>;
2428                                         type = "critical";
2429                                 };
2430                         };
2431                 };
2432
2433                 cpuss0-thermal {
2434                         polling-delay-passive = <0>;
2435                         polling-delay = <0>;
2436
2437                         thermal-sensors = <&tsens0 5>;
2438
2439                         trips {
2440                                 cpuss0_alert0: trip-point0 {
2441                                         temperature = <90000>;
2442                                         hysteresis = <2000>;
2443                                         type = "hot";
2444                                 };
2445                                 cpuss0_crit: cluster0-crit {
2446                                         temperature = <110000>;
2447                                         hysteresis = <0>;
2448                                         type = "critical";
2449                                 };
2450                         };
2451                 };
2452
2453                 cpuss1-thermal {
2454                         polling-delay-passive = <0>;
2455                         polling-delay = <0>;
2456
2457                         thermal-sensors = <&tsens0 6>;
2458
2459                         trips {
2460                                 cpuss1_alert0: trip-point0 {
2461                                         temperature = <90000>;
2462                                         hysteresis = <2000>;
2463                                         type = "hot";
2464                                 };
2465                                 cpuss1_crit: cluster0-crit {
2466                                         temperature = <110000>;
2467                                         hysteresis = <0>;
2468                                         type = "critical";
2469                                 };
2470                         };
2471                 };
2472
2473                 gpuss0-thermal {
2474                         polling-delay-passive = <0>;
2475                         polling-delay = <0>;
2476
2477                         thermal-sensors = <&tsens1 1>;
2478
2479                         trips {
2480                                 gpuss0_alert0: trip-point0 {
2481                                         temperature = <90000>;
2482                                         hysteresis = <2000>;
2483                                         type = "hot";
2484                                 };
2485
2486                                 gpuss0_crit: gpuss0-crit {
2487                                         temperature = <110000>;
2488                                         hysteresis = <0>;
2489                                         type = "critical";
2490                                 };
2491                         };
2492                 };
2493
2494                 gpuss1-thermal {
2495                         polling-delay-passive = <0>;
2496                         polling-delay = <0>;
2497
2498                         thermal-sensors = <&tsens1 2>;
2499
2500                         trips {
2501                                 gpuss1_alert0: trip-point0 {
2502                                         temperature = <90000>;
2503                                         hysteresis = <2000>;
2504                                         type = "hot";
2505                                 };
2506
2507                                 gpuss1_crit: gpuss1-crit {
2508                                         temperature = <110000>;
2509                                         hysteresis = <0>;
2510                                         type = "critical";
2511                                 };
2512                         };
2513                 };
2514
2515                 nspss0-thermal {
2516                         polling-delay-passive = <0>;
2517                         polling-delay = <0>;
2518
2519                         thermal-sensors = <&tsens1 3>;
2520
2521                         trips {
2522                                 nspss0_alert0: trip-point0 {
2523                                         temperature = <90000>;
2524                                         hysteresis = <2000>;
2525                                         type = "hot";
2526                                 };
2527
2528                                 nspss0_crit: nspss0-crit {
2529                                         temperature = <110000>;
2530                                         hysteresis = <0>;
2531                                         type = "critical";
2532                                 };
2533                         };
2534                 };
2535
2536                 nspss1-thermal {
2537                         polling-delay-passive = <0>;
2538                         polling-delay = <0>;
2539
2540                         thermal-sensors = <&tsens1 4>;
2541
2542                         trips {
2543                                 nspss1_alert0: trip-point0 {
2544                                         temperature = <90000>;
2545                                         hysteresis = <2000>;
2546                                         type = "hot";
2547                                 };
2548
2549                                 nspss1_crit: nspss1-crit {
2550                                         temperature = <110000>;
2551                                         hysteresis = <0>;
2552                                         type = "critical";
2553                                 };
2554                         };
2555                 };
2556
2557                 video-thermal {
2558                         polling-delay-passive = <0>;
2559                         polling-delay = <0>;
2560
2561                         thermal-sensors = <&tsens1 5>;
2562
2563                         trips {
2564                                 video_alert0: trip-point0 {
2565                                         temperature = <90000>;
2566                                         hysteresis = <2000>;
2567                                         type = "hot";
2568                                 };
2569
2570                                 video_crit: video-crit {
2571                                         temperature = <110000>;
2572                                         hysteresis = <0>;
2573                                         type = "critical";
2574                                 };
2575                         };
2576                 };
2577
2578                 ddr-thermal {
2579                         polling-delay-passive = <0>;
2580                         polling-delay = <0>;
2581
2582                         thermal-sensors = <&tsens1 6>;
2583
2584                         trips {
2585                                 ddr_alert0: trip-point0 {
2586                                         temperature = <90000>;
2587                                         hysteresis = <2000>;
2588                                         type = "hot";
2589                                 };
2590
2591                                 ddr_crit: ddr-crit {
2592                                         temperature = <110000>;
2593                                         hysteresis = <0>;
2594                                         type = "critical";
2595                                 };
2596                         };
2597                 };
2598
2599                 mdmss0-thermal {
2600                         polling-delay-passive = <0>;
2601                         polling-delay = <0>;
2602
2603                         thermal-sensors = <&tsens1 7>;
2604
2605                         trips {
2606                                 mdmss0_alert0: trip-point0 {
2607                                         temperature = <90000>;
2608                                         hysteresis = <2000>;
2609                                         type = "hot";
2610                                 };
2611
2612                                 mdmss0_crit: mdmss0-crit {
2613                                         temperature = <110000>;
2614                                         hysteresis = <0>;
2615                                         type = "critical";
2616                                 };
2617                         };
2618                 };
2619
2620                 mdmss1-thermal {
2621                         polling-delay-passive = <0>;
2622                         polling-delay = <0>;
2623
2624                         thermal-sensors = <&tsens1 8>;
2625
2626                         trips {
2627                                 mdmss1_alert0: trip-point0 {
2628                                         temperature = <90000>;
2629                                         hysteresis = <2000>;
2630                                         type = "hot";
2631                                 };
2632
2633                                 mdmss1_crit: mdmss1-crit {
2634                                         temperature = <110000>;
2635                                         hysteresis = <0>;
2636                                         type = "critical";
2637                                 };
2638                         };
2639                 };
2640
2641                 mdmss2-thermal {
2642                         polling-delay-passive = <0>;
2643                         polling-delay = <0>;
2644
2645                         thermal-sensors = <&tsens1 9>;
2646
2647                         trips {
2648                                 mdmss2_alert0: trip-point0 {
2649                                         temperature = <90000>;
2650                                         hysteresis = <2000>;
2651                                         type = "hot";
2652                                 };
2653
2654                                 mdmss2_crit: mdmss2-crit {
2655                                         temperature = <110000>;
2656                                         hysteresis = <0>;
2657                                         type = "critical";
2658                                 };
2659                         };
2660                 };
2661
2662                 mdmss3-thermal {
2663                         polling-delay-passive = <0>;
2664                         polling-delay = <0>;
2665
2666                         thermal-sensors = <&tsens1 10>;
2667
2668                         trips {
2669                                 mdmss3_alert0: trip-point0 {
2670                                         temperature = <90000>;
2671                                         hysteresis = <2000>;
2672                                         type = "hot";
2673                                 };
2674
2675                                 mdmss3_crit: mdmss3-crit {
2676                                         temperature = <110000>;
2677                                         hysteresis = <0>;
2678                                         type = "critical";
2679                                 };
2680                         };
2681                 };
2682
2683                 camera0-thermal {
2684                         polling-delay-passive = <0>;
2685                         polling-delay = <0>;
2686
2687                         thermal-sensors = <&tsens1 11>;
2688
2689                         trips {
2690                                 camera0_alert0: trip-point0 {
2691                                         temperature = <90000>;
2692                                         hysteresis = <2000>;
2693                                         type = "hot";
2694                                 };
2695
2696                                 camera0_crit: camera0-crit {
2697                                         temperature = <110000>;
2698                                         hysteresis = <0>;
2699                                         type = "critical";
2700                                 };
2701                         };
2702                 };
2703         };
2704
2705         timer {
2706                 compatible = "arm,armv8-timer";
2707                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2708                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2709                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2710                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2711         };
2712 };