arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-aoss-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         aliases {
  34                 mmc1 = &sdhc_1;
  35                 mmc2 = &sdhc_2;
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi3 = &spi3;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi8 = &spi8;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56         };
  57
  58         clocks {
  59                 xo_board: xo-board {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <38400000>;
  62                         #clock-cells = <0>;
  63                 };
  64
  65                 sleep_clk: sleep-clk {
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32764>;
  68                         #clock-cells = <0>;
  69                 };
  70         };
  71
  72         reserved_memory: reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 hyp_mem: memory@80000000 {
  78                         reg = <0x0 0x80000000 0x0 0x600000>;
  79                         no-map;
  80                 };
  81
  82                 xbl_mem: memory@80600000 {
  83                         reg = <0x0 0x80600000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 aop_mem: memory@80800000 {
  88                         reg = <0x0 0x80800000 0x0 0x20000>;
  89                         no-map;
  90                 };
  91
  92                 aop_cmd_db_mem: memory@80820000 {
  93                         reg = <0x0 0x80820000 0x0 0x20000>;
  94                         compatible = "qcom,cmd-db";
  95                         no-map;
  96                 };
  97
  98                 sec_apps_mem: memory@808ff000 {
  99                         reg = <0x0 0x808ff000 0x0 0x1000>;
 100                         no-map;
 101                 };
 102
 103                 smem_mem: memory@80900000 {
 104                         reg = <0x0 0x80900000 0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 tz_mem: memory@80b00000 {
 109                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 110                         no-map;
 111                 };
 112
 113                 rmtfs_mem: memory@94600000 {
 114                         compatible = "qcom,rmtfs-mem";
 115                         reg = <0x0 0x94600000 0x0 0x200000>;
 116                         no-map;
 117
 118                         qcom,client-id = <1>;
 119                         qcom,vmid = <15>;
 120                 };
 121         };
 122
 123         cpus {
 124                 #address-cells = <2>;
 125                 #size-cells = <0>;
 126
 127                 CPU0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo468";
 130                         reg = <0x0 0x0>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 133                                            &LITTLE_CPU_SLEEP_1
 134                                            &CLUSTER_SLEEP_0>;
 135                         capacity-dmips-mhz = <1024>;
 136                         dynamic-power-coefficient = <100>;
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 139                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 140                         next-level-cache = <&L2_0>;
 141                         #cooling-cells = <2>;
 142                         qcom,freq-domain = <&cpufreq_hw 0>;
 143                         L2_0: l2-cache {
 144                                 compatible = "cache";
 145                                 next-level-cache = <&L3_0>;
 146                                 L3_0: l3-cache {
 147                                         compatible = "cache";
 148                                 };
 149                         };
 150                 };
 151
 152                 CPU1: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "qcom,kryo468";
 155                         reg = <0x0 0x100>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 158                                            &LITTLE_CPU_SLEEP_1
 159                                            &CLUSTER_SLEEP_0>;
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <100>;
 162                         next-level-cache = <&L2_100>;
 163                         operating-points-v2 = <&cpu0_opp_table>;
 164                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 165                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 166                         #cooling-cells = <2>;
 167                         qcom,freq-domain = <&cpufreq_hw 0>;
 168                         L2_100: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU2: cpu@200 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo468";
 177                         reg = <0x0 0x200>;
 178                         enable-method = "psci";
 179                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 180                                            &LITTLE_CPU_SLEEP_1
 181                                            &CLUSTER_SLEEP_0>;
 182                         capacity-dmips-mhz = <1024>;
 183                         dynamic-power-coefficient = <100>;
 184                         next-level-cache = <&L2_200>;
 185                         operating-points-v2 = <&cpu0_opp_table>;
 186                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         #cooling-cells = <2>;
 189                         qcom,freq-domain = <&cpufreq_hw 0>;
 190                         L2_200: l2-cache {
 191                                 compatible = "cache";
 192                                 next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 CPU3: cpu@300 {
 197                         device_type = "cpu";
 198                         compatible = "qcom,kryo468";
 199                         reg = <0x0 0x300>;
 200                         enable-method = "psci";
 201                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 202                                            &LITTLE_CPU_SLEEP_1
 203                                            &CLUSTER_SLEEP_0>;
 204                         capacity-dmips-mhz = <1024>;
 205                         dynamic-power-coefficient = <100>;
 206                         next-level-cache = <&L2_300>;
 207                         operating-points-v2 = <&cpu0_opp_table>;
 208                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 209                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 210                         #cooling-cells = <2>;
 211                         qcom,freq-domain = <&cpufreq_hw 0>;
 212                         L2_300: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 CPU4: cpu@400 {
 219                         device_type = "cpu";
 220                         compatible = "qcom,kryo468";
 221                         reg = <0x0 0x400>;
 222                         enable-method = "psci";
 223                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 224                                            &LITTLE_CPU_SLEEP_1
 225                                            &CLUSTER_SLEEP_0>;
 226                         capacity-dmips-mhz = <1024>;
 227                         dynamic-power-coefficient = <100>;
 228                         next-level-cache = <&L2_400>;
 229                         operating-points-v2 = <&cpu0_opp_table>;
 230                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 231                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 232                         #cooling-cells = <2>;
 233                         qcom,freq-domain = <&cpufreq_hw 0>;
 234                         L2_400: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 CPU5: cpu@500 {
 241                         device_type = "cpu";
 242                         compatible = "qcom,kryo468";
 243                         reg = <0x0 0x500>;
 244                         enable-method = "psci";
 245                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 246                                            &LITTLE_CPU_SLEEP_1
 247                                            &CLUSTER_SLEEP_0>;
 248                         capacity-dmips-mhz = <1024>;
 249                         dynamic-power-coefficient = <100>;
 250                         next-level-cache = <&L2_500>;
 251                         operating-points-v2 = <&cpu0_opp_table>;
 252                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 253                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 254                         #cooling-cells = <2>;
 255                         qcom,freq-domain = <&cpufreq_hw 0>;
 256                         L2_500: l2-cache {
 257                                 compatible = "cache";
 258                                 next-level-cache = <&L3_0>;
 259                         };
 260                 };
 261
 262                 CPU6: cpu@600 {
 263                         device_type = "cpu";
 264                         compatible = "qcom,kryo468";
 265                         reg = <0x0 0x600>;
 266                         enable-method = "psci";
 267                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 268                                            &BIG_CPU_SLEEP_1
 269                                            &CLUSTER_SLEEP_0>;
 270                         capacity-dmips-mhz = <1740>;
 271                         dynamic-power-coefficient = <405>;
 272                         next-level-cache = <&L2_600>;
 273                         operating-points-v2 = <&cpu6_opp_table>;
 274                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 275                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 276                         #cooling-cells = <2>;
 277                         qcom,freq-domain = <&cpufreq_hw 1>;
 278                         L2_600: l2-cache {
 279                                 compatible = "cache";
 280                                 next-level-cache = <&L3_0>;
 281                         };
 282                 };
 283
 284                 CPU7: cpu@700 {
 285                         device_type = "cpu";
 286                         compatible = "qcom,kryo468";
 287                         reg = <0x0 0x700>;
 288                         enable-method = "psci";
 289                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 290                                            &BIG_CPU_SLEEP_1
 291                                            &CLUSTER_SLEEP_0>;
 292                         capacity-dmips-mhz = <1740>;
 293                         dynamic-power-coefficient = <405>;
 294                         next-level-cache = <&L2_700>;
 295                         operating-points-v2 = <&cpu6_opp_table>;
 296                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 297                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 298                         #cooling-cells = <2>;
 299                         qcom,freq-domain = <&cpufreq_hw 1>;
 300                         L2_700: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 cpu-map {
 307                         cluster0 {
 308                                 core0 {
 309                                         cpu = <&CPU0>;
 310                                 };
 311
 312                                 core1 {
 313                                         cpu = <&CPU1>;
 314                                 };
 315
 316                                 core2 {
 317                                         cpu = <&CPU2>;
 318                                 };
 319
 320                                 core3 {
 321                                         cpu = <&CPU3>;
 322                                 };
 323
 324                                 core4 {
 325                                         cpu = <&CPU4>;
 326                                 };
 327
 328                                 core5 {
 329                                         cpu = <&CPU5>;
 330                                 };
 331
 332                                 core6 {
 333                                         cpu = <&CPU6>;
 334                                 };
 335
 336                                 core7 {
 337                                         cpu = <&CPU7>;
 338                                 };
 339                         };
 340                 };
 341
 342                 idle-states {
 343                         entry-method = "psci";
 344
 345                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 346                                 compatible = "arm,idle-state";
 347                                 idle-state-name = "little-power-down";
 348                                 arm,psci-suspend-param = <0x40000003>;
 349                                 entry-latency-us = <549>;
 350                                 exit-latency-us = <901>;
 351                                 min-residency-us = <1774>;
 352                                 local-timer-stop;
 353                         };
 354
 355                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 356                                 compatible = "arm,idle-state";
 357                                 idle-state-name = "little-rail-power-down";
 358                                 arm,psci-suspend-param = <0x40000004>;
 359                                 entry-latency-us = <702>;
 360                                 exit-latency-us = <915>;
 361                                 min-residency-us = <4001>;
 362                                 local-timer-stop;
 363                         };
 364
 365                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 366                                 compatible = "arm,idle-state";
 367                                 idle-state-name = "big-power-down";
 368                                 arm,psci-suspend-param = <0x40000003>;
 369                                 entry-latency-us = <523>;
 370                                 exit-latency-us = <1244>;
 371                                 min-residency-us = <2207>;
 372                                 local-timer-stop;
 373                         };
 374
 375                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 376                                 compatible = "arm,idle-state";
 377                                 idle-state-name = "big-rail-power-down";
 378                                 arm,psci-suspend-param = <0x40000004>;
 379                                 entry-latency-us = <526>;
 380                                 exit-latency-us = <1854>;
 381                                 min-residency-us = <5555>;
 382                                 local-timer-stop;
 383                         };
 384
 385                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 386                                 compatible = "arm,idle-state";
 387                                 idle-state-name = "cluster-power-down";
 388                                 arm,psci-suspend-param = <0x40003444>;
 389                                 entry-latency-us = <3263>;
 390                                 exit-latency-us = <6562>;
 391                                 min-residency-us = <9926>;
 392                                 local-timer-stop;
 393                         };
 394                 };
 395         };
 396
 397         cpu0_opp_table: cpu0_opp_table {
 398                 compatible = "operating-points-v2";
 399                 opp-shared;
 400
 401                 cpu0_opp1: opp-300000000 {
 402                         opp-hz = /bits/ 64 <300000000>;
 403                         opp-peak-kBps = <1200000 4800000>;
 404                 };
 405
 406                 cpu0_opp2: opp-576000000 {
 407                         opp-hz = /bits/ 64 <576000000>;
 408                         opp-peak-kBps = <1200000 4800000>;
 409                 };
 410
 411                 cpu0_opp3: opp-768000000 {
 412                         opp-hz = /bits/ 64 <768000000>;
 413                         opp-peak-kBps = <1200000 4800000>;
 414                 };
 415
 416                 cpu0_opp4: opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <1804000 8908800>;
 419                 };
 420
 421                 cpu0_opp5: opp-1248000000 {
 422                         opp-hz = /bits/ 64 <1248000000>;
 423                         opp-peak-kBps = <2188000 12902400>;
 424                 };
 425
 426                 cpu0_opp6: opp-1324800000 {
 427                         opp-hz = /bits/ 64 <1324800000>;
 428                         opp-peak-kBps = <2188000 12902400>;
 429                 };
 430
 431                 cpu0_opp7: opp-1516800000 {
 432                         opp-hz = /bits/ 64 <1516800000>;
 433                         opp-peak-kBps = <3072000 15052800>;
 434                 };
 435
 436                 cpu0_opp8: opp-1612800000 {
 437                         opp-hz = /bits/ 64 <1612800000>;
 438                         opp-peak-kBps = <3072000 15052800>;
 439                 };
 440
 441                 cpu0_opp9: opp-1708800000 {
 442                         opp-hz = /bits/ 64 <1708800000>;
 443                         opp-peak-kBps = <3072000 15052800>;
 444                 };
 445
 446                 cpu0_opp10: opp-1804800000 {
 447                         opp-hz = /bits/ 64 <1804800000>;
 448                         opp-peak-kBps = <4068000 22425600>;
 449                 };
 450         };
 451
 452         cpu6_opp_table: cpu6_opp_table {
 453                 compatible = "operating-points-v2";
 454                 opp-shared;
 455
 456                 cpu6_opp1: opp-300000000 {
 457                         opp-hz = /bits/ 64 <300000000>;
 458                         opp-peak-kBps = <2188000 8908800>;
 459                 };
 460
 461                 cpu6_opp2: opp-652800000 {
 462                         opp-hz = /bits/ 64 <652800000>;
 463                         opp-peak-kBps = <2188000 8908800>;
 464                 };
 465
 466                 cpu6_opp3: opp-825600000 {
 467                         opp-hz = /bits/ 64 <825600000>;
 468                         opp-peak-kBps = <2188000 8908800>;
 469                 };
 470
 471                 cpu6_opp4: opp-979200000 {
 472                         opp-hz = /bits/ 64 <979200000>;
 473                         opp-peak-kBps = <2188000 8908800>;
 474                 };
 475
 476                 cpu6_opp5: opp-1113600000 {
 477                         opp-hz = /bits/ 64 <1113600000>;
 478                         opp-peak-kBps = <2188000 8908800>;
 479                 };
 480
 481                 cpu6_opp6: opp-1267200000 {
 482                         opp-hz = /bits/ 64 <1267200000>;
 483                         opp-peak-kBps = <4068000 12902400>;
 484                 };
 485
 486                 cpu6_opp7: opp-1555200000 {
 487                         opp-hz = /bits/ 64 <1555200000>;
 488                         opp-peak-kBps = <4068000 15052800>;
 489                 };
 490
 491                 cpu6_opp8: opp-1708800000 {
 492                         opp-hz = /bits/ 64 <1708800000>;
 493                         opp-peak-kBps = <6220000 19353600>;
 494                 };
 495
 496                 cpu6_opp9: opp-1843200000 {
 497                         opp-hz = /bits/ 64 <1843200000>;
 498                         opp-peak-kBps = <6220000 19353600>;
 499                 };
 500
 501                 cpu6_opp10: opp-1900800000 {
 502                         opp-hz = /bits/ 64 <1900800000>;
 503                         opp-peak-kBps = <6220000 22425600>;
 504                 };
 505
 506                 cpu6_opp11: opp-1996800000 {
 507                         opp-hz = /bits/ 64 <1996800000>;
 508                         opp-peak-kBps = <6220000 22425600>;
 509                 };
 510
 511                 cpu6_opp12: opp-2112000000 {
 512                         opp-hz = /bits/ 64 <2112000000>;
 513                         opp-peak-kBps = <6220000 22425600>;
 514                 };
 515
 516                 cpu6_opp13: opp-2208000000 {
 517                         opp-hz = /bits/ 64 <2208000000>;
 518                         opp-peak-kBps = <7216000 22425600>;
 519                 };
 520
 521                 cpu6_opp14: opp-2323200000 {
 522                         opp-hz = /bits/ 64 <2323200000>;
 523                         opp-peak-kBps = <7216000 22425600>;
 524                 };
 525
 526                 cpu6_opp15: opp-2400000000 {
 527                         opp-hz = /bits/ 64 <2400000000>;
 528                         opp-peak-kBps = <8532000 23347200>;
 529                 };
 530
 531                 cpu6_opp16: opp-2553600000 {
 532                         opp-hz = /bits/ 64 <2553600000>;
 533                         opp-peak-kBps = <8532000 23347200>;
 534                 };
 535         };
 536
 537         memory@80000000 {
 538                 device_type = "memory";
 539                 /* We expect the bootloader to fill in the size */
 540                 reg = <0 0x80000000 0 0>;
 541         };
 542
 543         pmu {
 544                 compatible = "arm,armv8-pmuv3";
 545                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 546         };
 547
 548         firmware {
 549                 scm {
 550                         compatible = "qcom,scm-sc7180", "qcom,scm";
 551                 };
 552         };
 553
 554         tcsr_mutex: hwlock {
 555                 compatible = "qcom,tcsr-mutex";
 556                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 557                 #hwlock-cells = <1>;
 558         };
 559
 560         smem {
 561                 compatible = "qcom,smem";
 562                 memory-region = <&smem_mem>;
 563                 hwlocks = <&tcsr_mutex 3>;
 564         };
 565
 566         smp2p-cdsp {
 567                 compatible = "qcom,smp2p";
 568                 qcom,smem = <94>, <432>;
 569
 570                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 571
 572                 mboxes = <&apss_shared 6>;
 573
 574                 qcom,local-pid = <0>;
 575                 qcom,remote-pid = <5>;
 576
 577                 cdsp_smp2p_out: master-kernel {
 578                         qcom,entry-name = "master-kernel";
 579                         #qcom,smem-state-cells = <1>;
 580                 };
 581
 582                 cdsp_smp2p_in: slave-kernel {
 583                         qcom,entry-name = "slave-kernel";
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588         };
 589
 590         smp2p-lpass {
 591                 compatible = "qcom,smp2p";
 592                 qcom,smem = <443>, <429>;
 593
 594                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 595
 596                 mboxes = <&apss_shared 10>;
 597
 598                 qcom,local-pid = <0>;
 599                 qcom,remote-pid = <2>;
 600
 601                 adsp_smp2p_out: master-kernel {
 602                         qcom,entry-name = "master-kernel";
 603                         #qcom,smem-state-cells = <1>;
 604                 };
 605
 606                 adsp_smp2p_in: slave-kernel {
 607                         qcom,entry-name = "slave-kernel";
 608
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612         };
 613
 614         smp2p-mpss {
 615                 compatible = "qcom,smp2p";
 616                 qcom,smem = <435>, <428>;
 617                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 618                 mboxes = <&apss_shared 14>;
 619                 qcom,local-pid = <0>;
 620                 qcom,remote-pid = <1>;
 621
 622                 modem_smp2p_out: master-kernel {
 623                         qcom,entry-name = "master-kernel";
 624                         #qcom,smem-state-cells = <1>;
 625                 };
 626
 627                 modem_smp2p_in: slave-kernel {
 628                         qcom,entry-name = "slave-kernel";
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                 };
 632
 633                 ipa_smp2p_out: ipa-ap-to-modem {
 634                         qcom,entry-name = "ipa";
 635                         #qcom,smem-state-cells = <1>;
 636                 };
 637
 638                 ipa_smp2p_in: ipa-modem-to-ap {
 639                         qcom,entry-name = "ipa";
 640                         interrupt-controller;
 641                         #interrupt-cells = <2>;
 642                 };
 643         };
 644
 645         psci {
 646                 compatible = "arm,psci-1.0";
 647                 method = "smc";
 648         };
 649
 650         soc: soc@0 {
 651                 #address-cells = <2>;
 652                 #size-cells = <2>;
 653                 ranges = <0 0 0 0 0x10 0>;
 654                 dma-ranges = <0 0 0 0 0x10 0>;
 655                 compatible = "simple-bus";
 656
 657                 gcc: clock-controller@100000 {
 658                         compatible = "qcom,gcc-sc7180";
 659                         reg = <0 0x00100000 0 0x1f0000>;
 660                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 661                                  <&rpmhcc RPMH_CXO_CLK_A>,
 662                                  <&sleep_clk>;
 663                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 664                         #clock-cells = <1>;
 665                         #reset-cells = <1>;
 666                         #power-domain-cells = <1>;
 667                 };
 668
 669                 qfprom: efuse@784000 {
 670                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 671                         reg = <0 0x00784000 0 0x8ff>,
 672                               <0 0x00780000 0 0x7a0>,
 673                               <0 0x00782000 0 0x100>,
 674                               <0 0x00786000 0 0x1fff>;
 675
 676                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 677                         clock-names = "core";
 678                         #address-cells = <1>;
 679                         #size-cells = <1>;
 680
 681                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 682                                 reg = <0x25b 0x1>;
 683                                 bits = <1 3>;
 684                         };
 685
 686                         gpu_speed_bin: gpu_speed_bin@1d2 {
 687                                 reg = <0x1d2 0x2>;
 688                                 bits = <5 8>;
 689                         };
 690                 };
 691
 692                 sdhc_1: sdhci@7c4000 {
 693                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 694                         reg = <0 0x7c4000 0 0x1000>,
 695                                 <0 0x07c5000 0 0x1000>;
 696                         reg-names = "hc", "cqhci";
 697
 698                         iommus = <&apps_smmu 0x60 0x0>;
 699                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 700                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 701                         interrupt-names = "hc_irq", "pwr_irq";
 702
 703                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 704                                  <&gcc GCC_SDCC1_AHB_CLK>,
 705                                  <&rpmhcc RPMH_CXO_CLK>;
 706                         clock-names = "core", "iface", "xo";
 707                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 708                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 709                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 710                         power-domains = <&rpmhpd SC7180_CX>;
 711                         operating-points-v2 = <&sdhc1_opp_table>;
 712
 713                         bus-width = <8>;
 714                         non-removable;
 715                         supports-cqe;
 716
 717                         mmc-ddr-1_8v;
 718                         mmc-hs200-1_8v;
 719                         mmc-hs400-1_8v;
 720                         mmc-hs400-enhanced-strobe;
 721
 722                         status = "disabled";
 723
 724                         sdhc1_opp_table: sdhc1-opp-table {
 725                                 compatible = "operating-points-v2";
 726
 727                                 opp-100000000 {
 728                                         opp-hz = /bits/ 64 <100000000>;
 729                                         required-opps = <&rpmhpd_opp_low_svs>;
 730                                         opp-peak-kBps = <1800000 600000>;
 731                                         opp-avg-kBps = <100000 0>;
 732                                 };
 733
 734                                 opp-384000000 {
 735                                         opp-hz = /bits/ 64 <384000000>;
 736                                         required-opps = <&rpmhpd_opp_nom>;
 737                                         opp-peak-kBps = <5400000 1600000>;
 738                                         opp-avg-kBps = <390000 0>;
 739                                 };
 740                         };
 741                 };
 742
 743                 qup_opp_table: qup-opp-table {
 744                         compatible = "operating-points-v2";
 745
 746                         opp-75000000 {
 747                                 opp-hz = /bits/ 64 <75000000>;
 748                                 required-opps = <&rpmhpd_opp_low_svs>;
 749                         };
 750
 751                         opp-100000000 {
 752                                 opp-hz = /bits/ 64 <100000000>;
 753                                 required-opps = <&rpmhpd_opp_svs>;
 754                         };
 755
 756                         opp-128000000 {
 757                                 opp-hz = /bits/ 64 <128000000>;
 758                                 required-opps = <&rpmhpd_opp_nom>;
 759                         };
 760                 };
 761
 762                 qupv3_id_0: geniqup@8c0000 {
 763                         compatible = "qcom,geni-se-qup";
 764                         reg = <0 0x008c0000 0 0x6000>;
 765                         clock-names = "m-ahb", "s-ahb";
 766                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 767                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 768                         #address-cells = <2>;
 769                         #size-cells = <2>;
 770                         ranges;
 771                         iommus = <&apps_smmu 0x43 0x0>;
 772                         status = "disabled";
 773
 774                         i2c0: i2c@880000 {
 775                                 compatible = "qcom,geni-i2c";
 776                                 reg = <0 0x00880000 0 0x4000>;
 777                                 clock-names = "se";
 778                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 779                                 pinctrl-names = "default";
 780                                 pinctrl-0 = <&qup_i2c0_default>;
 781                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 782                                 #address-cells = <1>;
 783                                 #size-cells = <0>;
 784                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 785                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 786                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 787                                 interconnect-names = "qup-core", "qup-config",
 788                                                         "qup-memory";
 789                                 status = "disabled";
 790                         };
 791
 792                         spi0: spi@880000 {
 793                                 compatible = "qcom,geni-spi";
 794                                 reg = <0 0x00880000 0 0x4000>;
 795                                 clock-names = "se";
 796                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 797                                 pinctrl-names = "default";
 798                                 pinctrl-0 = <&qup_spi0_default>;
 799                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 800                                 #address-cells = <1>;
 801                                 #size-cells = <0>;
 802                                 power-domains = <&rpmhpd SC7180_CX>;
 803                                 operating-points-v2 = <&qup_opp_table>;
 804                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 805                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 806                                 interconnect-names = "qup-core", "qup-config";
 807                                 status = "disabled";
 808                         };
 809
 810                         uart0: serial@880000 {
 811                                 compatible = "qcom,geni-uart";
 812                                 reg = <0 0x00880000 0 0x4000>;
 813                                 clock-names = "se";
 814                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 815                                 pinctrl-names = "default";
 816                                 pinctrl-0 = <&qup_uart0_default>;
 817                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 818                                 power-domains = <&rpmhpd SC7180_CX>;
 819                                 operating-points-v2 = <&qup_opp_table>;
 820                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 821                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 822                                 interconnect-names = "qup-core", "qup-config";
 823                                 status = "disabled";
 824                         };
 825
 826                         i2c1: i2c@884000 {
 827                                 compatible = "qcom,geni-i2c";
 828                                 reg = <0 0x00884000 0 0x4000>;
 829                                 clock-names = "se";
 830                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 831                                 pinctrl-names = "default";
 832                                 pinctrl-0 = <&qup_i2c1_default>;
 833                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 837                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 838                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 839                                 interconnect-names = "qup-core", "qup-config",
 840                                                         "qup-memory";
 841                                 status = "disabled";
 842                         };
 843
 844                         spi1: spi@884000 {
 845                                 compatible = "qcom,geni-spi";
 846                                 reg = <0 0x00884000 0 0x4000>;
 847                                 clock-names = "se";
 848                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 849                                 pinctrl-names = "default";
 850                                 pinctrl-0 = <&qup_spi1_default>;
 851                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 852                                 #address-cells = <1>;
 853                                 #size-cells = <0>;
 854                                 power-domains = <&rpmhpd SC7180_CX>;
 855                                 operating-points-v2 = <&qup_opp_table>;
 856                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 857                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 858                                 interconnect-names = "qup-core", "qup-config";
 859                                 status = "disabled";
 860                         };
 861
 862                         uart1: serial@884000 {
 863                                 compatible = "qcom,geni-uart";
 864                                 reg = <0 0x00884000 0 0x4000>;
 865                                 clock-names = "se";
 866                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 867                                 pinctrl-names = "default";
 868                                 pinctrl-0 = <&qup_uart1_default>;
 869                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 870                                 power-domains = <&rpmhpd SC7180_CX>;
 871                                 operating-points-v2 = <&qup_opp_table>;
 872                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 873                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 874                                 interconnect-names = "qup-core", "qup-config";
 875                                 status = "disabled";
 876                         };
 877
 878                         i2c2: i2c@888000 {
 879                                 compatible = "qcom,geni-i2c";
 880                                 reg = <0 0x00888000 0 0x4000>;
 881                                 clock-names = "se";
 882                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 883                                 pinctrl-names = "default";
 884                                 pinctrl-0 = <&qup_i2c2_default>;
 885                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 886                                 #address-cells = <1>;
 887                                 #size-cells = <0>;
 888                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 889                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 890                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 891                                 interconnect-names = "qup-core", "qup-config",
 892                                                         "qup-memory";
 893                                 status = "disabled";
 894                         };
 895
 896                         uart2: serial@888000 {
 897                                 compatible = "qcom,geni-uart";
 898                                 reg = <0 0x00888000 0 0x4000>;
 899                                 clock-names = "se";
 900                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 901                                 pinctrl-names = "default";
 902                                 pinctrl-0 = <&qup_uart2_default>;
 903                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 904                                 power-domains = <&rpmhpd SC7180_CX>;
 905                                 operating-points-v2 = <&qup_opp_table>;
 906                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 907                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 908                                 interconnect-names = "qup-core", "qup-config";
 909                                 status = "disabled";
 910                         };
 911
 912                         i2c3: i2c@88c000 {
 913                                 compatible = "qcom,geni-i2c";
 914                                 reg = <0 0x0088c000 0 0x4000>;
 915                                 clock-names = "se";
 916                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 917                                 pinctrl-names = "default";
 918                                 pinctrl-0 = <&qup_i2c3_default>;
 919                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 923                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 924                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 925                                 interconnect-names = "qup-core", "qup-config",
 926                                                         "qup-memory";
 927                                 status = "disabled";
 928                         };
 929
 930                         spi3: spi@88c000 {
 931                                 compatible = "qcom,geni-spi";
 932                                 reg = <0 0x0088c000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 935                                 pinctrl-names = "default";
 936                                 pinctrl-0 = <&qup_spi3_default>;
 937                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 938                                 #address-cells = <1>;
 939                                 #size-cells = <0>;
 940                                 power-domains = <&rpmhpd SC7180_CX>;
 941                                 operating-points-v2 = <&qup_opp_table>;
 942                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 943                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 944                                 interconnect-names = "qup-core", "qup-config";
 945                                 status = "disabled";
 946                         };
 947
 948                         uart3: serial@88c000 {
 949                                 compatible = "qcom,geni-uart";
 950                                 reg = <0 0x0088c000 0 0x4000>;
 951                                 clock-names = "se";
 952                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 953                                 pinctrl-names = "default";
 954                                 pinctrl-0 = <&qup_uart3_default>;
 955                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 956                                 power-domains = <&rpmhpd SC7180_CX>;
 957                                 operating-points-v2 = <&qup_opp_table>;
 958                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 959                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 960                                 interconnect-names = "qup-core", "qup-config";
 961                                 status = "disabled";
 962                         };
 963
 964                         i2c4: i2c@890000 {
 965                                 compatible = "qcom,geni-i2c";
 966                                 reg = <0 0x00890000 0 0x4000>;
 967                                 clock-names = "se";
 968                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 969                                 pinctrl-names = "default";
 970                                 pinctrl-0 = <&qup_i2c4_default>;
 971                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 975                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 976                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 977                                 interconnect-names = "qup-core", "qup-config",
 978                                                         "qup-memory";
 979                                 status = "disabled";
 980                         };
 981
 982                         uart4: serial@890000 {
 983                                 compatible = "qcom,geni-uart";
 984                                 reg = <0 0x00890000 0 0x4000>;
 985                                 clock-names = "se";
 986                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 987                                 pinctrl-names = "default";
 988                                 pinctrl-0 = <&qup_uart4_default>;
 989                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 990                                 power-domains = <&rpmhpd SC7180_CX>;
 991                                 operating-points-v2 = <&qup_opp_table>;
 992                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 993                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 994                                 interconnect-names = "qup-core", "qup-config";
 995                                 status = "disabled";
 996                         };
 997
 998                         i2c5: i2c@894000 {
 999                                 compatible = "qcom,geni-i2c";
1000                                 reg = <0 0x00894000 0 0x4000>;
1001                                 clock-names = "se";
1002                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1003                                 pinctrl-names = "default";
1004                                 pinctrl-0 = <&qup_i2c5_default>;
1005                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1006                                 #address-cells = <1>;
1007                                 #size-cells = <0>;
1008                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1009                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1010                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1011                                 interconnect-names = "qup-core", "qup-config",
1012                                                         "qup-memory";
1013                                 status = "disabled";
1014                         };
1015
1016                         spi5: spi@894000 {
1017                                 compatible = "qcom,geni-spi";
1018                                 reg = <0 0x00894000 0 0x4000>;
1019                                 clock-names = "se";
1020                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1021                                 pinctrl-names = "default";
1022                                 pinctrl-0 = <&qup_spi5_default>;
1023                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 power-domains = <&rpmhpd SC7180_CX>;
1027                                 operating-points-v2 = <&qup_opp_table>;
1028                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1029                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1030                                 interconnect-names = "qup-core", "qup-config";
1031                                 status = "disabled";
1032                         };
1033
1034                         uart5: serial@894000 {
1035                                 compatible = "qcom,geni-uart";
1036                                 reg = <0 0x00894000 0 0x4000>;
1037                                 clock-names = "se";
1038                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1039                                 pinctrl-names = "default";
1040                                 pinctrl-0 = <&qup_uart5_default>;
1041                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1042                                 power-domains = <&rpmhpd SC7180_CX>;
1043                                 operating-points-v2 = <&qup_opp_table>;
1044                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1045                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1046                                 interconnect-names = "qup-core", "qup-config";
1047                                 status = "disabled";
1048                         };
1049                 };
1050
1051                 qupv3_id_1: geniqup@ac0000 {
1052                         compatible = "qcom,geni-se-qup";
1053                         reg = <0 0x00ac0000 0 0x6000>;
1054                         clock-names = "m-ahb", "s-ahb";
1055                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1056                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1057                         #address-cells = <2>;
1058                         #size-cells = <2>;
1059                         ranges;
1060                         iommus = <&apps_smmu 0x4c3 0x0>;
1061                         status = "disabled";
1062
1063                         i2c6: i2c@a80000 {
1064                                 compatible = "qcom,geni-i2c";
1065                                 reg = <0 0x00a80000 0 0x4000>;
1066                                 clock-names = "se";
1067                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1068                                 pinctrl-names = "default";
1069                                 pinctrl-0 = <&qup_i2c6_default>;
1070                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1071                                 #address-cells = <1>;
1072                                 #size-cells = <0>;
1073                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1074                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1075                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1076                                 interconnect-names = "qup-core", "qup-config",
1077                                                         "qup-memory";
1078                                 status = "disabled";
1079                         };
1080
1081                         spi6: spi@a80000 {
1082                                 compatible = "qcom,geni-spi";
1083                                 reg = <0 0x00a80000 0 0x4000>;
1084                                 clock-names = "se";
1085                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1086                                 pinctrl-names = "default";
1087                                 pinctrl-0 = <&qup_spi6_default>;
1088                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1089                                 #address-cells = <1>;
1090                                 #size-cells = <0>;
1091                                 power-domains = <&rpmhpd SC7180_CX>;
1092                                 operating-points-v2 = <&qup_opp_table>;
1093                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1094                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1095                                 interconnect-names = "qup-core", "qup-config";
1096                                 status = "disabled";
1097                         };
1098
1099                         uart6: serial@a80000 {
1100                                 compatible = "qcom,geni-uart";
1101                                 reg = <0 0x00a80000 0 0x4000>;
1102                                 clock-names = "se";
1103                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1104                                 pinctrl-names = "default";
1105                                 pinctrl-0 = <&qup_uart6_default>;
1106                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1107                                 power-domains = <&rpmhpd SC7180_CX>;
1108                                 operating-points-v2 = <&qup_opp_table>;
1109                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1110                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1111                                 interconnect-names = "qup-core", "qup-config";
1112                                 status = "disabled";
1113                         };
1114
1115                         i2c7: i2c@a84000 {
1116                                 compatible = "qcom,geni-i2c";
1117                                 reg = <0 0x00a84000 0 0x4000>;
1118                                 clock-names = "se";
1119                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&qup_i2c7_default>;
1122                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1126                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1127                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1128                                 interconnect-names = "qup-core", "qup-config",
1129                                                         "qup-memory";
1130                                 status = "disabled";
1131                         };
1132
1133                         uart7: serial@a84000 {
1134                                 compatible = "qcom,geni-uart";
1135                                 reg = <0 0x00a84000 0 0x4000>;
1136                                 clock-names = "se";
1137                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1138                                 pinctrl-names = "default";
1139                                 pinctrl-0 = <&qup_uart7_default>;
1140                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1141                                 power-domains = <&rpmhpd SC7180_CX>;
1142                                 operating-points-v2 = <&qup_opp_table>;
1143                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1144                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1145                                 interconnect-names = "qup-core", "qup-config";
1146                                 status = "disabled";
1147                         };
1148
1149                         i2c8: i2c@a88000 {
1150                                 compatible = "qcom,geni-i2c";
1151                                 reg = <0 0x00a88000 0 0x4000>;
1152                                 clock-names = "se";
1153                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1154                                 pinctrl-names = "default";
1155                                 pinctrl-0 = <&qup_i2c8_default>;
1156                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1157                                 #address-cells = <1>;
1158                                 #size-cells = <0>;
1159                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1160                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1161                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1162                                 interconnect-names = "qup-core", "qup-config",
1163                                                         "qup-memory";
1164                                 status = "disabled";
1165                         };
1166
1167                         spi8: spi@a88000 {
1168                                 compatible = "qcom,geni-spi";
1169                                 reg = <0 0x00a88000 0 0x4000>;
1170                                 clock-names = "se";
1171                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1172                                 pinctrl-names = "default";
1173                                 pinctrl-0 = <&qup_spi8_default>;
1174                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1175                                 #address-cells = <1>;
1176                                 #size-cells = <0>;
1177                                 power-domains = <&rpmhpd SC7180_CX>;
1178                                 operating-points-v2 = <&qup_opp_table>;
1179                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1180                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1181                                 interconnect-names = "qup-core", "qup-config";
1182                                 status = "disabled";
1183                         };
1184
1185                         uart8: serial@a88000 {
1186                                 compatible = "qcom,geni-debug-uart";
1187                                 reg = <0 0x00a88000 0 0x4000>;
1188                                 clock-names = "se";
1189                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1190                                 pinctrl-names = "default";
1191                                 pinctrl-0 = <&qup_uart8_default>;
1192                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1193                                 power-domains = <&rpmhpd SC7180_CX>;
1194                                 operating-points-v2 = <&qup_opp_table>;
1195                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1196                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1197                                 interconnect-names = "qup-core", "qup-config";
1198                                 status = "disabled";
1199                         };
1200
1201                         i2c9: i2c@a8c000 {
1202                                 compatible = "qcom,geni-i2c";
1203                                 reg = <0 0x00a8c000 0 0x4000>;
1204                                 clock-names = "se";
1205                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1206                                 pinctrl-names = "default";
1207                                 pinctrl-0 = <&qup_i2c9_default>;
1208                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1209                                 #address-cells = <1>;
1210                                 #size-cells = <0>;
1211                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1212                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1213                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1214                                 interconnect-names = "qup-core", "qup-config",
1215                                                         "qup-memory";
1216                                 status = "disabled";
1217                         };
1218
1219                         uart9: serial@a8c000 {
1220                                 compatible = "qcom,geni-uart";
1221                                 reg = <0 0x00a8c000 0 0x4000>;
1222                                 clock-names = "se";
1223                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1224                                 pinctrl-names = "default";
1225                                 pinctrl-0 = <&qup_uart9_default>;
1226                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1227                                 power-domains = <&rpmhpd SC7180_CX>;
1228                                 operating-points-v2 = <&qup_opp_table>;
1229                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1230                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1231                                 interconnect-names = "qup-core", "qup-config";
1232                                 status = "disabled";
1233                         };
1234
1235                         i2c10: i2c@a90000 {
1236                                 compatible = "qcom,geni-i2c";
1237                                 reg = <0 0x00a90000 0 0x4000>;
1238                                 clock-names = "se";
1239                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1240                                 pinctrl-names = "default";
1241                                 pinctrl-0 = <&qup_i2c10_default>;
1242                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1243                                 #address-cells = <1>;
1244                                 #size-cells = <0>;
1245                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1246                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1247                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1248                                 interconnect-names = "qup-core", "qup-config",
1249                                                         "qup-memory";
1250                                 status = "disabled";
1251                         };
1252
1253                         spi10: spi@a90000 {
1254                                 compatible = "qcom,geni-spi";
1255                                 reg = <0 0x00a90000 0 0x4000>;
1256                                 clock-names = "se";
1257                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1258                                 pinctrl-names = "default";
1259                                 pinctrl-0 = <&qup_spi10_default>;
1260                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1261                                 #address-cells = <1>;
1262                                 #size-cells = <0>;
1263                                 power-domains = <&rpmhpd SC7180_CX>;
1264                                 operating-points-v2 = <&qup_opp_table>;
1265                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1266                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1267                                 interconnect-names = "qup-core", "qup-config";
1268                                 status = "disabled";
1269                         };
1270
1271                         uart10: serial@a90000 {
1272                                 compatible = "qcom,geni-uart";
1273                                 reg = <0 0x00a90000 0 0x4000>;
1274                                 clock-names = "se";
1275                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1276                                 pinctrl-names = "default";
1277                                 pinctrl-0 = <&qup_uart10_default>;
1278                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1279                                 power-domains = <&rpmhpd SC7180_CX>;
1280                                 operating-points-v2 = <&qup_opp_table>;
1281                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1282                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1283                                 interconnect-names = "qup-core", "qup-config";
1284                                 status = "disabled";
1285                         };
1286
1287                         i2c11: i2c@a94000 {
1288                                 compatible = "qcom,geni-i2c";
1289                                 reg = <0 0x00a94000 0 0x4000>;
1290                                 clock-names = "se";
1291                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1292                                 pinctrl-names = "default";
1293                                 pinctrl-0 = <&qup_i2c11_default>;
1294                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1295                                 #address-cells = <1>;
1296                                 #size-cells = <0>;
1297                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1298                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1299                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1300                                 interconnect-names = "qup-core", "qup-config",
1301                                                         "qup-memory";
1302                                 status = "disabled";
1303                         };
1304
1305                         spi11: spi@a94000 {
1306                                 compatible = "qcom,geni-spi";
1307                                 reg = <0 0x00a94000 0 0x4000>;
1308                                 clock-names = "se";
1309                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1310                                 pinctrl-names = "default";
1311                                 pinctrl-0 = <&qup_spi11_default>;
1312                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1313                                 #address-cells = <1>;
1314                                 #size-cells = <0>;
1315                                 power-domains = <&rpmhpd SC7180_CX>;
1316                                 operating-points-v2 = <&qup_opp_table>;
1317                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1318                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1319                                 interconnect-names = "qup-core", "qup-config";
1320                                 status = "disabled";
1321                         };
1322
1323                         uart11: serial@a94000 {
1324                                 compatible = "qcom,geni-uart";
1325                                 reg = <0 0x00a94000 0 0x4000>;
1326                                 clock-names = "se";
1327                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1328                                 pinctrl-names = "default";
1329                                 pinctrl-0 = <&qup_uart11_default>;
1330                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1331                                 power-domains = <&rpmhpd SC7180_CX>;
1332                                 operating-points-v2 = <&qup_opp_table>;
1333                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1334                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1335                                 interconnect-names = "qup-core", "qup-config";
1336                                 status = "disabled";
1337                         };
1338                 };
1339
1340                 config_noc: interconnect@1500000 {
1341                         compatible = "qcom,sc7180-config-noc";
1342                         reg = <0 0x01500000 0 0x28000>;
1343                         #interconnect-cells = <2>;
1344                         qcom,bcm-voters = <&apps_bcm_voter>;
1345                 };
1346
1347                 system_noc: interconnect@1620000 {
1348                         compatible = "qcom,sc7180-system-noc";
1349                         reg = <0 0x01620000 0 0x17080>;
1350                         #interconnect-cells = <2>;
1351                         qcom,bcm-voters = <&apps_bcm_voter>;
1352                 };
1353
1354                 mc_virt: interconnect@1638000 {
1355                         compatible = "qcom,sc7180-mc-virt";
1356                         reg = <0 0x01638000 0 0x1000>;
1357                         #interconnect-cells = <2>;
1358                         qcom,bcm-voters = <&apps_bcm_voter>;
1359                 };
1360
1361                 qup_virt: interconnect@1650000 {
1362                         compatible = "qcom,sc7180-qup-virt";
1363                         reg = <0 0x01650000 0 0x1000>;
1364                         #interconnect-cells = <2>;
1365                         qcom,bcm-voters = <&apps_bcm_voter>;
1366                 };
1367
1368                 aggre1_noc: interconnect@16e0000 {
1369                         compatible = "qcom,sc7180-aggre1-noc";
1370                         reg = <0 0x016e0000 0 0x15080>;
1371                         #interconnect-cells = <2>;
1372                         qcom,bcm-voters = <&apps_bcm_voter>;
1373                 };
1374
1375                 aggre2_noc: interconnect@1705000 {
1376                         compatible = "qcom,sc7180-aggre2-noc";
1377                         reg = <0 0x01705000 0 0x9000>;
1378                         #interconnect-cells = <2>;
1379                         qcom,bcm-voters = <&apps_bcm_voter>;
1380                 };
1381
1382                 compute_noc: interconnect@170e000 {
1383                         compatible = "qcom,sc7180-compute-noc";
1384                         reg = <0 0x0170e000 0 0x6000>;
1385                         #interconnect-cells = <2>;
1386                         qcom,bcm-voters = <&apps_bcm_voter>;
1387                 };
1388
1389                 mmss_noc: interconnect@1740000 {
1390                         compatible = "qcom,sc7180-mmss-noc";
1391                         reg = <0 0x01740000 0 0x1c100>;
1392                         #interconnect-cells = <2>;
1393                         qcom,bcm-voters = <&apps_bcm_voter>;
1394                 };
1395
1396                 ipa_virt: interconnect@1e00000 {
1397                         compatible = "qcom,sc7180-ipa-virt";
1398                         reg = <0 0x01e00000 0 0x1000>;
1399                         #interconnect-cells = <2>;
1400                         qcom,bcm-voters = <&apps_bcm_voter>;
1401                 };
1402
1403                 ipa: ipa@1e40000 {
1404                         compatible = "qcom,sc7180-ipa";
1405
1406                         iommus = <&apps_smmu 0x440 0x0>,
1407                                  <&apps_smmu 0x442 0x0>;
1408                         reg = <0 0x1e40000 0 0x7000>,
1409                               <0 0x1e47000 0 0x2000>,
1410                               <0 0x1e04000 0 0x2c000>;
1411                         reg-names = "ipa-reg",
1412                                     "ipa-shared",
1413                                     "gsi";
1414
1415                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1416                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1417                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1418                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1419                         interrupt-names = "ipa",
1420                                           "gsi",
1421                                           "ipa-clock-query",
1422                                           "ipa-setup-ready";
1423
1424                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1425                         clock-names = "core";
1426
1427                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1428                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1429                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1430                         interconnect-names = "memory",
1431                                              "imem",
1432                                              "config";
1433
1434                         qcom,smem-states = <&ipa_smp2p_out 0>,
1435                                            <&ipa_smp2p_out 1>;
1436                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1437                                                 "ipa-clock-enabled";
1438
1439                         status = "disabled";
1440                 };
1441
1442                 tcsr_mutex_regs: syscon@1f40000 {
1443                         compatible = "syscon";
1444                         reg = <0 0x01f40000 0 0x40000>;
1445                 };
1446
1447                 tcsr_regs: syscon@1fc0000 {
1448                         compatible = "syscon";
1449                         reg = <0 0x01fc0000 0 0x40000>;
1450                 };
1451
1452                 tlmm: pinctrl@3500000 {
1453                         compatible = "qcom,sc7180-pinctrl";
1454                         reg = <0 0x03500000 0 0x300000>,
1455                               <0 0x03900000 0 0x300000>,
1456                               <0 0x03d00000 0 0x300000>;
1457                         reg-names = "west", "north", "south";
1458                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1459                         gpio-controller;
1460                         #gpio-cells = <2>;
1461                         interrupt-controller;
1462                         #interrupt-cells = <2>;
1463                         gpio-ranges = <&tlmm 0 0 120>;
1464                         wakeup-parent = <&pdc>;
1465
1466                         dp_hot_plug_det: dp-hot-plug-det {
1467                                 pinmux {
1468                                         pins = "gpio117";
1469                                         function = "dp_hot";
1470                                 };
1471                         };
1472
1473                         qspi_clk: qspi-clk {
1474                                 pinmux {
1475                                         pins = "gpio63";
1476                                         function = "qspi_clk";
1477                                 };
1478                         };
1479
1480                         qspi_cs0: qspi-cs0 {
1481                                 pinmux {
1482                                         pins = "gpio68";
1483                                         function = "qspi_cs";
1484                                 };
1485                         };
1486
1487                         qspi_cs1: qspi-cs1 {
1488                                 pinmux {
1489                                         pins = "gpio72";
1490                                         function = "qspi_cs";
1491                                 };
1492                         };
1493
1494                         qspi_data01: qspi-data01 {
1495                                 pinmux-data {
1496                                         pins = "gpio64", "gpio65";
1497                                         function = "qspi_data";
1498                                 };
1499                         };
1500
1501                         qspi_data12: qspi-data12 {
1502                                 pinmux-data {
1503                                         pins = "gpio66", "gpio67";
1504                                         function = "qspi_data";
1505                                 };
1506                         };
1507
1508                         qup_i2c0_default: qup-i2c0-default {
1509                                 pinmux {
1510                                         pins = "gpio34", "gpio35";
1511                                         function = "qup00";
1512                                 };
1513                         };
1514
1515                         qup_i2c1_default: qup-i2c1-default {
1516                                 pinmux {
1517                                         pins = "gpio0", "gpio1";
1518                                         function = "qup01";
1519                                 };
1520                         };
1521
1522                         qup_i2c2_default: qup-i2c2-default {
1523                                 pinmux {
1524                                         pins = "gpio15", "gpio16";
1525                                         function = "qup02_i2c";
1526                                 };
1527                         };
1528
1529                         qup_i2c3_default: qup-i2c3-default {
1530                                 pinmux {
1531                                         pins = "gpio38", "gpio39";
1532                                         function = "qup03";
1533                                 };
1534                         };
1535
1536                         qup_i2c4_default: qup-i2c4-default {
1537                                 pinmux {
1538                                         pins = "gpio115", "gpio116";
1539                                         function = "qup04_i2c";
1540                                 };
1541                         };
1542
1543                         qup_i2c5_default: qup-i2c5-default {
1544                                 pinmux {
1545                                         pins = "gpio25", "gpio26";
1546                                         function = "qup05";
1547                                 };
1548                         };
1549
1550                         qup_i2c6_default: qup-i2c6-default {
1551                                 pinmux {
1552                                         pins = "gpio59", "gpio60";
1553                                         function = "qup10";
1554                                 };
1555                         };
1556
1557                         qup_i2c7_default: qup-i2c7-default {
1558                                 pinmux {
1559                                         pins = "gpio6", "gpio7";
1560                                         function = "qup11_i2c";
1561                                 };
1562                         };
1563
1564                         qup_i2c8_default: qup-i2c8-default {
1565                                 pinmux {
1566                                         pins = "gpio42", "gpio43";
1567                                         function = "qup12";
1568                                 };
1569                         };
1570
1571                         qup_i2c9_default: qup-i2c9-default {
1572                                 pinmux {
1573                                         pins = "gpio46", "gpio47";
1574                                         function = "qup13_i2c";
1575                                 };
1576                         };
1577
1578                         qup_i2c10_default: qup-i2c10-default {
1579                                 pinmux {
1580                                         pins = "gpio86", "gpio87";
1581                                         function = "qup14";
1582                                 };
1583                         };
1584
1585                         qup_i2c11_default: qup-i2c11-default {
1586                                 pinmux {
1587                                         pins = "gpio53", "gpio54";
1588                                         function = "qup15";
1589                                 };
1590                         };
1591
1592                         qup_spi0_default: qup-spi0-default {
1593                                 pinmux {
1594                                         pins = "gpio34", "gpio35",
1595                                                "gpio36", "gpio37";
1596                                         function = "qup00";
1597                                 };
1598                         };
1599
1600                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1601                                 pinmux {
1602                                         pins = "gpio34", "gpio35",
1603                                                "gpio36";
1604                                         function = "qup00";
1605                                 };
1606
1607                                 pinmux-cs {
1608                                         pins = "gpio37";
1609                                         function = "gpio";
1610                                 };
1611                         };
1612
1613                         qup_spi1_default: qup-spi1-default {
1614                                 pinmux {
1615                                         pins = "gpio0", "gpio1",
1616                                                "gpio2", "gpio3";
1617                                         function = "qup01";
1618                                 };
1619                         };
1620
1621                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1622                                 pinmux {
1623                                         pins = "gpio0", "gpio1",
1624                                                "gpio2";
1625                                         function = "qup01";
1626                                 };
1627
1628                                 pinmux-cs {
1629                                         pins = "gpio3";
1630                                         function = "gpio";
1631                                 };
1632                         };
1633
1634                         qup_spi3_default: qup-spi3-default {
1635                                 pinmux {
1636                                         pins = "gpio38", "gpio39",
1637                                                "gpio40", "gpio41";
1638                                         function = "qup03";
1639                                 };
1640                         };
1641
1642                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1643                                 pinmux {
1644                                         pins = "gpio38", "gpio39",
1645                                                "gpio40";
1646                                         function = "qup03";
1647                                 };
1648
1649                                 pinmux-cs {
1650                                         pins = "gpio41";
1651                                         function = "gpio";
1652                                 };
1653                         };
1654
1655                         qup_spi5_default: qup-spi5-default {
1656                                 pinmux {
1657                                         pins = "gpio25", "gpio26",
1658                                                "gpio27", "gpio28";
1659                                         function = "qup05";
1660                                 };
1661                         };
1662
1663                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1664                                 pinmux {
1665                                         pins = "gpio25", "gpio26",
1666                                                "gpio27";
1667                                         function = "qup05";
1668                                 };
1669
1670                                 pinmux-cs {
1671                                         pins = "gpio28";
1672                                         function = "gpio";
1673                                 };
1674                         };
1675
1676                         qup_spi6_default: qup-spi6-default {
1677                                 pinmux {
1678                                         pins = "gpio59", "gpio60",
1679                                                "gpio61", "gpio62";
1680                                         function = "qup10";
1681                                 };
1682                         };
1683
1684                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1685                                 pinmux {
1686                                         pins = "gpio59", "gpio60",
1687                                                "gpio61";
1688                                         function = "qup10";
1689                                 };
1690
1691                                 pinmux-cs {
1692                                         pins = "gpio62";
1693                                         function = "gpio";
1694                                 };
1695                         };
1696
1697                         qup_spi8_default: qup-spi8-default {
1698                                 pinmux {
1699                                         pins = "gpio42", "gpio43",
1700                                                "gpio44", "gpio45";
1701                                         function = "qup12";
1702                                 };
1703                         };
1704
1705                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1706                                 pinmux {
1707                                         pins = "gpio42", "gpio43",
1708                                                "gpio44";
1709                                         function = "qup12";
1710                                 };
1711
1712                                 pinmux-cs {
1713                                         pins = "gpio45";
1714                                         function = "gpio";
1715                                 };
1716                         };
1717
1718                         qup_spi10_default: qup-spi10-default {
1719                                 pinmux {
1720                                         pins = "gpio86", "gpio87",
1721                                                "gpio88", "gpio89";
1722                                         function = "qup14";
1723                                 };
1724                         };
1725
1726                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1727                                 pinmux {
1728                                         pins = "gpio86", "gpio87",
1729                                                "gpio88";
1730                                         function = "qup14";
1731                                 };
1732
1733                                 pinmux-cs {
1734                                         pins = "gpio89";
1735                                         function = "gpio";
1736                                 };
1737                         };
1738
1739                         qup_spi11_default: qup-spi11-default {
1740                                 pinmux {
1741                                         pins = "gpio53", "gpio54",
1742                                                "gpio55", "gpio56";
1743                                         function = "qup15";
1744                                 };
1745                         };
1746
1747                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1748                                 pinmux {
1749                                         pins = "gpio53", "gpio54",
1750                                                "gpio55";
1751                                         function = "qup15";
1752                                 };
1753
1754                                 pinmux-cs {
1755                                         pins = "gpio56";
1756                                         function = "gpio";
1757                                 };
1758                         };
1759
1760                         qup_uart0_default: qup-uart0-default {
1761                                 pinmux {
1762                                         pins = "gpio34", "gpio35",
1763                                                "gpio36", "gpio37";
1764                                         function = "qup00";
1765                                 };
1766                         };
1767
1768                         qup_uart1_default: qup-uart1-default {
1769                                 pinmux {
1770                                         pins = "gpio0", "gpio1",
1771                                                "gpio2", "gpio3";
1772                                         function = "qup01";
1773                                 };
1774                         };
1775
1776                         qup_uart2_default: qup-uart2-default {
1777                                 pinmux {
1778                                         pins = "gpio15", "gpio16";
1779                                         function = "qup02_uart";
1780                                 };
1781                         };
1782
1783                         qup_uart3_default: qup-uart3-default {
1784                                 pinmux {
1785                                         pins = "gpio38", "gpio39",
1786                                                "gpio40", "gpio41";
1787                                         function = "qup03";
1788                                 };
1789                         };
1790
1791                         qup_uart4_default: qup-uart4-default {
1792                                 pinmux {
1793                                         pins = "gpio115", "gpio116";
1794                                         function = "qup04_uart";
1795                                 };
1796                         };
1797
1798                         qup_uart5_default: qup-uart5-default {
1799                                 pinmux {
1800                                         pins = "gpio25", "gpio26",
1801                                                "gpio27", "gpio28";
1802                                         function = "qup05";
1803                                 };
1804                         };
1805
1806                         qup_uart6_default: qup-uart6-default {
1807                                 pinmux {
1808                                         pins = "gpio59", "gpio60",
1809                                                "gpio61", "gpio62";
1810                                         function = "qup10";
1811                                 };
1812                         };
1813
1814                         qup_uart7_default: qup-uart7-default {
1815                                 pinmux {
1816                                         pins = "gpio6", "gpio7";
1817                                         function = "qup11_uart";
1818                                 };
1819                         };
1820
1821                         qup_uart8_default: qup-uart8-default {
1822                                 pinmux {
1823                                         pins = "gpio44", "gpio45";
1824                                         function = "qup12";
1825                                 };
1826                         };
1827
1828                         qup_uart9_default: qup-uart9-default {
1829                                 pinmux {
1830                                         pins = "gpio46", "gpio47";
1831                                         function = "qup13_uart";
1832                                 };
1833                         };
1834
1835                         qup_uart10_default: qup-uart10-default {
1836                                 pinmux {
1837                                         pins = "gpio86", "gpio87",
1838                                                "gpio88", "gpio89";
1839                                         function = "qup14";
1840                                 };
1841                         };
1842
1843                         qup_uart11_default: qup-uart11-default {
1844                                 pinmux {
1845                                         pins = "gpio53", "gpio54",
1846                                                "gpio55", "gpio56";
1847                                         function = "qup15";
1848                                 };
1849                         };
1850
1851                         sec_mi2s_active: sec-mi2s-active {
1852                                 pinmux {
1853                                         pins = "gpio49", "gpio50", "gpio51";
1854                                         function = "mi2s_1";
1855                                 };
1856                         };
1857
1858                         pri_mi2s_active: pri-mi2s-active {
1859                                 pinmux {
1860                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1861                                         function = "mi2s_0";
1862                                 };
1863                         };
1864
1865                         pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1866                                 pinmux {
1867                                         pins = "gpio57";
1868                                         function = "lpass_ext";
1869                                 };
1870                         };
1871                 };
1872
1873                 remoteproc_mpss: remoteproc@4080000 {
1874                         compatible = "qcom,sc7180-mpss-pas";
1875                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1876                         reg-names = "qdsp6", "rmb";
1877
1878                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1879                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1880                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1881                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1882                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1883                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1884                         interrupt-names = "wdog", "fatal", "ready", "handover",
1885                                           "stop-ack", "shutdown-ack";
1886
1887                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1888                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1889                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
1890                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1891                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1892                                  <&rpmhcc RPMH_CXO_CLK>;
1893                         clock-names = "iface", "bus", "nav", "snoc_axi",
1894                                       "mnoc_axi", "xo";
1895
1896                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1897                                         <&rpmhpd SC7180_CX>,
1898                                         <&rpmhpd SC7180_MX>,
1899                                         <&rpmhpd SC7180_MSS>;
1900                         power-domain-names = "load_state", "cx", "mx", "mss";
1901
1902                         memory-region = <&mpss_mem>;
1903
1904                         qcom,smem-states = <&modem_smp2p_out 0>;
1905                         qcom,smem-state-names = "stop";
1906
1907                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1908                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
1909                         reset-names = "mss_restart", "pdc_reset";
1910
1911                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1912                         qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1913
1914                         status = "disabled";
1915
1916                         glink-edge {
1917                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1918                                 label = "modem";
1919                                 qcom,remote-pid = <1>;
1920                                 mboxes = <&apss_shared 12>;
1921                         };
1922                 };
1923
1924                 gpu: gpu@5000000 {
1925                         compatible = "qcom,adreno-618.0", "qcom,adreno";
1926                         #stream-id-cells = <16>;
1927                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1928                                 <0 0x05061000 0 0x800>;
1929                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1930                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1931                         iommus = <&adreno_smmu 0>;
1932                         operating-points-v2 = <&gpu_opp_table>;
1933                         qcom,gmu = <&gmu>;
1934
1935                         #cooling-cells = <2>;
1936
1937                         nvmem-cells = <&gpu_speed_bin>;
1938                         nvmem-cell-names = "speed_bin";
1939
1940                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1941                         interconnect-names = "gfx-mem";
1942
1943                         gpu_opp_table: opp-table {
1944                                 compatible = "operating-points-v2";
1945
1946                                 opp-825000000 {
1947                                         opp-hz = /bits/ 64 <825000000>;
1948                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1949                                         opp-peak-kBps = <8532000>;
1950                                         opp-supported-hw = <0x04>;
1951                                 };
1952
1953                                 opp-800000000 {
1954                                         opp-hz = /bits/ 64 <800000000>;
1955                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1956                                         opp-peak-kBps = <8532000>;
1957                                         opp-supported-hw = <0x07>;
1958                                 };
1959
1960                                 opp-650000000 {
1961                                         opp-hz = /bits/ 64 <650000000>;
1962                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1963                                         opp-peak-kBps = <7216000>;
1964                                         opp-supported-hw = <0x07>;
1965                                 };
1966
1967                                 opp-565000000 {
1968                                         opp-hz = /bits/ 64 <565000000>;
1969                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1970                                         opp-peak-kBps = <5412000>;
1971                                         opp-supported-hw = <0x07>;
1972                                 };
1973
1974                                 opp-430000000 {
1975                                         opp-hz = /bits/ 64 <430000000>;
1976                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1977                                         opp-peak-kBps = <5412000>;
1978                                         opp-supported-hw = <0x07>;
1979                                 };
1980
1981                                 opp-355000000 {
1982                                         opp-hz = /bits/ 64 <355000000>;
1983                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1984                                         opp-peak-kBps = <3072000>;
1985                                         opp-supported-hw = <0x07>;
1986                                 };
1987
1988                                 opp-267000000 {
1989                                         opp-hz = /bits/ 64 <267000000>;
1990                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1991                                         opp-peak-kBps = <3072000>;
1992                                         opp-supported-hw = <0x07>;
1993                                 };
1994
1995                                 opp-180000000 {
1996                                         opp-hz = /bits/ 64 <180000000>;
1997                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1998                                         opp-peak-kBps = <1804000>;
1999                                         opp-supported-hw = <0x07>;
2000                                 };
2001                         };
2002                 };
2003
2004                 adreno_smmu: iommu@5040000 {
2005                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2006                         reg = <0 0x05040000 0 0x10000>;
2007                         #iommu-cells = <1>;
2008                         #global-interrupts = <2>;
2009                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2010                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2011                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2012                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2013                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2014                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2015                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2016                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2017                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2018                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2019
2020                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2021                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2022                         clock-names = "bus", "iface";
2023
2024                         power-domains = <&gpucc CX_GDSC>;
2025                 };
2026
2027                 gmu: gmu@506a000 {
2028                         compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2029                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2030                                 <0 0x0b490000 0 0x10000>;
2031                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2032                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2033                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2034                         interrupt-names = "hfi", "gmu";
2035                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2036                                <&gpucc GPU_CC_CXO_CLK>,
2037                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2038                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2039                         clock-names = "gmu", "cxo", "axi", "memnoc";
2040                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2041                         power-domain-names = "cx", "gx";
2042                         iommus = <&adreno_smmu 5>;
2043                         operating-points-v2 = <&gmu_opp_table>;
2044
2045                         gmu_opp_table: opp-table {
2046                                 compatible = "operating-points-v2";
2047
2048                                 opp-200000000 {
2049                                         opp-hz = /bits/ 64 <200000000>;
2050                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2051                                 };
2052                         };
2053                 };
2054
2055                 gpucc: clock-controller@5090000 {
2056                         compatible = "qcom,sc7180-gpucc";
2057                         reg = <0 0x05090000 0 0x9000>;
2058                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2059                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2060                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2061                         clock-names = "bi_tcxo",
2062                                       "gcc_gpu_gpll0_clk_src",
2063                                       "gcc_gpu_gpll0_div_clk_src";
2064                         #clock-cells = <1>;
2065                         #reset-cells = <1>;
2066                         #power-domain-cells = <1>;
2067                 };
2068
2069                 stm@6002000 {
2070                         compatible = "arm,coresight-stm", "arm,primecell";
2071                         reg = <0 0x06002000 0 0x1000>,
2072                               <0 0x16280000 0 0x180000>;
2073                         reg-names = "stm-base", "stm-stimulus-base";
2074
2075                         clocks = <&aoss_qmp>;
2076                         clock-names = "apb_pclk";
2077
2078                         out-ports {
2079                                 port {
2080                                         stm_out: endpoint {
2081                                                 remote-endpoint = <&funnel0_in7>;
2082                                         };
2083                                 };
2084                         };
2085                 };
2086
2087                 funnel@6041000 {
2088                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2089                         reg = <0 0x06041000 0 0x1000>;
2090
2091                         clocks = <&aoss_qmp>;
2092                         clock-names = "apb_pclk";
2093
2094                         out-ports {
2095                                 port {
2096                                         funnel0_out: endpoint {
2097                                                 remote-endpoint = <&merge_funnel_in0>;
2098                                         };
2099                                 };
2100                         };
2101
2102                         in-ports {
2103                                 #address-cells = <1>;
2104                                 #size-cells = <0>;
2105
2106                                 port@7 {
2107                                         reg = <7>;
2108                                         funnel0_in7: endpoint {
2109                                                 remote-endpoint = <&stm_out>;
2110                                         };
2111                                 };
2112                         };
2113                 };
2114
2115                 funnel@6042000 {
2116                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2117                         reg = <0 0x06042000 0 0x1000>;
2118
2119                         clocks = <&aoss_qmp>;
2120                         clock-names = "apb_pclk";
2121
2122                         out-ports {
2123                                 port {
2124                                         funnel1_out: endpoint {
2125                                                 remote-endpoint = <&merge_funnel_in1>;
2126                                         };
2127                                 };
2128                         };
2129
2130                         in-ports {
2131                                 #address-cells = <1>;
2132                                 #size-cells = <0>;
2133
2134                                 port@4 {
2135                                         reg = <4>;
2136                                         funnel1_in4: endpoint {
2137                                                 remote-endpoint = <&apss_merge_funnel_out>;
2138                                         };
2139                                 };
2140                         };
2141                 };
2142
2143                 funnel@6045000 {
2144                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2145                         reg = <0 0x06045000 0 0x1000>;
2146
2147                         clocks = <&aoss_qmp>;
2148                         clock-names = "apb_pclk";
2149
2150                         out-ports {
2151                                 port {
2152                                         merge_funnel_out: endpoint {
2153                                                 remote-endpoint = <&swao_funnel_in>;
2154                                         };
2155                                 };
2156                         };
2157
2158                         in-ports {
2159                                 #address-cells = <1>;
2160                                 #size-cells = <0>;
2161
2162                                 port@0 {
2163                                         reg = <0>;
2164                                         merge_funnel_in0: endpoint {
2165                                                 remote-endpoint = <&funnel0_out>;
2166                                         };
2167                                 };
2168
2169                                 port@1 {
2170                                         reg = <1>;
2171                                         merge_funnel_in1: endpoint {
2172                                                 remote-endpoint = <&funnel1_out>;
2173                                         };
2174                                 };
2175                         };
2176                 };
2177
2178                 replicator@6046000 {
2179                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2180                         reg = <0 0x06046000 0 0x1000>;
2181
2182                         clocks = <&aoss_qmp>;
2183                         clock-names = "apb_pclk";
2184
2185                         out-ports {
2186                                 port {
2187                                         replicator_out: endpoint {
2188                                                 remote-endpoint = <&etr_in>;
2189                                         };
2190                                 };
2191                         };
2192
2193                         in-ports {
2194                                 port {
2195                                         replicator_in: endpoint {
2196                                                 remote-endpoint = <&swao_replicator_out>;
2197                                         };
2198                                 };
2199                         };
2200                 };
2201
2202                 etr@6048000 {
2203                         compatible = "arm,coresight-tmc", "arm,primecell";
2204                         reg = <0 0x06048000 0 0x1000>;
2205                         iommus = <&apps_smmu 0x04a0 0x20>;
2206
2207                         clocks = <&aoss_qmp>;
2208                         clock-names = "apb_pclk";
2209                         arm,scatter-gather;
2210
2211                         in-ports {
2212                                 port {
2213                                         etr_in: endpoint {
2214                                                 remote-endpoint = <&replicator_out>;
2215                                         };
2216                                 };
2217                         };
2218                 };
2219
2220                 funnel@6b04000 {
2221                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2222                         reg = <0 0x06b04000 0 0x1000>;
2223
2224                         clocks = <&aoss_qmp>;
2225                         clock-names = "apb_pclk";
2226
2227                         out-ports {
2228                                 port {
2229                                         swao_funnel_out: endpoint {
2230                                                 remote-endpoint = <&etf_in>;
2231                                         };
2232                                 };
2233                         };
2234
2235                         in-ports {
2236                                 #address-cells = <1>;
2237                                 #size-cells = <0>;
2238
2239                                 port@7 {
2240                                         reg = <7>;
2241                                         swao_funnel_in: endpoint {
2242                                                 remote-endpoint = <&merge_funnel_out>;
2243                                         };
2244                                 };
2245                         };
2246                 };
2247
2248                 etf@6b05000 {
2249                         compatible = "arm,coresight-tmc", "arm,primecell";
2250                         reg = <0 0x06b05000 0 0x1000>;
2251
2252                         clocks = <&aoss_qmp>;
2253                         clock-names = "apb_pclk";
2254
2255                         out-ports {
2256                                 port {
2257                                         etf_out: endpoint {
2258                                                 remote-endpoint = <&swao_replicator_in>;
2259                                         };
2260                                 };
2261                         };
2262
2263                         in-ports {
2264                                 port {
2265                                         etf_in: endpoint {
2266                                                 remote-endpoint = <&swao_funnel_out>;
2267                                         };
2268                                 };
2269                         };
2270                 };
2271
2272                 replicator@6b06000 {
2273                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2274                         reg = <0 0x06b06000 0 0x1000>;
2275
2276                         clocks = <&aoss_qmp>;
2277                         clock-names = "apb_pclk";
2278                         qcom,replicator-loses-context;
2279
2280                         out-ports {
2281                                 port {
2282                                         swao_replicator_out: endpoint {
2283                                                 remote-endpoint = <&replicator_in>;
2284                                         };
2285                                 };
2286                         };
2287
2288                         in-ports {
2289                                 port {
2290                                         swao_replicator_in: endpoint {
2291                                                 remote-endpoint = <&etf_out>;
2292                                         };
2293                                 };
2294                         };
2295                 };
2296
2297                 etm@7040000 {
2298                         compatible = "arm,coresight-etm4x", "arm,primecell";
2299                         reg = <0 0x07040000 0 0x1000>;
2300
2301                         cpu = <&CPU0>;
2302
2303                         clocks = <&aoss_qmp>;
2304                         clock-names = "apb_pclk";
2305                         arm,coresight-loses-context-with-cpu;
2306                         qcom,skip-power-up;
2307
2308                         out-ports {
2309                                 port {
2310                                         etm0_out: endpoint {
2311                                                 remote-endpoint = <&apss_funnel_in0>;
2312                                         };
2313                                 };
2314                         };
2315                 };
2316
2317                 etm@7140000 {
2318                         compatible = "arm,coresight-etm4x", "arm,primecell";
2319                         reg = <0 0x07140000 0 0x1000>;
2320
2321                         cpu = <&CPU1>;
2322
2323                         clocks = <&aoss_qmp>;
2324                         clock-names = "apb_pclk";
2325                         arm,coresight-loses-context-with-cpu;
2326                         qcom,skip-power-up;
2327
2328                         out-ports {
2329                                 port {
2330                                         etm1_out: endpoint {
2331                                                 remote-endpoint = <&apss_funnel_in1>;
2332                                         };
2333                                 };
2334                         };
2335                 };
2336
2337                 etm@7240000 {
2338                         compatible = "arm,coresight-etm4x", "arm,primecell";
2339                         reg = <0 0x07240000 0 0x1000>;
2340
2341                         cpu = <&CPU2>;
2342
2343                         clocks = <&aoss_qmp>;
2344                         clock-names = "apb_pclk";
2345                         arm,coresight-loses-context-with-cpu;
2346                         qcom,skip-power-up;
2347
2348                         out-ports {
2349                                 port {
2350                                         etm2_out: endpoint {
2351                                                 remote-endpoint = <&apss_funnel_in2>;
2352                                         };
2353                                 };
2354                         };
2355                 };
2356
2357                 etm@7340000 {
2358                         compatible = "arm,coresight-etm4x", "arm,primecell";
2359                         reg = <0 0x07340000 0 0x1000>;
2360
2361                         cpu = <&CPU3>;
2362
2363                         clocks = <&aoss_qmp>;
2364                         clock-names = "apb_pclk";
2365                         arm,coresight-loses-context-with-cpu;
2366                         qcom,skip-power-up;
2367
2368                         out-ports {
2369                                 port {
2370                                         etm3_out: endpoint {
2371                                                 remote-endpoint = <&apss_funnel_in3>;
2372                                         };
2373                                 };
2374                         };
2375                 };
2376
2377                 etm@7440000 {
2378                         compatible = "arm,coresight-etm4x", "arm,primecell";
2379                         reg = <0 0x07440000 0 0x1000>;
2380
2381                         cpu = <&CPU4>;
2382
2383                         clocks = <&aoss_qmp>;
2384                         clock-names = "apb_pclk";
2385                         arm,coresight-loses-context-with-cpu;
2386                         qcom,skip-power-up;
2387
2388                         out-ports {
2389                                 port {
2390                                         etm4_out: endpoint {
2391                                                 remote-endpoint = <&apss_funnel_in4>;
2392                                         };
2393                                 };
2394                         };
2395                 };
2396
2397                 etm@7540000 {
2398                         compatible = "arm,coresight-etm4x", "arm,primecell";
2399                         reg = <0 0x07540000 0 0x1000>;
2400
2401                         cpu = <&CPU5>;
2402
2403                         clocks = <&aoss_qmp>;
2404                         clock-names = "apb_pclk";
2405                         arm,coresight-loses-context-with-cpu;
2406                         qcom,skip-power-up;
2407
2408                         out-ports {
2409                                 port {
2410                                         etm5_out: endpoint {
2411                                                 remote-endpoint = <&apss_funnel_in5>;
2412                                         };
2413                                 };
2414                         };
2415                 };
2416
2417                 etm@7640000 {
2418                         compatible = "arm,coresight-etm4x", "arm,primecell";
2419                         reg = <0 0x07640000 0 0x1000>;
2420
2421                         cpu = <&CPU6>;
2422
2423                         clocks = <&aoss_qmp>;
2424                         clock-names = "apb_pclk";
2425                         arm,coresight-loses-context-with-cpu;
2426                         qcom,skip-power-up;
2427
2428                         out-ports {
2429                                 port {
2430                                         etm6_out: endpoint {
2431                                                 remote-endpoint = <&apss_funnel_in6>;
2432                                         };
2433                                 };
2434                         };
2435                 };
2436
2437                 etm@7740000 {
2438                         compatible = "arm,coresight-etm4x", "arm,primecell";
2439                         reg = <0 0x07740000 0 0x1000>;
2440
2441                         cpu = <&CPU7>;
2442
2443                         clocks = <&aoss_qmp>;
2444                         clock-names = "apb_pclk";
2445                         arm,coresight-loses-context-with-cpu;
2446                         qcom,skip-power-up;
2447
2448                         out-ports {
2449                                 port {
2450                                         etm7_out: endpoint {
2451                                                 remote-endpoint = <&apss_funnel_in7>;
2452                                         };
2453                                 };
2454                         };
2455                 };
2456
2457                 funnel@7800000 { /* APSS Funnel */
2458                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2459                         reg = <0 0x07800000 0 0x1000>;
2460
2461                         clocks = <&aoss_qmp>;
2462                         clock-names = "apb_pclk";
2463
2464                         out-ports {
2465                                 port {
2466                                         apss_funnel_out: endpoint {
2467                                                 remote-endpoint = <&apss_merge_funnel_in>;
2468                                         };
2469                                 };
2470                         };
2471
2472                         in-ports {
2473                                 #address-cells = <1>;
2474                                 #size-cells = <0>;
2475
2476                                 port@0 {
2477                                         reg = <0>;
2478                                         apss_funnel_in0: endpoint {
2479                                                 remote-endpoint = <&etm0_out>;
2480                                         };
2481                                 };
2482
2483                                 port@1 {
2484                                         reg = <1>;
2485                                         apss_funnel_in1: endpoint {
2486                                                 remote-endpoint = <&etm1_out>;
2487                                         };
2488                                 };
2489
2490                                 port@2 {
2491                                         reg = <2>;
2492                                         apss_funnel_in2: endpoint {
2493                                                 remote-endpoint = <&etm2_out>;
2494                                         };
2495                                 };
2496
2497                                 port@3 {
2498                                         reg = <3>;
2499                                         apss_funnel_in3: endpoint {
2500                                                 remote-endpoint = <&etm3_out>;
2501                                         };
2502                                 };
2503
2504                                 port@4 {
2505                                         reg = <4>;
2506                                         apss_funnel_in4: endpoint {
2507                                                 remote-endpoint = <&etm4_out>;
2508                                         };
2509                                 };
2510
2511                                 port@5 {
2512                                         reg = <5>;
2513                                         apss_funnel_in5: endpoint {
2514                                                 remote-endpoint = <&etm5_out>;
2515                                         };
2516                                 };
2517
2518                                 port@6 {
2519                                         reg = <6>;
2520                                         apss_funnel_in6: endpoint {
2521                                                 remote-endpoint = <&etm6_out>;
2522                                         };
2523                                 };
2524
2525                                 port@7 {
2526                                         reg = <7>;
2527                                         apss_funnel_in7: endpoint {
2528                                                 remote-endpoint = <&etm7_out>;
2529                                         };
2530                                 };
2531                         };
2532                 };
2533
2534                 funnel@7810000 {
2535                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2536                         reg = <0 0x07810000 0 0x1000>;
2537
2538                         clocks = <&aoss_qmp>;
2539                         clock-names = "apb_pclk";
2540
2541                         out-ports {
2542                                 port {
2543                                         apss_merge_funnel_out: endpoint {
2544                                                 remote-endpoint = <&funnel1_in4>;
2545                                         };
2546                                 };
2547                         };
2548
2549                         in-ports {
2550                                 port {
2551                                         apss_merge_funnel_in: endpoint {
2552                                                 remote-endpoint = <&apss_funnel_out>;
2553                                         };
2554                                 };
2555                         };
2556                 };
2557
2558                 sdhc_2: sdhci@8804000 {
2559                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2560                         reg = <0 0x08804000 0 0x1000>;
2561
2562                         iommus = <&apps_smmu 0x80 0>;
2563                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2564                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2565                         interrupt-names = "hc_irq", "pwr_irq";
2566
2567                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2568                                  <&gcc GCC_SDCC2_AHB_CLK>,
2569                                  <&rpmhcc RPMH_CXO_CLK>;
2570                         clock-names = "core", "iface", "xo";
2571
2572                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2573                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2574                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2575                         power-domains = <&rpmhpd SC7180_CX>;
2576                         operating-points-v2 = <&sdhc2_opp_table>;
2577
2578                         bus-width = <4>;
2579
2580                         status = "disabled";
2581
2582                         sdhc2_opp_table: sdhc2-opp-table {
2583                                 compatible = "operating-points-v2";
2584
2585                                 opp-100000000 {
2586                                         opp-hz = /bits/ 64 <100000000>;
2587                                         required-opps = <&rpmhpd_opp_low_svs>;
2588                                         opp-peak-kBps = <1800000 600000>;
2589                                         opp-avg-kBps = <100000 0>;
2590                                 };
2591
2592                                 opp-202000000 {
2593                                         opp-hz = /bits/ 64 <202000000>;
2594                                         required-opps = <&rpmhpd_opp_nom>;
2595                                         opp-peak-kBps = <5400000 1600000>;
2596                                         opp-avg-kBps = <200000 0>;
2597                                 };
2598                         };
2599                 };
2600
2601                 qspi_opp_table: qspi-opp-table {
2602                         compatible = "operating-points-v2";
2603
2604                         opp-75000000 {
2605                                 opp-hz = /bits/ 64 <75000000>;
2606                                 required-opps = <&rpmhpd_opp_low_svs>;
2607                         };
2608
2609                         opp-150000000 {
2610                                 opp-hz = /bits/ 64 <150000000>;
2611                                 required-opps = <&rpmhpd_opp_svs>;
2612                         };
2613
2614                         opp-300000000 {
2615                                 opp-hz = /bits/ 64 <300000000>;
2616                                 required-opps = <&rpmhpd_opp_nom>;
2617                         };
2618                 };
2619
2620                 qspi: spi@88dc000 {
2621                         compatible = "qcom,qspi-v1";
2622                         reg = <0 0x088dc000 0 0x600>;
2623                         #address-cells = <1>;
2624                         #size-cells = <0>;
2625                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2626                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2627                                  <&gcc GCC_QSPI_CORE_CLK>;
2628                         clock-names = "iface", "core";
2629                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2630                                         &config_noc SLAVE_QSPI_0 0>;
2631                         interconnect-names = "qspi-config";
2632                         power-domains = <&rpmhpd SC7180_CX>;
2633                         operating-points-v2 = <&qspi_opp_table>;
2634                         status = "disabled";
2635                 };
2636
2637                 usb_1_hsphy: phy@88e3000 {
2638                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2639                         reg = <0 0x088e3000 0 0x400>;
2640                         status = "disabled";
2641                         #phy-cells = <0>;
2642                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2643                                  <&rpmhcc RPMH_CXO_CLK>;
2644                         clock-names = "cfg_ahb", "ref";
2645                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2646
2647                         nvmem-cells = <&qusb2p_hstx_trim>;
2648                 };
2649
2650                 usb_1_qmpphy: phy-wrapper@88e9000 {
2651                         compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2652                         reg = <0 0x088e9000 0 0x18c>,
2653                               <0 0x088e8000 0 0x3c>,
2654                               <0 0x088ea000 0 0x18c>;
2655                         status = "disabled";
2656                         #address-cells = <2>;
2657                         #size-cells = <2>;
2658                         ranges;
2659
2660                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2661                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2662                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2663                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2664                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2665
2666                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2667                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2668                         reset-names = "phy", "common";
2669
2670                         usb_1_ssphy: usb3-phy@88e9200 {
2671                                 reg = <0 0x088e9200 0 0x128>,
2672                                       <0 0x088e9400 0 0x200>,
2673                                       <0 0x088e9c00 0 0x218>,
2674                                       <0 0x088e9600 0 0x128>,
2675                                       <0 0x088e9800 0 0x200>,
2676                                       <0 0x088e9a00 0 0x18>;
2677                                 #clock-cells = <0>;
2678                                 #phy-cells = <0>;
2679                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2680                                 clock-names = "pipe0";
2681                                 clock-output-names = "usb3_phy_pipe_clk_src";
2682                         };
2683
2684                         dp_phy: dp-phy@88ea200 {
2685                                 reg = <0 0x088ea200 0 0x200>,
2686                                       <0 0x088ea400 0 0x200>,
2687                                       <0 0x088eaa00 0 0x200>,
2688                                       <0 0x088ea600 0 0x200>,
2689                                       <0 0x088ea800 0 0x200>;
2690                                 #clock-cells = <1>;
2691                                 #phy-cells = <0>;
2692                         };
2693                 };
2694
2695                 dc_noc: interconnect@9160000 {
2696                         compatible = "qcom,sc7180-dc-noc";
2697                         reg = <0 0x09160000 0 0x03200>;
2698                         #interconnect-cells = <2>;
2699                         qcom,bcm-voters = <&apps_bcm_voter>;
2700                 };
2701
2702                 system-cache-controller@9200000 {
2703                         compatible = "qcom,sc7180-llcc";
2704                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2705                         reg-names = "llcc_base", "llcc_broadcast_base";
2706                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2707                 };
2708
2709                 gem_noc: interconnect@9680000 {
2710                         compatible = "qcom,sc7180-gem-noc";
2711                         reg = <0 0x09680000 0 0x3e200>;
2712                         #interconnect-cells = <2>;
2713                         qcom,bcm-voters = <&apps_bcm_voter>;
2714                 };
2715
2716                 npu_noc: interconnect@9990000 {
2717                         compatible = "qcom,sc7180-npu-noc";
2718                         reg = <0 0x09990000 0 0x1600>;
2719                         #interconnect-cells = <2>;
2720                         qcom,bcm-voters = <&apps_bcm_voter>;
2721                 };
2722
2723                 usb_1: usb@a6f8800 {
2724                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2725                         reg = <0 0x0a6f8800 0 0x400>;
2726                         status = "disabled";
2727                         #address-cells = <2>;
2728                         #size-cells = <2>;
2729                         ranges;
2730                         dma-ranges;
2731
2732                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2733                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2734                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2735                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2736                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2737                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2738                                       "sleep";
2739
2740                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2741                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2742                         assigned-clock-rates = <19200000>, <150000000>;
2743
2744                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2745                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2746                                               <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2747                                               <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2748                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2749                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2750
2751                         power-domains = <&gcc USB30_PRIM_GDSC>;
2752
2753                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2754
2755                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2756                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2757                         interconnect-names = "usb-ddr", "apps-usb";
2758
2759                         usb_1_dwc3: dwc3@a600000 {
2760                                 compatible = "snps,dwc3";
2761                                 reg = <0 0x0a600000 0 0xe000>;
2762                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2763                                 iommus = <&apps_smmu 0x540 0>;
2764                                 snps,dis_u2_susphy_quirk;
2765                                 snps,dis_enblslpm_quirk;
2766                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2767                                 phy-names = "usb2-phy", "usb3-phy";
2768                                 maximum-speed = "super-speed";
2769                         };
2770                 };
2771
2772                 venus: video-codec@aa00000 {
2773                         compatible = "qcom,sc7180-venus";
2774                         reg = <0 0x0aa00000 0 0xff000>;
2775                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2776                         power-domains = <&videocc VENUS_GDSC>,
2777                                         <&videocc VCODEC0_GDSC>,
2778                                         <&rpmhpd SC7180_CX>;
2779                         power-domain-names = "venus", "vcodec0", "cx";
2780                         operating-points-v2 = <&venus_opp_table>;
2781                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2782                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2783                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2784                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2785                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2786                         clock-names = "core", "iface", "bus",
2787                                       "vcodec0_core", "vcodec0_bus";
2788                         iommus = <&apps_smmu 0x0c00 0x60>;
2789                         memory-region = <&venus_mem>;
2790                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2791                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2792                         interconnect-names = "video-mem", "cpu-cfg";
2793
2794                         video-decoder {
2795                                 compatible = "venus-decoder";
2796                         };
2797
2798                         video-encoder {
2799                                 compatible = "venus-encoder";
2800                         };
2801
2802                         venus_opp_table: venus-opp-table {
2803                                 compatible = "operating-points-v2";
2804
2805                                 opp-150000000 {
2806                                         opp-hz = /bits/ 64 <150000000>;
2807                                         required-opps = <&rpmhpd_opp_low_svs>;
2808                                 };
2809
2810                                 opp-270000000 {
2811                                         opp-hz = /bits/ 64 <270000000>;
2812                                         required-opps = <&rpmhpd_opp_svs>;
2813                                 };
2814
2815                                 opp-340000000 {
2816                                         opp-hz = /bits/ 64 <340000000>;
2817                                         required-opps = <&rpmhpd_opp_svs_l1>;
2818                                 };
2819
2820                                 opp-434000000 {
2821                                         opp-hz = /bits/ 64 <434000000>;
2822                                         required-opps = <&rpmhpd_opp_nom>;
2823                                 };
2824
2825                                 opp-500000097 {
2826                                         opp-hz = /bits/ 64 <500000097>;
2827                                         required-opps = <&rpmhpd_opp_turbo>;
2828                                 };
2829                         };
2830                 };
2831
2832                 videocc: clock-controller@ab00000 {
2833                         compatible = "qcom,sc7180-videocc";
2834                         reg = <0 0x0ab00000 0 0x10000>;
2835                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2836                         clock-names = "bi_tcxo";
2837                         #clock-cells = <1>;
2838                         #reset-cells = <1>;
2839                         #power-domain-cells = <1>;
2840                 };
2841
2842                 camnoc_virt: interconnect@ac00000 {
2843                         compatible = "qcom,sc7180-camnoc-virt";
2844                         reg = <0 0x0ac00000 0 0x1000>;
2845                         #interconnect-cells = <2>;
2846                         qcom,bcm-voters = <&apps_bcm_voter>;
2847                 };
2848
2849                 camcc: clock-controller@ad00000 {
2850                         compatible = "qcom,sc7180-camcc";
2851                         reg = <0 0x0ad00000 0 0x10000>;
2852                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2853                                <&gcc GCC_CAMERA_AHB_CLK>,
2854                                <&gcc GCC_CAMERA_XO_CLK>;
2855                         clock-names = "bi_tcxo", "iface", "xo";
2856                         #clock-cells = <1>;
2857                         #reset-cells = <1>;
2858                         #power-domain-cells = <1>;
2859                 };
2860
2861                 mdss: mdss@ae00000 {
2862                         compatible = "qcom,sc7180-mdss";
2863                         reg = <0 0x0ae00000 0 0x1000>;
2864                         reg-names = "mdss";
2865
2866                         power-domains = <&dispcc MDSS_GDSC>;
2867
2868                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2869                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2870                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2871                         clock-names = "iface", "ahb", "core";
2872
2873                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2874                         assigned-clock-rates = <300000000>;
2875
2876                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2877                         interrupt-controller;
2878                         #interrupt-cells = <1>;
2879
2880                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2881                         interconnect-names = "mdp0-mem";
2882
2883                         iommus = <&apps_smmu 0x800 0x2>;
2884
2885                         #address-cells = <2>;
2886                         #size-cells = <2>;
2887                         ranges;
2888
2889                         status = "disabled";
2890
2891                         mdp: mdp@ae01000 {
2892                                 compatible = "qcom,sc7180-dpu";
2893                                 reg = <0 0x0ae01000 0 0x8f000>,
2894                                       <0 0x0aeb0000 0 0x2008>;
2895                                 reg-names = "mdp", "vbif";
2896
2897                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2898                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2899                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
2900                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2901                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2902                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2903                                 clock-names = "bus", "iface", "rot", "lut", "core",
2904                                               "vsync";
2905                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2906                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2907                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
2908                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
2909                                 assigned-clock-rates = <300000000>,
2910                                                        <19200000>,
2911                                                        <19200000>,
2912                                                        <19200000>;
2913                                 operating-points-v2 = <&mdp_opp_table>;
2914                                 power-domains = <&rpmhpd SC7180_CX>;
2915
2916                                 interrupt-parent = <&mdss>;
2917                                 interrupts = <0>;
2918
2919                                 status = "disabled";
2920
2921                                 ports {
2922                                         #address-cells = <1>;
2923                                         #size-cells = <0>;
2924
2925                                         port@0 {
2926                                                 reg = <0>;
2927                                                 dpu_intf1_out: endpoint {
2928                                                         remote-endpoint = <&dsi0_in>;
2929                                                 };
2930                                         };
2931                                 };
2932
2933                                 mdp_opp_table: mdp-opp-table {
2934                                         compatible = "operating-points-v2";
2935
2936                                         opp-200000000 {
2937                                                 opp-hz = /bits/ 64 <200000000>;
2938                                                 required-opps = <&rpmhpd_opp_low_svs>;
2939                                         };
2940
2941                                         opp-300000000 {
2942                                                 opp-hz = /bits/ 64 <300000000>;
2943                                                 required-opps = <&rpmhpd_opp_svs>;
2944                                         };
2945
2946                                         opp-345000000 {
2947                                                 opp-hz = /bits/ 64 <345000000>;
2948                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2949                                         };
2950
2951                                         opp-460000000 {
2952                                                 opp-hz = /bits/ 64 <460000000>;
2953                                                 required-opps = <&rpmhpd_opp_nom>;
2954                                         };
2955                                 };
2956
2957                         };
2958
2959                         dsi0: dsi@ae94000 {
2960                                 compatible = "qcom,mdss-dsi-ctrl";
2961                                 reg = <0 0x0ae94000 0 0x400>;
2962                                 reg-names = "dsi_ctrl";
2963
2964                                 interrupt-parent = <&mdss>;
2965                                 interrupts = <4>;
2966
2967                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2968                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2969                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2970                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2971                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2972                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2973                                 clock-names = "byte",
2974                                               "byte_intf",
2975                                               "pixel",
2976                                               "core",
2977                                               "iface",
2978                                               "bus";
2979
2980                                 operating-points-v2 = <&dsi_opp_table>;
2981                                 power-domains = <&rpmhpd SC7180_CX>;
2982
2983                                 phys = <&dsi_phy>;
2984                                 phy-names = "dsi";
2985
2986                                 #address-cells = <1>;
2987                                 #size-cells = <0>;
2988
2989                                 status = "disabled";
2990
2991                                 ports {
2992                                         #address-cells = <1>;
2993                                         #size-cells = <0>;
2994
2995                                         port@0 {
2996                                                 reg = <0>;
2997                                                 dsi0_in: endpoint {
2998                                                         remote-endpoint = <&dpu_intf1_out>;
2999                                                 };
3000                                         };
3001
3002                                         port@1 {
3003                                                 reg = <1>;
3004                                                 dsi0_out: endpoint {
3005                                                 };
3006                                         };
3007                                 };
3008
3009                                 dsi_opp_table: dsi-opp-table {
3010                                         compatible = "operating-points-v2";
3011
3012                                         opp-187500000 {
3013                                                 opp-hz = /bits/ 64 <187500000>;
3014                                                 required-opps = <&rpmhpd_opp_low_svs>;
3015                                         };
3016
3017                                         opp-300000000 {
3018                                                 opp-hz = /bits/ 64 <300000000>;
3019                                                 required-opps = <&rpmhpd_opp_svs>;
3020                                         };
3021
3022                                         opp-358000000 {
3023                                                 opp-hz = /bits/ 64 <358000000>;
3024                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3025                                         };
3026                                 };
3027                         };
3028
3029                         dsi_phy: dsi-phy@ae94400 {
3030                                 compatible = "qcom,dsi-phy-10nm";
3031                                 reg = <0 0x0ae94400 0 0x200>,
3032                                       <0 0x0ae94600 0 0x280>,
3033                                       <0 0x0ae94a00 0 0x1e0>;
3034                                 reg-names = "dsi_phy",
3035                                             "dsi_phy_lane",
3036                                             "dsi_pll";
3037
3038                                 #clock-cells = <1>;
3039                                 #phy-cells = <0>;
3040
3041                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3042                                          <&rpmhcc RPMH_CXO_CLK>;
3043                                 clock-names = "iface", "ref";
3044
3045                                 status = "disabled";
3046                         };
3047                 };
3048
3049                 dispcc: clock-controller@af00000 {
3050                         compatible = "qcom,sc7180-dispcc";
3051                         reg = <0 0x0af00000 0 0x200000>;
3052                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3053                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3054                                  <&dsi_phy 0>,
3055                                  <&dsi_phy 1>,
3056                                  <&dp_phy 0>,
3057                                  <&dp_phy 1>;
3058                         clock-names = "bi_tcxo",
3059                                       "gcc_disp_gpll0_clk_src",
3060                                       "dsi0_phy_pll_out_byteclk",
3061                                       "dsi0_phy_pll_out_dsiclk",
3062                                       "dp_phy_pll_link_clk",
3063                                       "dp_phy_pll_vco_div_clk";
3064                         #clock-cells = <1>;
3065                         #reset-cells = <1>;
3066                         #power-domain-cells = <1>;
3067                 };
3068
3069                 pdc: interrupt-controller@b220000 {
3070                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3071                         reg = <0 0x0b220000 0 0x30000>;
3072                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3073                         #interrupt-cells = <2>;
3074                         interrupt-parent = <&intc>;
3075                         interrupt-controller;
3076                 };
3077
3078                 pdc_reset: reset-controller@b2e0000 {
3079                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3080                         reg = <0 0x0b2e0000 0 0x20000>;
3081                         #reset-cells = <1>;
3082                 };
3083
3084                 tsens0: thermal-sensor@c263000 {
3085                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3086                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3087                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3088                         #qcom,sensors = <15>;
3089                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3090                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3091                         interrupt-names = "uplow","critical";
3092                         #thermal-sensor-cells = <1>;
3093                 };
3094
3095                 tsens1: thermal-sensor@c265000 {
3096                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3097                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3098                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3099                         #qcom,sensors = <10>;
3100                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3101                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3102                         interrupt-names = "uplow","critical";
3103                         #thermal-sensor-cells = <1>;
3104                 };
3105
3106                 aoss_reset: reset-controller@c2a0000 {
3107                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3108                         reg = <0 0x0c2a0000 0 0x31000>;
3109                         #reset-cells = <1>;
3110                 };
3111
3112                 aoss_qmp: power-controller@c300000 {
3113                         compatible = "qcom,sc7180-aoss-qmp";
3114                         reg = <0 0x0c300000 0 0x100000>;
3115                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3116                         mboxes = <&apss_shared 0>;
3117
3118                         #clock-cells = <0>;
3119                         #power-domain-cells = <1>;
3120                 };
3121
3122                 spmi_bus: spmi@c440000 {
3123                         compatible = "qcom,spmi-pmic-arb";
3124                         reg = <0 0x0c440000 0 0x1100>,
3125                               <0 0x0c600000 0 0x2000000>,
3126                               <0 0x0e600000 0 0x100000>,
3127                               <0 0x0e700000 0 0xa0000>,
3128                               <0 0x0c40a000 0 0x26000>;
3129                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3130                         interrupt-names = "periph_irq";
3131                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3132                         qcom,ee = <0>;
3133                         qcom,channel = <0>;
3134                         #address-cells = <1>;
3135                         #size-cells = <1>;
3136                         interrupt-controller;
3137                         #interrupt-cells = <4>;
3138                         cell-index = <0>;
3139                 };
3140
3141                 apps_smmu: iommu@15000000 {
3142                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3143                         reg = <0 0x15000000 0 0x100000>;
3144                         #iommu-cells = <2>;
3145                         #global-interrupts = <1>;
3146                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3147                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3148                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3149                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3150                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3151                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3152                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3153                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3154                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3155                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3156                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3157                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3158                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3159                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3160                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3161                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3162                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3163                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3164                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3165                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3166                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3167                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3168                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3169                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3170                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3171                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3172                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3173                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3174                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3175                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3176                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3177                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3178                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3179                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3180                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3181                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3182                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3183                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3184                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3185                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3186                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3187                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3188                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3189                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3190                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3191                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3192                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3193                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3194                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3195                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3196                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3197                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3198                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3199                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3200                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3201                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3202                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3203                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3204                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3205                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3206                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3207                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3208                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3209                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3210                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3211                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3212                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3213                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3214                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3215                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3216                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3217                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3218                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3219                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3220                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3221                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3222                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3223                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3224                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3225                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3226                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3227                 };
3228
3229                 intc: interrupt-controller@17a00000 {
3230                         compatible = "arm,gic-v3";
3231                         #address-cells = <2>;
3232                         #size-cells = <2>;
3233                         ranges;
3234                         #interrupt-cells = <3>;
3235                         interrupt-controller;
3236                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3237                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3238                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3239
3240                         msi-controller@17a40000 {
3241                                 compatible = "arm,gic-v3-its";
3242                                 msi-controller;
3243                                 #msi-cells = <1>;
3244                                 reg = <0 0x17a40000 0 0x20000>;
3245                                 status = "disabled";
3246                         };
3247                 };
3248
3249                 apss_shared: mailbox@17c00000 {
3250                         compatible = "qcom,sc7180-apss-shared";
3251                         reg = <0 0x17c00000 0 0x10000>;
3252                         #mbox-cells = <1>;
3253                 };
3254
3255                 watchdog@17c10000 {
3256                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3257                         reg = <0 0x17c10000 0 0x1000>;
3258                         clocks = <&sleep_clk>;
3259                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3260                 };
3261
3262                 timer@17c20000{
3263                         #address-cells = <2>;
3264                         #size-cells = <2>;
3265                         ranges;
3266                         compatible = "arm,armv7-timer-mem";
3267                         reg = <0 0x17c20000 0 0x1000>;
3268
3269                         frame@17c21000 {
3270                                 frame-number = <0>;
3271                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3272                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3273                                 reg = <0 0x17c21000 0 0x1000>,
3274                                       <0 0x17c22000 0 0x1000>;
3275                         };
3276
3277                         frame@17c23000 {
3278                                 frame-number = <1>;
3279                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3280                                 reg = <0 0x17c23000 0 0x1000>;
3281                                 status = "disabled";
3282                         };
3283
3284                         frame@17c25000 {
3285                                 frame-number = <2>;
3286                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3287                                 reg = <0 0x17c25000 0 0x1000>;
3288                                 status = "disabled";
3289                         };
3290
3291                         frame@17c27000 {
3292                                 frame-number = <3>;
3293                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3294                                 reg = <0 0x17c27000 0 0x1000>;
3295                                 status = "disabled";
3296                         };
3297
3298                         frame@17c29000 {
3299                                 frame-number = <4>;
3300                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3301                                 reg = <0 0x17c29000 0 0x1000>;
3302                                 status = "disabled";
3303                         };
3304
3305                         frame@17c2b000 {
3306                                 frame-number = <5>;
3307                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3308                                 reg = <0 0x17c2b000 0 0x1000>;
3309                                 status = "disabled";
3310                         };
3311
3312                         frame@17c2d000 {
3313                                 frame-number = <6>;
3314                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3315                                 reg = <0 0x17c2d000 0 0x1000>;
3316                                 status = "disabled";
3317                         };
3318                 };
3319
3320                 apps_rsc: rsc@18200000 {
3321                         compatible = "qcom,rpmh-rsc";
3322                         reg = <0 0x18200000 0 0x10000>,
3323                               <0 0x18210000 0 0x10000>,
3324                               <0 0x18220000 0 0x10000>;
3325                         reg-names = "drv-0", "drv-1", "drv-2";
3326                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3327                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3328                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3329                         qcom,tcs-offset = <0xd00>;
3330                         qcom,drv-id = <2>;
3331                         qcom,tcs-config = <ACTIVE_TCS  2>,
3332                                           <SLEEP_TCS   3>,
3333                                           <WAKE_TCS    3>,
3334                                           <CONTROL_TCS 1>;
3335
3336                         rpmhcc: clock-controller {
3337                                 compatible = "qcom,sc7180-rpmh-clk";
3338                                 clocks = <&xo_board>;
3339                                 clock-names = "xo";
3340                                 #clock-cells = <1>;
3341                         };
3342
3343                         rpmhpd: power-controller {
3344                                 compatible = "qcom,sc7180-rpmhpd";
3345                                 #power-domain-cells = <1>;
3346                                 operating-points-v2 = <&rpmhpd_opp_table>;
3347
3348                                 rpmhpd_opp_table: opp-table {
3349                                         compatible = "operating-points-v2";
3350
3351                                         rpmhpd_opp_ret: opp1 {
3352                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3353                                         };
3354
3355                                         rpmhpd_opp_min_svs: opp2 {
3356                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3357                                         };
3358
3359                                         rpmhpd_opp_low_svs: opp3 {
3360                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3361                                         };
3362
3363                                         rpmhpd_opp_svs: opp4 {
3364                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3365                                         };
3366
3367                                         rpmhpd_opp_svs_l1: opp5 {
3368                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3369                                         };
3370
3371                                         rpmhpd_opp_svs_l2: opp6 {
3372                                                 opp-level = <224>;
3373                                         };
3374
3375                                         rpmhpd_opp_nom: opp7 {
3376                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3377                                         };
3378
3379                                         rpmhpd_opp_nom_l1: opp8 {
3380                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3381                                         };
3382
3383                                         rpmhpd_opp_nom_l2: opp9 {
3384                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3385                                         };
3386
3387                                         rpmhpd_opp_turbo: opp10 {
3388                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3389                                         };
3390
3391                                         rpmhpd_opp_turbo_l1: opp11 {
3392                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3393                                         };
3394                                 };
3395                         };
3396
3397                         apps_bcm_voter: bcm_voter {
3398                                 compatible = "qcom,bcm-voter";
3399                         };
3400                 };
3401
3402                 osm_l3: interconnect@18321000 {
3403                         compatible = "qcom,sc7180-osm-l3";
3404                         reg = <0 0x18321000 0 0x1400>;
3405
3406                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3407                         clock-names = "xo", "alternate";
3408
3409                         #interconnect-cells = <1>;
3410                 };
3411
3412                 cpufreq_hw: cpufreq@18323000 {
3413                         compatible = "qcom,cpufreq-hw";
3414                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3415                         reg-names = "freq-domain0", "freq-domain1";
3416
3417                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3418                         clock-names = "xo", "alternate";
3419
3420                         #freq-domain-cells = <1>;
3421                 };
3422
3423                 wifi: wifi@18800000 {
3424                         compatible = "qcom,wcn3990-wifi";
3425                         reg = <0 0x18800000 0 0x800000>;
3426                         reg-names = "membase";
3427                         iommus = <&apps_smmu 0xc0 0x1>;
3428                         interrupts =
3429                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3430                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3431                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3432                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3433                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3434                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3435                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3436                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3437                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3438                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3439                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3440                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3441                         memory-region = <&wlan_mem>;
3442                         qcom,msa-fixed-perm;
3443                         status = "disabled";
3444                 };
3445
3446                 lpasscc: clock-controller@62d00000 {
3447                         compatible = "qcom,sc7180-lpasscorecc";
3448                         reg = <0 0x62d00000 0 0x50000>,
3449                               <0 0x62780000 0 0x30000>;
3450                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3451                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3452                                  <&rpmhcc RPMH_CXO_CLK>;
3453                         clock-names = "iface", "bi_tcxo";
3454                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3455                         #clock-cells = <1>;
3456                         #power-domain-cells = <1>;
3457                 };
3458
3459                 lpass_cpu: lpass@62f00000 {
3460                         compatible = "qcom,sc7180-lpass-cpu";
3461
3462                         reg = <0 0x62f00000 0 0x29000>;
3463                         reg-names = "lpass-lpaif";
3464
3465                         iommus = <&apps_smmu 0x1020 0>,
3466                                 <&apps_smmu 0x1021 0>;
3467
3468                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3469
3470                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3471                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3472                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3473                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3474                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3475                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3476
3477                         clock-names = "pcnoc-sway-clk", "audio-core",
3478                                         "mclk0", "pcnoc-mport-clk",
3479                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3480
3481
3482                         #sound-dai-cells = <1>;
3483                         #address-cells = <1>;
3484                         #size-cells = <0>;
3485
3486                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3487                         interrupt-names = "lpass-irq-lpaif";
3488                 };
3489
3490                 lpass_hm: clock-controller@63000000 {
3491                         compatible = "qcom,sc7180-lpasshm";
3492                         reg = <0 0x63000000 0 0x28>;
3493                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3494                                  <&rpmhcc RPMH_CXO_CLK>;
3495                         clock-names = "iface", "bi_tcxo";
3496                         #clock-cells = <1>;
3497                         #power-domain-cells = <1>;
3498                 };
3499         };
3500
3501         thermal-zones {
3502                 cpu0_thermal: cpu0-thermal {
3503                         polling-delay-passive = <250>;
3504                         polling-delay = <0>;
3505
3506                         thermal-sensors = <&tsens0 1>;
3507                         sustainable-power = <768>;
3508
3509                         trips {
3510                                 cpu0_alert0: trip-point0 {
3511                                         temperature = <90000>;
3512                                         hysteresis = <2000>;
3513                                         type = "passive";
3514                                 };
3515
3516                                 cpu0_alert1: trip-point1 {
3517                                         temperature = <95000>;
3518                                         hysteresis = <2000>;
3519                                         type = "passive";
3520                                 };
3521
3522                                 cpu0_crit: cpu_crit {
3523                                         temperature = <110000>;
3524                                         hysteresis = <1000>;
3525                                         type = "critical";
3526                                 };
3527                         };
3528
3529                         cooling-maps {
3530                                 map0 {
3531                                         trip = <&cpu0_alert0>;
3532                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3533                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3534                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3535                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3536                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3537                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3538                                 };
3539                                 map1 {
3540                                         trip = <&cpu0_alert1>;
3541                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3542                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3543                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3544                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3545                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3546                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3547                                 };
3548                         };
3549                 };
3550
3551                 cpu1_thermal: cpu1-thermal {
3552                         polling-delay-passive = <250>;
3553                         polling-delay = <0>;
3554
3555                         thermal-sensors = <&tsens0 2>;
3556                         sustainable-power = <768>;
3557
3558                         trips {
3559                                 cpu1_alert0: trip-point0 {
3560                                         temperature = <90000>;
3561                                         hysteresis = <2000>;
3562                                         type = "passive";
3563                                 };
3564
3565                                 cpu1_alert1: trip-point1 {
3566                                         temperature = <95000>;
3567                                         hysteresis = <2000>;
3568                                         type = "passive";
3569                                 };
3570
3571                                 cpu1_crit: cpu_crit {
3572                                         temperature = <110000>;
3573                                         hysteresis = <1000>;
3574                                         type = "critical";
3575                                 };
3576                         };
3577
3578                         cooling-maps {
3579                                 map0 {
3580                                         trip = <&cpu1_alert0>;
3581                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3582                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3583                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3584                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3585                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3586                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3587                                 };
3588                                 map1 {
3589                                         trip = <&cpu1_alert1>;
3590                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3591                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3592                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3593                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3594                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3595                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3596                                 };
3597                         };
3598                 };
3599
3600                 cpu2_thermal: cpu2-thermal {
3601                         polling-delay-passive = <250>;
3602                         polling-delay = <0>;
3603
3604                         thermal-sensors = <&tsens0 3>;
3605                         sustainable-power = <768>;
3606
3607                         trips {
3608                                 cpu2_alert0: trip-point0 {
3609                                         temperature = <90000>;
3610                                         hysteresis = <2000>;
3611                                         type = "passive";
3612                                 };
3613
3614                                 cpu2_alert1: trip-point1 {
3615                                         temperature = <95000>;
3616                                         hysteresis = <2000>;
3617                                         type = "passive";
3618                                 };
3619
3620                                 cpu2_crit: cpu_crit {
3621                                         temperature = <110000>;
3622                                         hysteresis = <1000>;
3623                                         type = "critical";
3624                                 };
3625                         };
3626
3627                         cooling-maps {
3628                                 map0 {
3629                                         trip = <&cpu2_alert0>;
3630                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3631                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3632                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3633                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3634                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3635                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3636                                 };
3637                                 map1 {
3638                                         trip = <&cpu2_alert1>;
3639                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3640                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3641                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3642                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3643                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3644                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3645                                 };
3646                         };
3647                 };
3648
3649                 cpu3_thermal: cpu3-thermal {
3650                         polling-delay-passive = <250>;
3651                         polling-delay = <0>;
3652
3653                         thermal-sensors = <&tsens0 4>;
3654                         sustainable-power = <768>;
3655
3656                         trips {
3657                                 cpu3_alert0: trip-point0 {
3658                                         temperature = <90000>;
3659                                         hysteresis = <2000>;
3660                                         type = "passive";
3661                                 };
3662
3663                                 cpu3_alert1: trip-point1 {
3664                                         temperature = <95000>;
3665                                         hysteresis = <2000>;
3666                                         type = "passive";
3667                                 };
3668
3669                                 cpu3_crit: cpu_crit {
3670                                         temperature = <110000>;
3671                                         hysteresis = <1000>;
3672                                         type = "critical";
3673                                 };
3674                         };
3675
3676                         cooling-maps {
3677                                 map0 {
3678                                         trip = <&cpu3_alert0>;
3679                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3680                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3681                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3682                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3684                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3685                                 };
3686                                 map1 {
3687                                         trip = <&cpu3_alert1>;
3688                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3690                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3691                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3692                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3693                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3694                                 };
3695                         };
3696                 };
3697
3698                 cpu4_thermal: cpu4-thermal {
3699                         polling-delay-passive = <250>;
3700                         polling-delay = <0>;
3701
3702                         thermal-sensors = <&tsens0 5>;
3703                         sustainable-power = <768>;
3704
3705                         trips {
3706                                 cpu4_alert0: trip-point0 {
3707                                         temperature = <90000>;
3708                                         hysteresis = <2000>;
3709                                         type = "passive";
3710                                 };
3711
3712                                 cpu4_alert1: trip-point1 {
3713                                         temperature = <95000>;
3714                                         hysteresis = <2000>;
3715                                         type = "passive";
3716                                 };
3717
3718                                 cpu4_crit: cpu_crit {
3719                                         temperature = <110000>;
3720                                         hysteresis = <1000>;
3721                                         type = "critical";
3722                                 };
3723                         };
3724
3725                         cooling-maps {
3726                                 map0 {
3727                                         trip = <&cpu4_alert0>;
3728                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3729                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3730                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3731                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3732                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3733                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3734                                 };
3735                                 map1 {
3736                                         trip = <&cpu4_alert1>;
3737                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3738                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3739                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3740                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3741                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3742                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3743                                 };
3744                         };
3745                 };
3746
3747                 cpu5_thermal: cpu5-thermal {
3748                         polling-delay-passive = <250>;
3749                         polling-delay = <0>;
3750
3751                         thermal-sensors = <&tsens0 6>;
3752                         sustainable-power = <768>;
3753
3754                         trips {
3755                                 cpu5_alert0: trip-point0 {
3756                                         temperature = <90000>;
3757                                         hysteresis = <2000>;
3758                                         type = "passive";
3759                                 };
3760
3761                                 cpu5_alert1: trip-point1 {
3762                                         temperature = <95000>;
3763                                         hysteresis = <2000>;
3764                                         type = "passive";
3765                                 };
3766
3767                                 cpu5_crit: cpu_crit {
3768                                         temperature = <110000>;
3769                                         hysteresis = <1000>;
3770                                         type = "critical";
3771                                 };
3772                         };
3773
3774                         cooling-maps {
3775                                 map0 {
3776                                         trip = <&cpu5_alert0>;
3777                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3780                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3781                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3782                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3783                                 };
3784                                 map1 {
3785                                         trip = <&cpu5_alert1>;
3786                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3787                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3788                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3789                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3790                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3791                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3792                                 };
3793                         };
3794                 };
3795
3796                 cpu6_thermal: cpu6-thermal {
3797                         polling-delay-passive = <250>;
3798                         polling-delay = <0>;
3799
3800                         thermal-sensors = <&tsens0 9>;
3801                         sustainable-power = <1202>;
3802
3803                         trips {
3804                                 cpu6_alert0: trip-point0 {
3805                                         temperature = <90000>;
3806                                         hysteresis = <2000>;
3807                                         type = "passive";
3808                                 };
3809
3810                                 cpu6_alert1: trip-point1 {
3811                                         temperature = <95000>;
3812                                         hysteresis = <2000>;
3813                                         type = "passive";
3814                                 };
3815
3816                                 cpu6_crit: cpu_crit {
3817                                         temperature = <110000>;
3818                                         hysteresis = <1000>;
3819                                         type = "critical";
3820                                 };
3821                         };
3822
3823                         cooling-maps {
3824                                 map0 {
3825                                         trip = <&cpu6_alert0>;
3826                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3827                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828                                 };
3829                                 map1 {
3830                                         trip = <&cpu6_alert1>;
3831                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3832                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3833                                 };
3834                         };
3835                 };
3836
3837                 cpu7_thermal: cpu7-thermal {
3838                         polling-delay-passive = <250>;
3839                         polling-delay = <0>;
3840
3841                         thermal-sensors = <&tsens0 10>;
3842                         sustainable-power = <1202>;
3843
3844                         trips {
3845                                 cpu7_alert0: trip-point0 {
3846                                         temperature = <90000>;
3847                                         hysteresis = <2000>;
3848                                         type = "passive";
3849                                 };
3850
3851                                 cpu7_alert1: trip-point1 {
3852                                         temperature = <95000>;
3853                                         hysteresis = <2000>;
3854                                         type = "passive";
3855                                 };
3856
3857                                 cpu7_crit: cpu_crit {
3858                                         temperature = <110000>;
3859                                         hysteresis = <1000>;
3860                                         type = "critical";
3861                                 };
3862                         };
3863
3864                         cooling-maps {
3865                                 map0 {
3866                                         trip = <&cpu7_alert0>;
3867                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3868                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3869                                 };
3870                                 map1 {
3871                                         trip = <&cpu7_alert1>;
3872                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3873                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3874                                 };
3875                         };
3876                 };
3877
3878                 cpu8_thermal: cpu8-thermal {
3879                         polling-delay-passive = <250>;
3880                         polling-delay = <0>;
3881
3882                         thermal-sensors = <&tsens0 11>;
3883                         sustainable-power = <1202>;
3884
3885                         trips {
3886                                 cpu8_alert0: trip-point0 {
3887                                         temperature = <90000>;
3888                                         hysteresis = <2000>;
3889                                         type = "passive";
3890                                 };
3891
3892                                 cpu8_alert1: trip-point1 {
3893                                         temperature = <95000>;
3894                                         hysteresis = <2000>;
3895                                         type = "passive";
3896                                 };
3897
3898                                 cpu8_crit: cpu_crit {
3899                                         temperature = <110000>;
3900                                         hysteresis = <1000>;
3901                                         type = "critical";
3902                                 };
3903                         };
3904
3905                         cooling-maps {
3906                                 map0 {
3907                                         trip = <&cpu8_alert0>;
3908                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3909                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3910                                 };
3911                                 map1 {
3912                                         trip = <&cpu8_alert1>;
3913                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3914                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3915                                 };
3916                         };
3917                 };
3918
3919                 cpu9_thermal: cpu9-thermal {
3920                         polling-delay-passive = <250>;
3921                         polling-delay = <0>;
3922
3923                         thermal-sensors = <&tsens0 12>;
3924                         sustainable-power = <1202>;
3925
3926                         trips {
3927                                 cpu9_alert0: trip-point0 {
3928                                         temperature = <90000>;
3929                                         hysteresis = <2000>;
3930                                         type = "passive";
3931                                 };
3932
3933                                 cpu9_alert1: trip-point1 {
3934                                         temperature = <95000>;
3935                                         hysteresis = <2000>;
3936                                         type = "passive";
3937                                 };
3938
3939                                 cpu9_crit: cpu_crit {
3940                                         temperature = <110000>;
3941                                         hysteresis = <1000>;
3942                                         type = "critical";
3943                                 };
3944                         };
3945
3946                         cooling-maps {
3947                                 map0 {
3948                                         trip = <&cpu9_alert0>;
3949                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3950                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3951                                 };
3952                                 map1 {
3953                                         trip = <&cpu9_alert1>;
3954                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3955                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3956                                 };
3957                         };
3958                 };
3959
3960                 aoss0-thermal {
3961                         polling-delay-passive = <250>;
3962                         polling-delay = <0>;
3963
3964                         thermal-sensors = <&tsens0 0>;
3965
3966                         trips {
3967                                 aoss0_alert0: trip-point0 {
3968                                         temperature = <90000>;
3969                                         hysteresis = <2000>;
3970                                         type = "hot";
3971                                 };
3972
3973                                 aoss0_crit: aoss0_crit {
3974                                         temperature = <110000>;
3975                                         hysteresis = <2000>;
3976                                         type = "critical";
3977                                 };
3978                         };
3979                 };
3980
3981                 cpuss0-thermal {
3982                         polling-delay-passive = <250>;
3983                         polling-delay = <0>;
3984
3985                         thermal-sensors = <&tsens0 7>;
3986
3987                         trips {
3988                                 cpuss0_alert0: trip-point0 {
3989                                         temperature = <90000>;
3990                                         hysteresis = <2000>;
3991                                         type = "hot";
3992                                 };
3993                                 cpuss0_crit: cluster0_crit {
3994                                         temperature = <110000>;
3995                                         hysteresis = <2000>;
3996                                         type = "critical";
3997                                 };
3998                         };
3999                 };
4000
4001                 cpuss1-thermal {
4002                         polling-delay-passive = <250>;
4003                         polling-delay = <0>;
4004
4005                         thermal-sensors = <&tsens0 8>;
4006
4007                         trips {
4008                                 cpuss1_alert0: trip-point0 {
4009                                         temperature = <90000>;
4010                                         hysteresis = <2000>;
4011                                         type = "hot";
4012                                 };
4013                                 cpuss1_crit: cluster0_crit {
4014                                         temperature = <110000>;
4015                                         hysteresis = <2000>;
4016                                         type = "critical";
4017                                 };
4018                         };
4019                 };
4020
4021                 gpuss0-thermal {
4022                         polling-delay-passive = <250>;
4023                         polling-delay = <0>;
4024
4025                         thermal-sensors = <&tsens0 13>;
4026
4027                         trips {
4028                                 gpuss0_alert0: trip-point0 {
4029                                         temperature = <95000>;
4030                                         hysteresis = <2000>;
4031                                         type = "passive";
4032                                 };
4033
4034                                 gpuss0_crit: gpuss0_crit {
4035                                         temperature = <110000>;
4036                                         hysteresis = <2000>;
4037                                         type = "critical";
4038                                 };
4039                         };
4040
4041                         cooling-maps {
4042                                 map0 {
4043                                         trip = <&gpuss0_alert0>;
4044                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4045                                 };
4046                         };
4047                 };
4048
4049                 gpuss1-thermal {
4050                         polling-delay-passive = <250>;
4051                         polling-delay = <0>;
4052
4053                         thermal-sensors = <&tsens0 14>;
4054
4055                         trips {
4056                                 gpuss1_alert0: trip-point0 {
4057                                         temperature = <95000>;
4058                                         hysteresis = <2000>;
4059                                         type = "passive";
4060                                 };
4061
4062                                 gpuss1_crit: gpuss1_crit {
4063                                         temperature = <110000>;
4064                                         hysteresis = <2000>;
4065                                         type = "critical";
4066                                 };
4067                         };
4068
4069                         cooling-maps {
4070                                 map0 {
4071                                         trip = <&gpuss1_alert0>;
4072                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4073                                 };
4074                         };
4075                 };
4076
4077                 aoss1-thermal {
4078                         polling-delay-passive = <250>;
4079                         polling-delay = <0>;
4080
4081                         thermal-sensors = <&tsens1 0>;
4082
4083                         trips {
4084                                 aoss1_alert0: trip-point0 {
4085                                         temperature = <90000>;
4086                                         hysteresis = <2000>;
4087                                         type = "hot";
4088                                 };
4089
4090                                 aoss1_crit: aoss1_crit {
4091                                         temperature = <110000>;
4092                                         hysteresis = <2000>;
4093                                         type = "critical";
4094                                 };
4095                         };
4096                 };
4097
4098                 cwlan-thermal {
4099                         polling-delay-passive = <250>;
4100                         polling-delay = <0>;
4101
4102                         thermal-sensors = <&tsens1 1>;
4103
4104                         trips {
4105                                 cwlan_alert0: trip-point0 {
4106                                         temperature = <90000>;
4107                                         hysteresis = <2000>;
4108                                         type = "hot";
4109                                 };
4110
4111                                 cwlan_crit: cwlan_crit {
4112                                         temperature = <110000>;
4113                                         hysteresis = <2000>;
4114                                         type = "critical";
4115                                 };
4116                         };
4117                 };
4118
4119                 audio-thermal {
4120                         polling-delay-passive = <250>;
4121                         polling-delay = <0>;
4122
4123                         thermal-sensors = <&tsens1 2>;
4124
4125                         trips {
4126                                 audio_alert0: trip-point0 {
4127                                         temperature = <90000>;
4128                                         hysteresis = <2000>;
4129                                         type = "hot";
4130                                 };
4131
4132                                 audio_crit: audio_crit {
4133                                         temperature = <110000>;
4134                                         hysteresis = <2000>;
4135                                         type = "critical";
4136                                 };
4137                         };
4138                 };
4139
4140                 ddr-thermal {
4141                         polling-delay-passive = <250>;
4142                         polling-delay = <0>;
4143
4144                         thermal-sensors = <&tsens1 3>;
4145
4146                         trips {
4147                                 ddr_alert0: trip-point0 {
4148                                         temperature = <90000>;
4149                                         hysteresis = <2000>;
4150                                         type = "hot";
4151                                 };
4152
4153                                 ddr_crit: ddr_crit {
4154                                         temperature = <110000>;
4155                                         hysteresis = <2000>;
4156                                         type = "critical";
4157                                 };
4158                         };
4159                 };
4160
4161                 q6-hvx-thermal {
4162                         polling-delay-passive = <250>;
4163                         polling-delay = <0>;
4164
4165                         thermal-sensors = <&tsens1 4>;
4166
4167                         trips {
4168                                 q6_hvx_alert0: trip-point0 {
4169                                         temperature = <90000>;
4170                                         hysteresis = <2000>;
4171                                         type = "hot";
4172                                 };
4173
4174                                 q6_hvx_crit: q6_hvx_crit {
4175                                         temperature = <110000>;
4176                                         hysteresis = <2000>;
4177                                         type = "critical";
4178                                 };
4179                         };
4180                 };
4181
4182                 camera-thermal {
4183                         polling-delay-passive = <250>;
4184                         polling-delay = <0>;
4185
4186                         thermal-sensors = <&tsens1 5>;
4187
4188                         trips {
4189                                 camera_alert0: trip-point0 {
4190                                         temperature = <90000>;
4191                                         hysteresis = <2000>;
4192                                         type = "hot";
4193                                 };
4194
4195                                 camera_crit: camera_crit {
4196                                         temperature = <110000>;
4197                                         hysteresis = <2000>;
4198                                         type = "critical";
4199                                 };
4200                         };
4201                 };
4202
4203                 mdm-core-thermal {
4204                         polling-delay-passive = <250>;
4205                         polling-delay = <0>;
4206
4207                         thermal-sensors = <&tsens1 6>;
4208
4209                         trips {
4210                                 mdm_alert0: trip-point0 {
4211                                         temperature = <90000>;
4212                                         hysteresis = <2000>;
4213                                         type = "hot";
4214                                 };
4215
4216                                 mdm_crit: mdm_crit {
4217                                         temperature = <110000>;
4218                                         hysteresis = <2000>;
4219                                         type = "critical";
4220                                 };
4221                         };
4222                 };
4223
4224                 mdm-dsp-thermal {
4225                         polling-delay-passive = <250>;
4226                         polling-delay = <0>;
4227
4228                         thermal-sensors = <&tsens1 7>;
4229
4230                         trips {
4231                                 mdm_dsp_alert0: trip-point0 {
4232                                         temperature = <90000>;
4233                                         hysteresis = <2000>;
4234                                         type = "hot";
4235                                 };
4236
4237                                 mdm_dsp_crit: mdm_dsp_crit {
4238                                         temperature = <110000>;
4239                                         hysteresis = <2000>;
4240                                         type = "critical";
4241                                 };
4242                         };
4243                 };
4244
4245                 npu-thermal {
4246                         polling-delay-passive = <250>;
4247                         polling-delay = <0>;
4248
4249                         thermal-sensors = <&tsens1 8>;
4250
4251                         trips {
4252                                 npu_alert0: trip-point0 {
4253                                         temperature = <90000>;
4254                                         hysteresis = <2000>;
4255                                         type = "hot";
4256                                 };
4257
4258                                 npu_crit: npu_crit {
4259                                         temperature = <110000>;
4260                                         hysteresis = <2000>;
4261                                         type = "critical";
4262                                 };
4263                         };
4264                 };
4265
4266                 video-thermal {
4267                         polling-delay-passive = <250>;
4268                         polling-delay = <0>;
4269
4270                         thermal-sensors = <&tsens1 9>;
4271
4272                         trips {
4273                                 video_alert0: trip-point0 {
4274                                         temperature = <90000>;
4275                                         hysteresis = <2000>;
4276                                         type = "hot";
4277                                 };
4278
4279                                 video_crit: video_crit {
4280                                         temperature = <110000>;
4281                                         hysteresis = <2000>;
4282                                         type = "critical";
4283                                 };
4284                         };
4285                 };
4286         };
4287
4288         timer {
4289                 compatible = "arm,armv8-timer";
4290                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4291                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4292                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4293                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4294         };
4295 };