arch/arm64/boot/dts/qcom/qcs404.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018, Linaro Limited
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
   6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/power/qcom-rpmpd.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         clocks {
  20                 xo_board: xo-board {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <19200000>;
  24                 };
  25
  26                 sleep_clk: sleep-clk {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <32768>;
  30                 };
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 CPU0: cpu@100 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53";
  40                         reg = <0x100>;
  41                         enable-method = "psci";
  42                         cpu-idle-states = <&CPU_SLEEP_0>;
  43                         next-level-cache = <&L2_0>;
  44                         #cooling-cells = <2>;
  45                         clocks = <&apcs_glb>;
  46                         operating-points-v2 = <&cpu_opp_table>;
  47                         power-domains = <&cpr>;
  48                         power-domain-names = "cpr";
  49                 };
  50
  51                 CPU1: cpu@101 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x101>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                         next-level-cache = <&L2_0>;
  58                         #cooling-cells = <2>;
  59                         clocks = <&apcs_glb>;
  60                         operating-points-v2 = <&cpu_opp_table>;
  61                         power-domains = <&cpr>;
  62                         power-domain-names = "cpr";
  63                 };
  64
  65                 CPU2: cpu@102 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53";
  68                         reg = <0x102>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                         next-level-cache = <&L2_0>;
  72                         #cooling-cells = <2>;
  73                         clocks = <&apcs_glb>;
  74                         operating-points-v2 = <&cpu_opp_table>;
  75                         power-domains = <&cpr>;
  76                         power-domain-names = "cpr";
  77                 };
  78
  79                 CPU3: cpu@103 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53";
  82                         reg = <0x103>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                         next-level-cache = <&L2_0>;
  86                         #cooling-cells = <2>;
  87                         clocks = <&apcs_glb>;
  88                         operating-points-v2 = <&cpu_opp_table>;
  89                         power-domains = <&cpr>;
  90                         power-domain-names = "cpr";
  91                 };
  92
  93                 L2_0: l2-cache {
  94                         compatible = "cache";
  95                         cache-level = <2>;
  96                 };
  97
  98                 idle-states {
  99                         entry-method = "psci";
 100
 101                         CPU_SLEEP_0: cpu-sleep-0 {
 102                                 compatible = "arm,idle-state";
 103                                 idle-state-name = "standalone-power-collapse";
 104                                 arm,psci-suspend-param = <0x40000003>;
 105                                 entry-latency-us = <125>;
 106                                 exit-latency-us = <180>;
 107                                 min-residency-us = <595>;
 108                                 local-timer-stop;
 109                         };
 110                 };
 111         };
 112
 113         cpu_opp_table: cpu-opp-table {
 114                 compatible = "operating-points-v2-kryo-cpu";
 115                 opp-shared;
 116
 117                 opp-1094400000 {
 118                         opp-hz = /bits/ 64 <1094400000>;
 119                         required-opps = <&cpr_opp1>;
 120                 };
 121                 opp-1248000000 {
 122                         opp-hz = /bits/ 64 <1248000000>;
 123                         required-opps = <&cpr_opp2>;
 124                 };
 125                 opp-1401600000 {
 126                         opp-hz = /bits/ 64 <1401600000>;
 127                         required-opps = <&cpr_opp3>;
 128                 };
 129         };
 130
 131         cpr_opp_table: cpr-opp-table {
 132                 compatible = "operating-points-v2-qcom-level";
 133
 134                 cpr_opp1: opp1 {
 135                         opp-level = <1>;
 136                         qcom,opp-fuse-level = <1>;
 137                 };
 138                 cpr_opp2: opp2 {
 139                         opp-level = <2>;
 140                         qcom,opp-fuse-level = <2>;
 141                 };
 142                 cpr_opp3: opp3 {
 143                         opp-level = <3>;
 144                         qcom,opp-fuse-level = <3>;
 145                 };
 146         };
 147
 148         firmware {
 149                 scm: scm {
 150                         compatible = "qcom,scm-qcs404", "qcom,scm";
 151                         #reset-cells = <1>;
 152                 };
 153         };
 154
 155         memory@80000000 {
 156                 device_type = "memory";
 157                 /* We expect the bootloader to fill in the size */
 158                 reg = <0 0x80000000 0 0>;
 159         };
 160
 161         psci {
 162                 compatible = "arm,psci-1.0";
 163                 method = "smc";
 164         };
 165
 166         reserved-memory {
 167                 #address-cells = <2>;
 168                 #size-cells = <2>;
 169                 ranges;
 170
 171                 tz_apps_mem: memory@85900000 {
 172                         reg = <0 0x85900000 0 0x500000>;
 173                         no-map;
 174                 };
 175
 176                 xbl_mem: memory@85e00000 {
 177                         reg = <0 0x85e00000 0 0x100000>;
 178                         no-map;
 179                 };
 180
 181                 smem_region: memory@85f00000 {
 182                         reg = <0 0x85f00000 0 0x200000>;
 183                         no-map;
 184                 };
 185
 186                 tz_mem: memory@86100000 {
 187                         reg = <0 0x86100000 0 0x300000>;
 188                         no-map;
 189                 };
 190
 191                 wlan_fw_mem: memory@86400000 {
 192                         reg = <0 0x86400000 0 0x1100000>;
 193                         no-map;
 194                 };
 195
 196                 adsp_fw_mem: memory@87500000 {
 197                         reg = <0 0x87500000 0 0x1a00000>;
 198                         no-map;
 199                 };
 200
 201                 cdsp_fw_mem: memory@88f00000 {
 202                         reg = <0 0x88f00000 0 0x600000>;
 203                         no-map;
 204                 };
 205
 206                 wlan_msa_mem: memory@89500000 {
 207                         reg = <0 0x89500000 0 0x100000>;
 208                         no-map;
 209                 };
 210
 211                 uefi_mem: memory@9f800000 {
 212                         reg = <0 0x9f800000 0 0x800000>;
 213                         no-map;
 214                 };
 215         };
 216
 217         rpm-glink {
 218                 compatible = "qcom,glink-rpm";
 219
 220                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 221                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 222                 mboxes = <&apcs_glb 0>;
 223
 224                 rpm_requests: glink-channel {
 225                         compatible = "qcom,rpm-qcs404";
 226                         qcom,glink-channels = "rpm_requests";
 227
 228                         rpmcc: clock-controller {
 229                                 compatible = "qcom,rpmcc-qcs404";
 230                                 #clock-cells = <1>;
 231                         };
 232
 233                         rpmpd: power-controller {
 234                                 compatible = "qcom,qcs404-rpmpd";
 235                                 #power-domain-cells = <1>;
 236                                 operating-points-v2 = <&rpmpd_opp_table>;
 237
 238                                 rpmpd_opp_table: opp-table {
 239                                         compatible = "operating-points-v2";
 240
 241                                         rpmpd_opp_ret: opp1 {
 242                                                 opp-level = <16>;
 243                                         };
 244
 245                                         rpmpd_opp_ret_plus: opp2 {
 246                                                 opp-level = <32>;
 247                                         };
 248
 249                                         rpmpd_opp_min_svs: opp3 {
 250                                                 opp-level = <48>;
 251                                         };
 252
 253                                         rpmpd_opp_low_svs: opp4 {
 254                                                 opp-level = <64>;
 255                                         };
 256
 257                                         rpmpd_opp_svs: opp5 {
 258                                                 opp-level = <128>;
 259                                         };
 260
 261                                         rpmpd_opp_svs_plus: opp6 {
 262                                                 opp-level = <192>;
 263                                         };
 264
 265                                         rpmpd_opp_nom: opp7 {
 266                                                 opp-level = <256>;
 267                                         };
 268
 269                                         rpmpd_opp_nom_plus: opp8 {
 270                                                 opp-level = <320>;
 271                                         };
 272
 273                                         rpmpd_opp_turbo: opp9 {
 274                                                 opp-level = <384>;
 275                                         };
 276
 277                                         rpmpd_opp_turbo_no_cpr: opp10 {
 278                                                 opp-level = <416>;
 279                                         };
 280
 281                                         rpmpd_opp_turbo_plus: opp11 {
 282                                                 opp-level = <512>;
 283                                         };
 284                                 };
 285                         };
 286                 };
 287         };
 288
 289         smem {
 290                 compatible = "qcom,smem";
 291
 292                 memory-region = <&smem_region>;
 293                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 294
 295                 hwlocks = <&tcsr_mutex 3>;
 296         };
 297
 298         tcsr_mutex: hwlock {
 299                 compatible = "qcom,tcsr-mutex";
 300                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 301                 #hwlock-cells = <1>;
 302         };
 303
 304         soc: soc@0 {
 305                 #address-cells = <1>;
 306                 #size-cells = <1>;
 307                 ranges = <0 0 0 0xffffffff>;
 308                 compatible = "simple-bus";
 309
 310                 turingcc: clock-controller@800000 {
 311                         compatible = "qcom,qcs404-turingcc";
 312                         reg = <0x00800000 0x30000>;
 313                         clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
 314
 315                         #clock-cells = <1>;
 316                         #reset-cells = <1>;
 317
 318                         status = "disabled";
 319                 };
 320
 321                 rpm_msg_ram: memory@60000 {
 322                         compatible = "qcom,rpm-msg-ram";
 323                         reg = <0x00060000 0x6000>;
 324                 };
 325
 326                 usb3_phy: phy@78000 {
 327                         compatible = "qcom,usb-ss-28nm-phy";
 328                         reg = <0x00078000 0x400>;
 329                         #phy-cells = <0>;
 330                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 331                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 332                                  <&gcc GCC_USB3_PHY_PIPE_CLK>;
 333                         clock-names = "ref", "ahb", "pipe";
 334                         resets = <&gcc GCC_USB3_PHY_BCR>,
 335                                  <&gcc GCC_USB3PHY_PHY_BCR>;
 336                         reset-names = "com", "phy";
 337                         status = "disabled";
 338                 };
 339
 340                 usb2_phy_prim: phy@7a000 {
 341                         compatible = "qcom,usb-hs-28nm-femtophy";
 342                         reg = <0x0007a000 0x200>;
 343                         #phy-cells = <0>;
 344                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 345                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 346                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 347                         clock-names = "ref", "ahb", "sleep";
 348                         resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
 349                                  <&gcc GCC_USB2A_PHY_BCR>;
 350                         reset-names = "phy", "por";
 351                         status = "disabled";
 352                 };
 353
 354                 usb2_phy_sec: phy@7c000 {
 355                         compatible = "qcom,usb-hs-28nm-femtophy";
 356                         reg = <0x0007c000 0x200>;
 357                         #phy-cells = <0>;
 358                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 359                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 360                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 361                         clock-names = "ref", "ahb", "sleep";
 362                         resets = <&gcc GCC_QUSB2_PHY_BCR>,
 363                                  <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
 364                         reset-names = "phy", "por";
 365                         status = "disabled";
 366                 };
 367
 368                 qfprom: qfprom@a4000 {
 369                         compatible = "qcom,qfprom";
 370                         reg = <0x000a4000 0x1000>;
 371                         #address-cells = <1>;
 372                         #size-cells = <1>;
 373                         tsens_caldata: caldata@d0 {
 374                                 reg = <0x1f8 0x14>;
 375                         };
 376                         cpr_efuse_speedbin: speedbin@13c {
 377                                 reg = <0x13c 0x4>;
 378                                 bits = <2 3>;
 379                         };
 380                         cpr_efuse_quot_offset1: qoffset1@231 {
 381                                 reg = <0x231 0x4>;
 382                                 bits = <4 7>;
 383                         };
 384                         cpr_efuse_quot_offset2: qoffset2@232 {
 385                                 reg = <0x232 0x4>;
 386                                 bits = <3 7>;
 387                         };
 388                         cpr_efuse_quot_offset3: qoffset3@233 {
 389                                 reg = <0x233 0x4>;
 390                                 bits = <2 7>;
 391                         };
 392                         cpr_efuse_init_voltage1: ivoltage1@229 {
 393                                 reg = <0x229 0x4>;
 394                                 bits = <4 6>;
 395                         };
 396                         cpr_efuse_init_voltage2: ivoltage2@22a {
 397                                 reg = <0x22a 0x4>;
 398                                 bits = <2 6>;
 399                         };
 400                         cpr_efuse_init_voltage3: ivoltage3@22b {
 401                                 reg = <0x22b 0x4>;
 402                                 bits = <0 6>;
 403                         };
 404                         cpr_efuse_quot1: quot1@22b {
 405                                 reg = <0x22b 0x4>;
 406                                 bits = <6 12>;
 407                         };
 408                         cpr_efuse_quot2: quot2@22d {
 409                                 reg = <0x22d 0x4>;
 410                                 bits = <2 12>;
 411                         };
 412                         cpr_efuse_quot3: quot3@230 {
 413                                 reg = <0x230 0x4>;
 414                                 bits = <0 12>;
 415                         };
 416                         cpr_efuse_ring1: ring1@228 {
 417                                 reg = <0x228 0x4>;
 418                                 bits = <0 3>;
 419                         };
 420                         cpr_efuse_ring2: ring2@228 {
 421                                 reg = <0x228 0x4>;
 422                                 bits = <4 3>;
 423                         };
 424                         cpr_efuse_ring3: ring3@229 {
 425                                 reg = <0x229 0x4>;
 426                                 bits = <0 3>;
 427                         };
 428                         cpr_efuse_revision: revision@218 {
 429                                 reg = <0x218 0x4>;
 430                                 bits = <3 3>;
 431                         };
 432                 };
 433
 434                 rng: rng@e3000 {
 435                         compatible = "qcom,prng-ee";
 436                         reg = <0x000e3000 0x1000>;
 437                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 438                         clock-names = "core";
 439                 };
 440
 441                 bimc: interconnect@400000 {
 442                         reg = <0x00400000 0x80000>;
 443                         compatible = "qcom,qcs404-bimc";
 444                         #interconnect-cells = <1>;
 445                         clock-names = "bus", "bus_a";
 446                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 447                                 <&rpmcc RPM_SMD_BIMC_A_CLK>;
 448                 };
 449
 450                 tsens: thermal-sensor@4a9000 {
 451                         compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
 452                         reg = <0x004a9000 0x1000>, /* TM */
 453                               <0x004a8000 0x1000>; /* SROT */
 454                         nvmem-cells = <&tsens_caldata>;
 455                         nvmem-cell-names = "calib";
 456                         #qcom,sensors = <10>;
 457                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 458                         interrupt-names = "uplow";
 459                         #thermal-sensor-cells = <1>;
 460                 };
 461
 462                 pcnoc: interconnect@500000 {
 463                         reg = <0x00500000 0x15080>;
 464                         compatible = "qcom,qcs404-pcnoc";
 465                         #interconnect-cells = <1>;
 466                         clock-names = "bus", "bus_a";
 467                         clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
 468                                 <&rpmcc RPM_SMD_PNOC_A_CLK>;
 469                 };
 470
 471                 snoc: interconnect@580000 {
 472                         reg = <0x00580000 0x23080>;
 473                         compatible = "qcom,qcs404-snoc";
 474                         #interconnect-cells = <1>;
 475                         clock-names = "bus", "bus_a";
 476                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 477                                 <&rpmcc RPM_SMD_SNOC_A_CLK>;
 478                 };
 479
 480                 remoteproc_cdsp: remoteproc@b00000 {
 481                         compatible = "qcom,qcs404-cdsp-pas";
 482                         reg = <0x00b00000 0x4040>;
 483
 484                         interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
 485                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 486                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 487                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 488                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 489                         interrupt-names = "wdog", "fatal", "ready",
 490                                           "handover", "stop-ack";
 491
 492                         clocks = <&xo_board>,
 493                                  <&gcc GCC_CDSP_CFG_AHB_CLK>,
 494                                  <&gcc GCC_CDSP_TBU_CLK>,
 495                                  <&gcc GCC_BIMC_CDSP_CLK>,
 496                                  <&turingcc TURING_WRAPPER_AON_CLK>,
 497                                  <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
 498                                  <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
 499                                  <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
 500                         clock-names = "xo",
 501                                       "sway",
 502                                       "tbu",
 503                                       "bimc",
 504                                       "ahb_aon",
 505                                       "q6ss_slave",
 506                                       "q6ss_master",
 507                                       "q6_axim";
 508
 509                         resets = <&gcc GCC_CDSP_RESTART>;
 510                         reset-names = "restart";
 511
 512                         qcom,halt-regs = <&tcsr 0x19004>;
 513
 514                         memory-region = <&cdsp_fw_mem>;
 515
 516                         qcom,smem-states = <&cdsp_smp2p_out 0>;
 517                         qcom,smem-state-names = "stop";
 518
 519                         status = "disabled";
 520
 521                         glink-edge {
 522                                 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
 523
 524                                 qcom,remote-pid = <5>;
 525                                 mboxes = <&apcs_glb 12>;
 526
 527                                 label = "cdsp";
 528                         };
 529                 };
 530
 531                 usb3: usb@7678800 {
 532                         compatible = "qcom,dwc3";
 533                         reg = <0x07678800 0x400>;
 534                         #address-cells = <1>;
 535                         #size-cells = <1>;
 536                         ranges;
 537                         clocks = <&gcc GCC_USB30_MASTER_CLK>,
 538                                  <&gcc GCC_SYS_NOC_USB3_CLK>,
 539                                  <&gcc GCC_USB30_SLEEP_CLK>,
 540                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
 541                         clock-names = "core", "iface", "sleep", "mock_utmi";
 542                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 543                                           <&gcc GCC_USB30_MASTER_CLK>;
 544                         assigned-clock-rates = <19200000>, <200000000>;
 545                         status = "disabled";
 546
 547                         dwc3@7580000 {
 548                                 compatible = "snps,dwc3";
 549                                 reg = <0x07580000 0xcd00>;
 550                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 551                                 phys = <&usb2_phy_sec>, <&usb3_phy>;
 552                                 phy-names = "usb2-phy", "usb3-phy";
 553                                 snps,has-lpm-erratum;
 554                                 snps,hird-threshold = /bits/ 8 <0x10>;
 555                                 snps,usb3_lpm_capable;
 556                                 dr_mode = "otg";
 557                         };
 558                 };
 559
 560                 usb2: usb@79b8800 {
 561                         compatible = "qcom,dwc3";
 562                         reg = <0x079b8800 0x400>;
 563                         #address-cells = <1>;
 564                         #size-cells = <1>;
 565                         ranges;
 566                         clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
 567                                  <&gcc GCC_PCNOC_USB2_CLK>,
 568                                  <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
 569                                  <&gcc GCC_USB20_MOCK_UTMI_CLK>;
 570                         clock-names = "core", "iface", "sleep", "mock_utmi";
 571                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 572                                           <&gcc GCC_USB_HS_SYSTEM_CLK>;
 573                         assigned-clock-rates = <19200000>, <133333333>;
 574                         status = "disabled";
 575
 576                         dwc3@78c0000 {
 577                                 compatible = "snps,dwc3";
 578                                 reg = <0x078c0000 0xcc00>;
 579                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 580                                 phys = <&usb2_phy_prim>;
 581                                 phy-names = "usb2-phy";
 582                                 snps,has-lpm-erratum;
 583                                 snps,hird-threshold = /bits/ 8 <0x10>;
 584                                 snps,usb3_lpm_capable;
 585                                 dr_mode = "peripheral";
 586                         };
 587                 };
 588
 589                 tlmm: pinctrl@1000000 {
 590                         compatible = "qcom,qcs404-pinctrl";
 591                         reg = <0x01000000 0x200000>,
 592                               <0x01300000 0x200000>,
 593                               <0x07b00000 0x200000>;
 594                         reg-names = "south", "north", "east";
 595                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 596                         gpio-ranges = <&tlmm 0 0 120>;
 597                         gpio-controller;
 598                         #gpio-cells = <2>;
 599                         interrupt-controller;
 600                         #interrupt-cells = <2>;
 601
 602                         blsp1_i2c0_default: blsp1-i2c0-default {
 603                                 pins = "gpio32", "gpio33";
 604                                 function = "blsp_i2c0";
 605                         };
 606
 607                         blsp1_i2c1_default: blsp1-i2c1-default {
 608                                 pins = "gpio24", "gpio25";
 609                                 function = "blsp_i2c1";
 610                         };
 611
 612                         blsp1_i2c2_default: blsp1-i2c2-default {
 613                                 sda {
 614                                         pins = "gpio19";
 615                                         function = "blsp_i2c_sda_a2";
 616                                 };
 617
 618                                 scl {
 619                                         pins = "gpio20";
 620                                         function = "blsp_i2c_scl_a2";
 621                                 };
 622                         };
 623
 624                         blsp1_i2c3_default: blsp1-i2c3-default {
 625                                 pins = "gpio84", "gpio85";
 626                                 function = "blsp_i2c3";
 627                         };
 628
 629                         blsp1_i2c4_default: blsp1-i2c4-default {
 630                                 pins = "gpio117", "gpio118";
 631                                 function = "blsp_i2c4";
 632                         };
 633
 634                         blsp1_uart0_default: blsp1-uart0-default {
 635                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 636                                 function = "blsp_uart0";
 637                         };
 638
 639                         blsp1_uart1_default: blsp1-uart1-default {
 640                                 pins = "gpio22", "gpio23";
 641                                 function = "blsp_uart1";
 642                         };
 643
 644                         blsp1_uart2_default: blsp1-uart2-default {
 645                                 rx {
 646                                         pins = "gpio18";
 647                                         function = "blsp_uart_rx_a2";
 648                                 };
 649
 650                                 tx {
 651                                         pins = "gpio17";
 652                                         function = "blsp_uart_tx_a2";
 653                                 };
 654                         };
 655
 656                         blsp1_uart3_default: blsp1-uart3-default {
 657                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 658                                 function = "blsp_uart3";
 659                         };
 660
 661                         blsp2_i2c0_default: blsp2-i2c0-default {
 662                                 pins = "gpio28", "gpio29";
 663                                 function = "blsp_i2c5";
 664                         };
 665
 666                         blsp1_spi0_default: blsp1-spi0-default {
 667                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 668                                 function = "blsp_spi0";
 669                         };
 670
 671                         blsp1_spi1_default: blsp1-spi1-default {
 672                                 pins = "gpio22", "gpio23", "gpio24", "gpio25";
 673                                 function = "blsp_spi1";
 674                         };
 675
 676                         blsp1_spi2_default: blsp1-spi2-default {
 677                                 pins = "gpio17", "gpio18", "gpio19", "gpio20";
 678                                 function = "blsp_spi2";
 679                         };
 680
 681                         blsp1_spi3_default: blsp1-spi3-default {
 682                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 683                                 function = "blsp_spi3";
 684                         };
 685
 686                         blsp1_spi4_default: blsp1-spi4-default {
 687                                 pins = "gpio37", "gpio38", "gpio117", "gpio118";
 688                                 function = "blsp_spi4";
 689                         };
 690
 691                         blsp2_spi0_default: blsp2-spi0-default {
 692                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 693                                 function = "blsp_spi5";
 694                         };
 695
 696                         blsp2_uart0_default: blsp2-uart0-default {
 697                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 698                                 function = "blsp_uart5";
 699                         };
 700                 };
 701
 702                 gcc: clock-controller@1800000 {
 703                         compatible = "qcom,gcc-qcs404";
 704                         reg = <0x01800000 0x80000>;
 705                         #clock-cells = <1>;
 706                         #reset-cells = <1>;
 707
 708                         assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
 709                         assigned-clock-rates = <19200000>;
 710                 };
 711
 712                 tcsr_mutex_regs: syscon@1905000 {
 713                         compatible = "syscon";
 714                         reg = <0x01905000 0x20000>;
 715                 };
 716
 717                 tcsr: syscon@1937000 {
 718                         compatible = "syscon";
 719                         reg = <0x01937000 0x25000>;
 720                 };
 721
 722                 spmi_bus: spmi@200f000 {
 723                         compatible = "qcom,spmi-pmic-arb";
 724                         reg = <0x0200f000 0x001000>,
 725                               <0x02400000 0x800000>,
 726                               <0x02c00000 0x800000>,
 727                               <0x03800000 0x200000>,
 728                               <0x0200a000 0x002100>;
 729                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 730                         interrupt-names = "periph_irq";
 731                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 732                         qcom,ee = <0>;
 733                         qcom,channel = <0>;
 734                         #address-cells = <2>;
 735                         #size-cells = <0>;
 736                         interrupt-controller;
 737                         #interrupt-cells = <4>;
 738                 };
 739
 740                 remoteproc_wcss: remoteproc@7400000 {
 741                         compatible = "qcom,qcs404-wcss-pas";
 742                         reg = <0x07400000 0x4040>;
 743
 744                         interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
 745                                               <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 746                                               <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 747                                               <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 748                                               <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 749                         interrupt-names = "wdog", "fatal", "ready",
 750                                           "handover", "stop-ack";
 751
 752                         clocks = <&xo_board>;
 753                         clock-names = "xo";
 754
 755                         memory-region = <&wlan_fw_mem>;
 756
 757                         qcom,smem-states = <&wcss_smp2p_out 0>;
 758                         qcom,smem-state-names = "stop";
 759
 760                         status = "disabled";
 761
 762                         glink-edge {
 763                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 764
 765                                 qcom,remote-pid = <1>;
 766                                 mboxes = <&apcs_glb 16>;
 767
 768                                 label = "wcss";
 769                         };
 770                 };
 771
 772                 pcie_phy: phy@7786000 {
 773                         compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
 774                         reg = <0x07786000 0xb8>;
 775
 776                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 777                         resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
 778                                  <&gcc 21>;
 779                         reset-names = "phy", "pipe";
 780
 781                         clock-output-names = "pcie_0_pipe_clk";
 782                         #phy-cells = <0>;
 783
 784                         status = "disabled";
 785                 };
 786
 787                 sdcc1: sdcc@7804000 {
 788                         compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
 789                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
 790                         reg-names = "hc", "cqhci";
 791
 792                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 793                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 794                         interrupt-names = "hc_irq", "pwr_irq";
 795
 796                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 797                                  <&gcc GCC_SDCC1_AHB_CLK>,
 798                                  <&xo_board>;
 799                         clock-names = "core", "iface", "xo";
 800
 801                         status = "disabled";
 802                 };
 803
 804                 blsp1_dma: dma-controller@7884000 {
 805                         compatible = "qcom,bam-v1.7.0";
 806                         reg = <0x07884000 0x25000>;
 807                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 808                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 809                         clock-names = "bam_clk";
 810                         #dma-cells = <1>;
 811                         qcom,ee = <0>;
 812                         status = "okay";
 813                 };
 814
 815                 blsp1_uart0: serial@78af000 {
 816                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 817                         reg = <0x078af000 0x200>;
 818                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 819                         clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 820                         clock-names = "core", "iface";
 821                         dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
 822                         dma-names = "rx", "tx";
 823                         pinctrl-names = "default";
 824                         pinctrl-0 = <&blsp1_uart0_default>;
 825                         status = "disabled";
 826                 };
 827
 828                 blsp1_uart1: serial@78b0000 {
 829                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 830                         reg = <0x078b0000 0x200>;
 831                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 832                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 833                         clock-names = "core", "iface";
 834                         dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
 835                         dma-names = "rx", "tx";
 836                         pinctrl-names = "default";
 837                         pinctrl-0 = <&blsp1_uart1_default>;
 838                         status = "disabled";
 839                 };
 840
 841                 blsp1_uart2: serial@78b1000 {
 842                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 843                         reg = <0x078b1000 0x200>;
 844                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 845                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 846                         clock-names = "core", "iface";
 847                         dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
 848                         dma-names = "rx", "tx";
 849                         pinctrl-names = "default";
 850                         pinctrl-0 = <&blsp1_uart2_default>;
 851                         status = "okay";
 852                 };
 853
 854                 ethernet: ethernet@7a80000 {
 855                         compatible = "qcom,qcs404-ethqos";
 856                         reg = <0x07a80000 0x10000>,
 857                                 <0x07a96000 0x100>;
 858                         reg-names = "stmmaceth", "rgmii";
 859                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
 860                         clocks = <&gcc GCC_ETH_AXI_CLK>,
 861                                 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
 862                                 <&gcc GCC_ETH_PTP_CLK>,
 863                                 <&gcc GCC_ETH_RGMII_CLK>;
 864                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 865                                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 866                         interrupt-names = "macirq", "eth_lpi";
 867
 868                         snps,tso;
 869                         rx-fifo-depth = <4096>;
 870                         tx-fifo-depth = <4096>;
 871
 872                         status = "disabled";
 873                 };
 874
 875                 wifi: wifi@a000000 {
 876                         compatible = "qcom,wcn3990-wifi";
 877                         reg = <0xa000000 0x800000>;
 878                         reg-names = "membase";
 879                         memory-region = <&wlan_msa_mem>;
 880                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 881                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 882                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 883                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 884                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 885                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 886                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 887                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 888                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
 889                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 890                                      <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
 891                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 892                         status = "disabled";
 893                 };
 894
 895                 blsp1_uart3: serial@78b2000 {
 896                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 897                         reg = <0x078b2000 0x200>;
 898                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 899                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 900                         clock-names = "core", "iface";
 901                         dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
 902                         dma-names = "rx", "tx";
 903                         pinctrl-names = "default";
 904                         pinctrl-0 = <&blsp1_uart3_default>;
 905                         status = "disabled";
 906                 };
 907
 908                 blsp1_i2c0: i2c@78b5000 {
 909                         compatible = "qcom,i2c-qup-v2.2.1";
 910                         reg = <0x078b5000 0x600>;
 911                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 912                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 913                                  <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
 914                         clock-names = "iface", "core";
 915                         pinctrl-names = "default";
 916                         pinctrl-0 = <&blsp1_i2c0_default>;
 917                         #address-cells = <1>;
 918                         #size-cells = <0>;
 919                         status = "disabled";
 920                 };
 921
 922                 blsp1_spi0: spi@78b5000 {
 923                         compatible = "qcom,spi-qup-v2.2.1";
 924                         reg = <0x078b5000 0x600>;
 925                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 926                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 927                                  <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
 928                         clock-names = "iface", "core";
 929                         pinctrl-names = "default";
 930                         pinctrl-0 = <&blsp1_spi0_default>;
 931                         #address-cells = <1>;
 932                         #size-cells = <0>;
 933                         status = "disabled";
 934                 };
 935
 936                 blsp1_i2c1: i2c@78b6000 {
 937                         compatible = "qcom,i2c-qup-v2.2.1";
 938                         reg = <0x078b6000 0x600>;
 939                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 940                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 941                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 942                         clock-names = "iface", "core";
 943                         pinctrl-names = "default";
 944                         pinctrl-0 = <&blsp1_i2c1_default>;
 945                         #address-cells = <1>;
 946                         #size-cells = <0>;
 947                         status = "disabled";
 948                 };
 949
 950                 blsp1_spi1: spi@78b6000 {
 951                         compatible = "qcom,spi-qup-v2.2.1";
 952                         reg = <0x078b6000 0x600>;
 953                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 954                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 955                                  <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
 956                         clock-names = "iface", "core";
 957                         pinctrl-names = "default";
 958                         pinctrl-0 = <&blsp1_spi1_default>;
 959                         #address-cells = <1>;
 960                         #size-cells = <0>;
 961                         status = "disabled";
 962                 };
 963
 964                 blsp1_i2c2: i2c@78b7000 {
 965                         compatible = "qcom,i2c-qup-v2.2.1";
 966                         reg = <0x078b7000 0x600>;
 967                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 968                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 969                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 970                         clock-names = "iface", "core";
 971                         pinctrl-names = "default";
 972                         pinctrl-0 = <&blsp1_i2c2_default>;
 973                         #address-cells = <1>;
 974                         #size-cells = <0>;
 975                         status = "disabled";
 976                 };
 977
 978                 blsp1_spi2: spi@78b7000 {
 979                         compatible = "qcom,spi-qup-v2.2.1";
 980                         reg = <0x078b7000 0x600>;
 981                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 982                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 983                                  <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
 984                         clock-names = "iface", "core";
 985                         pinctrl-names = "default";
 986                         pinctrl-0 = <&blsp1_spi2_default>;
 987                         #address-cells = <1>;
 988                         #size-cells = <0>;
 989                         status = "disabled";
 990                 };
 991
 992                 blsp1_i2c3: i2c@78b8000 {
 993                         compatible = "qcom,i2c-qup-v2.2.1";
 994                         reg = <0x078b8000 0x600>;
 995                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 996                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 997                                  <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 998                         clock-names = "iface", "core";
 999                         pinctrl-names = "default";
1000                         pinctrl-0 = <&blsp1_i2c3_default>;
1001                         #address-cells = <1>;
1002                         #size-cells = <0>;
1003                         status = "disabled";
1004                 };
1005
1006                 blsp1_spi3: spi@78b8000 {
1007                         compatible = "qcom,spi-qup-v2.2.1";
1008                         reg = <0x078b8000 0x600>;
1009                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1010                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1011                                  <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
1012                         clock-names = "iface", "core";
1013                         pinctrl-names = "default";
1014                         pinctrl-0 = <&blsp1_spi3_default>;
1015                         #address-cells = <1>;
1016                         #size-cells = <0>;
1017                         status = "disabled";
1018                 };
1019
1020                 blsp1_i2c4: i2c@78b9000 {
1021                         compatible = "qcom,i2c-qup-v2.2.1";
1022                         reg = <0x078b9000 0x600>;
1023                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1024                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1025                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1026                         clock-names = "iface", "core";
1027                         pinctrl-names = "default";
1028                         pinctrl-0 = <&blsp1_i2c4_default>;
1029                         #address-cells = <1>;
1030                         #size-cells = <0>;
1031                         status = "disabled";
1032                 };
1033
1034                 blsp1_spi4: spi@78b9000 {
1035                         compatible = "qcom,spi-qup-v2.2.1";
1036                         reg = <0x078b9000 0x600>;
1037                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1038                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1039                                  <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
1040                         clock-names = "iface", "core";
1041                         pinctrl-names = "default";
1042                         pinctrl-0 = <&blsp1_spi4_default>;
1043                         #address-cells = <1>;
1044                         #size-cells = <0>;
1045                         status = "disabled";
1046                 };
1047
1048                 blsp2_dma: dma-controller@7ac4000 {
1049                         compatible = "qcom,bam-v1.7.0";
1050                         reg = <0x07ac4000 0x17000>;
1051                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1052                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1053                         clock-names = "bam_clk";
1054                         #dma-cells = <1>;
1055                         qcom,ee = <0>;
1056                         status = "disabled";
1057                 };
1058
1059                 blsp2_uart0: serial@7aef000 {
1060                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1061                         reg = <0x07aef000 0x200>;
1062                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1063                         clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1064                         clock-names = "core", "iface";
1065                         dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
1066                         dma-names = "rx", "tx";
1067                         pinctrl-names = "default";
1068                         pinctrl-0 = <&blsp2_uart0_default>;
1069                         status = "disabled";
1070                 };
1071
1072                 blsp2_i2c0: i2c@7af5000 {
1073                         compatible = "qcom,i2c-qup-v2.2.1";
1074                         reg = <0x07af5000 0x600>;
1075                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1076                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1077                                  <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
1078                         clock-names = "iface", "core";
1079                         pinctrl-names = "default";
1080                         pinctrl-0 = <&blsp2_i2c0_default>;
1081                         #address-cells = <1>;
1082                         #size-cells = <0>;
1083                         status = "disabled";
1084                 };
1085
1086                 blsp2_spi0: spi@7af5000 {
1087                         compatible = "qcom,spi-qup-v2.2.1";
1088                         reg = <0x07af5000 0x600>;
1089                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1090                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1091                                  <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
1092                         clock-names = "iface", "core";
1093                         pinctrl-names = "default";
1094                         pinctrl-0 = <&blsp2_spi0_default>;
1095                         #address-cells = <1>;
1096                         #size-cells = <0>;
1097                         status = "disabled";
1098                 };
1099
1100                 imem@8600000 {
1101                         compatible = "simple-mfd";
1102                         reg = <0x08600000 0x1000>;
1103
1104                         #address-cells = <1>;
1105                         #size-cells = <1>;
1106
1107                         ranges = <0 0x08600000 0x1000>;
1108
1109                         pil-reloc@94c {
1110                                 compatible = "qcom,pil-reloc-info";
1111                                 reg = <0x94c 0xc8>;
1112                         };
1113                 };
1114
1115                 intc: interrupt-controller@b000000 {
1116                         compatible = "qcom,msm-qgic2";
1117                         interrupt-controller;
1118                         #interrupt-cells = <3>;
1119                         reg = <0x0b000000 0x1000>,
1120                               <0x0b002000 0x1000>;
1121                 };
1122
1123                 apcs_glb: mailbox@b011000 {
1124                         compatible = "qcom,qcs404-apcs-apps-global", "syscon";
1125                         reg = <0x0b011000 0x1000>;
1126                         #mbox-cells = <1>;
1127                         clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1128                         clock-names = "pll", "aux";
1129                         #clock-cells = <0>;
1130                 };
1131
1132                 apcs_hfpll: clock-controller@b016000 {
1133                         compatible = "qcom,hfpll";
1134                         reg = <0x0b016000 0x30>;
1135                         #clock-cells = <0>;
1136                         clock-output-names = "apcs_hfpll";
1137                         clocks = <&xo_board>;
1138                         clock-names = "xo";
1139                 };
1140
1141                 watchdog@b017000 {
1142                         compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1143                         reg = <0x0b017000 0x1000>;
1144                         clocks = <&sleep_clk>;
1145                 };
1146
1147                 cpr: power-controller@b018000 {
1148                         compatible = "qcom,qcs404-cpr", "qcom,cpr";
1149                         reg = <0x0b018000 0x1000>;
1150                         interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1151                         clocks = <&xo_board>;
1152                         clock-names = "ref";
1153                         vdd-apc-supply = <&pms405_s3>;
1154                         #power-domain-cells = <0>;
1155                         operating-points-v2 = <&cpr_opp_table>;
1156                         acc-syscon = <&tcsr>;
1157
1158                         nvmem-cells = <&cpr_efuse_quot_offset1>,
1159                                 <&cpr_efuse_quot_offset2>,
1160                                 <&cpr_efuse_quot_offset3>,
1161                                 <&cpr_efuse_init_voltage1>,
1162                                 <&cpr_efuse_init_voltage2>,
1163                                 <&cpr_efuse_init_voltage3>,
1164                                 <&cpr_efuse_quot1>,
1165                                 <&cpr_efuse_quot2>,
1166                                 <&cpr_efuse_quot3>,
1167                                 <&cpr_efuse_ring1>,
1168                                 <&cpr_efuse_ring2>,
1169                                 <&cpr_efuse_ring3>,
1170                                 <&cpr_efuse_revision>;
1171                         nvmem-cell-names = "cpr_quotient_offset1",
1172                                 "cpr_quotient_offset2",
1173                                 "cpr_quotient_offset3",
1174                                 "cpr_init_voltage1",
1175                                 "cpr_init_voltage2",
1176                                 "cpr_init_voltage3",
1177                                 "cpr_quotient1",
1178                                 "cpr_quotient2",
1179                                 "cpr_quotient3",
1180                                 "cpr_ring_osc1",
1181                                 "cpr_ring_osc2",
1182                                 "cpr_ring_osc3",
1183                                 "cpr_fuse_revision";
1184                 };
1185
1186                 timer@b120000 {
1187                         #address-cells = <1>;
1188                         #size-cells = <1>;
1189                         ranges;
1190                         compatible = "arm,armv7-timer-mem";
1191                         reg = <0x0b120000 0x1000>;
1192                         clock-frequency = <19200000>;
1193
1194                         frame@b121000 {
1195                                 frame-number = <0>;
1196                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1197                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1198                                 reg = <0x0b121000 0x1000>,
1199                                       <0x0b122000 0x1000>;
1200                         };
1201
1202                         frame@b123000 {
1203                                 frame-number = <1>;
1204                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1205                                 reg = <0x0b123000 0x1000>;
1206                                 status = "disabled";
1207                         };
1208
1209                         frame@b124000 {
1210                                 frame-number = <2>;
1211                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1212                                 reg = <0x0b124000 0x1000>;
1213                                 status = "disabled";
1214                         };
1215
1216                         frame@b125000 {
1217                                 frame-number = <3>;
1218                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1219                                 reg = <0x0b125000 0x1000>;
1220                                 status = "disabled";
1221                         };
1222
1223                         frame@b126000 {
1224                                 frame-number = <4>;
1225                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1226                                 reg = <0x0b126000 0x1000>;
1227                                 status = "disabled";
1228                         };
1229
1230                         frame@b127000 {
1231                                 frame-number = <5>;
1232                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1233                                 reg = <0xb127000 0x1000>;
1234                                 status = "disabled";
1235                         };
1236
1237                         frame@b128000 {
1238                                 frame-number = <6>;
1239                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1240                                 reg = <0x0b128000 0x1000>;
1241                                 status = "disabled";
1242                         };
1243                 };
1244
1245                 remoteproc_adsp: remoteproc@c700000 {
1246                         compatible = "qcom,qcs404-adsp-pas";
1247                         reg = <0x0c700000 0x4040>;
1248
1249                         interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1250                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1251                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1252                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1253                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1254                         interrupt-names = "wdog", "fatal", "ready",
1255                                           "handover", "stop-ack";
1256
1257                         clocks = <&xo_board>;
1258                         clock-names = "xo";
1259
1260                         memory-region = <&adsp_fw_mem>;
1261
1262                         qcom,smem-states = <&adsp_smp2p_out 0>;
1263                         qcom,smem-state-names = "stop";
1264
1265                         status = "disabled";
1266
1267                         glink-edge {
1268                                 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
1269
1270                                 qcom,remote-pid = <2>;
1271                                 mboxes = <&apcs_glb 8>;
1272
1273                                 label = "adsp";
1274                         };
1275                 };
1276
1277                 pcie: pci@10000000 {
1278                         compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
1279                         reg =  <0x10000000 0xf1d>,
1280                                <0x10000f20 0xa8>,
1281                                <0x07780000 0x2000>,
1282                                <0x10001000 0x2000>;
1283                         reg-names = "dbi", "elbi", "parf", "config";
1284                         device_type = "pci";
1285                         linux,pci-domain = <0>;
1286                         bus-range = <0x00 0xff>;
1287                         num-lanes = <1>;
1288                         #address-cells = <3>;
1289                         #size-cells = <2>;
1290
1291                         ranges = <0x81000000 0 0          0x10003000 0 0x00010000>, /* I/O */
1292                                  <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
1293
1294                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1295                         interrupt-names = "msi";
1296                         #interrupt-cells = <1>;
1297                         interrupt-map-mask = <0 0 0 0x7>;
1298                         interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1299                                         <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1300                                         <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1301                                         <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1302                         clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1303                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1304                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1305                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1306                         clock-names = "iface", "aux", "master_bus", "slave_bus";
1307
1308                         resets = <&gcc 18>,
1309                                  <&gcc 17>,
1310                                  <&gcc 15>,
1311                                  <&gcc 19>,
1312                                  <&gcc GCC_PCIE_0_BCR>,
1313                                  <&gcc 16>;
1314                         reset-names = "axi_m",
1315                                       "axi_s",
1316                                       "axi_m_sticky",
1317                                       "pipe_sticky",
1318                                       "pwr",
1319                                       "ahb";
1320
1321                         phys = <&pcie_phy>;
1322                         phy-names = "pciephy";
1323
1324                         status = "disabled";
1325                 };
1326         };
1327
1328         timer {
1329                 compatible = "arm,armv8-timer";
1330                 interrupts = <GIC_PPI 2 0xff08>,
1331                              <GIC_PPI 3 0xff08>,
1332                              <GIC_PPI 4 0xff08>,
1333                              <GIC_PPI 1 0xff08>;
1334         };
1335
1336         smp2p-adsp {
1337                 compatible = "qcom,smp2p";
1338                 qcom,smem = <443>, <429>;
1339                 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
1340                 mboxes = <&apcs_glb 10>;
1341                 qcom,local-pid = <0>;
1342                 qcom,remote-pid = <2>;
1343
1344                 adsp_smp2p_out: master-kernel {
1345                         qcom,entry-name = "master-kernel";
1346                         #qcom,smem-state-cells = <1>;
1347                 };
1348
1349                 adsp_smp2p_in: slave-kernel {
1350                         qcom,entry-name = "slave-kernel";
1351                         interrupt-controller;
1352                         #interrupt-cells = <2>;
1353                 };
1354         };
1355
1356         smp2p-cdsp {
1357                 compatible = "qcom,smp2p";
1358                 qcom,smem = <94>, <432>;
1359                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
1360                 mboxes = <&apcs_glb 14>;
1361                 qcom,local-pid = <0>;
1362                 qcom,remote-pid = <5>;
1363
1364                 cdsp_smp2p_out: master-kernel {
1365                         qcom,entry-name = "master-kernel";
1366                         #qcom,smem-state-cells = <1>;
1367                 };
1368
1369                 cdsp_smp2p_in: slave-kernel {
1370                         qcom,entry-name = "slave-kernel";
1371                         interrupt-controller;
1372                         #interrupt-cells = <2>;
1373                 };
1374         };
1375
1376         smp2p-wcss {
1377                 compatible = "qcom,smp2p";
1378                 qcom,smem = <435>, <428>;
1379                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1380                 mboxes = <&apcs_glb 18>;
1381                 qcom,local-pid = <0>;
1382                 qcom,remote-pid = <1>;
1383
1384                 wcss_smp2p_out: master-kernel {
1385                         qcom,entry-name = "master-kernel";
1386                         #qcom,smem-state-cells = <1>;
1387                 };
1388
1389                 wcss_smp2p_in: slave-kernel {
1390                         qcom,entry-name = "slave-kernel";
1391                         interrupt-controller;
1392                         #interrupt-cells = <2>;
1393                 };
1394         };
1395
1396         thermal-zones {
1397                 aoss-thermal {
1398                         polling-delay-passive = <250>;
1399                         polling-delay = <1000>;
1400
1401                         thermal-sensors = <&tsens 0>;
1402
1403                         trips {
1404                                 aoss_alert0: trip-point0 {
1405                                         temperature = <105000>;
1406                                         hysteresis = <2000>;
1407                                         type = "hot";
1408                                 };
1409                         };
1410                 };
1411
1412                 q6-hvx-thermal {
1413                         polling-delay-passive = <250>;
1414                         polling-delay = <1000>;
1415
1416                         thermal-sensors = <&tsens 1>;
1417
1418                         trips {
1419                                 q6_hvx_alert0: trip-point0 {
1420                                         temperature = <105000>;
1421                                         hysteresis = <2000>;
1422                                         type = "hot";
1423                                 };
1424                         };
1425                 };
1426
1427                 lpass-thermal {
1428                         polling-delay-passive = <250>;
1429                         polling-delay = <1000>;
1430
1431                         thermal-sensors = <&tsens 2>;
1432
1433                         trips {
1434                                 lpass_alert0: trip-point0 {
1435                                         temperature = <105000>;
1436                                         hysteresis = <2000>;
1437                                         type = "hot";
1438                                 };
1439                         };
1440                 };
1441
1442                 wlan-thermal {
1443                         polling-delay-passive = <250>;
1444                         polling-delay = <1000>;
1445
1446                         thermal-sensors = <&tsens 3>;
1447
1448                         trips {
1449                                 wlan_alert0: trip-point0 {
1450                                         temperature = <105000>;
1451                                         hysteresis = <2000>;
1452                                         type = "hot";
1453                                 };
1454                         };
1455                 };
1456
1457                 cluster-thermal {
1458                         polling-delay-passive = <250>;
1459                         polling-delay = <1000>;
1460
1461                         thermal-sensors = <&tsens 4>;
1462
1463                         trips {
1464                                 cluster_alert0: trip-point0 {
1465                                         temperature = <95000>;
1466                                         hysteresis = <2000>;
1467                                         type = "hot";
1468                                 };
1469                                 cluster_alert1: trip-point1 {
1470                                         temperature = <105000>;
1471                                         hysteresis = <2000>;
1472                                         type = "passive";
1473                                 };
1474                                 cluster_crit: cluster_crit {
1475                                         temperature = <120000>;
1476                                         hysteresis = <2000>;
1477                                         type = "critical";
1478                                 };
1479                         };
1480                         cooling-maps {
1481                                 map0 {
1482                                         trip = <&cluster_alert1>;
1483                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1484                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1485                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1486                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1487                                 };
1488                         };
1489                 };
1490
1491                 cpu0-thermal {
1492                         polling-delay-passive = <250>;
1493                         polling-delay = <1000>;
1494
1495                         thermal-sensors = <&tsens 5>;
1496
1497                         trips {
1498                                 cpu0_alert0: trip-point0 {
1499                                         temperature = <95000>;
1500                                         hysteresis = <2000>;
1501                                         type = "hot";
1502                                 };
1503                                 cpu0_alert1: trip-point1 {
1504                                         temperature = <105000>;
1505                                         hysteresis = <2000>;
1506                                         type = "passive";
1507                                 };
1508                                 cpu0_crit: cpu_crit {
1509                                         temperature = <120000>;
1510                                         hysteresis = <2000>;
1511                                         type = "critical";
1512                                 };
1513                         };
1514                         cooling-maps {
1515                                 map0 {
1516                                         trip = <&cpu0_alert1>;
1517                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1518                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1519                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1520                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1521                                 };
1522                         };
1523                 };
1524
1525                 cpu1-thermal {
1526                         polling-delay-passive = <250>;
1527                         polling-delay = <1000>;
1528
1529                         thermal-sensors = <&tsens 6>;
1530
1531                         trips {
1532                                 cpu1_alert0: trip-point0 {
1533                                         temperature = <95000>;
1534                                         hysteresis = <2000>;
1535                                         type = "hot";
1536                                 };
1537                                 cpu1_alert1: trip-point1 {
1538                                         temperature = <105000>;
1539                                         hysteresis = <2000>;
1540                                         type = "passive";
1541                                 };
1542                                 cpu1_crit: cpu_crit {
1543                                         temperature = <120000>;
1544                                         hysteresis = <2000>;
1545                                         type = "critical";
1546                                 };
1547                         };
1548                         cooling-maps {
1549                                 map0 {
1550                                         trip = <&cpu1_alert1>;
1551                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1552                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1553                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1554                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1555                                 };
1556                         };
1557                 };
1558
1559                 cpu2-thermal {
1560                         polling-delay-passive = <250>;
1561                         polling-delay = <1000>;
1562
1563                         thermal-sensors = <&tsens 7>;
1564
1565                         trips {
1566                                 cpu2_alert0: trip-point0 {
1567                                         temperature = <95000>;
1568                                         hysteresis = <2000>;
1569                                         type = "hot";
1570                                 };
1571                                 cpu2_alert1: trip-point1 {
1572                                         temperature = <105000>;
1573                                         hysteresis = <2000>;
1574                                         type = "passive";
1575                                 };
1576                                 cpu2_crit: cpu_crit {
1577                                         temperature = <120000>;
1578                                         hysteresis = <2000>;
1579                                         type = "critical";
1580                                 };
1581                         };
1582                         cooling-maps {
1583                                 map0 {
1584                                         trip = <&cpu2_alert1>;
1585                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1586                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1587                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1588                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1589                                 };
1590                         };
1591                 };
1592
1593                 cpu3-thermal {
1594                         polling-delay-passive = <250>;
1595                         polling-delay = <1000>;
1596
1597                         thermal-sensors = <&tsens 8>;
1598
1599                         trips {
1600                                 cpu3_alert0: trip-point0 {
1601                                         temperature = <95000>;
1602                                         hysteresis = <2000>;
1603                                         type = "hot";
1604                                 };
1605                                 cpu3_alert1: trip-point1 {
1606                                         temperature = <105000>;
1607                                         hysteresis = <2000>;
1608                                         type = "passive";
1609                                 };
1610                                 cpu3_crit: cpu_crit {
1611                                         temperature = <120000>;
1612                                         hysteresis = <2000>;
1613                                         type = "critical";
1614                                 };
1615                         };
1616                         cooling-maps {
1617                                 map0 {
1618                                         trip = <&cpu3_alert1>;
1619                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1620                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1621                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1622                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1623                                 };
1624                         };
1625                 };
1626
1627                 gpu-thermal {
1628                         polling-delay-passive = <250>;
1629                         polling-delay = <1000>;
1630
1631                         thermal-sensors = <&tsens 9>;
1632
1633                         trips {
1634                                 gpu_alert0: trip-point0 {
1635                                         temperature = <95000>;
1636                                         hysteresis = <2000>;
1637                                         type = "hot";
1638                                 };
1639                         };
1640                 };
1641         };
1642 };