arch/arm64/boot/dts/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/power/qcom-rpmpd.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         qcom,msm-id = <292 0x0>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         chosen { };
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 /* We expect the bootloader to fill in the reg */
  24                 reg = <0x0 0x80000000 0x0 0x0>;
  25         };
  26
  27         reserved-memory {
  28                 #address-cells = <2>;
  29                 #size-cells = <2>;
  30                 ranges;
  31
  32                 hyp_mem: memory@85800000 {
  33                         reg = <0x0 0x85800000 0x0 0x600000>;
  34                         no-map;
  35                 };
  36
  37                 xbl_mem: memory@85e00000 {
  38                         reg = <0x0 0x85e00000 0x0 0x100000>;
  39                         no-map;
  40                 };
  41
  42                 smem_mem: smem-mem@86000000 {
  43                         reg = <0x0 0x86000000 0x0 0x200000>;
  44                         no-map;
  45                 };
  46
  47                 tz_mem: memory@86200000 {
  48                         reg = <0x0 0x86200000 0x0 0x2d00000>;
  49                         no-map;
  50                 };
  51
  52                 rmtfs_mem: memory@88f00000 {
  53                         compatible = "qcom,rmtfs-mem";
  54                         reg = <0x0 0x88f00000 0x0 0x200000>;
  55                         no-map;
  56
  57                         qcom,client-id = <1>;
  58                         qcom,vmid = <15>;
  59                 };
  60
  61                 spss_mem: memory@8ab00000 {
  62                         reg = <0x0 0x8ab00000 0x0 0x700000>;
  63                         no-map;
  64                 };
  65
  66                 adsp_mem: memory@8b200000 {
  67                         reg = <0x0 0x8b200000 0x0 0x1a00000>;
  68                         no-map;
  69                 };
  70
  71                 mpss_mem: memory@8cc00000 {
  72                         reg = <0x0 0x8cc00000 0x0 0x7000000>;
  73                         no-map;
  74                 };
  75
  76                 venus_mem: memory@93c00000 {
  77                         reg = <0x0 0x93c00000 0x0 0x500000>;
  78                         no-map;
  79                 };
  80
  81                 mba_mem: memory@94100000 {
  82                         reg = <0x0 0x94100000 0x0 0x200000>;
  83                         no-map;
  84                 };
  85
  86                 slpi_mem: memory@94300000 {
  87                         reg = <0x0 0x94300000 0x0 0xf00000>;
  88                         no-map;
  89                 };
  90
  91                 ipa_fw_mem: memory@95200000 {
  92                         reg = <0x0 0x95200000 0x0 0x10000>;
  93                         no-map;
  94                 };
  95
  96                 ipa_gsi_mem: memory@95210000 {
  97                         reg = <0x0 0x95210000 0x0 0x5000>;
  98                         no-map;
  99                 };
 100
 101                 gpu_mem: memory@95600000 {
 102                         reg = <0x0 0x95600000 0x0 0x100000>;
 103                         no-map;
 104                 };
 105
 106                 wlan_msa_mem: memory@95700000 {
 107                         reg = <0x0 0x95700000 0x0 0x100000>;
 108                         no-map;
 109                 };
 110         };
 111
 112         clocks {
 113                 xo: xo-board {
 114                         compatible = "fixed-clock";
 115                         #clock-cells = <0>;
 116                         clock-frequency = <19200000>;
 117                         clock-output-names = "xo_board";
 118                 };
 119
 120                 sleep_clk {
 121                         compatible = "fixed-clock";
 122                         #clock-cells = <0>;
 123                         clock-frequency = <32764>;
 124                 };
 125         };
 126
 127         cpus {
 128                 #address-cells = <2>;
 129                 #size-cells = <0>;
 130
 131                 CPU0: cpu@0 {
 132                         device_type = "cpu";
 133                         compatible = "qcom,kryo280";
 134                         reg = <0x0 0x0>;
 135                         enable-method = "psci";
 136                         capacity-dmips-mhz = <1024>;
 137                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 138                         next-level-cache = <&L2_0>;
 139                         L2_0: l2-cache {
 140                                 compatible = "arm,arch-cache";
 141                                 cache-level = <2>;
 142                         };
 143                         L1_I_0: l1-icache {
 144                                 compatible = "arm,arch-cache";
 145                         };
 146                         L1_D_0: l1-dcache {
 147                                 compatible = "arm,arch-cache";
 148                         };
 149                 };
 150
 151                 CPU1: cpu@1 {
 152                         device_type = "cpu";
 153                         compatible = "qcom,kryo280";
 154                         reg = <0x0 0x1>;
 155                         enable-method = "psci";
 156                         capacity-dmips-mhz = <1024>;
 157                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 158                         next-level-cache = <&L2_0>;
 159                         L1_I_1: l1-icache {
 160                                 compatible = "arm,arch-cache";
 161                         };
 162                         L1_D_1: l1-dcache {
 163                                 compatible = "arm,arch-cache";
 164                         };
 165                 };
 166
 167                 CPU2: cpu@2 {
 168                         device_type = "cpu";
 169                         compatible = "qcom,kryo280";
 170                         reg = <0x0 0x2>;
 171                         enable-method = "psci";
 172                         capacity-dmips-mhz = <1024>;
 173                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 174                         next-level-cache = <&L2_0>;
 175                         L1_I_2: l1-icache {
 176                                 compatible = "arm,arch-cache";
 177                         };
 178                         L1_D_2: l1-dcache {
 179                                 compatible = "arm,arch-cache";
 180                         };
 181                 };
 182
 183                 CPU3: cpu@3 {
 184                         device_type = "cpu";
 185                         compatible = "qcom,kryo280";
 186                         reg = <0x0 0x3>;
 187                         enable-method = "psci";
 188                         capacity-dmips-mhz = <1024>;
 189                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 190                         next-level-cache = <&L2_0>;
 191                         L1_I_3: l1-icache {
 192                                 compatible = "arm,arch-cache";
 193                         };
 194                         L1_D_3: l1-dcache {
 195                                 compatible = "arm,arch-cache";
 196                         };
 197                 };
 198
 199                 CPU4: cpu@100 {
 200                         device_type = "cpu";
 201                         compatible = "qcom,kryo280";
 202                         reg = <0x0 0x100>;
 203                         enable-method = "psci";
 204                         capacity-dmips-mhz = <1536>;
 205                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 206                         next-level-cache = <&L2_1>;
 207                         L2_1: l2-cache {
 208                                 compatible = "arm,arch-cache";
 209                                 cache-level = <2>;
 210                         };
 211                         L1_I_100: l1-icache {
 212                                 compatible = "arm,arch-cache";
 213                         };
 214                         L1_D_100: l1-dcache {
 215                                 compatible = "arm,arch-cache";
 216                         };
 217                 };
 218
 219                 CPU5: cpu@101 {
 220                         device_type = "cpu";
 221                         compatible = "qcom,kryo280";
 222                         reg = <0x0 0x101>;
 223                         enable-method = "psci";
 224                         capacity-dmips-mhz = <1536>;
 225                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 226                         next-level-cache = <&L2_1>;
 227                         L1_I_101: l1-icache {
 228                                 compatible = "arm,arch-cache";
 229                         };
 230                         L1_D_101: l1-dcache {
 231                                 compatible = "arm,arch-cache";
 232                         };
 233                 };
 234
 235                 CPU6: cpu@102 {
 236                         device_type = "cpu";
 237                         compatible = "qcom,kryo280";
 238                         reg = <0x0 0x102>;
 239                         enable-method = "psci";
 240                         capacity-dmips-mhz = <1536>;
 241                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 242                         next-level-cache = <&L2_1>;
 243                         L1_I_102: l1-icache {
 244                                 compatible = "arm,arch-cache";
 245                         };
 246                         L1_D_102: l1-dcache {
 247                                 compatible = "arm,arch-cache";
 248                         };
 249                 };
 250
 251                 CPU7: cpu@103 {
 252                         device_type = "cpu";
 253                         compatible = "qcom,kryo280";
 254                         reg = <0x0 0x103>;
 255                         enable-method = "psci";
 256                         capacity-dmips-mhz = <1536>;
 257                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 258                         next-level-cache = <&L2_1>;
 259                         L1_I_103: l1-icache {
 260                                 compatible = "arm,arch-cache";
 261                         };
 262                         L1_D_103: l1-dcache {
 263                                 compatible = "arm,arch-cache";
 264                         };
 265                 };
 266
 267                 cpu-map {
 268                         cluster0 {
 269                                 core0 {
 270                                         cpu = <&CPU0>;
 271                                 };
 272
 273                                 core1 {
 274                                         cpu = <&CPU1>;
 275                                 };
 276
 277                                 core2 {
 278                                         cpu = <&CPU2>;
 279                                 };
 280
 281                                 core3 {
 282                                         cpu = <&CPU3>;
 283                                 };
 284                         };
 285
 286                         cluster1 {
 287                                 core0 {
 288                                         cpu = <&CPU4>;
 289                                 };
 290
 291                                 core1 {
 292                                         cpu = <&CPU5>;
 293                                 };
 294
 295                                 core2 {
 296                                         cpu = <&CPU6>;
 297                                 };
 298
 299                                 core3 {
 300                                         cpu = <&CPU7>;
 301                                 };
 302                         };
 303                 };
 304
 305                 idle-states {
 306                         entry-method = "psci";
 307
 308                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 309                                 compatible = "arm,idle-state";
 310                                 idle-state-name = "little-retention";
 311                                 arm,psci-suspend-param = <0x00000002>;
 312                                 entry-latency-us = <81>;
 313                                 exit-latency-us = <86>;
 314                                 min-residency-us = <200>;
 315                         };
 316
 317                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 318                                 compatible = "arm,idle-state";
 319                                 idle-state-name = "little-power-collapse";
 320                                 arm,psci-suspend-param = <0x40000003>;
 321                                 entry-latency-us = <273>;
 322                                 exit-latency-us = <612>;
 323                                 min-residency-us = <1000>;
 324                                 local-timer-stop;
 325                         };
 326
 327                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 328                                 compatible = "arm,idle-state";
 329                                 idle-state-name = "big-retention";
 330                                 arm,psci-suspend-param = <0x00000002>;
 331                                 entry-latency-us = <79>;
 332                                 exit-latency-us = <82>;
 333                                 min-residency-us = <200>;
 334                         };
 335
 336                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 337                                 compatible = "arm,idle-state";
 338                                 idle-state-name = "big-power-collapse";
 339                                 arm,psci-suspend-param = <0x40000003>;
 340                                 entry-latency-us = <336>;
 341                                 exit-latency-us = <525>;
 342                                 min-residency-us = <1000>;
 343                                 local-timer-stop;
 344                         };
 345                 };
 346         };
 347
 348         firmware {
 349                 scm {
 350                         compatible = "qcom,scm-msm8998", "qcom,scm";
 351                 };
 352         };
 353
 354         tcsr_mutex: hwlock {
 355                 compatible = "qcom,tcsr-mutex";
 356                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 357                 #hwlock-cells = <1>;
 358         };
 359
 360         psci {
 361                 compatible = "arm,psci-1.0";
 362                 method = "smc";
 363         };
 364
 365         rpm-glink {
 366                 compatible = "qcom,glink-rpm";
 367
 368                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 369                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 370                 mboxes = <&apcs_glb 0>;
 371
 372                 rpm_requests: rpm-requests {
 373                         compatible = "qcom,rpm-msm8998";
 374                         qcom,glink-channels = "rpm_requests";
 375
 376                         rpmcc: clock-controller {
 377                                 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
 378                                 #clock-cells = <1>;
 379                         };
 380
 381                         rpmpd: power-controller {
 382                                 compatible = "qcom,msm8998-rpmpd";
 383                                 #power-domain-cells = <1>;
 384                                 operating-points-v2 = <&rpmpd_opp_table>;
 385
 386                                 rpmpd_opp_table: opp-table {
 387                                         compatible = "operating-points-v2";
 388
 389                                         rpmpd_opp_ret: opp1 {
 390                                                 opp-level = <RPM_SMD_LEVEL_RETENTION>;
 391                                         };
 392
 393                                         rpmpd_opp_ret_plus: opp2 {
 394                                                 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
 395                                         };
 396
 397                                         rpmpd_opp_min_svs: opp3 {
 398                                                 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 399                                         };
 400
 401                                         rpmpd_opp_low_svs: opp4 {
 402                                                 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 403                                         };
 404
 405                                         rpmpd_opp_svs: opp5 {
 406                                                 opp-level = <RPM_SMD_LEVEL_SVS>;
 407                                         };
 408
 409                                         rpmpd_opp_svs_plus: opp6 {
 410                                                 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 411                                         };
 412
 413                                         rpmpd_opp_nom: opp7 {
 414                                                 opp-level = <RPM_SMD_LEVEL_NOM>;
 415                                         };
 416
 417                                         rpmpd_opp_nom_plus: opp8 {
 418                                                 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 419                                         };
 420
 421                                         rpmpd_opp_turbo: opp9 {
 422                                                 opp-level = <RPM_SMD_LEVEL_TURBO>;
 423                                         };
 424
 425                                         rpmpd_opp_turbo_plus: opp10 {
 426                                                 opp-level = <RPM_SMD_LEVEL_BINNING>;
 427                                         };
 428                                 };
 429                         };
 430                 };
 431         };
 432
 433         smem {
 434                 compatible = "qcom,smem";
 435                 memory-region = <&smem_mem>;
 436                 hwlocks = <&tcsr_mutex 3>;
 437         };
 438
 439         smp2p-lpass {
 440                 compatible = "qcom,smp2p";
 441                 qcom,smem = <443>, <429>;
 442
 443                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 444
 445                 mboxes = <&apcs_glb 10>;
 446
 447                 qcom,local-pid = <0>;
 448                 qcom,remote-pid = <2>;
 449
 450                 adsp_smp2p_out: master-kernel {
 451                         qcom,entry-name = "master-kernel";
 452                         #qcom,smem-state-cells = <1>;
 453                 };
 454
 455                 adsp_smp2p_in: slave-kernel {
 456                         qcom,entry-name = "slave-kernel";
 457
 458                         interrupt-controller;
 459                         #interrupt-cells = <2>;
 460                 };
 461         };
 462
 463         smp2p-mpss {
 464                 compatible = "qcom,smp2p";
 465                 qcom,smem = <435>, <428>;
 466                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 467                 mboxes = <&apcs_glb 14>;
 468                 qcom,local-pid = <0>;
 469                 qcom,remote-pid = <1>;
 470
 471                 modem_smp2p_out: master-kernel {
 472                         qcom,entry-name = "master-kernel";
 473                         #qcom,smem-state-cells = <1>;
 474                 };
 475
 476                 modem_smp2p_in: slave-kernel {
 477                         qcom,entry-name = "slave-kernel";
 478                         interrupt-controller;
 479                         #interrupt-cells = <2>;
 480                 };
 481         };
 482
 483         smp2p-slpi {
 484                 compatible = "qcom,smp2p";
 485                 qcom,smem = <481>, <430>;
 486                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 487                 mboxes = <&apcs_glb 26>;
 488                 qcom,local-pid = <0>;
 489                 qcom,remote-pid = <3>;
 490
 491                 slpi_smp2p_out: master-kernel {
 492                         qcom,entry-name = "master-kernel";
 493                         #qcom,smem-state-cells = <1>;
 494                 };
 495
 496                 slpi_smp2p_in: slave-kernel {
 497                         qcom,entry-name = "slave-kernel";
 498                         interrupt-controller;
 499                         #interrupt-cells = <2>;
 500                 };
 501         };
 502
 503         thermal-zones {
 504                 cpu0-thermal {
 505                         polling-delay-passive = <250>;
 506                         polling-delay = <1000>;
 507
 508                         thermal-sensors = <&tsens0 1>;
 509
 510                         trips {
 511                                 cpu0_alert0: trip-point0 {
 512                                         temperature = <75000>;
 513                                         hysteresis = <2000>;
 514                                         type = "passive";
 515                                 };
 516
 517                                 cpu0_crit: cpu_crit {
 518                                         temperature = <110000>;
 519                                         hysteresis = <2000>;
 520                                         type = "critical";
 521                                 };
 522                         };
 523                 };
 524
 525                 cpu1-thermal {
 526                         polling-delay-passive = <250>;
 527                         polling-delay = <1000>;
 528
 529                         thermal-sensors = <&tsens0 2>;
 530
 531                         trips {
 532                                 cpu1_alert0: trip-point0 {
 533                                         temperature = <75000>;
 534                                         hysteresis = <2000>;
 535                                         type = "passive";
 536                                 };
 537
 538                                 cpu1_crit: cpu_crit {
 539                                         temperature = <110000>;
 540                                         hysteresis = <2000>;
 541                                         type = "critical";
 542                                 };
 543                         };
 544                 };
 545
 546                 cpu2-thermal {
 547                         polling-delay-passive = <250>;
 548                         polling-delay = <1000>;
 549
 550                         thermal-sensors = <&tsens0 3>;
 551
 552                         trips {
 553                                 cpu2_alert0: trip-point0 {
 554                                         temperature = <75000>;
 555                                         hysteresis = <2000>;
 556                                         type = "passive";
 557                                 };
 558
 559                                 cpu2_crit: cpu_crit {
 560                                         temperature = <110000>;
 561                                         hysteresis = <2000>;
 562                                         type = "critical";
 563                                 };
 564                         };
 565                 };
 566
 567                 cpu3-thermal {
 568                         polling-delay-passive = <250>;
 569                         polling-delay = <1000>;
 570
 571                         thermal-sensors = <&tsens0 4>;
 572
 573                         trips {
 574                                 cpu3_alert0: trip-point0 {
 575                                         temperature = <75000>;
 576                                         hysteresis = <2000>;
 577                                         type = "passive";
 578                                 };
 579
 580                                 cpu3_crit: cpu_crit {
 581                                         temperature = <110000>;
 582                                         hysteresis = <2000>;
 583                                         type = "critical";
 584                                 };
 585                         };
 586                 };
 587
 588                 cpu4-thermal {
 589                         polling-delay-passive = <250>;
 590                         polling-delay = <1000>;
 591
 592                         thermal-sensors = <&tsens0 7>;
 593
 594                         trips {
 595                                 cpu4_alert0: trip-point0 {
 596                                         temperature = <75000>;
 597                                         hysteresis = <2000>;
 598                                         type = "passive";
 599                                 };
 600
 601                                 cpu4_crit: cpu_crit {
 602                                         temperature = <110000>;
 603                                         hysteresis = <2000>;
 604                                         type = "critical";
 605                                 };
 606                         };
 607                 };
 608
 609                 cpu5-thermal {
 610                         polling-delay-passive = <250>;
 611                         polling-delay = <1000>;
 612
 613                         thermal-sensors = <&tsens0 8>;
 614
 615                         trips {
 616                                 cpu5_alert0: trip-point0 {
 617                                         temperature = <75000>;
 618                                         hysteresis = <2000>;
 619                                         type = "passive";
 620                                 };
 621
 622                                 cpu5_crit: cpu_crit {
 623                                         temperature = <110000>;
 624                                         hysteresis = <2000>;
 625                                         type = "critical";
 626                                 };
 627                         };
 628                 };
 629
 630                 cpu6-thermal {
 631                         polling-delay-passive = <250>;
 632                         polling-delay = <1000>;
 633
 634                         thermal-sensors = <&tsens0 9>;
 635
 636                         trips {
 637                                 cpu6_alert0: trip-point0 {
 638                                         temperature = <75000>;
 639                                         hysteresis = <2000>;
 640                                         type = "passive";
 641                                 };
 642
 643                                 cpu6_crit: cpu_crit {
 644                                         temperature = <110000>;
 645                                         hysteresis = <2000>;
 646                                         type = "critical";
 647                                 };
 648                         };
 649                 };
 650
 651                 cpu7-thermal {
 652                         polling-delay-passive = <250>;
 653                         polling-delay = <1000>;
 654
 655                         thermal-sensors = <&tsens0 10>;
 656
 657                         trips {
 658                                 cpu7_alert0: trip-point0 {
 659                                         temperature = <75000>;
 660                                         hysteresis = <2000>;
 661                                         type = "passive";
 662                                 };
 663
 664                                 cpu7_crit: cpu_crit {
 665                                         temperature = <110000>;
 666                                         hysteresis = <2000>;
 667                                         type = "critical";
 668                                 };
 669                         };
 670                 };
 671
 672                 gpu-thermal-bottom {
 673                         polling-delay-passive = <250>;
 674                         polling-delay = <1000>;
 675
 676                         thermal-sensors = <&tsens0 12>;
 677
 678                         trips {
 679                                 gpu1_alert0: trip-point0 {
 680                                         temperature = <90000>;
 681                                         hysteresis = <2000>;
 682                                         type = "hot";
 683                                 };
 684                         };
 685                 };
 686
 687                 gpu-thermal-top {
 688                         polling-delay-passive = <250>;
 689                         polling-delay = <1000>;
 690
 691                         thermal-sensors = <&tsens0 13>;
 692
 693                         trips {
 694                                 gpu2_alert0: trip-point0 {
 695                                         temperature = <90000>;
 696                                         hysteresis = <2000>;
 697                                         type = "hot";
 698                                 };
 699                         };
 700                 };
 701
 702                 clust0-mhm-thermal {
 703                         polling-delay-passive = <250>;
 704                         polling-delay = <1000>;
 705
 706                         thermal-sensors = <&tsens0 5>;
 707
 708                         trips {
 709                                 cluster0_mhm_alert0: trip-point0 {
 710                                         temperature = <90000>;
 711                                         hysteresis = <2000>;
 712                                         type = "hot";
 713                                 };
 714                         };
 715                 };
 716
 717                 clust1-mhm-thermal {
 718                         polling-delay-passive = <250>;
 719                         polling-delay = <1000>;
 720
 721                         thermal-sensors = <&tsens0 6>;
 722
 723                         trips {
 724                                 cluster1_mhm_alert0: trip-point0 {
 725                                         temperature = <90000>;
 726                                         hysteresis = <2000>;
 727                                         type = "hot";
 728                                 };
 729                         };
 730                 };
 731
 732                 cluster1-l2-thermal {
 733                         polling-delay-passive = <250>;
 734                         polling-delay = <1000>;
 735
 736                         thermal-sensors = <&tsens0 11>;
 737
 738                         trips {
 739                                 cluster1_l2_alert0: trip-point0 {
 740                                         temperature = <90000>;
 741                                         hysteresis = <2000>;
 742                                         type = "hot";
 743                                 };
 744                         };
 745                 };
 746
 747                 modem-thermal {
 748                         polling-delay-passive = <250>;
 749                         polling-delay = <1000>;
 750
 751                         thermal-sensors = <&tsens1 1>;
 752
 753                         trips {
 754                                 modem_alert0: trip-point0 {
 755                                         temperature = <90000>;
 756                                         hysteresis = <2000>;
 757                                         type = "hot";
 758                                 };
 759                         };
 760                 };
 761
 762                 mem-thermal {
 763                         polling-delay-passive = <250>;
 764                         polling-delay = <1000>;
 765
 766                         thermal-sensors = <&tsens1 2>;
 767
 768                         trips {
 769                                 mem_alert0: trip-point0 {
 770                                         temperature = <90000>;
 771                                         hysteresis = <2000>;
 772                                         type = "hot";
 773                                 };
 774                         };
 775                 };
 776
 777                 wlan-thermal {
 778                         polling-delay-passive = <250>;
 779                         polling-delay = <1000>;
 780
 781                         thermal-sensors = <&tsens1 3>;
 782
 783                         trips {
 784                                 wlan_alert0: trip-point0 {
 785                                         temperature = <90000>;
 786                                         hysteresis = <2000>;
 787                                         type = "hot";
 788                                 };
 789                         };
 790                 };
 791
 792                 q6-dsp-thermal {
 793                         polling-delay-passive = <250>;
 794                         polling-delay = <1000>;
 795
 796                         thermal-sensors = <&tsens1 4>;
 797
 798                         trips {
 799                                 q6_dsp_alert0: trip-point0 {
 800                                         temperature = <90000>;
 801                                         hysteresis = <2000>;
 802                                         type = "hot";
 803                                 };
 804                         };
 805                 };
 806
 807                 camera-thermal {
 808                         polling-delay-passive = <250>;
 809                         polling-delay = <1000>;
 810
 811                         thermal-sensors = <&tsens1 5>;
 812
 813                         trips {
 814                                 camera_alert0: trip-point0 {
 815                                         temperature = <90000>;
 816                                         hysteresis = <2000>;
 817                                         type = "hot";
 818                                 };
 819                         };
 820                 };
 821
 822                 multimedia-thermal {
 823                         polling-delay-passive = <250>;
 824                         polling-delay = <1000>;
 825
 826                         thermal-sensors = <&tsens1 6>;
 827
 828                         trips {
 829                                 multimedia_alert0: trip-point0 {
 830                                         temperature = <90000>;
 831                                         hysteresis = <2000>;
 832                                         type = "hot";
 833                                 };
 834                         };
 835                 };
 836         };
 837
 838         timer {
 839                 compatible = "arm,armv8-timer";
 840                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 841                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 842                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 843                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 844         };
 845
 846         soc: soc {
 847                 #address-cells = <1>;
 848                 #size-cells = <1>;
 849                 ranges = <0 0 0 0xffffffff>;
 850                 compatible = "simple-bus";
 851
 852                 gcc: clock-controller@100000 {
 853                         compatible = "qcom,gcc-msm8998";
 854                         #clock-cells = <1>;
 855                         #reset-cells = <1>;
 856                         #power-domain-cells = <1>;
 857                         reg = <0x00100000 0xb0000>;
 858                 };
 859
 860                 rpm_msg_ram: memory@778000 {
 861                         compatible = "qcom,rpm-msg-ram";
 862                         reg = <0x00778000 0x7000>;
 863                 };
 864
 865                 qfprom: qfprom@780000 {
 866                         compatible = "qcom,qfprom";
 867                         reg = <0x00780000 0x621c>;
 868                         #address-cells = <1>;
 869                         #size-cells = <1>;
 870
 871                         qusb2_hstx_trim: hstx-trim@423a {
 872                                 reg = <0x423a 0x1>;
 873                                 bits = <0 4>;
 874                         };
 875                 };
 876
 877                 tsens0: thermal@10ab000 {
 878                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 879                         reg = <0x010ab000 0x1000>, /* TM */
 880                               <0x010aa000 0x1000>; /* SROT */
 881                         #qcom,sensors = <14>;
 882                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 883                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 884                         interrupt-names = "uplow", "critical";
 885                         #thermal-sensor-cells = <1>;
 886                 };
 887
 888                 tsens1: thermal@10ae000 {
 889                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 890                         reg = <0x010ae000 0x1000>, /* TM */
 891                               <0x010ad000 0x1000>; /* SROT */
 892                         #qcom,sensors = <8>;
 893                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 894                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 895                         interrupt-names = "uplow", "critical";
 896                         #thermal-sensor-cells = <1>;
 897                 };
 898
 899                 anoc1_smmu: iommu@1680000 {
 900                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 901                         reg = <0x01680000 0x10000>;
 902                         #iommu-cells = <1>;
 903
 904                         #global-interrupts = <0>;
 905                         interrupts =
 906                                 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 907                                 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 908                                 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
 909                                 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
 910                                 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
 911                                 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 912                 };
 913
 914                 anoc2_smmu: iommu@16c0000 {
 915                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 916                         reg = <0x016c0000 0x40000>;
 917                         #iommu-cells = <1>;
 918
 919                         #global-interrupts = <0>;
 920                         interrupts =
 921                                 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 922                                 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
 923                                 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
 924                                 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
 925                                 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
 926                                 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
 927                                 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
 928                                 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
 929                                 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
 930                                 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
 931                 };
 932
 933                 pcie0: pci@1c00000 {
 934                         compatible = "qcom,pcie-msm8996";
 935                         reg =   <0x01c00000 0x2000>,
 936                                 <0x1b000000 0xf1d>,
 937                                 <0x1b000f20 0xa8>,
 938                                 <0x1b100000 0x100000>;
 939                         reg-names = "parf", "dbi", "elbi", "config";
 940                         device_type = "pci";
 941                         linux,pci-domain = <0>;
 942                         bus-range = <0x00 0xff>;
 943                         #address-cells = <3>;
 944                         #size-cells = <2>;
 945                         num-lanes = <1>;
 946                         phys = <&pciephy>;
 947                         phy-names = "pciephy";
 948                         status = "disabled";
 949
 950                         ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
 951                                  <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
 952
 953                         #interrupt-cells = <1>;
 954                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 955                         interrupt-names = "msi";
 956                         interrupt-map-mask = <0 0 0 0x7>;
 957                         interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
 958                                         <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
 959                                         <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
 960                                         <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
 961
 962                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 963                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 964                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 965                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 966                                  <&gcc GCC_PCIE_0_AUX_CLK>;
 967                         clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
 968
 969                         power-domains = <&gcc PCIE_0_GDSC>;
 970                         iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
 971                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
 972                 };
 973
 974                 pcie_phy: phy@1c06000 {
 975                         compatible = "qcom,msm8998-qmp-pcie-phy";
 976                         reg = <0x01c06000 0x18c>;
 977                         #address-cells = <1>;
 978                         #size-cells = <1>;
 979                         status = "disabled";
 980                         ranges;
 981
 982                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 983                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 984                                  <&gcc GCC_PCIE_CLKREF_CLK>;
 985                         clock-names = "aux", "cfg_ahb", "ref";
 986
 987                         resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
 988                         reset-names = "phy", "common";
 989
 990                         vdda-phy-supply = <&vreg_l1a_0p875>;
 991                         vdda-pll-supply = <&vreg_l2a_1p2>;
 992
 993                         pciephy: lane@1c06800 {
 994                                 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
 995                                 #phy-cells = <0>;
 996
 997                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 998                                 clock-names = "pipe0";
 999                                 clock-output-names = "pcie_0_pipe_clk_src";
1000                                 #clock-cells = <0>;
1001                         };
1002                 };
1003
1004                 ufshc: ufshc@1da4000 {
1005                         compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1006                         reg = <0x01da4000 0x2500>;
1007                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1008                         phys = <&ufsphy_lanes>;
1009                         phy-names = "ufsphy";
1010                         lanes-per-direction = <2>;
1011                         power-domains = <&gcc UFS_GDSC>;
1012                         status = "disabled";
1013                         #reset-cells = <1>;
1014
1015                         clock-names =
1016                                 "core_clk",
1017                                 "bus_aggr_clk",
1018                                 "iface_clk",
1019                                 "core_clk_unipro",
1020                                 "ref_clk",
1021                                 "tx_lane0_sync_clk",
1022                                 "rx_lane0_sync_clk",
1023                                 "rx_lane1_sync_clk";
1024                         clocks =
1025                                 <&gcc GCC_UFS_AXI_CLK>,
1026                                 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1027                                 <&gcc GCC_UFS_AHB_CLK>,
1028                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1029                                 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1030                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1031                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1032                                 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1033                         freq-table-hz =
1034                                 <50000000 200000000>,
1035                                 <0 0>,
1036                                 <0 0>,
1037                                 <37500000 150000000>,
1038                                 <0 0>,
1039                                 <0 0>,
1040                                 <0 0>,
1041                                 <0 0>;
1042
1043                         resets = <&gcc GCC_UFS_BCR>;
1044                         reset-names = "rst";
1045                 };
1046
1047                 ufsphy: phy@1da7000 {
1048                         compatible = "qcom,msm8998-qmp-ufs-phy";
1049                         reg = <0x01da7000 0x18c>;
1050                         #address-cells = <1>;
1051                         #size-cells = <1>;
1052                         status = "disabled";
1053                         ranges;
1054
1055                         clock-names =
1056                                 "ref",
1057                                 "ref_aux";
1058                         clocks =
1059                                 <&gcc GCC_UFS_CLKREF_CLK>,
1060                                 <&gcc GCC_UFS_PHY_AUX_CLK>;
1061
1062                         reset-names = "ufsphy";
1063                         resets = <&ufshc 0>;
1064
1065                         ufsphy_lanes: lanes@1da7400 {
1066                                 reg = <0x01da7400 0x128>,
1067                                       <0x01da7600 0x1fc>,
1068                                       <0x01da7c00 0x1dc>,
1069                                       <0x01da7800 0x128>,
1070                                       <0x01da7a00 0x1fc>;
1071                                 #phy-cells = <0>;
1072                         };
1073                 };
1074
1075                 tcsr_mutex_regs: syscon@1f40000 {
1076                         compatible = "syscon";
1077                         reg = <0x01f40000 0x40000>;
1078                 };
1079
1080                 tlmm: pinctrl@3400000 {
1081                         compatible = "qcom,msm8998-pinctrl";
1082                         reg = <0x03400000 0xc00000>;
1083                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1084                         gpio-controller;
1085                         #gpio-cells = <0x2>;
1086                         interrupt-controller;
1087                         #interrupt-cells = <0x2>;
1088
1089                         sdc2_clk_on: sdc2_clk_on {
1090                                 config {
1091                                         pins = "sdc2_clk";
1092                                         bias-disable;
1093                                         drive-strength = <16>;
1094                                 };
1095                         };
1096
1097                         sdc2_clk_off: sdc2_clk_off {
1098                                 config {
1099                                         pins = "sdc2_clk";
1100                                         bias-disable;
1101                                         drive-strength = <2>;
1102                                 };
1103                         };
1104
1105                         sdc2_cmd_on: sdc2_cmd_on {
1106                                 config {
1107                                         pins = "sdc2_cmd";
1108                                         bias-pull-up;
1109                                         drive-strength = <10>;
1110                                 };
1111                         };
1112
1113                         sdc2_cmd_off: sdc2_cmd_off {
1114                                 config {
1115                                         pins = "sdc2_cmd";
1116                                         bias-pull-up;
1117                                         drive-strength = <2>;
1118                                 };
1119                         };
1120
1121                         sdc2_data_on: sdc2_data_on {
1122                                 config {
1123                                         pins = "sdc2_data";
1124                                         bias-pull-up;
1125                                         drive-strength = <10>;
1126                                 };
1127                         };
1128
1129                         sdc2_data_off: sdc2_data_off {
1130                                 config {
1131                                         pins = "sdc2_data";
1132                                         bias-pull-up;
1133                                         drive-strength = <2>;
1134                                 };
1135                         };
1136
1137                         sdc2_cd_on: sdc2_cd_on {
1138                                 mux {
1139                                         pins = "gpio95";
1140                                         function = "gpio";
1141                                 };
1142
1143                                 config {
1144                                         pins = "gpio95";
1145                                         bias-pull-up;
1146                                         drive-strength = <2>;
1147                                 };
1148                         };
1149
1150                         sdc2_cd_off: sdc2_cd_off {
1151                                 mux {
1152                                         pins = "gpio95";
1153                                         function = "gpio";
1154                                 };
1155
1156                                 config {
1157                                         pins = "gpio95";
1158                                         bias-pull-up;
1159                                         drive-strength = <2>;
1160                                 };
1161                         };
1162
1163                         blsp1_uart3_on: blsp1_uart3_on {
1164                                 tx {
1165                                         pins = "gpio45";
1166                                         function = "blsp_uart3_a";
1167                                         drive-strength = <2>;
1168                                         bias-disable;
1169                                 };
1170
1171                                 rx {
1172                                         pins = "gpio46";
1173                                         function = "blsp_uart3_a";
1174                                         drive-strength = <2>;
1175                                         bias-disable;
1176                                 };
1177
1178                                 cts {
1179                                         pins = "gpio47";
1180                                         function = "blsp_uart3_a";
1181                                         drive-strength = <2>;
1182                                         bias-disable;
1183                                 };
1184
1185                                 rfr {
1186                                         pins = "gpio48";
1187                                         function = "blsp_uart3_a";
1188                                         drive-strength = <2>;
1189                                         bias-disable;
1190                                 };
1191                         };
1192
1193                         blsp1_i2c1_default: blsp1-i2c1-default {
1194                                 pins = "gpio2", "gpio3";
1195                                 function = "blsp_i2c1";
1196                                 drive-strength = <2>;
1197                                 bias-disable;
1198                         };
1199
1200                         blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1201                                 pins = "gpio2", "gpio3";
1202                                 function = "blsp_i2c1";
1203                                 drive-strength = <2>;
1204                                 bias-pull-up;
1205                         };
1206
1207                         blsp1_i2c2_default: blsp1-i2c2-default {
1208                                 pins = "gpio32", "gpio33";
1209                                 function = "blsp_i2c2";
1210                                 drive-strength = <2>;
1211                                 bias-disable;
1212                         };
1213
1214                         blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1215                                 pins = "gpio32", "gpio33";
1216                                 function = "blsp_i2c2";
1217                                 drive-strength = <2>;
1218                                 bias-pull-up;
1219                         };
1220
1221                         blsp1_i2c3_default: blsp1-i2c3-default {
1222                                 pins = "gpio47", "gpio48";
1223                                 function = "blsp_i2c3";
1224                                 drive-strength = <2>;
1225                                 bias-disable;
1226                         };
1227
1228                         blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1229                                 pins = "gpio47", "gpio48";
1230                                 function = "blsp_i2c3";
1231                                 drive-strength = <2>;
1232                                 bias-pull-up;
1233                         };
1234
1235                         blsp1_i2c4_default: blsp1-i2c4-default {
1236                                 pins = "gpio10", "gpio11";
1237                                 function = "blsp_i2c4";
1238                                 drive-strength = <2>;
1239                                 bias-disable;
1240                         };
1241
1242                         blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1243                                 pins = "gpio10", "gpio11";
1244                                 function = "blsp_i2c4";
1245                                 drive-strength = <2>;
1246                                 bias-pull-up;
1247                         };
1248
1249                         blsp1_i2c5_default: blsp1-i2c5-default {
1250                                 pins = "gpio87", "gpio88";
1251                                 function = "blsp_i2c5";
1252                                 drive-strength = <2>;
1253                                 bias-disable;
1254                         };
1255
1256                         blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1257                                 pins = "gpio87", "gpio88";
1258                                 function = "blsp_i2c5";
1259                                 drive-strength = <2>;
1260                                 bias-pull-up;
1261                         };
1262
1263                         blsp1_i2c6_default: blsp1-i2c6-default {
1264                                 pins = "gpio43", "gpio44";
1265                                 function = "blsp_i2c6";
1266                                 drive-strength = <2>;
1267                                 bias-disable;
1268                         };
1269
1270                         blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1271                                 pins = "gpio43", "gpio44";
1272                                 function = "blsp_i2c6";
1273                                 drive-strength = <2>;
1274                                 bias-pull-up;
1275                         };
1276                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1277                         blsp2_i2c1_default: blsp2-i2c1-default {
1278                                 pins = "gpio55", "gpio56";
1279                                 function = "blsp_i2c7";
1280                                 drive-strength = <2>;
1281                                 bias-disable;
1282                         };
1283
1284                         blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1285                                 pins = "gpio55", "gpio56";
1286                                 function = "blsp_i2c7";
1287                                 drive-strength = <2>;
1288                                 bias-pull-up;
1289                         };
1290
1291                         blsp2_i2c2_default: blsp2-i2c2-default {
1292                                 pins = "gpio6", "gpio7";
1293                                 function = "blsp_i2c8";
1294                                 drive-strength = <2>;
1295                                 bias-disable;
1296                         };
1297
1298                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1299                                 pins = "gpio6", "gpio7";
1300                                 function = "blsp_i2c8";
1301                                 drive-strength = <2>;
1302                                 bias-pull-up;
1303                         };
1304
1305                         blsp2_i2c3_default: blsp2-i2c3-default {
1306                                 pins = "gpio51", "gpio52";
1307                                 function = "blsp_i2c9";
1308                                 drive-strength = <2>;
1309                                 bias-disable;
1310                         };
1311
1312                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1313                                 pins = "gpio51", "gpio52";
1314                                 function = "blsp_i2c9";
1315                                 drive-strength = <2>;
1316                                 bias-pull-up;
1317                         };
1318
1319                         blsp2_i2c4_default: blsp2-i2c4-default {
1320                                 pins = "gpio67", "gpio68";
1321                                 function = "blsp_i2c10";
1322                                 drive-strength = <2>;
1323                                 bias-disable;
1324                         };
1325
1326                         blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1327                                 pins = "gpio67", "gpio68";
1328                                 function = "blsp_i2c10";
1329                                 drive-strength = <2>;
1330                                 bias-pull-up;
1331                         };
1332
1333                         blsp2_i2c5_default: blsp2-i2c5-default {
1334                                 pins = "gpio60", "gpio61";
1335                                 function = "blsp_i2c11";
1336                                 drive-strength = <2>;
1337                                 bias-disable;
1338                         };
1339
1340                         blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1341                                 pins = "gpio60", "gpio61";
1342                                 function = "blsp_i2c11";
1343                                 drive-strength = <2>;
1344                                 bias-pull-up;
1345                         };
1346
1347                         blsp2_i2c6_default: blsp2-i2c6-default {
1348                                 pins = "gpio83", "gpio84";
1349                                 function = "blsp_i2c12";
1350                                 drive-strength = <2>;
1351                                 bias-disable;
1352                         };
1353
1354                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1355                                 pins = "gpio83", "gpio84";
1356                                 function = "blsp_i2c12";
1357                                 drive-strength = <2>;
1358                                 bias-pull-up;
1359                         };
1360                 };
1361
1362                 remoteproc_mss: remoteproc@4080000 {
1363                         compatible = "qcom,msm8998-mss-pil";
1364                         reg = <0x04080000 0x100>, <0x04180000 0x20>;
1365                         reg-names = "qdsp6", "rmb";
1366
1367                         interrupts-extended =
1368                                 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1369                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1370                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1371                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1372                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1373                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1374                         interrupt-names = "wdog", "fatal", "ready",
1375                                           "handover", "stop-ack",
1376                                           "shutdown-ack";
1377
1378                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1379                                  <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1380                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1381                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1382                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1383                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1384                                  <&rpmcc RPM_SMD_QDSS_CLK>,
1385                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1386                         clock-names = "iface", "bus", "mem", "gpll0_mss",
1387                                       "snoc_axi", "mnoc_axi", "qdss", "xo";
1388
1389                         qcom,smem-states = <&modem_smp2p_out 0>;
1390                         qcom,smem-state-names = "stop";
1391
1392                         resets = <&gcc GCC_MSS_RESTART>;
1393                         reset-names = "mss_restart";
1394
1395                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1396
1397                         power-domains = <&rpmpd MSM8998_VDDCX>,
1398                                         <&rpmpd MSM8998_VDDMX>;
1399                         power-domain-names = "cx", "mx";
1400
1401                         status = "disabled";
1402
1403                         mba {
1404                                 memory-region = <&mba_mem>;
1405                         };
1406
1407                         mpss {
1408                                 memory-region = <&mpss_mem>;
1409                         };
1410
1411                         glink-edge {
1412                                 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1413                                 label = "modem";
1414                                 qcom,remote-pid = <1>;
1415                                 mboxes = <&apcs_glb 15>;
1416                         };
1417                 };
1418
1419                 gpucc: clock-controller@5065000 {
1420                         compatible = "qcom,msm8998-gpucc";
1421                         #clock-cells = <1>;
1422                         #reset-cells = <1>;
1423                         #power-domain-cells = <1>;
1424                         reg = <0x05065000 0x9000>;
1425
1426                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1427                                  <&gcc GPLL0_OUT_MAIN>;
1428                         clock-names = "xo",
1429                                       "gpll0";
1430                 };
1431
1432                 remoteproc_slpi: remoteproc@5800000 {
1433                         compatible = "qcom,msm8998-slpi-pas";
1434                         reg = <0x05800000 0x4040>;
1435
1436                         interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1437                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1438                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1439                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1440                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1441                         interrupt-names = "wdog", "fatal", "ready",
1442                                           "handover", "stop-ack";
1443
1444                         px-supply = <&vreg_lvs2a_1p8>;
1445
1446                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1447                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1448                         clock-names = "xo", "aggre2";
1449
1450                         memory-region = <&slpi_mem>;
1451
1452                         qcom,smem-states = <&slpi_smp2p_out 0>;
1453                         qcom,smem-state-names = "stop";
1454
1455                         power-domains = <&rpmpd MSM8998_SSCCX>;
1456                         power-domain-names = "ssc_cx";
1457
1458                         status = "disabled";
1459
1460                         glink-edge {
1461                                 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1462                                 label = "dsps";
1463                                 qcom,remote-pid = <3>;
1464                                 mboxes = <&apcs_glb 27>;
1465                         };
1466                 };
1467
1468                 stm: stm@6002000 {
1469                         compatible = "arm,coresight-stm", "arm,primecell";
1470                         reg = <0x06002000 0x1000>,
1471                               <0x16280000 0x180000>;
1472                         reg-names = "stm-base", "stm-data-base";
1473                         status = "disabled";
1474
1475                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1476                         clock-names = "apb_pclk", "atclk";
1477
1478                         out-ports {
1479                                 port {
1480                                         stm_out: endpoint {
1481                                                 remote-endpoint = <&funnel0_in7>;
1482                                         };
1483                                 };
1484                         };
1485                 };
1486
1487                 funnel1: funnel@6041000 {
1488                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1489                         reg = <0x06041000 0x1000>;
1490                         status = "disabled";
1491
1492                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1493                         clock-names = "apb_pclk", "atclk";
1494
1495                         out-ports {
1496                                 port {
1497                                         funnel0_out: endpoint {
1498                                                 remote-endpoint =
1499                                                   <&merge_funnel_in0>;
1500                                         };
1501                                 };
1502                         };
1503
1504                         in-ports {
1505                                 #address-cells = <1>;
1506                                 #size-cells = <0>;
1507
1508                                 port@7 {
1509                                         reg = <7>;
1510                                         funnel0_in7: endpoint {
1511                                                 remote-endpoint = <&stm_out>;
1512                                         };
1513                                 };
1514                         };
1515                 };
1516
1517                 funnel2: funnel@6042000 {
1518                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1519                         reg = <0x06042000 0x1000>;
1520                         status = "disabled";
1521
1522                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1523                         clock-names = "apb_pclk", "atclk";
1524
1525                         out-ports {
1526                                 port {
1527                                         funnel1_out: endpoint {
1528                                                 remote-endpoint =
1529                                                   <&merge_funnel_in1>;
1530                                         };
1531                                 };
1532                         };
1533
1534                         in-ports {
1535                                 #address-cells = <1>;
1536                                 #size-cells = <0>;
1537
1538                                 port@6 {
1539                                         reg = <6>;
1540                                         funnel1_in6: endpoint {
1541                                                 remote-endpoint =
1542                                                   <&apss_merge_funnel_out>;
1543                                         };
1544                                 };
1545                         };
1546                 };
1547
1548                 funnel3: funnel@6045000 {
1549                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1550                         reg = <0x06045000 0x1000>;
1551                         status = "disabled";
1552
1553                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1554                         clock-names = "apb_pclk", "atclk";
1555
1556                         out-ports {
1557                                 port {
1558                                         merge_funnel_out: endpoint {
1559                                                 remote-endpoint =
1560                                                   <&etf_in>;
1561                                         };
1562                                 };
1563                         };
1564
1565                         in-ports {
1566                                 #address-cells = <1>;
1567                                 #size-cells = <0>;
1568
1569                                 port@0 {
1570                                         reg = <0>;
1571                                         merge_funnel_in0: endpoint {
1572                                                 remote-endpoint =
1573                                                   <&funnel0_out>;
1574                                         };
1575                                 };
1576
1577                                 port@1 {
1578                                         reg = <1>;
1579                                         merge_funnel_in1: endpoint {
1580                                                 remote-endpoint =
1581                                                   <&funnel1_out>;
1582                                         };
1583                                 };
1584                         };
1585                 };
1586
1587                 replicator1: replicator@6046000 {
1588                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1589                         reg = <0x06046000 0x1000>;
1590                         status = "disabled";
1591
1592                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1593                         clock-names = "apb_pclk", "atclk";
1594
1595                         out-ports {
1596                                 port {
1597                                         replicator_out: endpoint {
1598                                                 remote-endpoint = <&etr_in>;
1599                                         };
1600                                 };
1601                         };
1602
1603                         in-ports {
1604                                 port {
1605                                         replicator_in: endpoint {
1606                                                 remote-endpoint = <&etf_out>;
1607                                         };
1608                                 };
1609                         };
1610                 };
1611
1612                 etf: etf@6047000 {
1613                         compatible = "arm,coresight-tmc", "arm,primecell";
1614                         reg = <0x06047000 0x1000>;
1615                         status = "disabled";
1616
1617                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1618                         clock-names = "apb_pclk", "atclk";
1619
1620                         out-ports {
1621                                 port {
1622                                         etf_out: endpoint {
1623                                                 remote-endpoint =
1624                                                   <&replicator_in>;
1625                                         };
1626                                 };
1627                         };
1628
1629                         in-ports {
1630                                 port {
1631                                         etf_in: endpoint {
1632                                                 remote-endpoint =
1633                                                   <&merge_funnel_out>;
1634                                         };
1635                                 };
1636                         };
1637                 };
1638
1639                 etr: etr@6048000 {
1640                         compatible = "arm,coresight-tmc", "arm,primecell";
1641                         reg = <0x06048000 0x1000>;
1642                         status = "disabled";
1643
1644                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1645                         clock-names = "apb_pclk", "atclk";
1646                         arm,scatter-gather;
1647
1648                         in-ports {
1649                                 port {
1650                                         etr_in: endpoint {
1651                                                 remote-endpoint =
1652                                                   <&replicator_out>;
1653                                         };
1654                                 };
1655                         };
1656                 };
1657
1658                 etm1: etm@7840000 {
1659                         compatible = "arm,coresight-etm4x", "arm,primecell";
1660                         reg = <0x07840000 0x1000>;
1661                         status = "disabled";
1662
1663                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1664                         clock-names = "apb_pclk", "atclk";
1665
1666                         cpu = <&CPU0>;
1667
1668                         out-ports {
1669                                 port {
1670                                         etm0_out: endpoint {
1671                                                 remote-endpoint =
1672                                                   <&apss_funnel_in0>;
1673                                         };
1674                                 };
1675                         };
1676                 };
1677
1678                 etm2: etm@7940000 {
1679                         compatible = "arm,coresight-etm4x", "arm,primecell";
1680                         reg = <0x07940000 0x1000>;
1681                         status = "disabled";
1682
1683                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1684                         clock-names = "apb_pclk", "atclk";
1685
1686                         cpu = <&CPU1>;
1687
1688                         out-ports {
1689                                 port {
1690                                         etm1_out: endpoint {
1691                                                 remote-endpoint =
1692                                                   <&apss_funnel_in1>;
1693                                         };
1694                                 };
1695                         };
1696                 };
1697
1698                 etm3: etm@7a40000 {
1699                         compatible = "arm,coresight-etm4x", "arm,primecell";
1700                         reg = <0x07a40000 0x1000>;
1701                         status = "disabled";
1702
1703                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1704                         clock-names = "apb_pclk", "atclk";
1705
1706                         cpu = <&CPU2>;
1707
1708                         out-ports {
1709                                 port {
1710                                         etm2_out: endpoint {
1711                                                 remote-endpoint =
1712                                                   <&apss_funnel_in2>;
1713                                         };
1714                                 };
1715                         };
1716                 };
1717
1718                 etm4: etm@7b40000 {
1719                         compatible = "arm,coresight-etm4x", "arm,primecell";
1720                         reg = <0x07b40000 0x1000>;
1721                         status = "disabled";
1722
1723                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1724                         clock-names = "apb_pclk", "atclk";
1725
1726                         cpu = <&CPU3>;
1727
1728                         out-ports {
1729                                 port {
1730                                         etm3_out: endpoint {
1731                                                 remote-endpoint =
1732                                                   <&apss_funnel_in3>;
1733                                         };
1734                                 };
1735                         };
1736                 };
1737
1738                 funnel4: funnel@7b60000 { /* APSS Funnel */
1739                         compatible = "arm,coresight-etm4x", "arm,primecell";
1740                         reg = <0x07b60000 0x1000>;
1741                         status = "disabled";
1742
1743                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1744                         clock-names = "apb_pclk", "atclk";
1745
1746                         out-ports {
1747                                 port {
1748                                         apss_funnel_out: endpoint {
1749                                                 remote-endpoint =
1750                                                   <&apss_merge_funnel_in>;
1751                                         };
1752                                 };
1753                         };
1754
1755                         in-ports {
1756                                 #address-cells = <1>;
1757                                 #size-cells = <0>;
1758
1759                                 port@0 {
1760                                         reg = <0>;
1761                                         apss_funnel_in0: endpoint {
1762                                                 remote-endpoint =
1763                                                   <&etm0_out>;
1764                                         };
1765                                 };
1766
1767                                 port@1 {
1768                                         reg = <1>;
1769                                         apss_funnel_in1: endpoint {
1770                                                 remote-endpoint =
1771                                                   <&etm1_out>;
1772                                         };
1773                                 };
1774
1775                                 port@2 {
1776                                         reg = <2>;
1777                                         apss_funnel_in2: endpoint {
1778                                                 remote-endpoint =
1779                                                   <&etm2_out>;
1780                                         };
1781                                 };
1782
1783                                 port@3 {
1784                                         reg = <3>;
1785                                         apss_funnel_in3: endpoint {
1786                                                 remote-endpoint =
1787                                                   <&etm3_out>;
1788                                         };
1789                                 };
1790
1791                                 port@4 {
1792                                         reg = <4>;
1793                                         apss_funnel_in4: endpoint {
1794                                                 remote-endpoint =
1795                                                   <&etm4_out>;
1796                                         };
1797                                 };
1798
1799                                 port@5 {
1800                                         reg = <5>;
1801                                         apss_funnel_in5: endpoint {
1802                                                 remote-endpoint =
1803                                                   <&etm5_out>;
1804                                         };
1805                                 };
1806
1807                                 port@6 {
1808                                         reg = <6>;
1809                                         apss_funnel_in6: endpoint {
1810                                                 remote-endpoint =
1811                                                   <&etm6_out>;
1812                                         };
1813                                 };
1814
1815                                 port@7 {
1816                                         reg = <7>;
1817                                         apss_funnel_in7: endpoint {
1818                                                 remote-endpoint =
1819                                                   <&etm7_out>;
1820                                         };
1821                                 };
1822                         };
1823                 };
1824
1825                 funnel5: funnel@7b70000 {
1826                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1827                         reg = <0x07b70000 0x1000>;
1828                         status = "disabled";
1829
1830                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1831                         clock-names = "apb_pclk", "atclk";
1832
1833                         out-ports {
1834                                 port {
1835                                         apss_merge_funnel_out: endpoint {
1836                                                 remote-endpoint =
1837                                                   <&funnel1_in6>;
1838                                         };
1839                                 };
1840                         };
1841
1842                         in-ports {
1843                                 port {
1844                                         apss_merge_funnel_in: endpoint {
1845                                                 remote-endpoint =
1846                                                   <&apss_funnel_out>;
1847                                         };
1848                                 };
1849                         };
1850                 };
1851
1852                 etm5: etm@7c40000 {
1853                         compatible = "arm,coresight-etm4x", "arm,primecell";
1854                         reg = <0x07c40000 0x1000>;
1855                         status = "disabled";
1856
1857                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1858                         clock-names = "apb_pclk", "atclk";
1859
1860                         cpu = <&CPU4>;
1861
1862                         port{
1863                                 etm4_out: endpoint {
1864                                         remote-endpoint = <&apss_funnel_in4>;
1865                                 };
1866                         };
1867                 };
1868
1869                 etm6: etm@7d40000 {
1870                         compatible = "arm,coresight-etm4x", "arm,primecell";
1871                         reg = <0x07d40000 0x1000>;
1872                         status = "disabled";
1873
1874                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1875                         clock-names = "apb_pclk", "atclk";
1876
1877                         cpu = <&CPU5>;
1878
1879                         port{
1880                                 etm5_out: endpoint {
1881                                         remote-endpoint = <&apss_funnel_in5>;
1882                                 };
1883                         };
1884                 };
1885
1886                 etm7: etm@7e40000 {
1887                         compatible = "arm,coresight-etm4x", "arm,primecell";
1888                         reg = <0x07e40000 0x1000>;
1889                         status = "disabled";
1890
1891                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1892                         clock-names = "apb_pclk", "atclk";
1893
1894                         cpu = <&CPU6>;
1895
1896                         port{
1897                                 etm6_out: endpoint {
1898                                         remote-endpoint = <&apss_funnel_in6>;
1899                                 };
1900                         };
1901                 };
1902
1903                 etm8: etm@7f40000 {
1904                         compatible = "arm,coresight-etm4x", "arm,primecell";
1905                         reg = <0x07f40000 0x1000>;
1906                         status = "disabled";
1907
1908                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1909                         clock-names = "apb_pclk", "atclk";
1910
1911                         cpu = <&CPU7>;
1912
1913                         port{
1914                                 etm7_out: endpoint {
1915                                         remote-endpoint = <&apss_funnel_in7>;
1916                                 };
1917                         };
1918                 };
1919
1920                 spmi_bus: spmi@800f000 {
1921                         compatible = "qcom,spmi-pmic-arb";
1922                         reg =   <0x0800f000 0x1000>,
1923                                 <0x08400000 0x1000000>,
1924                                 <0x09400000 0x1000000>,
1925                                 <0x0a400000 0x220000>,
1926                                 <0x0800a000 0x3000>;
1927                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1928                         interrupt-names = "periph_irq";
1929                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1930                         qcom,ee = <0>;
1931                         qcom,channel = <0>;
1932                         #address-cells = <2>;
1933                         #size-cells = <0>;
1934                         interrupt-controller;
1935                         #interrupt-cells = <4>;
1936                         cell-index = <0>;
1937                 };
1938
1939                 usb3: usb@a8f8800 {
1940                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1941                         reg = <0x0a8f8800 0x400>;
1942                         status = "disabled";
1943                         #address-cells = <1>;
1944                         #size-cells = <1>;
1945                         ranges;
1946
1947                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1948                                  <&gcc GCC_USB30_MASTER_CLK>,
1949                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
1950                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1951                                  <&gcc GCC_USB30_SLEEP_CLK>;
1952                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1953                                       "sleep";
1954
1955                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1956                                           <&gcc GCC_USB30_MASTER_CLK>;
1957                         assigned-clock-rates = <19200000>, <120000000>;
1958
1959                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1960                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1961                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
1962
1963                         power-domains = <&gcc USB_30_GDSC>;
1964
1965                         resets = <&gcc GCC_USB_30_BCR>;
1966
1967                         usb3_dwc3: dwc3@a800000 {
1968                                 compatible = "snps,dwc3";
1969                                 reg = <0x0a800000 0xcd00>;
1970                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1971                                 snps,dis_u2_susphy_quirk;
1972                                 snps,dis_enblslpm_quirk;
1973                                 phys = <&qusb2phy>, <&usb1_ssphy>;
1974                                 phy-names = "usb2-phy", "usb3-phy";
1975                                 snps,has-lpm-erratum;
1976                                 snps,hird-threshold = /bits/ 8 <0x10>;
1977                         };
1978                 };
1979
1980                 usb3phy: phy@c010000 {
1981                         compatible = "qcom,msm8998-qmp-usb3-phy";
1982                         reg = <0x0c010000 0x18c>;
1983                         status = "disabled";
1984                         #clock-cells = <1>;
1985                         #address-cells = <1>;
1986                         #size-cells = <1>;
1987                         ranges;
1988
1989                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1990                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1991                                  <&gcc GCC_USB3_CLKREF_CLK>;
1992                         clock-names = "aux", "cfg_ahb", "ref";
1993
1994                         resets = <&gcc GCC_USB3_PHY_BCR>,
1995                                  <&gcc GCC_USB3PHY_PHY_BCR>;
1996                         reset-names = "phy", "common";
1997
1998                         usb1_ssphy: lane@c010200 {
1999                                 reg = <0xc010200 0x128>,
2000                                       <0xc010400 0x200>,
2001                                       <0xc010c00 0x20c>,
2002                                       <0xc010600 0x128>,
2003                                       <0xc010800 0x200>;
2004                                 #phy-cells = <0>;
2005                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2006                                 clock-names = "pipe0";
2007                                 clock-output-names = "usb3_phy_pipe_clk_src";
2008                         };
2009                 };
2010
2011                 qusb2phy: phy@c012000 {
2012                         compatible = "qcom,msm8998-qusb2-phy";
2013                         reg = <0x0c012000 0x2a8>;
2014                         status = "disabled";
2015                         #phy-cells = <0>;
2016
2017                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2018                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2019                         clock-names = "cfg_ahb", "ref";
2020
2021                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2022
2023                         nvmem-cells = <&qusb2_hstx_trim>;
2024                 };
2025
2026                 sdhc2: sdhci@c0a4900 {
2027                         compatible = "qcom,sdhci-msm-v4";
2028                         reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2029                         reg-names = "hc_mem", "core_mem";
2030
2031                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2032                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2033                         interrupt-names = "hc_irq", "pwr_irq";
2034
2035                         clock-names = "iface", "core", "xo";
2036                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2037                                  <&gcc GCC_SDCC2_APPS_CLK>,
2038                                  <&xo>;
2039                         bus-width = <4>;
2040                         status = "disabled";
2041                 };
2042
2043                 blsp1_dma: dma-controller@c144000 {
2044                         compatible = "qcom,bam-v1.7.0";
2045                         reg = <0x0c144000 0x25000>;
2046                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2047                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2048                         clock-names = "bam_clk";
2049                         #dma-cells = <1>;
2050                         qcom,ee = <0>;
2051                         qcom,controlled-remotely;
2052                         num-channels = <18>;
2053                         qcom,num-ees = <4>;
2054                 };
2055
2056                 blsp1_uart3: serial@c171000 {
2057                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2058                         reg = <0x0c171000 0x1000>;
2059                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2060                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2061                                  <&gcc GCC_BLSP1_AHB_CLK>;
2062                         clock-names = "core", "iface";
2063                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2064                         dma-names = "tx", "rx";
2065                         pinctrl-names = "default";
2066                         pinctrl-0 = <&blsp1_uart3_on>;
2067                         status = "disabled";
2068                 };
2069
2070                 blsp1_i2c1: i2c@c175000 {
2071                         compatible = "qcom,i2c-qup-v2.2.1";
2072                         reg = <0x0c175000 0x600>;
2073                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2074
2075                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2076                                  <&gcc GCC_BLSP1_AHB_CLK>;
2077                         clock-names = "core", "iface";
2078                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2079                         dma-names = "tx", "rx";
2080                         pinctrl-names = "default", "sleep";
2081                         pinctrl-0 = <&blsp1_i2c1_default>;
2082                         pinctrl-1 = <&blsp1_i2c1_sleep>;
2083                         clock-frequency = <400000>;
2084
2085                         status = "disabled";
2086                         #address-cells = <1>;
2087                         #size-cells = <0>;
2088                 };
2089
2090                 blsp1_i2c2: i2c@c176000 {
2091                         compatible = "qcom,i2c-qup-v2.2.1";
2092                         reg = <0x0c176000 0x600>;
2093                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2094
2095                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2096                                  <&gcc GCC_BLSP1_AHB_CLK>;
2097                         clock-names = "core", "iface";
2098                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2099                         dma-names = "tx", "rx";
2100                         pinctrl-names = "default", "sleep";
2101                         pinctrl-0 = <&blsp1_i2c2_default>;
2102                         pinctrl-1 = <&blsp1_i2c2_sleep>;
2103                         clock-frequency = <400000>;
2104
2105                         status = "disabled";
2106                         #address-cells = <1>;
2107                         #size-cells = <0>;
2108                 };
2109
2110                 blsp1_i2c3: i2c@c177000 {
2111                         compatible = "qcom,i2c-qup-v2.2.1";
2112                         reg = <0x0c177000 0x600>;
2113                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2114
2115                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2116                                  <&gcc GCC_BLSP1_AHB_CLK>;
2117                         clock-names = "core", "iface";
2118                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2119                         dma-names = "tx", "rx";
2120                         pinctrl-names = "default", "sleep";
2121                         pinctrl-0 = <&blsp1_i2c3_default>;
2122                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2123                         clock-frequency = <400000>;
2124
2125                         status = "disabled";
2126                         #address-cells = <1>;
2127                         #size-cells = <0>;
2128                 };
2129
2130                 blsp1_i2c4: i2c@c178000 {
2131                         compatible = "qcom,i2c-qup-v2.2.1";
2132                         reg = <0x0c178000 0x600>;
2133                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2134
2135                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2136                                  <&gcc GCC_BLSP1_AHB_CLK>;
2137                         clock-names = "core", "iface";
2138                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2139                         dma-names = "tx", "rx";
2140                         pinctrl-names = "default", "sleep";
2141                         pinctrl-0 = <&blsp1_i2c4_default>;
2142                         pinctrl-1 = <&blsp1_i2c4_sleep>;
2143                         clock-frequency = <400000>;
2144
2145                         status = "disabled";
2146                         #address-cells = <1>;
2147                         #size-cells = <0>;
2148                 };
2149
2150                 blsp1_i2c5: i2c@c179000 {
2151                         compatible = "qcom,i2c-qup-v2.2.1";
2152                         reg = <0x0c179000 0x600>;
2153                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2154
2155                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2156                                  <&gcc GCC_BLSP1_AHB_CLK>;
2157                         clock-names = "core", "iface";
2158                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2159                         dma-names = "tx", "rx";
2160                         pinctrl-names = "default", "sleep";
2161                         pinctrl-0 = <&blsp1_i2c5_default>;
2162                         pinctrl-1 = <&blsp1_i2c5_sleep>;
2163                         clock-frequency = <400000>;
2164
2165                         status = "disabled";
2166                         #address-cells = <1>;
2167                         #size-cells = <0>;
2168                 };
2169
2170                 blsp1_i2c6: i2c@c17a000 {
2171                         compatible = "qcom,i2c-qup-v2.2.1";
2172                         reg = <0x0c17a000 0x600>;
2173                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2174
2175                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2176                                  <&gcc GCC_BLSP1_AHB_CLK>;
2177                         clock-names = "core", "iface";
2178                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2179                         dma-names = "tx", "rx";
2180                         pinctrl-names = "default", "sleep";
2181                         pinctrl-0 = <&blsp1_i2c6_default>;
2182                         pinctrl-1 = <&blsp1_i2c6_sleep>;
2183                         clock-frequency = <400000>;
2184
2185                         status = "disabled";
2186                         #address-cells = <1>;
2187                         #size-cells = <0>;
2188                 };
2189
2190                 blsp2_dma: dma@c184000 {
2191                         compatible = "qcom,bam-v1.7.0";
2192                         reg = <0x0c184000 0x25000>;
2193                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2194                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2195                         clock-names = "bam_clk";
2196                         #dma-cells = <1>;
2197                         qcom,ee = <0>;
2198                         qcom,controlled-remotely;
2199                         num-channels = <18>;
2200                         qcom,num-ees = <4>;
2201                 };
2202
2203                 blsp2_uart1: serial@c1b0000 {
2204                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2205                         reg = <0x0c1b0000 0x1000>;
2206                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2207                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2208                                  <&gcc GCC_BLSP2_AHB_CLK>;
2209                         clock-names = "core", "iface";
2210                         status = "disabled";
2211                 };
2212
2213                 blsp2_i2c1: i2c@c1b5000 {
2214                         compatible = "qcom,i2c-qup-v2.2.1";
2215                         reg = <0x0c1b5000 0x600>;
2216                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2217
2218                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2219                                  <&gcc GCC_BLSP2_AHB_CLK>;
2220                         clock-names = "core", "iface";
2221                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2222                         dma-names = "tx", "rx";
2223                         pinctrl-names = "default", "sleep";
2224                         pinctrl-0 = <&blsp2_i2c1_default>;
2225                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2226                         clock-frequency = <400000>;
2227
2228                         status = "disabled";
2229                         #address-cells = <1>;
2230                         #size-cells = <0>;
2231                 };
2232
2233                 blsp2_i2c2: i2c@c1b6000 {
2234                         compatible = "qcom,i2c-qup-v2.2.1";
2235                         reg = <0x0c1b6000 0x600>;
2236                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2237
2238                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2239                                  <&gcc GCC_BLSP2_AHB_CLK>;
2240                         clock-names = "core", "iface";
2241                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2242                         dma-names = "tx", "rx";
2243                         pinctrl-names = "default", "sleep";
2244                         pinctrl-0 = <&blsp2_i2c2_default>;
2245                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2246                         clock-frequency = <400000>;
2247
2248                         status = "disabled";
2249                         #address-cells = <1>;
2250                         #size-cells = <0>;
2251                 };
2252
2253                 blsp2_i2c3: i2c@c1b7000 {
2254                         compatible = "qcom,i2c-qup-v2.2.1";
2255                         reg = <0x0c1b7000 0x600>;
2256                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2257
2258                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2259                                  <&gcc GCC_BLSP2_AHB_CLK>;
2260                         clock-names = "core", "iface";
2261                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2262                         dma-names = "tx", "rx";
2263                         pinctrl-names = "default", "sleep";
2264                         pinctrl-0 = <&blsp2_i2c3_default>;
2265                         pinctrl-1 = <&blsp2_i2c3_sleep>;
2266                         clock-frequency = <400000>;
2267
2268                         status = "disabled";
2269                         #address-cells = <1>;
2270                         #size-cells = <0>;
2271                 };
2272
2273                 blsp2_i2c4: i2c@c1b8000 {
2274                         compatible = "qcom,i2c-qup-v2.2.1";
2275                         reg = <0x0c1b8000 0x600>;
2276                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2277
2278                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2279                                  <&gcc GCC_BLSP2_AHB_CLK>;
2280                         clock-names = "core", "iface";
2281                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2282                         dma-names = "tx", "rx";
2283                         pinctrl-names = "default", "sleep";
2284                         pinctrl-0 = <&blsp2_i2c4_default>;
2285                         pinctrl-1 = <&blsp2_i2c4_sleep>;
2286                         clock-frequency = <400000>;
2287
2288                         status = "disabled";
2289                         #address-cells = <1>;
2290                         #size-cells = <0>;
2291                 };
2292
2293                 blsp2_i2c5: i2c@c1b9000 {
2294                         compatible = "qcom,i2c-qup-v2.2.1";
2295                         reg = <0x0c1b9000 0x600>;
2296                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2297
2298                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2299                                  <&gcc GCC_BLSP2_AHB_CLK>;
2300                         clock-names = "core", "iface";
2301                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2302                         dma-names = "tx", "rx";
2303                         pinctrl-names = "default", "sleep";
2304                         pinctrl-0 = <&blsp2_i2c5_default>;
2305                         pinctrl-1 = <&blsp2_i2c5_sleep>;
2306                         clock-frequency = <400000>;
2307
2308                         status = "disabled";
2309                         #address-cells = <1>;
2310                         #size-cells = <0>;
2311                 };
2312
2313                 blsp2_i2c6: i2c@c1ba000 {
2314                         compatible = "qcom,i2c-qup-v2.2.1";
2315                         reg = <0x0c1ba000 0x600>;
2316                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2317
2318                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2319                                  <&gcc GCC_BLSP2_AHB_CLK>;
2320                         clock-names = "core", "iface";
2321                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2322                         dma-names = "tx", "rx";
2323                         pinctrl-names = "default", "sleep";
2324                         pinctrl-0 = <&blsp2_i2c6_default>;
2325                         pinctrl-1 = <&blsp2_i2c6_sleep>;
2326                         clock-frequency = <400000>;
2327
2328                         status = "disabled";
2329                         #address-cells = <1>;
2330                         #size-cells = <0>;
2331                 };
2332
2333                 remoteproc_adsp: remoteproc@17300000 {
2334                         compatible = "qcom,msm8998-adsp-pas";
2335                         reg = <0x17300000 0x4040>;
2336
2337                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2338                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2339                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2340                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2341                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2342                         interrupt-names = "wdog", "fatal", "ready",
2343                                           "handover", "stop-ack";
2344
2345                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2346                         clock-names = "xo";
2347
2348                         memory-region = <&adsp_mem>;
2349
2350                         qcom,smem-states = <&adsp_smp2p_out 0>;
2351                         qcom,smem-state-names = "stop";
2352
2353                         power-domains = <&rpmpd MSM8998_VDDCX>;
2354                         power-domain-names = "cx";
2355
2356                         status = "disabled";
2357
2358                         glink-edge {
2359                                 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2360                                 label = "lpass";
2361                                 qcom,remote-pid = <2>;
2362                                 mboxes = <&apcs_glb 9>;
2363                         };
2364                 };
2365
2366                 apcs_glb: mailbox@17911000 {
2367                         compatible = "qcom,msm8998-apcs-hmss-global";
2368                         reg = <0x17911000 0x1000>;
2369
2370                         #mbox-cells = <1>;
2371                 };
2372
2373                 timer@17920000 {
2374                         #address-cells = <1>;
2375                         #size-cells = <1>;
2376                         ranges;
2377                         compatible = "arm,armv7-timer-mem";
2378                         reg = <0x17920000 0x1000>;
2379
2380                         frame@17921000 {
2381                                 frame-number = <0>;
2382                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2383                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2384                                 reg = <0x17921000 0x1000>,
2385                                       <0x17922000 0x1000>;
2386                         };
2387
2388                         frame@17923000 {
2389                                 frame-number = <1>;
2390                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2391                                 reg = <0x17923000 0x1000>;
2392                                 status = "disabled";
2393                         };
2394
2395                         frame@17924000 {
2396                                 frame-number = <2>;
2397                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2398                                 reg = <0x17924000 0x1000>;
2399                                 status = "disabled";
2400                         };
2401
2402                         frame@17925000 {
2403                                 frame-number = <3>;
2404                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2405                                 reg = <0x17925000 0x1000>;
2406                                 status = "disabled";
2407                         };
2408
2409                         frame@17926000 {
2410                                 frame-number = <4>;
2411                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2412                                 reg = <0x17926000 0x1000>;
2413                                 status = "disabled";
2414                         };
2415
2416                         frame@17927000 {
2417                                 frame-number = <5>;
2418                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2419                                 reg = <0x17927000 0x1000>;
2420                                 status = "disabled";
2421                         };
2422
2423                         frame@17928000 {
2424                                 frame-number = <6>;
2425                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2426                                 reg = <0x17928000 0x1000>;
2427                                 status = "disabled";
2428                         };
2429                 };
2430
2431                 intc: interrupt-controller@17a00000 {
2432                         compatible = "arm,gic-v3";
2433                         reg = <0x17a00000 0x10000>,       /* GICD */
2434                               <0x17b00000 0x100000>;      /* GICR * 8 */
2435                         #interrupt-cells = <3>;
2436                         #address-cells = <1>;
2437                         #size-cells = <1>;
2438                         ranges;
2439                         interrupt-controller;
2440                         #redistributor-regions = <1>;
2441                         redistributor-stride = <0x0 0x20000>;
2442                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2443                 };
2444
2445                 wifi: wifi@18800000 {
2446                         compatible = "qcom,wcn3990-wifi";
2447                         status = "disabled";
2448                         reg = <0x18800000 0x800000>;
2449                         reg-names = "membase";
2450                         memory-region = <&wlan_msa_mem>;
2451                         clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
2452                         clock-names = "cxo_ref_clk_pin";
2453                         interrupts =
2454                                 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2455                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2456                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2457                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2458                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2459                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2460                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2461                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2462                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2463                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2464                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2465                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2466                         iommus = <&anoc2_smmu 0x1900>,
2467                                  <&anoc2_smmu 0x1901>;
2468                         qcom,snoc-host-cap-8bit-quirk;
2469                 };
2470         };
2471 };