1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,apr.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
23 compatible = "fixed-clock";
25 clock-frequency = <19200000>;
26 clock-output-names = "xo_board";
29 sleep_clk: sleep-clk {
30 compatible = "fixed-clock";
32 clock-frequency = <32764>;
33 clock-output-names = "sleep_clk";
43 compatible = "qcom,kryo";
45 enable-method = "psci";
46 cpu-idle-states = <&CPU_SLEEP_0>;
47 capacity-dmips-mhz = <1024>;
49 operating-points-v2 = <&cluster0_opp>;
51 next-level-cache = <&L2_0>;
60 compatible = "qcom,kryo";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
64 capacity-dmips-mhz = <1024>;
66 operating-points-v2 = <&cluster0_opp>;
68 next-level-cache = <&L2_0>;
73 compatible = "qcom,kryo";
75 enable-method = "psci";
76 cpu-idle-states = <&CPU_SLEEP_0>;
77 capacity-dmips-mhz = <1024>;
79 operating-points-v2 = <&cluster1_opp>;
81 next-level-cache = <&L2_1>;
90 compatible = "qcom,kryo";
92 enable-method = "psci";
93 cpu-idle-states = <&CPU_SLEEP_0>;
94 capacity-dmips-mhz = <1024>;
96 operating-points-v2 = <&cluster1_opp>;
98 next-level-cache = <&L2_1>;
124 entry-method = "psci";
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 idle-state-name = "standalone-power-collapse";
129 arm,psci-suspend-param = <0x00000004>;
130 entry-latency-us = <130>;
131 exit-latency-us = <80>;
132 min-residency-us = <300>;
137 cluster0_opp: opp_table0 {
138 compatible = "operating-points-v2-kryo-cpu";
139 nvmem-cells = <&speedbin_efuse>;
142 /* Nominal fmax for now */
144 opp-hz = /bits/ 64 <307200000>;
145 opp-supported-hw = <0x77>;
146 clock-latency-ns = <200000>;
149 opp-hz = /bits/ 64 <422400000>;
150 opp-supported-hw = <0x77>;
151 clock-latency-ns = <200000>;
154 opp-hz = /bits/ 64 <480000000>;
155 opp-supported-hw = <0x77>;
156 clock-latency-ns = <200000>;
159 opp-hz = /bits/ 64 <556800000>;
160 opp-supported-hw = <0x77>;
161 clock-latency-ns = <200000>;
164 opp-hz = /bits/ 64 <652800000>;
165 opp-supported-hw = <0x77>;
166 clock-latency-ns = <200000>;
169 opp-hz = /bits/ 64 <729600000>;
170 opp-supported-hw = <0x77>;
171 clock-latency-ns = <200000>;
174 opp-hz = /bits/ 64 <844800000>;
175 opp-supported-hw = <0x77>;
176 clock-latency-ns = <200000>;
179 opp-hz = /bits/ 64 <960000000>;
180 opp-supported-hw = <0x77>;
181 clock-latency-ns = <200000>;
184 opp-hz = /bits/ 64 <1036800000>;
185 opp-supported-hw = <0x77>;
186 clock-latency-ns = <200000>;
189 opp-hz = /bits/ 64 <1113600000>;
190 opp-supported-hw = <0x77>;
191 clock-latency-ns = <200000>;
194 opp-hz = /bits/ 64 <1190400000>;
195 opp-supported-hw = <0x77>;
196 clock-latency-ns = <200000>;
199 opp-hz = /bits/ 64 <1228800000>;
200 opp-supported-hw = <0x77>;
201 clock-latency-ns = <200000>;
204 opp-hz = /bits/ 64 <1324800000>;
205 opp-supported-hw = <0x77>;
206 clock-latency-ns = <200000>;
209 opp-hz = /bits/ 64 <1401600000>;
210 opp-supported-hw = <0x77>;
211 clock-latency-ns = <200000>;
214 opp-hz = /bits/ 64 <1478400000>;
215 opp-supported-hw = <0x77>;
216 clock-latency-ns = <200000>;
219 opp-hz = /bits/ 64 <1593600000>;
220 opp-supported-hw = <0x77>;
221 clock-latency-ns = <200000>;
225 cluster1_opp: opp_table1 {
226 compatible = "operating-points-v2-kryo-cpu";
227 nvmem-cells = <&speedbin_efuse>;
230 /* Nominal fmax for now */
232 opp-hz = /bits/ 64 <307200000>;
233 opp-supported-hw = <0x77>;
234 clock-latency-ns = <200000>;
237 opp-hz = /bits/ 64 <403200000>;
238 opp-supported-hw = <0x77>;
239 clock-latency-ns = <200000>;
242 opp-hz = /bits/ 64 <480000000>;
243 opp-supported-hw = <0x77>;
244 clock-latency-ns = <200000>;
247 opp-hz = /bits/ 64 <556800000>;
248 opp-supported-hw = <0x77>;
249 clock-latency-ns = <200000>;
252 opp-hz = /bits/ 64 <652800000>;
253 opp-supported-hw = <0x77>;
254 clock-latency-ns = <200000>;
257 opp-hz = /bits/ 64 <729600000>;
258 opp-supported-hw = <0x77>;
259 clock-latency-ns = <200000>;
262 opp-hz = /bits/ 64 <806400000>;
263 opp-supported-hw = <0x77>;
264 clock-latency-ns = <200000>;
267 opp-hz = /bits/ 64 <883200000>;
268 opp-supported-hw = <0x77>;
269 clock-latency-ns = <200000>;
272 opp-hz = /bits/ 64 <940800000>;
273 opp-supported-hw = <0x77>;
274 clock-latency-ns = <200000>;
277 opp-hz = /bits/ 64 <1036800000>;
278 opp-supported-hw = <0x77>;
279 clock-latency-ns = <200000>;
282 opp-hz = /bits/ 64 <1113600000>;
283 opp-supported-hw = <0x77>;
284 clock-latency-ns = <200000>;
287 opp-hz = /bits/ 64 <1190400000>;
288 opp-supported-hw = <0x77>;
289 clock-latency-ns = <200000>;
292 opp-hz = /bits/ 64 <1248000000>;
293 opp-supported-hw = <0x77>;
294 clock-latency-ns = <200000>;
297 opp-hz = /bits/ 64 <1324800000>;
298 opp-supported-hw = <0x77>;
299 clock-latency-ns = <200000>;
302 opp-hz = /bits/ 64 <1401600000>;
303 opp-supported-hw = <0x77>;
304 clock-latency-ns = <200000>;
307 opp-hz = /bits/ 64 <1478400000>;
308 opp-supported-hw = <0x77>;
309 clock-latency-ns = <200000>;
312 opp-hz = /bits/ 64 <1555200000>;
313 opp-supported-hw = <0x77>;
314 clock-latency-ns = <200000>;
317 opp-hz = /bits/ 64 <1632000000>;
318 opp-supported-hw = <0x77>;
319 clock-latency-ns = <200000>;
322 opp-hz = /bits/ 64 <1708800000>;
323 opp-supported-hw = <0x77>;
324 clock-latency-ns = <200000>;
327 opp-hz = /bits/ 64 <1785600000>;
328 opp-supported-hw = <0x77>;
329 clock-latency-ns = <200000>;
332 opp-hz = /bits/ 64 <1824000000>;
333 opp-supported-hw = <0x77>;
334 clock-latency-ns = <200000>;
337 opp-hz = /bits/ 64 <1920000000>;
338 opp-supported-hw = <0x77>;
339 clock-latency-ns = <200000>;
342 opp-hz = /bits/ 64 <1996800000>;
343 opp-supported-hw = <0x77>;
344 clock-latency-ns = <200000>;
347 opp-hz = /bits/ 64 <2073600000>;
348 opp-supported-hw = <0x77>;
349 clock-latency-ns = <200000>;
352 opp-hz = /bits/ 64 <2150400000>;
353 opp-supported-hw = <0x77>;
354 clock-latency-ns = <200000>;
360 compatible = "qcom,scm-msm8996";
361 qcom,dload-mode = <&tcsr 0x13000>;
366 compatible = "qcom,tcsr-mutex";
367 syscon = <&tcsr_mutex_regs 0 0x1000>;
372 device_type = "memory";
373 /* We expect the bootloader to fill in the reg */
374 reg = <0x0 0x80000000 0x0 0x0>;
378 compatible = "arm,psci-1.0";
383 #address-cells = <2>;
387 mba_region: mba@91500000 {
388 reg = <0x0 0x91500000 0x0 0x200000>;
392 slpi_region: slpi@90b00000 {
393 reg = <0x0 0x90b00000 0x0 0xa00000>;
397 venus_region: venus@90400000 {
398 reg = <0x0 0x90400000 0x0 0x700000>;
402 adsp_region: adsp@8ea00000 {
403 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
407 mpss_region: mpss@88800000 {
408 reg = <0x0 0x88800000 0x0 0x6200000>;
412 smem_mem: smem-mem@86000000 {
413 reg = <0x0 0x86000000 0x0 0x200000>;
418 reg = <0x0 0x85800000 0x0 0x800000>;
423 reg = <0x0 0x86200000 0x0 0x2600000>;
428 compatible = "qcom,rmtfs-mem";
430 size = <0x0 0x200000>;
431 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
434 qcom,client-id = <1>;
438 zap_shader_region: gpu@8f200000 {
439 compatible = "shared-dma-pool";
440 reg = <0x0 0x90b00000 0x0 0xa00000>;
446 compatible = "qcom,glink-rpm";
448 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
450 qcom,rpm-msg-ram = <&rpm_msg_ram>;
452 mboxes = <&apcs_glb 0>;
454 rpm_requests: rpm-requests {
455 compatible = "qcom,rpm-msm8996";
456 qcom,glink-channels = "rpm_requests";
459 compatible = "qcom,rpmcc-msm8996";
463 rpmpd: power-controller {
464 compatible = "qcom,msm8996-rpmpd";
465 #power-domain-cells = <1>;
466 operating-points-v2 = <&rpmpd_opp_table>;
468 rpmpd_opp_table: opp-table {
469 compatible = "operating-points-v2";
500 compatible = "qcom,smem";
501 memory-region = <&smem_mem>;
502 hwlocks = <&tcsr_mutex 3>;
506 compatible = "qcom,smp2p";
507 qcom,smem = <443>, <429>;
509 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
511 mboxes = <&apcs_glb 10>;
513 qcom,local-pid = <0>;
514 qcom,remote-pid = <2>;
516 smp2p_adsp_out: master-kernel {
517 qcom,entry-name = "master-kernel";
518 #qcom,smem-state-cells = <1>;
521 smp2p_adsp_in: slave-kernel {
522 qcom,entry-name = "slave-kernel";
524 interrupt-controller;
525 #interrupt-cells = <2>;
530 compatible = "qcom,smp2p";
531 qcom,smem = <435>, <428>;
533 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
535 mboxes = <&apcs_glb 14>;
537 qcom,local-pid = <0>;
538 qcom,remote-pid = <1>;
540 modem_smp2p_out: master-kernel {
541 qcom,entry-name = "master-kernel";
542 #qcom,smem-state-cells = <1>;
545 modem_smp2p_in: slave-kernel {
546 qcom,entry-name = "slave-kernel";
548 interrupt-controller;
549 #interrupt-cells = <2>;
554 compatible = "qcom,smp2p";
555 qcom,smem = <481>, <430>;
557 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
559 mboxes = <&apcs_glb 26>;
561 qcom,local-pid = <0>;
562 qcom,remote-pid = <3>;
564 smp2p_slpi_in: slave-kernel {
565 qcom,entry-name = "slave-kernel";
566 interrupt-controller;
567 #interrupt-cells = <2>;
570 smp2p_slpi_out: master-kernel {
571 qcom,entry-name = "master-kernel";
572 #qcom,smem-state-cells = <1>;
577 #address-cells = <1>;
579 ranges = <0 0 0 0xffffffff>;
580 compatible = "simple-bus";
582 pcie_phy: phy@34000 {
583 compatible = "qcom,msm8996-qmp-pcie-phy";
584 reg = <0x00034000 0x488>;
586 #address-cells = <1>;
590 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
591 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
592 <&gcc GCC_PCIE_CLKREF_CLK>;
593 clock-names = "aux", "cfg_ahb", "ref";
595 resets = <&gcc GCC_PCIE_PHY_BCR>,
596 <&gcc GCC_PCIE_PHY_COM_BCR>,
597 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
598 reset-names = "phy", "common", "cfg";
601 pciephy_0: lane@35000 {
602 reg = <0x00035000 0x130>,
607 clock-output-names = "pcie_0_pipe_clk_src";
608 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609 clock-names = "pipe0";
610 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611 reset-names = "lane0";
614 pciephy_1: lane@36000 {
615 reg = <0x00036000 0x130>,
620 clock-output-names = "pcie_1_pipe_clk_src";
621 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622 clock-names = "pipe1";
623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624 reset-names = "lane1";
627 pciephy_2: lane@37000 {
628 reg = <0x00037000 0x130>,
633 clock-output-names = "pcie_2_pipe_clk_src";
634 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635 clock-names = "pipe2";
636 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637 reset-names = "lane2";
641 rpm_msg_ram: memory@68000 {
642 compatible = "qcom,rpm-msg-ram";
643 reg = <0x00068000 0x6000>;
647 compatible = "qcom,qfprom";
648 reg = <0x00074000 0x8ff>;
649 #address-cells = <1>;
652 qusb2p_hstx_trim: hstx_trim@24e {
657 qusb2s_hstx_trim: hstx_trim@24f {
662 speedbin_efuse: speedbin@133 {
669 compatible = "qcom,prng-ee";
670 reg = <0x00083000 0x1000>;
671 clocks = <&gcc GCC_PRNG_AHB_CLK>;
672 clock-names = "core";
675 gcc: clock-controller@300000 {
676 compatible = "qcom,gcc-msm8996";
679 #power-domain-cells = <1>;
680 reg = <0x00300000 0x90000>;
682 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
683 clock-names = "cxo2";
686 tsens0: thermal-sensor@4a9000 {
687 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
688 reg = <0x004a9000 0x1000>, /* TM */
689 <0x004a8000 0x1000>; /* SROT */
690 #qcom,sensors = <13>;
691 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-names = "uplow", "critical";
694 #thermal-sensor-cells = <1>;
697 tsens1: thermal-sensor@4ad000 {
698 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
699 reg = <0x004ad000 0x1000>, /* TM */
700 <0x004ac000 0x1000>; /* SROT */
702 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
704 interrupt-names = "uplow", "critical";
705 #thermal-sensor-cells = <1>;
708 tcsr_mutex_regs: syscon@740000 {
709 compatible = "syscon";
710 reg = <0x00740000 0x40000>;
713 tcsr: syscon@7a0000 {
714 compatible = "qcom,tcsr-msm8996", "syscon";
715 reg = <0x007a0000 0x18000>;
718 mmcc: clock-controller@8c0000 {
719 compatible = "qcom,mmcc-msm8996";
722 #power-domain-cells = <1>;
723 reg = <0x008c0000 0x40000>;
724 assigned-clocks = <&mmcc MMPLL9_PLL>,
729 assigned-clock-rates = <624000000>,
737 compatible = "qcom,mdss";
739 reg = <0x00900000 0x1000>,
742 reg-names = "mdss_phys",
746 power-domains = <&mmcc MDSS_GDSC>;
747 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
749 interrupt-controller;
750 #interrupt-cells = <1>;
752 clocks = <&mmcc MDSS_AHB_CLK>;
753 clock-names = "iface";
755 #address-cells = <1>;
762 compatible = "qcom,mdp5";
763 reg = <0x00901000 0x90000>;
764 reg-names = "mdp_phys";
766 interrupt-parent = <&mdss>;
767 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&mmcc MDSS_AHB_CLK>,
770 <&mmcc MDSS_AXI_CLK>,
771 <&mmcc MDSS_MDP_CLK>,
772 <&mmcc SMMU_MDP_AXI_CLK>,
773 <&mmcc MDSS_VSYNC_CLK>;
774 clock-names = "iface",
780 iommus = <&mdp_smmu 0>;
782 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
783 <&mmcc MDSS_VSYNC_CLK>;
784 assigned-clock-rates = <300000000>,
788 #address-cells = <1>;
793 mdp5_intf3_out: endpoint {
794 remote-endpoint = <&hdmi_in>;
800 mdp5_intf1_out: endpoint {
801 remote-endpoint = <&dsi0_in>;
808 compatible = "qcom,mdss-dsi-ctrl";
809 reg = <0x00994000 0x400>;
810 reg-names = "dsi_ctrl";
812 interrupt-parent = <&mdss>;
813 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&mmcc MDSS_MDP_CLK>,
816 <&mmcc MDSS_BYTE0_CLK>,
817 <&mmcc MDSS_AHB_CLK>,
818 <&mmcc MDSS_AXI_CLK>,
819 <&mmcc MMSS_MISC_AHB_CLK>,
820 <&mmcc MDSS_PCLK0_CLK>,
821 <&mmcc MDSS_ESC0_CLK>;
822 clock-names = "mdp_core",
834 #address-cells = <1>;
838 #address-cells = <1>;
844 remote-endpoint = <&mdp5_intf1_out>;
856 dsi0_phy: dsi-phy@994400 {
857 compatible = "qcom,dsi-phy-14nm";
858 reg = <0x00994400 0x100>,
861 reg-names = "dsi_phy",
868 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
869 clock-names = "iface", "ref";
873 hdmi: hdmi-tx@9a0000 {
874 compatible = "qcom,hdmi-tx-8996";
875 reg = <0x009a0000 0x50c>,
878 reg-names = "core_physical",
882 interrupt-parent = <&mdss>;
883 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&mmcc MDSS_MDP_CLK>,
886 <&mmcc MDSS_AHB_CLK>,
887 <&mmcc MDSS_HDMI_CLK>,
888 <&mmcc MDSS_HDMI_AHB_CLK>,
889 <&mmcc MDSS_EXTPCLK_CLK>;
898 phy-names = "hdmi_phy";
899 #sound-dai-cells = <1>;
904 #address-cells = <1>;
910 remote-endpoint = <&mdp5_intf3_out>;
916 hdmi_phy: hdmi-phy@9a0600 {
918 compatible = "qcom,hdmi-phy-8996";
919 reg = <0x009a0600 0x1c4>,
925 reg-names = "hdmi_pll",
932 clocks = <&mmcc MDSS_AHB_CLK>,
933 <&gcc GCC_HDMI_CLKREF_CLK>;
934 clock-names = "iface",
942 compatible = "qcom,adreno-530.2", "qcom,adreno";
943 #stream-id-cells = <16>;
945 reg = <0x00b00000 0x3f000>;
946 reg-names = "kgsl_3d0_reg_memory";
948 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
952 <&mmcc GPU_GX_RBBMTIMER_CLK>,
953 <&gcc GCC_BIMC_GFX_CLK>,
954 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
956 clock-names = "core",
962 power-domains = <&mmcc GPU_GX_GDSC>;
963 iommus = <&adreno_smmu 0>;
965 nvmem-cells = <&speedbin_efuse>;
966 nvmem-cell-names = "speed_bin";
968 qcom,gpu-quirk-two-pass-use-wfi;
969 qcom,gpu-quirk-fault-detect-mask;
971 operating-points-v2 = <&gpu_opp_table>;
975 #cooling-cells = <2>;
977 gpu_opp_table: opp-table {
978 compatible ="operating-points-v2";
981 * 624Mhz and 560Mhz are only available on speed
982 * bin (1 << 0). All the rest are available on
983 * all bins of the hardware
986 opp-hz = /bits/ 64 <624000000>;
987 opp-supported-hw = <0x01>;
990 opp-hz = /bits/ 64 <560000000>;
991 opp-supported-hw = <0x01>;
994 opp-hz = /bits/ 64 <510000000>;
995 opp-supported-hw = <0xFF>;
998 opp-hz = /bits/ 64 <401800000>;
999 opp-supported-hw = <0xFF>;
1002 opp-hz = /bits/ 64 <315000000>;
1003 opp-supported-hw = <0xFF>;
1006 opp-hz = /bits/ 64 <214000000>;
1007 opp-supported-hw = <0xFF>;
1010 opp-hz = /bits/ 64 <133000000>;
1011 opp-supported-hw = <0xFF>;
1016 memory-region = <&zap_shader_region>;
1020 tlmm: pinctrl@1010000 {
1021 compatible = "qcom,msm8996-pinctrl";
1022 reg = <0x01010000 0x300000>;
1023 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1025 gpio-ranges = <&tlmm 0 0 150>;
1027 interrupt-controller;
1028 #interrupt-cells = <2>;
1030 blsp1_spi1_default: blsp1-spi1-default {
1032 pins = "gpio0", "gpio1", "gpio3";
1033 function = "blsp_spi1";
1034 drive-strength = <12>;
1041 drive-strength = <16>;
1047 blsp1_spi1_sleep: blsp1-spi1-sleep {
1048 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1050 drive-strength = <2>;
1054 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1055 pins = "gpio4", "gpio5";
1056 function = "blsp_uart8";
1057 drive-strength = <16>;
1061 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1062 pins = "gpio4", "gpio5";
1064 drive-strength = <2>;
1068 blsp2_i2c2_default: blsp2-i2c2 {
1069 pins = "gpio6", "gpio7";
1070 function = "blsp_i2c8";
1071 drive-strength = <16>;
1075 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1076 pins = "gpio6", "gpio7";
1078 drive-strength = <2>;
1082 cci0_default: cci0-default {
1083 pins = "gpio17", "gpio18";
1084 function = "cci_i2c";
1085 drive-strength = <16>;
1090 camera_rear_default: camera-rear-default {
1091 camera0_mclk: mclk0 {
1093 function = "cam_mclk";
1094 drive-strength = <16>;
1101 drive-strength = <16>;
1105 camera0_pwdn: pwdn {
1108 drive-strength = <16>;
1113 cci1_default: cci1-default {
1114 pins = "gpio19", "gpio20";
1115 function = "cci_i2c";
1116 drive-strength = <16>;
1121 camera_board_default: camera-board-default {
1124 function = "cam_mclk";
1125 drive-strength = <16>;
1132 drive-strength = <16>;
1139 drive-strength = <16>;
1145 camera_front_default: camera-front-default {
1146 camera2_mclk: mclk2 {
1148 function = "cam_mclk";
1149 drive-strength = <16>;
1156 drive-strength = <16>;
1163 drive-strength = <16>;
1168 pcie0_state_on: pcie0-state-on {
1172 drive-strength = <2>;
1178 function = "pci_e0";
1179 drive-strength = <2>;
1186 drive-strength = <2>;
1191 pcie0_state_off: pcie0-state-off {
1195 drive-strength = <2>;
1202 drive-strength = <2>;
1209 drive-strength = <2>;
1214 blsp1_i2c3_default: blsp1-i2c2-default {
1215 pins = "gpio47", "gpio48";
1216 function = "blsp_i2c3";
1217 drive-strength = <16>;
1221 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1222 pins = "gpio47", "gpio48";
1224 drive-strength = <2>;
1228 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1229 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1230 function = "blsp_uart9";
1231 drive-strength = <16>;
1235 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1236 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1237 function = "blsp_uart9";
1238 drive-strength = <2>;
1242 wcd_intr_default: wcd-intr-default{
1245 drive-strength = <2>;
1250 blsp2_i2c1_default: blsp2-i2c1 {
1251 pins = "gpio55", "gpio56";
1252 function = "blsp_i2c7";
1253 drive-strength = <16>;
1257 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1258 pins = "gpio55", "gpio56";
1260 drive-strength = <2>;
1264 blsp2_i2c5_default: blsp2-i2c5 {
1265 pins = "gpio60", "gpio61";
1266 function = "blsp_i2c11";
1267 drive-strength = <2>;
1271 /* Sleep state for BLSP2_I2C5 is missing.. */
1273 cdc_reset_active: cdc-reset-active {
1276 drive-strength = <16>;
1281 cdc_reset_sleep: cdc-reset-sleep {
1284 drive-strength = <16>;
1289 blsp2_spi6_default: blsp2-spi5-default {
1291 pins = "gpio85", "gpio86", "gpio88";
1292 function = "blsp_spi12";
1293 drive-strength = <12>;
1300 drive-strength = <16>;
1306 blsp2_spi6_sleep: blsp2-spi5-sleep {
1307 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1309 drive-strength = <2>;
1313 blsp2_i2c6_default: blsp2-i2c6 {
1314 pins = "gpio87", "gpio88";
1315 function = "blsp_i2c12";
1316 drive-strength = <16>;
1320 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1321 pins = "gpio87", "gpio88";
1323 drive-strength = <2>;
1327 pcie1_state_on: pcie1-state-on {
1331 drive-strength = <2>;
1337 function = "pci_e1";
1338 drive-strength = <2>;
1345 drive-strength = <2>;
1350 pcie1_state_off: pcie1-state-off {
1351 /* Perst is missing? */
1355 drive-strength = <2>;
1362 drive-strength = <2>;
1367 pcie2_state_on: pcie2-state-on {
1371 drive-strength = <2>;
1377 function = "pci_e2";
1378 drive-strength = <2>;
1385 drive-strength = <2>;
1390 pcie2_state_off: pcie2-state-off {
1391 /* Perst is missing? */
1395 drive-strength = <2>;
1402 drive-strength = <2>;
1407 sdc1_state_on: sdc1-state-on {
1411 drive-strength = <16>;
1417 drive-strength = <10>;
1423 drive-strength = <10>;
1432 sdc1_state_off: sdc1-state-off {
1436 drive-strength = <2>;
1442 drive-strength = <2>;
1448 drive-strength = <2>;
1457 sdc2_state_on: sdc2-clk-on {
1461 drive-strength = <16>;
1467 drive-strength = <10>;
1473 drive-strength = <10>;
1477 sdc2_state_off: sdc2-clk-off {
1481 drive-strength = <2>;
1487 drive-strength = <2>;
1493 drive-strength = <2>;
1498 spmi_bus: qcom,spmi@400f000 {
1499 compatible = "qcom,spmi-pmic-arb";
1500 reg = <0x0400f000 0x1000>,
1501 <0x04400000 0x800000>,
1502 <0x04c00000 0x800000>,
1503 <0x05800000 0x200000>,
1504 <0x0400a000 0x002100>;
1505 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1506 interrupt-names = "periph_irq";
1507 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1510 #address-cells = <2>;
1512 interrupt-controller;
1513 #interrupt-cells = <4>;
1517 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1518 compatible = "simple-pm-bus";
1519 #address-cells = <1>;
1523 pcie0: pcie@600000 {
1524 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1525 status = "disabled";
1526 power-domains = <&gcc PCIE0_GDSC>;
1527 bus-range = <0x00 0xff>;
1530 reg = <0x00600000 0x2000>,
1533 <0x0c100000 0x100000>;
1534 reg-names = "parf", "dbi", "elbi","config";
1536 phys = <&pciephy_0>;
1537 phy-names = "pciephy";
1539 #address-cells = <3>;
1541 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1542 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1544 device_type = "pci";
1546 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1547 interrupt-names = "msi";
1548 #interrupt-cells = <1>;
1549 interrupt-map-mask = <0 0 0 0x7>;
1550 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1551 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1552 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1553 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1555 pinctrl-names = "default", "sleep";
1556 pinctrl-0 = <&pcie0_state_on>;
1557 pinctrl-1 = <&pcie0_state_off>;
1559 linux,pci-domain = <0>;
1561 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1562 <&gcc GCC_PCIE_0_AUX_CLK>,
1563 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1564 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1565 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1567 clock-names = "pipe",
1575 pcie1: pcie@608000 {
1576 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1577 power-domains = <&gcc PCIE1_GDSC>;
1578 bus-range = <0x00 0xff>;
1581 status = "disabled";
1583 reg = <0x00608000 0x2000>,
1586 <0x0d100000 0x100000>;
1588 reg-names = "parf", "dbi", "elbi","config";
1590 phys = <&pciephy_1>;
1591 phy-names = "pciephy";
1593 #address-cells = <3>;
1595 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1596 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1598 device_type = "pci";
1600 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1601 interrupt-names = "msi";
1602 #interrupt-cells = <1>;
1603 interrupt-map-mask = <0 0 0 0x7>;
1604 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1605 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1606 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1607 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1609 pinctrl-names = "default", "sleep";
1610 pinctrl-0 = <&pcie1_state_on>;
1611 pinctrl-1 = <&pcie1_state_off>;
1613 linux,pci-domain = <1>;
1615 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1616 <&gcc GCC_PCIE_1_AUX_CLK>,
1617 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1618 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1619 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1621 clock-names = "pipe",
1628 pcie2: pcie@610000 {
1629 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1630 power-domains = <&gcc PCIE2_GDSC>;
1631 bus-range = <0x00 0xff>;
1633 status = "disabled";
1634 reg = <0x00610000 0x2000>,
1637 <0x0e100000 0x100000>;
1639 reg-names = "parf", "dbi", "elbi","config";
1641 phys = <&pciephy_2>;
1642 phy-names = "pciephy";
1644 #address-cells = <3>;
1646 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1647 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1649 device_type = "pci";
1651 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1652 interrupt-names = "msi";
1653 #interrupt-cells = <1>;
1654 interrupt-map-mask = <0 0 0 0x7>;
1655 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1656 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1657 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1658 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1660 pinctrl-names = "default", "sleep";
1661 pinctrl-0 = <&pcie2_state_on>;
1662 pinctrl-1 = <&pcie2_state_off>;
1664 linux,pci-domain = <2>;
1665 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1666 <&gcc GCC_PCIE_2_AUX_CLK>,
1667 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1668 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1669 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1671 clock-names = "pipe",
1679 ufshc: ufshc@624000 {
1680 compatible = "qcom,ufshc";
1681 reg = <0x00624000 0x2500>;
1682 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1684 phys = <&ufsphy_lane>;
1685 phy-names = "ufsphy";
1687 power-domains = <&gcc UFS_GDSC>;
1695 "core_clk_unipro_src",
1699 "tx_lane0_sync_clk",
1700 "rx_lane0_sync_clk";
1702 <&gcc UFS_AXI_CLK_SRC>,
1703 <&gcc GCC_UFS_AXI_CLK>,
1704 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1705 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1706 <&gcc GCC_UFS_AHB_CLK>,
1707 <&gcc UFS_ICE_CORE_CLK_SRC>,
1708 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1709 <&gcc GCC_UFS_ICE_CORE_CLK>,
1710 <&rpmcc RPM_SMD_LN_BB_CLK>,
1711 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1712 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1714 <100000000 200000000>,
1719 <150000000 300000000>,
1726 lanes-per-direction = <1>;
1728 status = "disabled";
1731 compatible = "qcom,ufs_variant";
1735 ufsphy: phy@627000 {
1736 compatible = "qcom,msm8996-qmp-ufs-phy";
1737 reg = <0x00627000 0x1c4>;
1738 #address-cells = <1>;
1742 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1743 clock-names = "ref";
1745 resets = <&ufshc 0>;
1746 reset-names = "ufsphy";
1747 status = "disabled";
1749 ufsphy_lane: lanes@627400 {
1750 reg = <0x627400 0x12c>,
1757 camss: camss@a00000 {
1758 compatible = "qcom,msm8996-camss";
1759 reg = <0x00a34000 0x1000>,
1761 <0x00a35000 0x1000>,
1763 <0x00a36000 0x1000>,
1771 <0x00a10000 0x1000>,
1772 <0x00a14000 0x1000>;
1773 reg-names = "csiphy0",
1787 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1788 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1789 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1790 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1791 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1792 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1793 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1794 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1795 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1796 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1797 interrupt-names = "csiphy0",
1807 power-domains = <&mmcc VFE0_GDSC>,
1809 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1810 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1811 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1812 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1813 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1814 <&mmcc CAMSS_CSI0_AHB_CLK>,
1815 <&mmcc CAMSS_CSI0_CLK>,
1816 <&mmcc CAMSS_CSI0PHY_CLK>,
1817 <&mmcc CAMSS_CSI0PIX_CLK>,
1818 <&mmcc CAMSS_CSI0RDI_CLK>,
1819 <&mmcc CAMSS_CSI1_AHB_CLK>,
1820 <&mmcc CAMSS_CSI1_CLK>,
1821 <&mmcc CAMSS_CSI1PHY_CLK>,
1822 <&mmcc CAMSS_CSI1PIX_CLK>,
1823 <&mmcc CAMSS_CSI1RDI_CLK>,
1824 <&mmcc CAMSS_CSI2_AHB_CLK>,
1825 <&mmcc CAMSS_CSI2_CLK>,
1826 <&mmcc CAMSS_CSI2PHY_CLK>,
1827 <&mmcc CAMSS_CSI2PIX_CLK>,
1828 <&mmcc CAMSS_CSI2RDI_CLK>,
1829 <&mmcc CAMSS_CSI3_AHB_CLK>,
1830 <&mmcc CAMSS_CSI3_CLK>,
1831 <&mmcc CAMSS_CSI3PHY_CLK>,
1832 <&mmcc CAMSS_CSI3PIX_CLK>,
1833 <&mmcc CAMSS_CSI3RDI_CLK>,
1834 <&mmcc CAMSS_AHB_CLK>,
1835 <&mmcc CAMSS_VFE0_CLK>,
1836 <&mmcc CAMSS_CSI_VFE0_CLK>,
1837 <&mmcc CAMSS_VFE0_AHB_CLK>,
1838 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1839 <&mmcc CAMSS_VFE1_CLK>,
1840 <&mmcc CAMSS_CSI_VFE1_CLK>,
1841 <&mmcc CAMSS_VFE1_AHB_CLK>,
1842 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1843 <&mmcc CAMSS_VFE_AHB_CLK>,
1844 <&mmcc CAMSS_VFE_AXI_CLK>;
1845 clock-names = "top_ahb",
1881 iommus = <&vfe_smmu 0>,
1885 status = "disabled";
1887 #address-cells = <1>;
1893 compatible = "qcom,msm8996-cci";
1894 #address-cells = <1>;
1896 reg = <0xa0c000 0x1000>;
1897 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1898 power-domains = <&mmcc CAMSS_GDSC>;
1899 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1900 <&mmcc CAMSS_CCI_AHB_CLK>,
1901 <&mmcc CAMSS_CCI_CLK>,
1902 <&mmcc CAMSS_AHB_CLK>;
1903 clock-names = "camss_top_ahb",
1907 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1908 <&mmcc CAMSS_CCI_CLK>;
1909 assigned-clock-rates = <80000000>, <37500000>;
1910 pinctrl-names = "default";
1911 pinctrl-0 = <&cci0_default &cci1_default>;
1912 status = "disabled";
1914 cci_i2c0: i2c-bus@0 {
1916 clock-frequency = <400000>;
1917 #address-cells = <1>;
1921 cci_i2c1: i2c-bus@1 {
1923 clock-frequency = <400000>;
1924 #address-cells = <1>;
1929 adreno_smmu: iommu@b40000 {
1930 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1931 reg = <0x00b40000 0x10000>;
1933 #global-interrupts = <1>;
1934 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&mmcc GPU_AHB_CLK>,
1940 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1941 clock-names = "iface", "bus";
1943 power-domains = <&mmcc GPU_GDSC>;
1946 venus: video-codec@c00000 {
1947 compatible = "qcom,msm8996-venus";
1948 reg = <0x00c00000 0xff000>;
1949 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1950 power-domains = <&mmcc VENUS_GDSC>;
1951 clocks = <&mmcc VIDEO_CORE_CLK>,
1952 <&mmcc VIDEO_AHB_CLK>,
1953 <&mmcc VIDEO_AXI_CLK>,
1954 <&mmcc VIDEO_MAXI_CLK>;
1955 clock-names = "core", "iface", "bus", "mbus";
1956 iommus = <&venus_smmu 0x00>,
1976 memory-region = <&venus_region>;
1977 status = "disabled";
1980 compatible = "venus-decoder";
1981 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1982 clock-names = "core";
1983 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1987 compatible = "venus-encoder";
1988 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1989 clock-names = "core";
1990 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1994 mdp_smmu: iommu@d00000 {
1995 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1996 reg = <0x00d00000 0x10000>;
1998 #global-interrupts = <1>;
1999 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2000 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2003 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2004 <&mmcc SMMU_MDP_AXI_CLK>;
2005 clock-names = "iface", "bus";
2007 power-domains = <&mmcc MDSS_GDSC>;
2010 venus_smmu: iommu@d40000 {
2011 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2012 reg = <0x00d40000 0x20000>;
2013 #global-interrupts = <1>;
2014 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2015 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2016 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2017 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2018 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2019 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2021 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2022 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2023 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2024 <&mmcc SMMU_VIDEO_AXI_CLK>;
2025 clock-names = "iface", "bus";
2030 vfe_smmu: iommu@da0000 {
2031 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2032 reg = <0x00da0000 0x10000>;
2034 #global-interrupts = <1>;
2035 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2036 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2037 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2038 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2039 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2040 <&mmcc SMMU_VFE_AXI_CLK>;
2041 clock-names = "iface",
2046 lpass_q6_smmu: iommu@1600000 {
2047 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2048 reg = <0x01600000 0x20000>;
2050 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2052 #global-interrupts = <1>;
2053 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2054 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2055 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2056 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2057 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2058 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2059 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2060 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2061 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2062 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2063 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2064 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2065 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2067 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2068 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2069 clock-names = "iface", "bus";
2073 compatible = "arm,coresight-stm", "arm,primecell";
2074 reg = <0x3002000 0x1000>,
2075 <0x8280000 0x180000>;
2076 reg-names = "stm-base", "stm-stimulus-base";
2078 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2079 clock-names = "apb_pclk", "atclk";
2092 compatible = "arm,coresight-tpiu", "arm,primecell";
2093 reg = <0x3020000 0x1000>;
2095 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2096 clock-names = "apb_pclk", "atclk";
2109 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2110 reg = <0x3021000 0x1000>;
2112 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2113 clock-names = "apb_pclk", "atclk";
2116 #address-cells = <1>;
2121 funnel0_in: endpoint {
2130 funnel0_out: endpoint {
2132 <&merge_funnel_in0>;
2139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2140 reg = <0x3022000 0x1000>;
2142 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2143 clock-names = "apb_pclk", "atclk";
2146 #address-cells = <1>;
2151 funnel1_in: endpoint {
2153 <&apss_merge_funnel_out>;
2160 funnel1_out: endpoint {
2162 <&merge_funnel_in1>;
2169 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2170 reg = <0x3023000 0x1000>;
2172 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2173 clock-names = "apb_pclk", "atclk";
2178 funnel2_out: endpoint {
2180 <&merge_funnel_in2>;
2187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2188 reg = <0x3025000 0x1000>;
2190 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2191 clock-names = "apb_pclk", "atclk";
2194 #address-cells = <1>;
2199 merge_funnel_in0: endpoint {
2207 merge_funnel_in1: endpoint {
2215 merge_funnel_in2: endpoint {
2224 merge_funnel_out: endpoint {
2232 replicator@3026000 {
2233 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2234 reg = <0x3026000 0x1000>;
2236 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2237 clock-names = "apb_pclk", "atclk";
2241 replicator_in: endpoint {
2249 #address-cells = <1>;
2254 replicator_out0: endpoint {
2262 replicator_out1: endpoint {
2271 compatible = "arm,coresight-tmc", "arm,primecell";
2272 reg = <0x3027000 0x1000>;
2274 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2275 clock-names = "apb_pclk", "atclk";
2281 <&merge_funnel_out>;
2297 compatible = "arm,coresight-tmc", "arm,primecell";
2298 reg = <0x3028000 0x1000>;
2300 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2301 clock-names = "apb_pclk", "atclk";
2315 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2316 reg = <0x3810000 0x1000>;
2318 clocks = <&rpmcc RPM_QDSS_CLK>;
2319 clock-names = "apb_pclk";
2325 compatible = "arm,coresight-etm4x", "arm,primecell";
2326 reg = <0x3840000 0x1000>;
2328 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2329 clock-names = "apb_pclk", "atclk";
2335 etm0_out: endpoint {
2337 <&apss_funnel0_in0>;
2344 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2345 reg = <0x3910000 0x1000>;
2347 clocks = <&rpmcc RPM_QDSS_CLK>;
2348 clock-names = "apb_pclk";
2354 compatible = "arm,coresight-etm4x", "arm,primecell";
2355 reg = <0x3940000 0x1000>;
2357 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2358 clock-names = "apb_pclk", "atclk";
2364 etm1_out: endpoint {
2366 <&apss_funnel0_in1>;
2372 funnel@39b0000 { /* APSS Funnel 0 */
2373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2374 reg = <0x39b0000 0x1000>;
2376 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2377 clock-names = "apb_pclk", "atclk";
2380 #address-cells = <1>;
2385 apss_funnel0_in0: endpoint {
2386 remote-endpoint = <&etm0_out>;
2392 apss_funnel0_in1: endpoint {
2393 remote-endpoint = <&etm1_out>;
2400 apss_funnel0_out: endpoint {
2402 <&apss_merge_funnel_in0>;
2409 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2410 reg = <0x3a10000 0x1000>;
2412 clocks = <&rpmcc RPM_QDSS_CLK>;
2413 clock-names = "apb_pclk";
2419 compatible = "arm,coresight-etm4x", "arm,primecell";
2420 reg = <0x3a40000 0x1000>;
2422 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2423 clock-names = "apb_pclk", "atclk";
2429 etm2_out: endpoint {
2431 <&apss_funnel1_in0>;
2438 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2439 reg = <0x3b10000 0x1000>;
2441 clocks = <&rpmcc RPM_QDSS_CLK>;
2442 clock-names = "apb_pclk";
2448 compatible = "arm,coresight-etm4x", "arm,primecell";
2449 reg = <0x3b40000 0x1000>;
2451 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2452 clock-names = "apb_pclk", "atclk";
2458 etm3_out: endpoint {
2460 <&apss_funnel1_in1>;
2466 funnel@3bb0000 { /* APSS Funnel 1 */
2467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2468 reg = <0x3bb0000 0x1000>;
2470 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2471 clock-names = "apb_pclk", "atclk";
2474 #address-cells = <1>;
2479 apss_funnel1_in0: endpoint {
2480 remote-endpoint = <&etm2_out>;
2486 apss_funnel1_in1: endpoint {
2487 remote-endpoint = <&etm3_out>;
2494 apss_funnel1_out: endpoint {
2496 <&apss_merge_funnel_in1>;
2503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2504 reg = <0x3bc0000 0x1000>;
2506 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2507 clock-names = "apb_pclk", "atclk";
2510 #address-cells = <1>;
2515 apss_merge_funnel_in0: endpoint {
2517 <&apss_funnel0_out>;
2523 apss_merge_funnel_in1: endpoint {
2525 <&apss_funnel1_out>;
2532 apss_merge_funnel_out: endpoint {
2540 kryocc: clock-controller@6400000 {
2541 compatible = "qcom,msm8996-apcc";
2542 reg = <0x06400000 0x90000>;
2545 clocks = <&xo_board>;
2551 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2552 reg = <0x06af8800 0x400>;
2553 #address-cells = <1>;
2557 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2558 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2559 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2561 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2562 <&gcc GCC_USB30_MASTER_CLK>,
2563 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2564 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2565 <&gcc GCC_USB30_SLEEP_CLK>,
2566 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2568 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2569 <&gcc GCC_USB30_MASTER_CLK>;
2570 assigned-clock-rates = <19200000>, <120000000>;
2572 power-domains = <&gcc USB30_GDSC>;
2573 status = "disabled";
2575 usb3_dwc3: dwc3@6a00000 {
2576 compatible = "snps,dwc3";
2577 reg = <0x06a00000 0xcc00>;
2578 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2579 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2580 phy-names = "usb2-phy", "usb3-phy";
2581 snps,dis_u2_susphy_quirk;
2582 snps,dis_enblslpm_quirk;
2586 usb3phy: phy@7410000 {
2587 compatible = "qcom,msm8996-qmp-usb3-phy";
2588 reg = <0x07410000 0x1c4>;
2590 #address-cells = <1>;
2594 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2595 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2596 <&gcc GCC_USB3_CLKREF_CLK>;
2597 clock-names = "aux", "cfg_ahb", "ref";
2599 resets = <&gcc GCC_USB3_PHY_BCR>,
2600 <&gcc GCC_USB3PHY_PHY_BCR>;
2601 reset-names = "phy", "common";
2602 status = "disabled";
2604 ssusb_phy_0: lane@7410200 {
2605 reg = <0x07410200 0x200>,
2610 clock-output-names = "usb3_phy_pipe_clk_src";
2611 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2612 clock-names = "pipe0";
2616 hsusb_phy1: phy@7411000 {
2617 compatible = "qcom,msm8996-qusb2-phy";
2618 reg = <0x07411000 0x180>;
2621 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2622 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2623 clock-names = "cfg_ahb", "ref";
2625 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2626 nvmem-cells = <&qusb2p_hstx_trim>;
2627 status = "disabled";
2630 hsusb_phy2: phy@7412000 {
2631 compatible = "qcom,msm8996-qusb2-phy";
2632 reg = <0x07412000 0x180>;
2635 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2636 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
2637 clock-names = "cfg_ahb", "ref";
2639 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2640 nvmem-cells = <&qusb2s_hstx_trim>;
2641 status = "disabled";
2644 sdhc1: sdhci@7464900 {
2645 compatible = "qcom,sdhci-msm-v4";
2646 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2647 reg-names = "hc_mem", "core_mem";
2649 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2650 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2651 interrupt-names = "hc_irq", "pwr_irq";
2653 clock-names = "iface", "core", "xo";
2654 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2655 <&gcc GCC_SDCC1_APPS_CLK>,
2658 pinctrl-names = "default", "sleep";
2659 pinctrl-0 = <&sdc1_state_on>;
2660 pinctrl-1 = <&sdc1_state_off>;
2664 status = "disabled";
2667 sdhc2: sdhci@74a4900 {
2668 compatible = "qcom,sdhci-msm-v4";
2669 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2670 reg-names = "hc_mem", "core_mem";
2672 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2673 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2674 interrupt-names = "hc_irq", "pwr_irq";
2676 clock-names = "iface", "core", "xo";
2677 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2678 <&gcc GCC_SDCC2_APPS_CLK>,
2681 pinctrl-names = "default", "sleep";
2682 pinctrl-0 = <&sdc2_state_on>;
2683 pinctrl-1 = <&sdc2_state_off>;
2686 status = "disabled";
2689 blsp1_dma: dma@7544000 {
2690 compatible = "qcom,bam-v1.7.0";
2691 reg = <0x07544000 0x2b000>;
2692 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2693 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2694 clock-names = "bam_clk";
2695 qcom,controlled-remotely;
2700 blsp1_uart2: serial@7570000 {
2701 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2702 reg = <0x07570000 0x1000>;
2703 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2704 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2705 <&gcc GCC_BLSP1_AHB_CLK>;
2706 clock-names = "core", "iface";
2707 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2708 dma-names = "tx", "rx";
2709 status = "disabled";
2712 blsp1_spi1: spi@7575000 {
2713 compatible = "qcom,spi-qup-v2.2.1";
2714 reg = <0x07575000 0x600>;
2715 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2716 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2717 <&gcc GCC_BLSP1_AHB_CLK>;
2718 clock-names = "core", "iface";
2719 pinctrl-names = "default", "sleep";
2720 pinctrl-0 = <&blsp1_spi1_default>;
2721 pinctrl-1 = <&blsp1_spi1_sleep>;
2722 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2723 dma-names = "tx", "rx";
2724 #address-cells = <1>;
2726 status = "disabled";
2729 blsp1_i2c3: i2c@7577000 {
2730 compatible = "qcom,i2c-qup-v2.2.1";
2731 reg = <0x07577000 0x1000>;
2732 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2733 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2734 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2735 clock-names = "iface", "core";
2736 pinctrl-names = "default", "sleep";
2737 pinctrl-0 = <&blsp1_i2c3_default>;
2738 pinctrl-1 = <&blsp1_i2c3_sleep>;
2739 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2740 dma-names = "tx", "rx";
2741 #address-cells = <1>;
2743 status = "disabled";
2746 blsp2_dma: dma@7584000 {
2747 compatible = "qcom,bam-v1.7.0";
2748 reg = <0x07584000 0x2b000>;
2749 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2750 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2751 clock-names = "bam_clk";
2752 qcom,controlled-remotely;
2757 blsp2_uart2: serial@75b0000 {
2758 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2759 reg = <0x075b0000 0x1000>;
2760 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2761 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2762 <&gcc GCC_BLSP2_AHB_CLK>;
2763 clock-names = "core", "iface";
2764 status = "disabled";
2767 blsp2_uart3: serial@75b1000 {
2768 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2769 reg = <0x075b1000 0x1000>;
2770 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2771 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2772 <&gcc GCC_BLSP2_AHB_CLK>;
2773 clock-names = "core", "iface";
2774 status = "disabled";
2777 blsp2_i2c1: i2c@75b5000 {
2778 compatible = "qcom,i2c-qup-v2.2.1";
2779 reg = <0x075b5000 0x1000>;
2780 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2781 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2782 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2783 clock-names = "iface", "core";
2784 pinctrl-names = "default", "sleep";
2785 pinctrl-0 = <&blsp2_i2c1_default>;
2786 pinctrl-1 = <&blsp2_i2c1_sleep>;
2787 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2788 dma-names = "tx", "rx";
2789 #address-cells = <1>;
2791 status = "disabled";
2794 blsp2_i2c2: i2c@75b6000 {
2795 compatible = "qcom,i2c-qup-v2.2.1";
2796 reg = <0x075b6000 0x1000>;
2797 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2798 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2799 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2800 clock-names = "iface", "core";
2801 pinctrl-names = "default", "sleep";
2802 pinctrl-0 = <&blsp2_i2c2_default>;
2803 pinctrl-1 = <&blsp2_i2c2_sleep>;
2804 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2805 dma-names = "tx", "rx";
2806 #address-cells = <1>;
2808 status = "disabled";
2811 blsp2_i2c5: i2c@75b9000 {
2812 compatible = "qcom,i2c-qup-v2.2.1";
2813 reg = <0x75b9000 0x1000>;
2814 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2815 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2816 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2817 clock-names = "iface", "core";
2818 pinctrl-names = "default";
2819 pinctrl-0 = <&blsp2_i2c5_default>;
2820 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
2821 dma-names = "tx", "rx";
2822 #address-cells = <1>;
2824 status = "disabled";
2827 blsp2_i2c6: i2c@75ba000 {
2828 compatible = "qcom,i2c-qup-v2.2.1";
2829 reg = <0x75ba000 0x1000>;
2830 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2831 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2832 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2833 clock-names = "iface", "core";
2834 pinctrl-names = "default", "sleep";
2835 pinctrl-0 = <&blsp2_i2c6_default>;
2836 pinctrl-1 = <&blsp2_i2c6_sleep>;
2837 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2838 dma-names = "tx", "rx";
2839 #address-cells = <1>;
2841 status = "disabled";
2844 blsp2_spi6: spi@75ba000{
2845 compatible = "qcom,spi-qup-v2.2.1";
2846 reg = <0x075ba000 0x600>;
2847 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2849 <&gcc GCC_BLSP2_AHB_CLK>;
2850 clock-names = "core", "iface";
2851 pinctrl-names = "default", "sleep";
2852 pinctrl-0 = <&blsp2_spi6_default>;
2853 pinctrl-1 = <&blsp2_spi6_sleep>;
2854 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
2855 dma-names = "tx", "rx";
2856 #address-cells = <1>;
2858 status = "disabled";
2862 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2863 reg = <0x076f8800 0x400>;
2864 #address-cells = <1>;
2868 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2869 <&gcc GCC_USB20_MASTER_CLK>,
2870 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2871 <&gcc GCC_USB20_SLEEP_CLK>,
2872 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2874 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2875 <&gcc GCC_USB20_MASTER_CLK>;
2876 assigned-clock-rates = <19200000>, <60000000>;
2878 power-domains = <&gcc USB30_GDSC>;
2879 qcom,select-utmi-as-pipe-clk;
2880 status = "disabled";
2883 compatible = "snps,dwc3";
2884 reg = <0x07600000 0xcc00>;
2885 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
2886 phys = <&hsusb_phy2>;
2887 phy-names = "usb2-phy";
2888 maximum-speed = "high-speed";
2889 snps,dis_u2_susphy_quirk;
2890 snps,dis_enblslpm_quirk;
2894 slimbam: dma-controller@9184000 {
2895 compatible = "qcom,bam-v1.7.0";
2896 qcom,controlled-remotely;
2897 reg = <0x09184000 0x32000>;
2898 num-channels = <31>;
2899 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2905 slim_msm: slim@91c0000 {
2906 compatible = "qcom,slim-ngd-v1.5.0";
2907 reg = <0x091c0000 0x2C000>;
2909 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2910 dmas = <&slimbam 3>, <&slimbam 4>,
2911 <&slimbam 5>, <&slimbam 6>;
2912 dma-names = "rx", "tx", "tx2", "rx2";
2913 #address-cells = <1>;
2917 #address-cells = <1>;
2920 tasha_ifd: tas-ifd {
2921 compatible = "slim217,1a0";
2926 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2927 pinctrl-names = "default";
2929 compatible = "slim217,1a0";
2932 interrupt-parent = <&tlmm>;
2933 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2934 <53 IRQ_TYPE_LEVEL_HIGH>;
2935 interrupt-names = "intr1", "intr2";
2936 interrupt-controller;
2937 #interrupt-cells = <1>;
2938 reset-gpios = <&tlmm 64 0>;
2940 slim-ifc-dev = <&tasha_ifd>;
2942 #sound-dai-cells = <1>;
2947 adsp_pil: remoteproc@9300000 {
2948 compatible = "qcom,msm8996-adsp-pil";
2949 reg = <0x09300000 0x80000>;
2951 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2952 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2953 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2954 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2955 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2956 interrupt-names = "wdog", "fatal", "ready",
2957 "handover", "stop-ack";
2959 clocks = <&xo_board>;
2962 memory-region = <&adsp_region>;
2964 qcom,smem-states = <&smp2p_adsp_out 0>;
2965 qcom,smem-state-names = "stop";
2967 power-domains = <&rpmpd MSM8996_VDDCX>;
2968 power-domain-names = "cx";
2970 status = "disabled";
2973 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2976 mboxes = <&apcs_glb 8>;
2977 qcom,smd-edge = <1>;
2978 qcom,remote-pid = <2>;
2979 #address-cells = <1>;
2982 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2983 compatible = "qcom,apr-v2";
2984 qcom,smd-channels = "apr_audio_svc";
2985 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2986 #address-cells = <1>;
2990 reg = <APR_SVC_ADSP_CORE>;
2991 compatible = "qcom,q6core";
2995 compatible = "qcom,q6afe";
2996 reg = <APR_SVC_AFE>;
2998 compatible = "qcom,q6afe-dais";
2999 #address-cells = <1>;
3001 #sound-dai-cells = <1>;
3009 compatible = "qcom,q6asm";
3010 reg = <APR_SVC_ASM>;
3012 compatible = "qcom,q6asm-dais";
3013 #address-cells = <1>;
3015 #sound-dai-cells = <1>;
3016 iommus = <&lpass_q6_smmu 1>;
3021 compatible = "qcom,q6adm";
3022 reg = <APR_SVC_ADM>;
3023 q6routing: routing {
3024 compatible = "qcom,q6adm-routing";
3025 #sound-dai-cells = <0>;
3033 apcs_glb: mailbox@9820000 {
3034 compatible = "qcom,msm8996-apcs-hmss-global";
3035 reg = <0x09820000 0x1000>;
3041 #address-cells = <1>;
3044 compatible = "arm,armv7-timer-mem";
3045 reg = <0x09840000 0x1000>;
3046 clock-frequency = <19200000>;
3050 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3051 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3052 reg = <0x09850000 0x1000>,
3053 <0x09860000 0x1000>;
3058 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3059 reg = <0x09870000 0x1000>;
3060 status = "disabled";
3065 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3066 reg = <0x09880000 0x1000>;
3067 status = "disabled";
3072 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3073 reg = <0x09890000 0x1000>;
3074 status = "disabled";
3079 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3080 reg = <0x098a0000 0x1000>;
3081 status = "disabled";
3086 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3087 reg = <0x098b0000 0x1000>;
3088 status = "disabled";
3093 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3094 reg = <0x098c0000 0x1000>;
3095 status = "disabled";
3099 saw3: syscon@9a10000 {
3100 compatible = "syscon";
3101 reg = <0x09a10000 0x1000>;
3104 intc: interrupt-controller@9bc0000 {
3105 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3106 #interrupt-cells = <3>;
3107 interrupt-controller;
3108 #redistributor-regions = <1>;
3109 redistributor-stride = <0x0 0x40000>;
3110 reg = <0x09bc0000 0x10000>,
3111 <0x09c00000 0x100000>;
3112 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3121 polling-delay-passive = <250>;
3122 polling-delay = <1000>;
3124 thermal-sensors = <&tsens0 3>;
3127 cpu0_alert0: trip-point0 {
3128 temperature = <75000>;
3129 hysteresis = <2000>;
3133 cpu0_crit: cpu_crit {
3134 temperature = <110000>;
3135 hysteresis = <2000>;
3142 polling-delay-passive = <250>;
3143 polling-delay = <1000>;
3145 thermal-sensors = <&tsens0 5>;
3148 cpu1_alert0: trip-point0 {
3149 temperature = <75000>;
3150 hysteresis = <2000>;
3154 cpu1_crit: cpu_crit {
3155 temperature = <110000>;
3156 hysteresis = <2000>;
3163 polling-delay-passive = <250>;
3164 polling-delay = <1000>;
3166 thermal-sensors = <&tsens0 8>;
3169 cpu2_alert0: trip-point0 {
3170 temperature = <75000>;
3171 hysteresis = <2000>;
3175 cpu2_crit: cpu_crit {
3176 temperature = <110000>;
3177 hysteresis = <2000>;
3184 polling-delay-passive = <250>;
3185 polling-delay = <1000>;
3187 thermal-sensors = <&tsens0 10>;
3190 cpu3_alert0: trip-point0 {
3191 temperature = <75000>;
3192 hysteresis = <2000>;
3196 cpu3_crit: cpu_crit {
3197 temperature = <110000>;
3198 hysteresis = <2000>;
3205 polling-delay-passive = <250>;
3206 polling-delay = <1000>;
3208 thermal-sensors = <&tsens1 6>;
3211 gpu1_alert0: trip-point0 {
3212 temperature = <90000>;
3213 hysteresis = <2000>;
3220 trip = <&gpu1_alert0>;
3221 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3226 gpu-thermal-bottom {
3227 polling-delay-passive = <250>;
3228 polling-delay = <1000>;
3230 thermal-sensors = <&tsens1 7>;
3233 gpu2_alert0: trip-point0 {
3234 temperature = <90000>;
3235 hysteresis = <2000>;
3242 trip = <&gpu2_alert0>;
3243 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3249 polling-delay-passive = <250>;
3250 polling-delay = <1000>;
3252 thermal-sensors = <&tsens0 1>;
3255 m4m_alert0: trip-point0 {
3256 temperature = <90000>;
3257 hysteresis = <2000>;
3263 l3-or-venus-thermal {
3264 polling-delay-passive = <250>;
3265 polling-delay = <1000>;
3267 thermal-sensors = <&tsens0 2>;
3270 l3_or_venus_alert0: trip-point0 {
3271 temperature = <90000>;
3272 hysteresis = <2000>;
3278 cluster0-l2-thermal {
3279 polling-delay-passive = <250>;
3280 polling-delay = <1000>;
3282 thermal-sensors = <&tsens0 7>;
3285 cluster0_l2_alert0: trip-point0 {
3286 temperature = <90000>;
3287 hysteresis = <2000>;
3293 cluster1-l2-thermal {
3294 polling-delay-passive = <250>;
3295 polling-delay = <1000>;
3297 thermal-sensors = <&tsens0 12>;
3300 cluster1_l2_alert0: trip-point0 {
3301 temperature = <90000>;
3302 hysteresis = <2000>;
3309 polling-delay-passive = <250>;
3310 polling-delay = <1000>;
3312 thermal-sensors = <&tsens1 1>;
3315 camera_alert0: trip-point0 {
3316 temperature = <90000>;
3317 hysteresis = <2000>;
3324 polling-delay-passive = <250>;
3325 polling-delay = <1000>;
3327 thermal-sensors = <&tsens1 2>;
3330 q6_dsp_alert0: trip-point0 {
3331 temperature = <90000>;
3332 hysteresis = <2000>;
3339 polling-delay-passive = <250>;
3340 polling-delay = <1000>;
3342 thermal-sensors = <&tsens1 3>;
3345 mem_alert0: trip-point0 {
3346 temperature = <90000>;
3347 hysteresis = <2000>;
3354 polling-delay-passive = <250>;
3355 polling-delay = <1000>;
3357 thermal-sensors = <&tsens1 4>;
3360 modemtx_alert0: trip-point0 {
3361 temperature = <90000>;
3362 hysteresis = <2000>;
3370 compatible = "arm,armv8-timer";
3371 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3372 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3373 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3374 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;