arch/arm64/boot/dts/qcom/ipq6018.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * IPQ6018 SoC device tree source
   4  *
   5  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  11 #include <dt-bindings/clock/qcom,apss-ipq.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&intc>;
  17
  18         clocks {
  19                 sleep_clk: sleep-clk {
  20                         compatible = "fixed-clock";
  21                         clock-frequency = <32000>;
  22                         #clock-cells = <0>;
  23                 };
  24
  25                 xo: xo {
  26                         compatible = "fixed-clock";
  27                         clock-frequency = <24000000>;
  28                         #clock-cells = <0>;
  29                 };
  30         };
  31
  32         cpus: cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 CPU0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         reg = <0x0>;
  40                         enable-method = "psci";
  41                         next-level-cache = <&L2_0>;
  42                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  43                         clock-names = "cpu";
  44                         operating-points-v2 = <&cpu_opp_table>;
  45                         cpu-supply = <&ipq6018_s2>;
  46                 };
  47
  48                 CPU1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         enable-method = "psci";
  52                         reg = <0x1>;
  53                         next-level-cache = <&L2_0>;
  54                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  55                         clock-names = "cpu";
  56                         operating-points-v2 = <&cpu_opp_table>;
  57                         cpu-supply = <&ipq6018_s2>;
  58                 };
  59
  60                 CPU2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         enable-method = "psci";
  64                         reg = <0x2>;
  65                         next-level-cache = <&L2_0>;
  66                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  67                         clock-names = "cpu";
  68                         operating-points-v2 = <&cpu_opp_table>;
  69                         cpu-supply = <&ipq6018_s2>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         enable-method = "psci";
  76                         reg = <0x3>;
  77                         next-level-cache = <&L2_0>;
  78                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  79                         clock-names = "cpu";
  80                         operating-points-v2 = <&cpu_opp_table>;
  81                         cpu-supply = <&ipq6018_s2>;
  82                 };
  83
  84                 L2_0: l2-cache {
  85                         compatible = "cache";
  86                         cache-level = <0x2>;
  87                 };
  88         };
  89
  90         cpu_opp_table: cpu_opp_table {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp-864000000 {
  95                         opp-hz = /bits/ 64 <864000000>;
  96                         opp-microvolt = <725000>;
  97                         clock-latency-ns = <200000>;
  98                 };
  99                 opp-1056000000 {
 100                         opp-hz = /bits/ 64 <1056000000>;
 101                         opp-microvolt = <787500>;
 102                         clock-latency-ns = <200000>;
 103                 };
 104                 opp-1320000000 {
 105                         opp-hz = /bits/ 64 <1320000000>;
 106                         opp-microvolt = <862500>;
 107                         clock-latency-ns = <200000>;
 108                 };
 109                 opp-1440000000 {
 110                         opp-hz = /bits/ 64 <1440000000>;
 111                         opp-microvolt = <925000>;
 112                         clock-latency-ns = <200000>;
 113                 };
 114                 opp-1608000000 {
 115                         opp-hz = /bits/ 64 <1608000000>;
 116                         opp-microvolt = <987500>;
 117                         clock-latency-ns = <200000>;
 118                 };
 119                 opp-1800000000 {
 120                         opp-hz = /bits/ 64 <1800000000>;
 121                         opp-microvolt = <1062500>;
 122                         clock-latency-ns = <200000>;
 123                 };
 124         };
 125
 126         firmware {
 127                 scm {
 128                         compatible = "qcom,scm";
 129                 };
 130         };
 131
 132         tcsr_mutex: hwlock {
 133                 compatible = "qcom,tcsr-mutex";
 134                 syscon = <&tcsr_mutex_regs 0 0x80>;
 135                 #hwlock-cells = <1>;
 136         };
 137
 138         pmuv8: pmu {
 139                 compatible = "arm,cortex-a53-pmu";
 140                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 141                                          IRQ_TYPE_LEVEL_HIGH)>;
 142         };
 143
 144         psci: psci {
 145                 compatible = "arm,psci-1.0";
 146                 method = "smc";
 147         };
 148
 149         reserved-memory {
 150                 #address-cells = <2>;
 151                 #size-cells = <2>;
 152                 ranges;
 153
 154                 rpm_msg_ram: memory@60000 {
 155                         reg = <0x0 0x60000 0x0 0x6000>;
 156                         no-map;
 157                 };
 158
 159                 tz: memory@4a600000 {
 160                         reg = <0x0 0x4a600000 0x0 0x00400000>;
 161                         no-map;
 162                 };
 163
 164                 smem_region: memory@4aa00000 {
 165                         reg = <0x0 0x4aa00000 0x0 0x00100000>;
 166                         no-map;
 167                 };
 168
 169                 q6_region: memory@4ab00000 {
 170                         reg = <0x0 0x4ab00000 0x0 0x05500000>;
 171                         no-map;
 172                 };
 173         };
 174
 175         smem {
 176                 compatible = "qcom,smem";
 177                 memory-region = <&smem_region>;
 178                 hwlocks = <&tcsr_mutex 0>;
 179         };
 180
 181         soc: soc {
 182                 #address-cells = <2>;
 183                 #size-cells = <2>;
 184                 ranges = <0 0 0 0 0x0 0xffffffff>;
 185                 dma-ranges;
 186                 compatible = "simple-bus";
 187
 188                 prng: qrng@e1000 {
 189                         compatible = "qcom,prng-ee";
 190                         reg = <0x0 0xe3000 0x0 0x1000>;
 191                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 192                         clock-names = "core";
 193                 };
 194
 195                 cryptobam: dma-controller@704000 {
 196                         compatible = "qcom,bam-v1.7.0";
 197                         reg = <0x0 0x00704000 0x0 0x20000>;
 198                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 199                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 200                         clock-names = "bam_clk";
 201                         #dma-cells = <1>;
 202                         qcom,ee = <1>;
 203                         qcom,controlled-remotely = <1>;
 204                         qcom,config-pipe-trust-reg = <0>;
 205                 };
 206
 207                 crypto: crypto@73a000 {
 208                         compatible = "qcom,crypto-v5.1";
 209                         reg = <0x0 0x0073a000 0x0 0x6000>;
 210                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 211                                 <&gcc GCC_CRYPTO_AXI_CLK>,
 212                                 <&gcc GCC_CRYPTO_CLK>;
 213                         clock-names = "iface", "bus", "core";
 214                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 215                         dma-names = "rx", "tx";
 216                 };
 217
 218                 tlmm: pinctrl@1000000 {
 219                         compatible = "qcom,ipq6018-pinctrl";
 220                         reg = <0x0 0x01000000 0x0 0x300000>;
 221                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 222                         gpio-controller;
 223                         #gpio-cells = <2>;
 224                         gpio-ranges = <&tlmm 0 80>;
 225                         interrupt-controller;
 226                         #interrupt-cells = <2>;
 227
 228                         serial_3_pins: serial3-pinmux {
 229                                 pins = "gpio44", "gpio45";
 230                                 function = "blsp2_uart";
 231                                 drive-strength = <8>;
 232                                 bias-pull-down;
 233                         };
 234
 235                         qpic_pins: qpic-pins {
 236                                 pins = "gpio1", "gpio3", "gpio4",
 237                                         "gpio5", "gpio6", "gpio7",
 238                                         "gpio8", "gpio10", "gpio11",
 239                                         "gpio12", "gpio13", "gpio14",
 240                                         "gpio15", "gpio17";
 241                                 function = "qpic_pad";
 242                                 drive-strength = <8>;
 243                                 bias-disable;
 244                         };
 245                 };
 246
 247                 gcc: gcc@1800000 {
 248                         compatible = "qcom,gcc-ipq6018";
 249                         reg = <0x0 0x01800000 0x0 0x80000>;
 250                         clocks = <&xo>, <&sleep_clk>;
 251                         clock-names = "xo", "sleep_clk";
 252                         #clock-cells = <1>;
 253                         #reset-cells = <1>;
 254                 };
 255
 256                 tcsr_mutex_regs: syscon@1905000 {
 257                         compatible = "syscon";
 258                         reg = <0x0 0x01905000 0x0 0x8000>;
 259                 };
 260
 261                 tcsr: syscon@1937000 {
 262                         compatible = "syscon";
 263                         reg = <0x0 0x01937000 0x0 0x21000>;
 264                 };
 265
 266                 blsp_dma: dma-controller@7884000 {
 267                         compatible = "qcom,bam-v1.7.0";
 268                         reg = <0x0 0x07884000 0x0 0x2b000>;
 269                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 271                         clock-names = "bam_clk";
 272                         #dma-cells = <1>;
 273                         qcom,ee = <0>;
 274                 };
 275
 276                 blsp1_uart3: serial@78b1000 {
 277                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 278                         reg = <0x0 0x078b1000 0x0 0x200>;
 279                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 281                                 <&gcc GCC_BLSP1_AHB_CLK>;
 282                         clock-names = "core", "iface";
 283                         status = "disabled";
 284                 };
 285
 286                 spi_0: spi@78b5000 {
 287                         compatible = "qcom,spi-qup-v2.2.1";
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         reg = <0x0 0x078b5000 0x0 0x600>;
 291                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 292                         spi-max-frequency = <50000000>;
 293                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 294                                 <&gcc GCC_BLSP1_AHB_CLK>;
 295                         clock-names = "core", "iface";
 296                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 297                         dma-names = "tx", "rx";
 298                         status = "disabled";
 299                 };
 300
 301                 spi_1: spi@78b6000 {
 302                         compatible = "qcom,spi-qup-v2.2.1";
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         reg = <0x0 0x078b6000 0x0 0x600>;
 306                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 307                         spi-max-frequency = <50000000>;
 308                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 309                                 <&gcc GCC_BLSP1_AHB_CLK>;
 310                         clock-names = "core", "iface";
 311                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 312                         dma-names = "tx", "rx";
 313                         status = "disabled";
 314                 };
 315
 316                 i2c_0: i2c@78b6000 {
 317                         compatible = "qcom,i2c-qup-v2.2.1";
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                         reg = <0x0 0x078b6000 0x0 0x600>;
 321                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 323                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 324                         clock-names = "iface", "core";
 325                         clock-frequency  = <400000>;
 326                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 327                         dma-names = "rx", "tx";
 328                         status = "disabled";
 329                 };
 330
 331                 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
 332                         compatible = "qcom,i2c-qup-v2.2.1";
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         reg = <0x0 0x078b7000 0x0 0x600>;
 336                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 338                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 339                         clock-names = "iface", "core";
 340                         clock-frequency  = <400000>;
 341                         dmas = <&blsp_dma 17>, <&blsp_dma 16>;
 342                         dma-names = "rx", "tx";
 343                         status = "disabled";
 344                 };
 345
 346                 qpic_bam: dma-controller@7984000 {
 347                         compatible = "qcom,bam-v1.7.0";
 348                         reg = <0x0 0x07984000 0x0 0x1a000>;
 349                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 350                         clocks = <&gcc GCC_QPIC_CLK>,
 351                                  <&gcc GCC_QPIC_AHB_CLK>;
 352                         clock-names = "iface_clk", "bam_clk";
 353                         #dma-cells = <1>;
 354                         qcom,ee = <0>;
 355                         status = "disabled";
 356                 };
 357
 358                 qpic_nand: nand@79b0000 {
 359                         compatible = "qcom,ipq6018-nand";
 360                         reg = <0x0 0x079b0000 0x0 0x10000>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         clocks = <&gcc GCC_QPIC_CLK>,
 364                                  <&gcc GCC_QPIC_AHB_CLK>;
 365                         clock-names = "core", "aon";
 366
 367                         dmas = <&qpic_bam 0>,
 368                                 <&qpic_bam 1>,
 369                                 <&qpic_bam 2>;
 370                         dma-names = "tx", "rx", "cmd";
 371                         pinctrl-0 = <&qpic_pins>;
 372                         pinctrl-names = "default";
 373                         status = "disabled";
 374                 };
 375
 376                 intc: interrupt-controller@b000000 {
 377                         compatible = "qcom,msm-qgic2";
 378                         interrupt-controller;
 379                         #interrupt-cells = <0x3>;
 380                         reg =   <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
 381                                 <0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
 382                                 <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
 383                                 <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
 384                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 385                 };
 386
 387                 pcie_phy: phy@84000 {
 388                         compatible = "qcom,ipq6018-qmp-pcie-phy";
 389                         reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
 390                         status = "disabled";
 391                         #address-cells = <2>;
 392                         #size-cells = <2>;
 393                         ranges;
 394
 395                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 396                                 <&gcc GCC_PCIE0_AHB_CLK>;
 397                         clock-names = "aux", "cfg_ahb";
 398
 399                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 400                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 401                         reset-names = "phy",
 402                                       "common";
 403
 404                         pcie_phy0: lane@84200 {
 405                                 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
 406                                       <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
 407                                       <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
 408                                 #phy-cells = <0>;
 409
 410                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 411                                 clock-names = "pipe0";
 412                                 clock-output-names = "gcc_pcie0_pipe_clk_src";
 413                                 #clock-cells = <0>;
 414                         };
 415                 };
 416
 417                 pcie0: pci@20000000 {
 418                         compatible = "qcom,pcie-ipq6018";
 419                         reg = <0x0 0x20000000 0x0 0xf1d>,
 420                               <0x0 0x20000f20 0x0 0xa8>,
 421                               <0x0 0x20001000 0x0 0x1000>,
 422                               <0x0 0x80000 0x0 0x4000>,
 423                               <0x0 0x20100000 0x0 0x1000>;
 424                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 425
 426                         device_type = "pci";
 427                         linux,pci-domain = <0>;
 428                         bus-range = <0x00 0xff>;
 429                         num-lanes = <1>;
 430                         #address-cells = <3>;
 431                         #size-cells = <2>;
 432
 433                         phys = <&pcie_phy0>;
 434                         phy-names = "pciephy";
 435
 436                         ranges = <0x81000000 0 0x20200000 0 0x20200000
 437                                   0 0x10000>, /* downstream I/O */
 438                                  <0x82000000 0 0x20220000 0 0x20220000
 439                                   0 0xfde0000>; /* non-prefetchable memory */
 440
 441                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 442                         interrupt-names = "msi";
 443
 444                         #interrupt-cells = <1>;
 445                         interrupt-map-mask = <0 0 0 0x7>;
 446                         interrupt-map = <0 0 0 1 &intc 0 75
 447                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 448                                         <0 0 0 2 &intc 0 78
 449                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 450                                         <0 0 0 3 &intc 0 79
 451                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 452                                         <0 0 0 4 &intc 0 83
 453                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 454
 455                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 456                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 457                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 458                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 459                                  <&gcc PCIE0_RCHNG_CLK>;
 460                         clock-names = "iface",
 461                                       "axi_m",
 462                                       "axi_s",
 463                                       "axi_bridge",
 464                                       "rchng";
 465
 466                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 467                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 468                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 469                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 470                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 471                                  <&gcc GCC_PCIE0_AHB_ARES>,
 472                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 473                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 474                         reset-names = "pipe",
 475                                       "sleep",
 476                                       "sticky",
 477                                       "axi_m",
 478                                       "axi_s",
 479                                       "ahb",
 480                                       "axi_m_sticky",
 481                                       "axi_s_sticky";
 482
 483                         status = "disabled";
 484                 };
 485
 486                 watchdog@b017000 {
 487                         compatible = "qcom,kpss-wdt";
 488                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 489                         reg = <0x0 0x0b017000 0x0 0x40>;
 490                         clocks = <&sleep_clk>;
 491                         timeout-sec = <10>;
 492                 };
 493
 494                 apcs_glb: mailbox@b111000 {
 495                         compatible = "qcom,ipq6018-apcs-apps-global";
 496                         reg = <0x0 0x0b111000 0x0 0x1000>;
 497                         #clock-cells = <1>;
 498                         clocks = <&a53pll>, <&xo>;
 499                         clock-names = "pll", "xo";
 500                         #mbox-cells = <1>;
 501                 };
 502
 503                 a53pll: clock@b116000 {
 504                         compatible = "qcom,ipq6018-a53pll";
 505                         reg = <0x0 0x0b116000 0x0 0x40>;
 506                         #clock-cells = <0>;
 507                         clocks = <&xo>;
 508                         clock-names = "xo";
 509                 };
 510
 511                 timer {
 512                         compatible = "arm,armv8-timer";
 513                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 514                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 515                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 516                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 517                 };
 518
 519                 timer@b120000 {
 520                         #address-cells = <2>;
 521                         #size-cells = <2>;
 522                         ranges;
 523                         compatible = "arm,armv7-timer-mem";
 524                         reg = <0x0 0x0b120000 0x0 0x1000>;
 525                         clock-frequency = <19200000>;
 526
 527                         frame@b120000 {
 528                                 frame-number = <0>;
 529                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 530                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 531                                 reg = <0x0 0x0b121000 0x0 0x1000>,
 532                                       <0x0 0x0b122000 0x0 0x1000>;
 533                         };
 534
 535                         frame@b123000 {
 536                                 frame-number = <1>;
 537                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 538                                 reg = <0x0 0xb123000 0x0 0x1000>;
 539                                 status = "disabled";
 540                         };
 541
 542                         frame@b124000 {
 543                                 frame-number = <2>;
 544                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 545                                 reg = <0x0 0x0b124000 0x0 0x1000>;
 546                                 status = "disabled";
 547                         };
 548
 549                         frame@b125000 {
 550                                 frame-number = <3>;
 551                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 552                                 reg = <0x0 0x0b125000 0x0 0x1000>;
 553                                 status = "disabled";
 554                         };
 555
 556                         frame@b126000 {
 557                                 frame-number = <4>;
 558                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 559                                 reg = <0x0 0x0b126000 0x0 0x1000>;
 560                                 status = "disabled";
 561                         };
 562
 563                         frame@b127000 {
 564                                 frame-number = <5>;
 565                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 566                                 reg = <0x0 0x0b127000 0x0 0x1000>;
 567                                 status = "disabled";
 568                         };
 569
 570                         frame@b128000 {
 571                                 frame-number = <6>;
 572                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 573                                 reg = <0x0 0x0b128000 0x0 0x1000>;
 574                                 status = "disabled";
 575                         };
 576                 };
 577
 578                 q6v5_wcss: remoteproc@cd00000 {
 579                         compatible = "qcom,ipq6018-wcss-pil";
 580                         reg = <0x0 0x0cd00000 0x0 0x4040>,
 581                               <0x0 0x004ab000 0x0 0x20>;
 582                         reg-names = "qdsp6",
 583                                     "rmb";
 584                         interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
 585                                               <&wcss_smp2p_in 0 0>,
 586                                               <&wcss_smp2p_in 1 0>,
 587                                               <&wcss_smp2p_in 2 0>,
 588                                               <&wcss_smp2p_in 3 0>;
 589                         interrupt-names = "wdog",
 590                                           "fatal",
 591                                           "ready",
 592                                           "handover",
 593                                           "stop-ack";
 594
 595                         resets = <&gcc GCC_WCSSAON_RESET>,
 596                                  <&gcc GCC_WCSS_BCR>,
 597                                  <&gcc GCC_WCSS_Q6_BCR>;
 598
 599                         reset-names = "wcss_aon_reset",
 600                                       "wcss_reset",
 601                                       "wcss_q6_reset";
 602
 603                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 604                         clock-names = "prng";
 605
 606                         qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
 607
 608                         qcom,smem-states = <&wcss_smp2p_out 0>,
 609                                            <&wcss_smp2p_out 1>;
 610                         qcom,smem-state-names = "shutdown",
 611                                                 "stop";
 612
 613                         memory-region = <&q6_region>;
 614
 615                         glink-edge {
 616                                 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
 617                                 qcom,remote-pid = <1>;
 618                                 mboxes = <&apcs_glb 8>;
 619
 620                                 qrtr_requests {
 621                                         qcom,glink-channels = "IPCRTR";
 622                                 };
 623                         };
 624                 };
 625
 626                 qusb_phy_1: qusb@59000 {
 627                         compatible = "qcom,ipq6018-qusb2-phy";
 628                         reg = <0x0 0x059000 0x0 0x180>;
 629                         #phy-cells = <0>;
 630
 631                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 632                                  <&xo>;
 633                         clock-names = "cfg_ahb", "ref";
 634
 635                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 636                         status = "disabled";
 637                 };
 638
 639                 usb2: usb2@7000000 {
 640                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 641                         reg = <0x0 0x070F8800 0x0 0x400>;
 642                         #address-cells = <2>;
 643                         #size-cells = <2>;
 644                         ranges;
 645                         clocks = <&gcc GCC_USB1_MASTER_CLK>,
 646                                  <&gcc GCC_USB1_SLEEP_CLK>,
 647                                  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 648                         clock-names = "master",
 649                                       "sleep",
 650                                       "mock_utmi";
 651
 652                         assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
 653                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 654                         assigned-clock-rates = <133330000>,
 655                                                <24000000>;
 656                         resets = <&gcc GCC_USB1_BCR>;
 657                         status = "disabled";
 658
 659                         dwc_1: usb@7000000 {
 660                                compatible = "snps,dwc3";
 661                                reg = <0x0 0x7000000 0x0 0xcd00>;
 662                                interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 663                                phys = <&qusb_phy_1>;
 664                                phy-names = "usb2-phy";
 665                                tx-fifo-resize;
 666                                snps,is-utmi-l1-suspend;
 667                                snps,hird-threshold = /bits/ 8 <0x0>;
 668                                snps,dis_u2_susphy_quirk;
 669                                snps,dis_u3_susphy_quirk;
 670                                dr_mode = "host";
 671                         };
 672                 };
 673
 674         };
 675
 676         wcss: wcss-smp2p {
 677                 compatible = "qcom,smp2p";
 678                 qcom,smem = <435>, <428>;
 679
 680                 interrupt-parent = <&intc>;
 681                 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
 682
 683                 mboxes = <&apcs_glb 9>;
 684
 685                 qcom,local-pid = <0>;
 686                 qcom,remote-pid = <1>;
 687
 688                 wcss_smp2p_out: master-kernel {
 689                         qcom,entry-name = "master-kernel";
 690                         #qcom,smem-state-cells = <1>;
 691                 };
 692
 693                 wcss_smp2p_in: slave-kernel {
 694                         qcom,entry-name = "slave-kernel";
 695                         interrupt-controller;
 696                         #interrupt-cells = <2>;
 697                 };
 698         };
 699
 700         rpm-glink {
 701                 compatible = "qcom,glink-rpm";
 702                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 703                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 704                 mboxes = <&apcs_glb 0>;
 705
 706                 rpm_requests: glink-channel {
 707                         compatible = "qcom,rpm-ipq6018";
 708                         qcom,glink-channels = "rpm_requests";
 709
 710                         regulators {
 711                                 compatible = "qcom,rpm-mp5496-regulators";
 712
 713                                 ipq6018_s2: s2 {
 714                                         regulator-min-microvolt = <725000>;
 715                                         regulator-max-microvolt = <1062500>;
 716                                         regulator-always-on;
 717                                 };
 718                         };
 719                 };
 720         };
 721 };