arch/arm64/boot/dts/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/memory/tegra186-mc.h>
   7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   8 #include <dt-bindings/power/tegra186-powergate.h>
   9 #include <dt-bindings/reset/tegra186-reset.h>
  10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
  11
  12 / {
  13         compatible = "nvidia,tegra186";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         misc@100000 {
  19                 compatible = "nvidia,tegra186-misc";
  20                 reg = <0x0 0x00100000 0x0 0xf000>,
  21                       <0x0 0x0010f000 0x0 0x1000>;
  22         };
  23
  24         gpio: gpio@2200000 {
  25                 compatible = "nvidia,tegra186-gpio";
  26                 reg-names = "security", "gpio";
  27                 reg = <0x0 0x2200000 0x0 0x10000>,
  28                       <0x0 0x2210000 0x0 0x10000>;
  29                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  34                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  35                 #interrupt-cells = <2>;
  36                 interrupt-controller;
  37                 #gpio-cells = <2>;
  38                 gpio-controller;
  39         };
  40
  41         ethernet@2490000 {
  42                 compatible = "nvidia,tegra186-eqos",
  43                              "snps,dwc-qos-ethernet-4.10";
  44                 reg = <0x0 0x02490000 0x0 0x10000>;
  45                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  46                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  47                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  48                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  49                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  50                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  51                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  52                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  53                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  54                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  55                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  56                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  57                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  58                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  59                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  60                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  61                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  62                 reset-names = "eqos";
  63                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
  64                                 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
  65                 interconnect-names = "dma-mem", "write";
  66                 iommus = <&smmu TEGRA186_SID_EQOS>;
  67                 status = "disabled";
  68
  69                 snps,write-requests = <1>;
  70                 snps,read-requests = <3>;
  71                 snps,burst-map = <0x7>;
  72                 snps,txpbl = <32>;
  73                 snps,rxpbl = <8>;
  74         };
  75
  76         aconnect@2900000 {
  77                 compatible = "nvidia,tegra186-aconnect",
  78                              "nvidia,tegra210-aconnect";
  79                 clocks = <&bpmp TEGRA186_CLK_APE>,
  80                          <&bpmp TEGRA186_CLK_APB2APE>;
  81                 clock-names = "ape", "apb2ape";
  82                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 ranges = <0x02900000 0x0 0x02900000 0x200000>;
  86                 status = "disabled";
  87
  88                 adma: dma-controller@2930000 {
  89                         compatible = "nvidia,tegra186-adma";
  90                         reg = <0x02930000 0x20000>;
  91                         interrupt-parent = <&agic>;
  92                         interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  93                                       <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  94                                       <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  95                                       <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  96                                       <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  97                                       <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  98                                       <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  99                                       <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 100                                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 101                                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 102                                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 104                                       <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 105                                       <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 106                                       <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 107                                       <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 108                                       <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 109                                       <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 110                                       <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 111                                       <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 112                                       <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 113                                       <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 114                                       <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 115                                       <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 116                                       <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 117                                       <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 118                                       <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 119                                       <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 120                                       <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 121                                       <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 122                                       <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 123                                       <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 124                         #dma-cells = <1>;
 125                         clocks = <&bpmp TEGRA186_CLK_AHUB>;
 126                         clock-names = "d_audio";
 127                         status = "disabled";
 128                 };
 129
 130                 agic: interrupt-controller@2a40000 {
 131                         compatible = "nvidia,tegra186-agic",
 132                                      "nvidia,tegra210-agic";
 133                         #interrupt-cells = <3>;
 134                         interrupt-controller;
 135                         reg = <0x02a41000 0x1000>,
 136                               <0x02a42000 0x2000>;
 137                         interrupts = <GIC_SPI 145
 138                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 139                         clocks = <&bpmp TEGRA186_CLK_APE>;
 140                         clock-names = "clk";
 141                         status = "disabled";
 142                 };
 143
 144                 tegra_ahub: ahub@2900800 {
 145                         compatible = "nvidia,tegra186-ahub";
 146                         reg = <0x02900800 0x800>;
 147                         clocks = <&bpmp TEGRA186_CLK_AHUB>;
 148                         clock-names = "ahub";
 149                         assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
 150                         assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 151                         #address-cells = <1>;
 152                         #size-cells = <1>;
 153                         ranges = <0x02900800 0x02900800 0x11800>;
 154                         status = "disabled";
 155
 156                         tegra_admaif: admaif@290f000 {
 157                                 compatible = "nvidia,tegra186-admaif";
 158                                 reg = <0x0290f000 0x1000>;
 159                                 dmas = <&adma 1>, <&adma 1>,
 160                                        <&adma 2>, <&adma 2>,
 161                                        <&adma 3>, <&adma 3>,
 162                                        <&adma 4>, <&adma 4>,
 163                                        <&adma 5>, <&adma 5>,
 164                                        <&adma 6>, <&adma 6>,
 165                                        <&adma 7>, <&adma 7>,
 166                                        <&adma 8>, <&adma 8>,
 167                                        <&adma 9>, <&adma 9>,
 168                                        <&adma 10>, <&adma 10>,
 169                                        <&adma 11>, <&adma 11>,
 170                                        <&adma 12>, <&adma 12>,
 171                                        <&adma 13>, <&adma 13>,
 172                                        <&adma 14>, <&adma 14>,
 173                                        <&adma 15>, <&adma 15>,
 174                                        <&adma 16>, <&adma 16>,
 175                                        <&adma 17>, <&adma 17>,
 176                                        <&adma 18>, <&adma 18>,
 177                                        <&adma 19>, <&adma 19>,
 178                                        <&adma 20>, <&adma 20>;
 179                                 dma-names = "rx1", "tx1",
 180                                             "rx2", "tx2",
 181                                             "rx3", "tx3",
 182                                             "rx4", "tx4",
 183                                             "rx5", "tx5",
 184                                             "rx6", "tx6",
 185                                             "rx7", "tx7",
 186                                             "rx8", "tx8",
 187                                             "rx9", "tx9",
 188                                             "rx10", "tx10",
 189                                             "rx11", "tx11",
 190                                             "rx12", "tx12",
 191                                             "rx13", "tx13",
 192                                             "rx14", "tx14",
 193                                             "rx15", "tx15",
 194                                             "rx16", "tx16",
 195                                             "rx17", "tx17",
 196                                             "rx18", "tx18",
 197                                             "rx19", "tx19",
 198                                             "rx20", "tx20";
 199                                 status = "disabled";
 200                         };
 201
 202                         tegra_i2s1: i2s@2901000 {
 203                                 compatible = "nvidia,tegra186-i2s",
 204                                              "nvidia,tegra210-i2s";
 205                                 reg = <0x2901000 0x100>;
 206                                 clocks = <&bpmp TEGRA186_CLK_I2S1>,
 207                                          <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
 208                                 clock-names = "i2s", "sync_input";
 209                                 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
 210                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 211                                 assigned-clock-rates = <1536000>;
 212                                 sound-name-prefix = "I2S1";
 213                                 status = "disabled";
 214                         };
 215
 216                         tegra_i2s2: i2s@2901100 {
 217                                 compatible = "nvidia,tegra186-i2s",
 218                                              "nvidia,tegra210-i2s";
 219                                 reg = <0x2901100 0x100>;
 220                                 clocks = <&bpmp TEGRA186_CLK_I2S2>,
 221                                          <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
 222                                 clock-names = "i2s", "sync_input";
 223                                 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
 224                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 225                                 assigned-clock-rates = <1536000>;
 226                                 sound-name-prefix = "I2S2";
 227                                 status = "disabled";
 228                         };
 229
 230                         tegra_i2s3: i2s@2901200 {
 231                                 compatible = "nvidia,tegra186-i2s",
 232                                              "nvidia,tegra210-i2s";
 233                                 reg = <0x2901200 0x100>;
 234                                 clocks = <&bpmp TEGRA186_CLK_I2S3>,
 235                                          <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
 236                                 clock-names = "i2s", "sync_input";
 237                                 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
 238                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 239                                 assigned-clock-rates = <1536000>;
 240                                 sound-name-prefix = "I2S3";
 241                                 status = "disabled";
 242                         };
 243
 244                         tegra_i2s4: i2s@2901300 {
 245                                 compatible = "nvidia,tegra186-i2s",
 246                                              "nvidia,tegra210-i2s";
 247                                 reg = <0x2901300 0x100>;
 248                                 clocks = <&bpmp TEGRA186_CLK_I2S4>,
 249                                          <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
 250                                 clock-names = "i2s", "sync_input";
 251                                 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
 252                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 253                                 assigned-clock-rates = <1536000>;
 254                                 sound-name-prefix = "I2S4";
 255                                 status = "disabled";
 256                         };
 257
 258                         tegra_i2s5: i2s@2901400 {
 259                                 compatible = "nvidia,tegra186-i2s",
 260                                              "nvidia,tegra210-i2s";
 261                                 reg = <0x2901400 0x100>;
 262                                 clocks = <&bpmp TEGRA186_CLK_I2S5>,
 263                                          <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
 264                                 clock-names = "i2s", "sync_input";
 265                                 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
 266                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 267                                 assigned-clock-rates = <1536000>;
 268                                 sound-name-prefix = "I2S5";
 269                                 status = "disabled";
 270                         };
 271
 272                         tegra_i2s6: i2s@2901500 {
 273                                 compatible = "nvidia,tegra186-i2s",
 274                                              "nvidia,tegra210-i2s";
 275                                 reg = <0x2901500 0x100>;
 276                                 clocks = <&bpmp TEGRA186_CLK_I2S6>,
 277                                          <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
 278                                 clock-names = "i2s", "sync_input";
 279                                 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
 280                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 281                                 assigned-clock-rates = <1536000>;
 282                                 sound-name-prefix = "I2S6";
 283                                 status = "disabled";
 284                         };
 285
 286                         tegra_dmic1: dmic@2904000 {
 287                                 compatible = "nvidia,tegra210-dmic";
 288                                 reg = <0x2904000 0x100>;
 289                                 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
 290                                 clock-names = "dmic";
 291                                 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
 292                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 293                                 assigned-clock-rates = <3072000>;
 294                                 sound-name-prefix = "DMIC1";
 295                                 status = "disabled";
 296                         };
 297
 298                         tegra_dmic2: dmic@2904100 {
 299                                 compatible = "nvidia,tegra210-dmic";
 300                                 reg = <0x2904100 0x100>;
 301                                 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
 302                                 clock-names = "dmic";
 303                                 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
 304                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 305                                 assigned-clock-rates = <3072000>;
 306                                 sound-name-prefix = "DMIC2";
 307                                 status = "disabled";
 308                         };
 309
 310                         tegra_dmic3: dmic@2904200 {
 311                                 compatible = "nvidia,tegra210-dmic";
 312                                 reg = <0x2904200 0x100>;
 313                                 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
 314                                 clock-names = "dmic";
 315                                 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
 316                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 317                                 assigned-clock-rates = <3072000>;
 318                                 sound-name-prefix = "DMIC3";
 319                                 status = "disabled";
 320                         };
 321
 322                         tegra_dmic4: dmic@2904300 {
 323                                 compatible = "nvidia,tegra210-dmic";
 324                                 reg = <0x2904300 0x100>;
 325                                 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
 326                                 clock-names = "dmic";
 327                                 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
 328                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 329                                 assigned-clock-rates = <3072000>;
 330                                 sound-name-prefix = "DMIC4";
 331                                 status = "disabled";
 332                         };
 333
 334                         tegra_dspk1: dspk@2905000 {
 335                                 compatible = "nvidia,tegra186-dspk";
 336                                 reg = <0x2905000 0x100>;
 337                                 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
 338                                 clock-names = "dspk";
 339                                 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
 340                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 341                                 assigned-clock-rates = <12288000>;
 342                                 sound-name-prefix = "DSPK1";
 343                                 status = "disabled";
 344                         };
 345
 346                         tegra_dspk2: dspk@2905100 {
 347                                 compatible = "nvidia,tegra186-dspk";
 348                                 reg = <0x2905100 0x100>;
 349                                 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
 350                                 clock-names = "dspk";
 351                                 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
 352                                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
 353                                 assigned-clock-rates = <12288000>;
 354                                 sound-name-prefix = "DSPK2";
 355                                 status = "disabled";
 356                         };
 357                 };
 358         };
 359
 360         mc: memory-controller@2c00000 {
 361                 compatible = "nvidia,tegra186-mc";
 362                 reg = <0x0 0x02c00000 0x0 0xb0000>;
 363                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 364                 status = "disabled";
 365
 366                 #interconnect-cells = <1>;
 367                 #address-cells = <2>;
 368                 #size-cells = <2>;
 369
 370                 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
 371
 372                 /*
 373                  * Memory clients have access to all 40 bits that the memory
 374                  * controller can address.
 375                  */
 376                 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
 377
 378                 emc: external-memory-controller@2c60000 {
 379                         compatible = "nvidia,tegra186-emc";
 380                         reg = <0x0 0x02c60000 0x0 0x50000>;
 381                         interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&bpmp TEGRA186_CLK_EMC>;
 383                         clock-names = "emc";
 384
 385                         #interconnect-cells = <0>;
 386
 387                         nvidia,bpmp = <&bpmp>;
 388                 };
 389         };
 390
 391         uarta: serial@3100000 {
 392                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 393                 reg = <0x0 0x03100000 0x0 0x40>;
 394                 reg-shift = <2>;
 395                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
 397                 clock-names = "serial";
 398                 resets = <&bpmp TEGRA186_RESET_UARTA>;
 399                 reset-names = "serial";
 400                 status = "disabled";
 401         };
 402
 403         uartb: serial@3110000 {
 404                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 405                 reg = <0x0 0x03110000 0x0 0x40>;
 406                 reg-shift = <2>;
 407                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
 409                 clock-names = "serial";
 410                 resets = <&bpmp TEGRA186_RESET_UARTB>;
 411                 reset-names = "serial";
 412                 status = "disabled";
 413         };
 414
 415         uartd: serial@3130000 {
 416                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 417                 reg = <0x0 0x03130000 0x0 0x40>;
 418                 reg-shift = <2>;
 419                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
 421                 clock-names = "serial";
 422                 resets = <&bpmp TEGRA186_RESET_UARTD>;
 423                 reset-names = "serial";
 424                 status = "disabled";
 425         };
 426
 427         uarte: serial@3140000 {
 428                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 429                 reg = <0x0 0x03140000 0x0 0x40>;
 430                 reg-shift = <2>;
 431                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 433                 clock-names = "serial";
 434                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 435                 reset-names = "serial";
 436                 status = "disabled";
 437         };
 438
 439         uartf: serial@3150000 {
 440                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 441                 reg = <0x0 0x03150000 0x0 0x40>;
 442                 reg-shift = <2>;
 443                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 445                 clock-names = "serial";
 446                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 447                 reset-names = "serial";
 448                 status = "disabled";
 449         };
 450
 451         gen1_i2c: i2c@3160000 {
 452                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 453                 reg = <0x0 0x03160000 0x0 0x10000>;
 454                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 458                 clock-names = "div-clk";
 459                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 460                 reset-names = "i2c";
 461                 status = "disabled";
 462         };
 463
 464         cam_i2c: i2c@3180000 {
 465                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 466                 reg = <0x0 0x03180000 0x0 0x10000>;
 467                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 471                 clock-names = "div-clk";
 472                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 473                 reset-names = "i2c";
 474                 status = "disabled";
 475         };
 476
 477         /* shares pads with dpaux1 */
 478         dp_aux_ch1_i2c: i2c@3190000 {
 479                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 480                 reg = <0x0 0x03190000 0x0 0x10000>;
 481                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 485                 clock-names = "div-clk";
 486                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 487                 reset-names = "i2c";
 488                 pinctrl-names = "default", "idle";
 489                 pinctrl-0 = <&state_dpaux1_i2c>;
 490                 pinctrl-1 = <&state_dpaux1_off>;
 491                 status = "disabled";
 492         };
 493
 494         /* controlled by BPMP, should not be enabled */
 495         pwr_i2c: i2c@31a0000 {
 496                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 497                 reg = <0x0 0x031a0000 0x0 0x10000>;
 498                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 502                 clock-names = "div-clk";
 503                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 504                 reset-names = "i2c";
 505                 status = "disabled";
 506         };
 507
 508         /* shares pads with dpaux0 */
 509         dp_aux_ch0_i2c: i2c@31b0000 {
 510                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 511                 reg = <0x0 0x031b0000 0x0 0x10000>;
 512                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 516                 clock-names = "div-clk";
 517                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 518                 reset-names = "i2c";
 519                 pinctrl-names = "default", "idle";
 520                 pinctrl-0 = <&state_dpaux_i2c>;
 521                 pinctrl-1 = <&state_dpaux_off>;
 522                 status = "disabled";
 523         };
 524
 525         gen7_i2c: i2c@31c0000 {
 526                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 527                 reg = <0x0 0x031c0000 0x0 0x10000>;
 528                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 532                 clock-names = "div-clk";
 533                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 534                 reset-names = "i2c";
 535                 status = "disabled";
 536         };
 537
 538         gen9_i2c: i2c@31e0000 {
 539                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 540                 reg = <0x0 0x031e0000 0x0 0x10000>;
 541                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 545                 clock-names = "div-clk";
 546                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 547                 reset-names = "i2c";
 548                 status = "disabled";
 549         };
 550
 551         pwm1: pwm@3280000 {
 552                 compatible = "nvidia,tegra186-pwm";
 553                 reg = <0x0 0x3280000 0x0 0x10000>;
 554                 clocks = <&bpmp TEGRA186_CLK_PWM1>;
 555                 clock-names = "pwm";
 556                 resets = <&bpmp TEGRA186_RESET_PWM1>;
 557                 reset-names = "pwm";
 558                 status = "disabled";
 559                 #pwm-cells = <2>;
 560         };
 561
 562         pwm2: pwm@3290000 {
 563                 compatible = "nvidia,tegra186-pwm";
 564                 reg = <0x0 0x3290000 0x0 0x10000>;
 565                 clocks = <&bpmp TEGRA186_CLK_PWM2>;
 566                 clock-names = "pwm";
 567                 resets = <&bpmp TEGRA186_RESET_PWM2>;
 568                 reset-names = "pwm";
 569                 status = "disabled";
 570                 #pwm-cells = <2>;
 571         };
 572
 573         pwm3: pwm@32a0000 {
 574                 compatible = "nvidia,tegra186-pwm";
 575                 reg = <0x0 0x32a0000 0x0 0x10000>;
 576                 clocks = <&bpmp TEGRA186_CLK_PWM3>;
 577                 clock-names = "pwm";
 578                 resets = <&bpmp TEGRA186_RESET_PWM3>;
 579                 reset-names = "pwm";
 580                 status = "disabled";
 581                 #pwm-cells = <2>;
 582         };
 583
 584         pwm5: pwm@32c0000 {
 585                 compatible = "nvidia,tegra186-pwm";
 586                 reg = <0x0 0x32c0000 0x0 0x10000>;
 587                 clocks = <&bpmp TEGRA186_CLK_PWM5>;
 588                 clock-names = "pwm";
 589                 resets = <&bpmp TEGRA186_RESET_PWM5>;
 590                 reset-names = "pwm";
 591                 status = "disabled";
 592                 #pwm-cells = <2>;
 593         };
 594
 595         pwm6: pwm@32d0000 {
 596                 compatible = "nvidia,tegra186-pwm";
 597                 reg = <0x0 0x32d0000 0x0 0x10000>;
 598                 clocks = <&bpmp TEGRA186_CLK_PWM6>;
 599                 clock-names = "pwm";
 600                 resets = <&bpmp TEGRA186_RESET_PWM6>;
 601                 reset-names = "pwm";
 602                 status = "disabled";
 603                 #pwm-cells = <2>;
 604         };
 605
 606         pwm7: pwm@32e0000 {
 607                 compatible = "nvidia,tegra186-pwm";
 608                 reg = <0x0 0x32e0000 0x0 0x10000>;
 609                 clocks = <&bpmp TEGRA186_CLK_PWM7>;
 610                 clock-names = "pwm";
 611                 resets = <&bpmp TEGRA186_RESET_PWM7>;
 612                 reset-names = "pwm";
 613                 status = "disabled";
 614                 #pwm-cells = <2>;
 615         };
 616
 617         pwm8: pwm@32f0000 {
 618                 compatible = "nvidia,tegra186-pwm";
 619                 reg = <0x0 0x32f0000 0x0 0x10000>;
 620                 clocks = <&bpmp TEGRA186_CLK_PWM8>;
 621                 clock-names = "pwm";
 622                 resets = <&bpmp TEGRA186_RESET_PWM8>;
 623                 reset-names = "pwm";
 624                 status = "disabled";
 625                 #pwm-cells = <2>;
 626         };
 627
 628         sdmmc1: mmc@3400000 {
 629                 compatible = "nvidia,tegra186-sdhci";
 630                 reg = <0x0 0x03400000 0x0 0x10000>;
 631                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
 633                          <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
 634                 clock-names = "sdhci", "tmclk";
 635                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 636                 reset-names = "sdhci";
 637                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
 638                                 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
 639                 interconnect-names = "dma-mem", "write";
 640                 iommus = <&smmu TEGRA186_SID_SDMMC1>;
 641                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 642                 pinctrl-0 = <&sdmmc1_3v3>;
 643                 pinctrl-1 = <&sdmmc1_1v8>;
 644                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 645                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 646                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 647                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 648                 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
 649                 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
 650                 nvidia,default-tap = <0x5>;
 651                 nvidia,default-trim = <0xb>;
 652                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
 653                                   <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 654                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 655                 status = "disabled";
 656         };
 657
 658         sdmmc2: mmc@3420000 {
 659                 compatible = "nvidia,tegra186-sdhci";
 660                 reg = <0x0 0x03420000 0x0 0x10000>;
 661                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
 663                          <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
 664                 clock-names = "sdhci", "tmclk";
 665                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 666                 reset-names = "sdhci";
 667                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
 668                                 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
 669                 interconnect-names = "dma-mem", "write";
 670                 iommus = <&smmu TEGRA186_SID_SDMMC2>;
 671                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 672                 pinctrl-0 = <&sdmmc2_3v3>;
 673                 pinctrl-1 = <&sdmmc2_1v8>;
 674                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 675                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 676                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 677                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 678                 nvidia,default-tap = <0x5>;
 679                 nvidia,default-trim = <0xb>;
 680                 status = "disabled";
 681         };
 682
 683         sdmmc3: mmc@3440000 {
 684                 compatible = "nvidia,tegra186-sdhci";
 685                 reg = <0x0 0x03440000 0x0 0x10000>;
 686                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 687                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
 688                          <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
 689                 clock-names = "sdhci", "tmclk";
 690                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 691                 reset-names = "sdhci";
 692                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
 693                                 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
 694                 interconnect-names = "dma-mem", "write";
 695                 iommus = <&smmu TEGRA186_SID_SDMMC3>;
 696                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 697                 pinctrl-0 = <&sdmmc3_3v3>;
 698                 pinctrl-1 = <&sdmmc3_1v8>;
 699                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 700                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 701                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 702                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 703                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 704                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 705                 nvidia,default-tap = <0x5>;
 706                 nvidia,default-trim = <0xb>;
 707                 status = "disabled";
 708         };
 709
 710         sdmmc4: mmc@3460000 {
 711                 compatible = "nvidia,tegra186-sdhci";
 712                 reg = <0x0 0x03460000 0x0 0x10000>;
 713                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
 715                          <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
 716                 clock-names = "sdhci", "tmclk";
 717                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
 718                                   <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 719                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 720                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 721                 reset-names = "sdhci";
 722                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
 723                                 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
 724                 interconnect-names = "dma-mem", "write";
 725                 iommus = <&smmu TEGRA186_SID_SDMMC4>;
 726                 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
 727                 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
 728                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 729                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
 730                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 731                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
 732                 nvidia,default-tap = <0x9>;
 733                 nvidia,default-trim = <0x5>;
 734                 nvidia,dqs-trim = <63>;
 735                 mmc-hs400-1_8v;
 736                 supports-cqe;
 737                 status = "disabled";
 738         };
 739
 740         hda@3510000 {
 741                 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
 742                 reg = <0x0 0x03510000 0x0 0x10000>;
 743                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 744                 clocks = <&bpmp TEGRA186_CLK_HDA>,
 745                          <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
 746                          <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
 747                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 748                 resets = <&bpmp TEGRA186_RESET_HDA>,
 749                          <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
 750                          <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
 751                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 752                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 753                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
 754                                 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
 755                 interconnect-names = "dma-mem", "write";
 756                 iommus = <&smmu TEGRA186_SID_HDA>;
 757                 status = "disabled";
 758         };
 759
 760         padctl: padctl@3520000 {
 761                 compatible = "nvidia,tegra186-xusb-padctl";
 762                 reg = <0x0 0x03520000 0x0 0x1000>,
 763                       <0x0 0x03540000 0x0 0x1000>;
 764                 reg-names = "padctl", "ao";
 765                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 766
 767                 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
 768                 reset-names = "padctl";
 769
 770                 status = "disabled";
 771
 772                 pads {
 773                         usb2 {
 774                                 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
 775                                 clock-names = "trk";
 776                                 status = "disabled";
 777
 778                                 lanes {
 779                                         usb2-0 {
 780                                                 status = "disabled";
 781                                                 #phy-cells = <0>;
 782                                         };
 783
 784                                         usb2-1 {
 785                                                 status = "disabled";
 786                                                 #phy-cells = <0>;
 787                                         };
 788
 789                                         usb2-2 {
 790                                                 status = "disabled";
 791                                                 #phy-cells = <0>;
 792                                         };
 793                                 };
 794                         };
 795
 796                         hsic {
 797                                 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
 798                                 clock-names = "trk";
 799                                 status = "disabled";
 800
 801                                 lanes {
 802                                         hsic-0 {
 803                                                 status = "disabled";
 804                                                 #phy-cells = <0>;
 805                                         };
 806                                 };
 807                         };
 808
 809                         usb3 {
 810                                 status = "disabled";
 811
 812                                 lanes {
 813                                         usb3-0 {
 814                                                 status = "disabled";
 815                                                 #phy-cells = <0>;
 816                                         };
 817
 818                                         usb3-1 {
 819                                                 status = "disabled";
 820                                                 #phy-cells = <0>;
 821                                         };
 822
 823                                         usb3-2 {
 824                                                 status = "disabled";
 825                                                 #phy-cells = <0>;
 826                                         };
 827                                 };
 828                         };
 829                 };
 830
 831                 ports {
 832                         usb2-0 {
 833                                 status = "disabled";
 834                         };
 835
 836                         usb2-1 {
 837                                 status = "disabled";
 838                         };
 839
 840                         usb2-2 {
 841                                 status = "disabled";
 842                         };
 843
 844                         hsic-0 {
 845                                 status = "disabled";
 846                         };
 847
 848                         usb3-0 {
 849                                 status = "disabled";
 850                         };
 851
 852                         usb3-1 {
 853                                 status = "disabled";
 854                         };
 855
 856                         usb3-2 {
 857                                 status = "disabled";
 858                         };
 859                 };
 860         };
 861
 862         usb@3530000 {
 863                 compatible = "nvidia,tegra186-xusb";
 864                 reg = <0x0 0x03530000 0x0 0x8000>,
 865                       <0x0 0x03538000 0x0 0x1000>;
 866                 reg-names = "hcd", "fpci";
 867                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 868                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
 870                          <&bpmp TEGRA186_CLK_XUSB_FALCON>,
 871                          <&bpmp TEGRA186_CLK_XUSB_SS>,
 872                          <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
 873                          <&bpmp TEGRA186_CLK_CLK_M>,
 874                          <&bpmp TEGRA186_CLK_XUSB_FS>,
 875                          <&bpmp TEGRA186_CLK_PLLU>,
 876                          <&bpmp TEGRA186_CLK_CLK_M>,
 877                          <&bpmp TEGRA186_CLK_PLLE>;
 878                 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
 879                               "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
 880                               "pll_u_480m", "clk_m", "pll_e";
 881                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
 882                                 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
 883                 power-domain-names = "xusb_host", "xusb_ss";
 884                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
 885                                 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
 886                 interconnect-names = "dma-mem", "write";
 887                 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
 888                 #address-cells = <1>;
 889                 #size-cells = <0>;
 890                 status = "disabled";
 891
 892                 nvidia,xusb-padctl = <&padctl>;
 893         };
 894
 895         usb@3550000 {
 896                 compatible = "nvidia,tegra186-xudc";
 897                 reg = <0x0 0x03550000 0x0 0x8000>,
 898                       <0x0 0x03558000 0x0 0x1000>;
 899                 reg-names = "base", "fpci";
 900                 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 901                 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
 902                          <&bpmp TEGRA186_CLK_XUSB_SS>,
 903                          <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
 904                          <&bpmp TEGRA186_CLK_XUSB_FS>;
 905                 clock-names = "dev", "ss", "ss_src", "fs_src";
 906                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
 907                                 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
 908                 interconnect-names = "dma-mem", "write";
 909                 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
 910                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
 911                                 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
 912                 power-domain-names = "dev", "ss";
 913                 nvidia,xusb-padctl = <&padctl>;
 914                 status = "disabled";
 915         };
 916
 917         fuse@3820000 {
 918                 compatible = "nvidia,tegra186-efuse";
 919                 reg = <0x0 0x03820000 0x0 0x10000>;
 920                 clocks = <&bpmp TEGRA186_CLK_FUSE>;
 921                 clock-names = "fuse";
 922         };
 923
 924         gic: interrupt-controller@3881000 {
 925                 compatible = "arm,gic-400";
 926                 #interrupt-cells = <3>;
 927                 interrupt-controller;
 928                 reg = <0x0 0x03881000 0x0 0x1000>,
 929                       <0x0 0x03882000 0x0 0x2000>,
 930                       <0x0 0x03884000 0x0 0x2000>,
 931                       <0x0 0x03886000 0x0 0x2000>;
 932                 interrupts = <GIC_PPI 9
 933                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 934                 interrupt-parent = <&gic>;
 935         };
 936
 937         cec@3960000 {
 938                 compatible = "nvidia,tegra186-cec";
 939                 reg = <0x0 0x03960000 0x0 0x10000>;
 940                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 941                 clocks = <&bpmp TEGRA186_CLK_CEC>;
 942                 clock-names = "cec";
 943                 status = "disabled";
 944         };
 945
 946         hsp_top0: hsp@3c00000 {
 947                 compatible = "nvidia,tegra186-hsp";
 948                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 949                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 950                 interrupt-names = "doorbell";
 951                 #mbox-cells = <2>;
 952                 status = "disabled";
 953         };
 954
 955         gen2_i2c: i2c@c240000 {
 956                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 957                 reg = <0x0 0x0c240000 0x0 0x10000>;
 958                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 959                 #address-cells = <1>;
 960                 #size-cells = <0>;
 961                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 962                 clock-names = "div-clk";
 963                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 964                 reset-names = "i2c";
 965                 status = "disabled";
 966         };
 967
 968         gen8_i2c: i2c@c250000 {
 969                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 970                 reg = <0x0 0x0c250000 0x0 0x10000>;
 971                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 972                 #address-cells = <1>;
 973                 #size-cells = <0>;
 974                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 975                 clock-names = "div-clk";
 976                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 977                 reset-names = "i2c";
 978                 status = "disabled";
 979         };
 980
 981         uartc: serial@c280000 {
 982                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 983                 reg = <0x0 0x0c280000 0x0 0x40>;
 984                 reg-shift = <2>;
 985                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 986                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 987                 clock-names = "serial";
 988                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 989                 reset-names = "serial";
 990                 status = "disabled";
 991         };
 992
 993         uartg: serial@c290000 {
 994                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 995                 reg = <0x0 0x0c290000 0x0 0x40>;
 996                 reg-shift = <2>;
 997                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 998                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 999                 clock-names = "serial";
1000                 resets = <&bpmp TEGRA186_RESET_UARTG>;
1001                 reset-names = "serial";
1002                 status = "disabled";
1003         };
1004
1005         rtc: rtc@c2a0000 {
1006                 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1007                 reg = <0 0x0c2a0000 0 0x10000>;
1008                 interrupt-parent = <&pmc>;
1009                 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1011                 clock-names = "rtc";
1012                 status = "disabled";
1013         };
1014
1015         gpio_aon: gpio@c2f0000 {
1016                 compatible = "nvidia,tegra186-gpio-aon";
1017                 reg-names = "security", "gpio";
1018                 reg = <0x0 0xc2f0000 0x0 0x1000>,
1019                       <0x0 0xc2f1000 0x0 0x1000>;
1020                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1021                 gpio-controller;
1022                 #gpio-cells = <2>;
1023                 interrupt-controller;
1024                 #interrupt-cells = <2>;
1025         };
1026
1027         pwm4: pwm@c340000 {
1028                 compatible = "nvidia,tegra186-pwm";
1029                 reg = <0x0 0xc340000 0x0 0x10000>;
1030                 clocks = <&bpmp TEGRA186_CLK_PWM4>;
1031                 clock-names = "pwm";
1032                 resets = <&bpmp TEGRA186_RESET_PWM4>;
1033                 reset-names = "pwm";
1034                 status = "disabled";
1035                 #pwm-cells = <2>;
1036         };
1037
1038         pmc: pmc@c360000 {
1039                 compatible = "nvidia,tegra186-pmc";
1040                 reg = <0 0x0c360000 0 0x10000>,
1041                       <0 0x0c370000 0 0x10000>,
1042                       <0 0x0c380000 0 0x10000>,
1043                       <0 0x0c390000 0 0x10000>;
1044                 reg-names = "pmc", "wake", "aotag", "scratch";
1045
1046                 #interrupt-cells = <2>;
1047                 interrupt-controller;
1048
1049                 sdmmc1_3v3: sdmmc1-3v3 {
1050                         pins = "sdmmc1-hv";
1051                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1052                 };
1053
1054                 sdmmc1_1v8: sdmmc1-1v8 {
1055                         pins = "sdmmc1-hv";
1056                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1057                 };
1058
1059                 sdmmc2_3v3: sdmmc2-3v3 {
1060                         pins = "sdmmc2-hv";
1061                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1062                 };
1063
1064                 sdmmc2_1v8: sdmmc2-1v8 {
1065                         pins = "sdmmc2-hv";
1066                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1067                 };
1068
1069                 sdmmc3_3v3: sdmmc3-3v3 {
1070                         pins = "sdmmc3-hv";
1071                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1072                 };
1073
1074                 sdmmc3_1v8: sdmmc3-1v8 {
1075                         pins = "sdmmc3-hv";
1076                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1077                 };
1078         };
1079
1080         ccplex@e000000 {
1081                 compatible = "nvidia,tegra186-ccplex-cluster";
1082                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
1083
1084                 nvidia,bpmp = <&bpmp>;
1085         };
1086
1087         pcie@10003000 {
1088                 compatible = "nvidia,tegra186-pcie";
1089                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1090                 device_type = "pci";
1091                 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1092                       <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1093                       <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1094                 reg-names = "pads", "afi", "cs";
1095
1096                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1097                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1098                 interrupt-names = "intr", "msi";
1099
1100                 #interrupt-cells = <1>;
1101                 interrupt-map-mask = <0 0 0 0>;
1102                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1103
1104                 bus-range = <0x00 0xff>;
1105                 #address-cells = <3>;
1106                 #size-cells = <2>;
1107
1108                 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1109                          <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1110                          <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1111                          <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1112                          <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1113                          <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1114
1115                 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1116                          <&bpmp TEGRA186_CLK_AFI>,
1117                          <&bpmp TEGRA186_CLK_PLLE>;
1118                 clock-names = "pex", "afi", "pll_e";
1119
1120                 resets = <&bpmp TEGRA186_RESET_PCIE>,
1121                          <&bpmp TEGRA186_RESET_AFI>,
1122                          <&bpmp TEGRA186_RESET_PCIEXCLK>;
1123                 reset-names = "pex", "afi", "pcie_x";
1124
1125                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1126                                 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1127                 interconnect-names = "dma-mem", "write";
1128
1129                 iommus = <&smmu TEGRA186_SID_AFI>;
1130                 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1131                 iommu-map-mask = <0x0>;
1132
1133                 status = "disabled";
1134
1135                 pci@1,0 {
1136                         device_type = "pci";
1137                         assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1138                         reg = <0x000800 0 0 0 0>;
1139                         status = "disabled";
1140
1141                         #address-cells = <3>;
1142                         #size-cells = <2>;
1143                         ranges;
1144
1145                         nvidia,num-lanes = <2>;
1146                 };
1147
1148                 pci@2,0 {
1149                         device_type = "pci";
1150                         assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1151                         reg = <0x001000 0 0 0 0>;
1152                         status = "disabled";
1153
1154                         #address-cells = <3>;
1155                         #size-cells = <2>;
1156                         ranges;
1157
1158                         nvidia,num-lanes = <1>;
1159                 };
1160
1161                 pci@3,0 {
1162                         device_type = "pci";
1163                         assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1164                         reg = <0x001800 0 0 0 0>;
1165                         status = "disabled";
1166
1167                         #address-cells = <3>;
1168                         #size-cells = <2>;
1169                         ranges;
1170
1171                         nvidia,num-lanes = <1>;
1172                 };
1173         };
1174
1175         smmu: iommu@12000000 {
1176                 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1177                 reg = <0 0x12000000 0 0x800000>;
1178                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1179                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1180                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1181                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1182                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1183                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1184                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1185                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1186                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1187                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1188                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1189                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1190                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1191                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1192                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1193                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1194                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1195                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1196                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1197                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1198                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1199                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1200                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1201                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1202                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1203                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1204                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1205                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1206                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1207                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1208                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1209                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1210                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1211                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1212                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1213                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1214                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1215                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1216                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1217                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1218                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1219                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1220                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1221                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1222                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1223                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1224                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1225                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1226                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1227                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1228                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1229                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1230                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1231                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1232                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1233                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1234                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1235                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1236                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1237                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1238                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1239                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1240                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1241                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1242                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1243                 stream-match-mask = <0x7f80>;
1244                 #global-interrupts = <1>;
1245                 #iommu-cells = <1>;
1246
1247                 nvidia,memory-controller = <&mc>;
1248         };
1249
1250         host1x@13e00000 {
1251                 compatible = "nvidia,tegra186-host1x";
1252                 reg = <0x0 0x13e00000 0x0 0x10000>,
1253                       <0x0 0x13e10000 0x0 0x10000>;
1254                 reg-names = "hypervisor", "vm";
1255                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1256                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1257                 interrupt-names = "syncpt", "host1x";
1258                 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1259                 clock-names = "host1x";
1260                 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1261                 reset-names = "host1x";
1262
1263                 #address-cells = <1>;
1264                 #size-cells = <1>;
1265
1266                 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1267
1268                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1269                 interconnect-names = "dma-mem";
1270
1271                 iommus = <&smmu TEGRA186_SID_HOST1X>;
1272
1273                 dpaux1: dpaux@15040000 {
1274                         compatible = "nvidia,tegra186-dpaux";
1275                         reg = <0x15040000 0x10000>;
1276                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1277                         clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1278                                  <&bpmp TEGRA186_CLK_PLLDP>;
1279                         clock-names = "dpaux", "parent";
1280                         resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1281                         reset-names = "dpaux";
1282                         status = "disabled";
1283
1284                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1285
1286                         state_dpaux1_aux: pinmux-aux {
1287                                 groups = "dpaux-io";
1288                                 function = "aux";
1289                         };
1290
1291                         state_dpaux1_i2c: pinmux-i2c {
1292                                 groups = "dpaux-io";
1293                                 function = "i2c";
1294                         };
1295
1296                         state_dpaux1_off: pinmux-off {
1297                                 groups = "dpaux-io";
1298                                 function = "off";
1299                         };
1300
1301                         i2c-bus {
1302                                 #address-cells = <1>;
1303                                 #size-cells = <0>;
1304                         };
1305                 };
1306
1307                 display-hub@15200000 {
1308                         compatible = "nvidia,tegra186-display";
1309                         reg = <0x15200000 0x00040000>;
1310                         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1311                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1312                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1313                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1314                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1315                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1316                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1317                         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1318                                       "wgrp3", "wgrp4", "wgrp5";
1319                         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1320                                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1321                                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1322                         clock-names = "disp", "dsc", "hub";
1323                         status = "disabled";
1324
1325                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1326
1327                         #address-cells = <1>;
1328                         #size-cells = <1>;
1329
1330                         ranges = <0x15200000 0x15200000 0x40000>;
1331
1332                         display@15200000 {
1333                                 compatible = "nvidia,tegra186-dc";
1334                                 reg = <0x15200000 0x10000>;
1335                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1336                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1337                                 clock-names = "dc";
1338                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1339                                 reset-names = "dc";
1340
1341                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1342                                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1343                                                 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1344                                 interconnect-names = "dma-mem", "read-1";
1345                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1346
1347                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1348                                 nvidia,head = <0>;
1349                         };
1350
1351                         display@15210000 {
1352                                 compatible = "nvidia,tegra186-dc";
1353                                 reg = <0x15210000 0x10000>;
1354                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1355                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1356                                 clock-names = "dc";
1357                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1358                                 reset-names = "dc";
1359
1360                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1361                                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1362                                                 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1363                                 interconnect-names = "dma-mem", "read-1";
1364                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1365
1366                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1367                                 nvidia,head = <1>;
1368                         };
1369
1370                         display@15220000 {
1371                                 compatible = "nvidia,tegra186-dc";
1372                                 reg = <0x15220000 0x10000>;
1373                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1374                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1375                                 clock-names = "dc";
1376                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1377                                 reset-names = "dc";
1378
1379                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1380                                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1381                                                 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1382                                 interconnect-names = "dma-mem", "read-1";
1383                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1384
1385                                 nvidia,outputs = <&sor0 &sor1>;
1386                                 nvidia,head = <2>;
1387                         };
1388                 };
1389
1390                 dsia: dsi@15300000 {
1391                         compatible = "nvidia,tegra186-dsi";
1392                         reg = <0x15300000 0x10000>;
1393                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1394                         clocks = <&bpmp TEGRA186_CLK_DSI>,
1395                                  <&bpmp TEGRA186_CLK_DSIA_LP>,
1396                                  <&bpmp TEGRA186_CLK_PLLD>;
1397                         clock-names = "dsi", "lp", "parent";
1398                         resets = <&bpmp TEGRA186_RESET_DSI>;
1399                         reset-names = "dsi";
1400                         status = "disabled";
1401
1402                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1403                 };
1404
1405                 vic@15340000 {
1406                         compatible = "nvidia,tegra186-vic";
1407                         reg = <0x15340000 0x40000>;
1408                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1409                         clocks = <&bpmp TEGRA186_CLK_VIC>;
1410                         clock-names = "vic";
1411                         resets = <&bpmp TEGRA186_RESET_VIC>;
1412                         reset-names = "vic";
1413
1414                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1415                         interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1416                                         <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1417                         interconnect-names = "dma-mem", "write";
1418                         iommus = <&smmu TEGRA186_SID_VIC>;
1419                 };
1420
1421                 dsib: dsi@15400000 {
1422                         compatible = "nvidia,tegra186-dsi";
1423                         reg = <0x15400000 0x10000>;
1424                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1425                         clocks = <&bpmp TEGRA186_CLK_DSIB>,
1426                                  <&bpmp TEGRA186_CLK_DSIB_LP>,
1427                                  <&bpmp TEGRA186_CLK_PLLD>;
1428                         clock-names = "dsi", "lp", "parent";
1429                         resets = <&bpmp TEGRA186_RESET_DSIB>;
1430                         reset-names = "dsi";
1431                         status = "disabled";
1432
1433                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1434                 };
1435
1436                 sor0: sor@15540000 {
1437                         compatible = "nvidia,tegra186-sor";
1438                         reg = <0x15540000 0x10000>;
1439                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1440                         clocks = <&bpmp TEGRA186_CLK_SOR0>,
1441                                  <&bpmp TEGRA186_CLK_SOR0_OUT>,
1442                                  <&bpmp TEGRA186_CLK_PLLD2>,
1443                                  <&bpmp TEGRA186_CLK_PLLDP>,
1444                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
1445                                  <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1446                         clock-names = "sor", "out", "parent", "dp", "safe",
1447                                       "pad";
1448                         resets = <&bpmp TEGRA186_RESET_SOR0>;
1449                         reset-names = "sor";
1450                         pinctrl-0 = <&state_dpaux_aux>;
1451                         pinctrl-1 = <&state_dpaux_i2c>;
1452                         pinctrl-2 = <&state_dpaux_off>;
1453                         pinctrl-names = "aux", "i2c", "off";
1454                         status = "disabled";
1455
1456                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1457                         nvidia,interface = <0>;
1458                 };
1459
1460                 sor1: sor@15580000 {
1461                         compatible = "nvidia,tegra186-sor";
1462                         reg = <0x15580000 0x10000>;
1463                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1464                         clocks = <&bpmp TEGRA186_CLK_SOR1>,
1465                                  <&bpmp TEGRA186_CLK_SOR1_OUT>,
1466                                  <&bpmp TEGRA186_CLK_PLLD3>,
1467                                  <&bpmp TEGRA186_CLK_PLLDP>,
1468                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
1469                                  <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1470                         clock-names = "sor", "out", "parent", "dp", "safe",
1471                                       "pad";
1472                         resets = <&bpmp TEGRA186_RESET_SOR1>;
1473                         reset-names = "sor";
1474                         pinctrl-0 = <&state_dpaux1_aux>;
1475                         pinctrl-1 = <&state_dpaux1_i2c>;
1476                         pinctrl-2 = <&state_dpaux1_off>;
1477                         pinctrl-names = "aux", "i2c", "off";
1478                         status = "disabled";
1479
1480                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1481                         nvidia,interface = <1>;
1482                 };
1483
1484                 dpaux: dpaux@155c0000 {
1485                         compatible = "nvidia,tegra186-dpaux";
1486                         reg = <0x155c0000 0x10000>;
1487                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488                         clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1489                                  <&bpmp TEGRA186_CLK_PLLDP>;
1490                         clock-names = "dpaux", "parent";
1491                         resets = <&bpmp TEGRA186_RESET_DPAUX>;
1492                         reset-names = "dpaux";
1493                         status = "disabled";
1494
1495                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1496
1497                         state_dpaux_aux: pinmux-aux {
1498                                 groups = "dpaux-io";
1499                                 function = "aux";
1500                         };
1501
1502                         state_dpaux_i2c: pinmux-i2c {
1503                                 groups = "dpaux-io";
1504                                 function = "i2c";
1505                         };
1506
1507                         state_dpaux_off: pinmux-off {
1508                                 groups = "dpaux-io";
1509                                 function = "off";
1510                         };
1511
1512                         i2c-bus {
1513                                 #address-cells = <1>;
1514                                 #size-cells = <0>;
1515                         };
1516                 };
1517
1518                 padctl@15880000 {
1519                         compatible = "nvidia,tegra186-dsi-padctl";
1520                         reg = <0x15880000 0x10000>;
1521                         resets = <&bpmp TEGRA186_RESET_DSI>;
1522                         reset-names = "dsi";
1523                         status = "disabled";
1524                 };
1525
1526                 dsic: dsi@15900000 {
1527                         compatible = "nvidia,tegra186-dsi";
1528                         reg = <0x15900000 0x10000>;
1529                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1530                         clocks = <&bpmp TEGRA186_CLK_DSIC>,
1531                                  <&bpmp TEGRA186_CLK_DSIC_LP>,
1532                                  <&bpmp TEGRA186_CLK_PLLD>;
1533                         clock-names = "dsi", "lp", "parent";
1534                         resets = <&bpmp TEGRA186_RESET_DSIC>;
1535                         reset-names = "dsi";
1536                         status = "disabled";
1537
1538                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1539                 };
1540
1541                 dsid: dsi@15940000 {
1542                         compatible = "nvidia,tegra186-dsi";
1543                         reg = <0x15940000 0x10000>;
1544                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1545                         clocks = <&bpmp TEGRA186_CLK_DSID>,
1546                                  <&bpmp TEGRA186_CLK_DSID_LP>,
1547                                  <&bpmp TEGRA186_CLK_PLLD>;
1548                         clock-names = "dsi", "lp", "parent";
1549                         resets = <&bpmp TEGRA186_RESET_DSID>;
1550                         reset-names = "dsi";
1551                         status = "disabled";
1552
1553                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1554                 };
1555         };
1556
1557         gpu@17000000 {
1558                 compatible = "nvidia,gp10b";
1559                 reg = <0x0 0x17000000 0x0 0x1000000>,
1560                       <0x0 0x18000000 0x0 0x1000000>;
1561                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1562                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1563                 interrupt-names = "stall", "nonstall";
1564
1565                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1566                          <&bpmp TEGRA186_CLK_GPU>;
1567                 clock-names = "gpu", "pwr";
1568                 resets = <&bpmp TEGRA186_RESET_GPU>;
1569                 reset-names = "gpu";
1570                 status = "disabled";
1571
1572                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1573                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1574                                 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1575                                 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1576                                 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1577                 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1578         };
1579
1580         sram@30000000 {
1581                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1582                 reg = <0x0 0x30000000 0x0 0x50000>;
1583                 #address-cells = <1>;
1584                 #size-cells = <1>;
1585                 ranges = <0x0 0x0 0x30000000 0x50000>;
1586
1587                 cpu_bpmp_tx: sram@4e000 {
1588                         reg = <0x4e000 0x1000>;
1589                         label = "cpu-bpmp-tx";
1590                         pool;
1591                 };
1592
1593                 cpu_bpmp_rx: sram@4f000 {
1594                         reg = <0x4f000 0x1000>;
1595                         label = "cpu-bpmp-rx";
1596                         pool;
1597                 };
1598         };
1599
1600         sata@3507000 {
1601                 compatible = "nvidia,tegra186-ahci";
1602                 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1603                       <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1604                       <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1605                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1606
1607                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1608                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1609                                 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1610                 interconnect-names = "dma-mem", "write";
1611                 iommus = <&smmu TEGRA186_SID_SATA>;
1612
1613                 clocks = <&bpmp TEGRA186_CLK_SATA>,
1614                          <&bpmp TEGRA186_CLK_SATA_OOB>;
1615                 clock-names = "sata", "sata-oob";
1616                 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1617                                   <&bpmp TEGRA186_CLK_SATA_OOB>;
1618                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1619                                          <&bpmp TEGRA186_CLK_PLLP>;
1620                 assigned-clock-rates = <102000000>,
1621                                        <204000000>;
1622                 resets = <&bpmp TEGRA186_RESET_SATA>,
1623                         <&bpmp TEGRA186_RESET_SATACOLD>;
1624                 reset-names = "sata", "sata-cold";
1625                 status = "disabled";
1626         };
1627
1628         bpmp: bpmp {
1629                 compatible = "nvidia,tegra186-bpmp";
1630                 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1631                                 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1632                                 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1633                                 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1634                 interconnect-names = "read", "write", "dma-mem", "dma-write";
1635                 iommus = <&smmu TEGRA186_SID_BPMP>;
1636                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1637                                     TEGRA_HSP_DB_MASTER_BPMP>;
1638                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1639                 #clock-cells = <1>;
1640                 #reset-cells = <1>;
1641                 #power-domain-cells = <1>;
1642
1643                 bpmp_i2c: i2c {
1644                         compatible = "nvidia,tegra186-bpmp-i2c";
1645                         nvidia,bpmp-bus-id = <5>;
1646                         #address-cells = <1>;
1647                         #size-cells = <0>;
1648                         status = "disabled";
1649                 };
1650
1651                 bpmp_thermal: thermal {
1652                         compatible = "nvidia,tegra186-bpmp-thermal";
1653                         #thermal-sensor-cells = <1>;
1654                 };
1655         };
1656
1657         cpus {
1658                 #address-cells = <1>;
1659                 #size-cells = <0>;
1660
1661                 denver_0: cpu@0 {
1662                         compatible = "nvidia,tegra186-denver";
1663                         device_type = "cpu";
1664                         i-cache-size = <0x20000>;
1665                         i-cache-line-size = <64>;
1666                         i-cache-sets = <512>;
1667                         d-cache-size = <0x10000>;
1668                         d-cache-line-size = <64>;
1669                         d-cache-sets = <256>;
1670                         next-level-cache = <&L2_DENVER>;
1671                         reg = <0x000>;
1672                 };
1673
1674                 denver_1: cpu@1 {
1675                         compatible = "nvidia,tegra186-denver";
1676                         device_type = "cpu";
1677                         i-cache-size = <0x20000>;
1678                         i-cache-line-size = <64>;
1679                         i-cache-sets = <512>;
1680                         d-cache-size = <0x10000>;
1681                         d-cache-line-size = <64>;
1682                         d-cache-sets = <256>;
1683                         next-level-cache = <&L2_DENVER>;
1684                         reg = <0x001>;
1685                 };
1686
1687                 ca57_0: cpu@2 {
1688                         compatible = "arm,cortex-a57";
1689                         device_type = "cpu";
1690                         i-cache-size = <0xC000>;
1691                         i-cache-line-size = <64>;
1692                         i-cache-sets = <256>;
1693                         d-cache-size = <0x8000>;
1694                         d-cache-line-size = <64>;
1695                         d-cache-sets = <256>;
1696                         next-level-cache = <&L2_A57>;
1697                         reg = <0x100>;
1698                 };
1699
1700                 ca57_1: cpu@3 {
1701                         compatible = "arm,cortex-a57";
1702                         device_type = "cpu";
1703                         i-cache-size = <0xC000>;
1704                         i-cache-line-size = <64>;
1705                         i-cache-sets = <256>;
1706                         d-cache-size = <0x8000>;
1707                         d-cache-line-size = <64>;
1708                         d-cache-sets = <256>;
1709                         next-level-cache = <&L2_A57>;
1710                         reg = <0x101>;
1711                 };
1712
1713                 ca57_2: cpu@4 {
1714                         compatible = "arm,cortex-a57";
1715                         device_type = "cpu";
1716                         i-cache-size = <0xC000>;
1717                         i-cache-line-size = <64>;
1718                         i-cache-sets = <256>;
1719                         d-cache-size = <0x8000>;
1720                         d-cache-line-size = <64>;
1721                         d-cache-sets = <256>;
1722                         next-level-cache = <&L2_A57>;
1723                         reg = <0x102>;
1724                 };
1725
1726                 ca57_3: cpu@5 {
1727                         compatible = "arm,cortex-a57";
1728                         device_type = "cpu";
1729                         i-cache-size = <0xC000>;
1730                         i-cache-line-size = <64>;
1731                         i-cache-sets = <256>;
1732                         d-cache-size = <0x8000>;
1733                         d-cache-line-size = <64>;
1734                         d-cache-sets = <256>;
1735                         next-level-cache = <&L2_A57>;
1736                         reg = <0x103>;
1737                 };
1738
1739                 L2_DENVER: l2-cache0 {
1740                         compatible = "cache";
1741                         cache-unified;
1742                         cache-level = <2>;
1743                         cache-size = <0x200000>;
1744                         cache-line-size = <64>;
1745                         cache-sets = <2048>;
1746                 };
1747
1748                 L2_A57: l2-cache1 {
1749                         compatible = "cache";
1750                         cache-unified;
1751                         cache-level = <2>;
1752                         cache-size = <0x200000>;
1753                         cache-line-size = <64>;
1754                         cache-sets = <2048>;
1755                 };
1756         };
1757
1758         pmu_denver {
1759                 compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
1760                 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1761                              <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1762                 interrupt-affinity = <&denver_0 &denver_1>;
1763         };
1764
1765         pmu_a57 {
1766                 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
1767                 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1768                              <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1769                              <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1770                              <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1771                 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
1772         };
1773
1774         sound {
1775                 status = "disabled";
1776
1777                 clocks = <&bpmp TEGRA186_CLK_PLLA>,
1778                          <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1779                 clock-names = "pll_a", "plla_out0";
1780                 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
1781                                   <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
1782                                   <&bpmp TEGRA186_CLK_AUD_MCLK>;
1783                 assigned-clock-parents = <0>,
1784                                          <&bpmp TEGRA186_CLK_PLLA>,
1785                                          <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1786                 /*
1787                  * PLLA supports dynamic ramp. Below initial rate is chosen
1788                  * for this to work and oscillate between base rates required
1789                  * for 8x and 11.025x sample rate streams.
1790                  */
1791                 assigned-clock-rates = <258000000>;
1792
1793                 iommus = <&smmu TEGRA186_SID_APE>;
1794         };
1795
1796         thermal-zones {
1797                 a57 {
1798                         polling-delay = <0>;
1799                         polling-delay-passive = <1000>;
1800
1801                         thermal-sensors =
1802                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1803
1804                         trips {
1805                                 critical {
1806                                         temperature = <101000>;
1807                                         hysteresis = <0>;
1808                                         type = "critical";
1809                                 };
1810                         };
1811
1812                         cooling-maps {
1813                         };
1814                 };
1815
1816                 denver {
1817                         polling-delay = <0>;
1818                         polling-delay-passive = <1000>;
1819
1820                         thermal-sensors =
1821                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1822
1823                         trips {
1824                                 critical {
1825                                         temperature = <101000>;
1826                                         hysteresis = <0>;
1827                                         type = "critical";
1828                                 };
1829                         };
1830
1831                         cooling-maps {
1832                         };
1833                 };
1834
1835                 gpu {
1836                         polling-delay = <0>;
1837                         polling-delay-passive = <1000>;
1838
1839                         thermal-sensors =
1840                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1841
1842                         trips {
1843                                 critical {
1844                                         temperature = <101000>;
1845                                         hysteresis = <0>;
1846                                         type = "critical";
1847                                 };
1848                         };
1849
1850                         cooling-maps {
1851                         };
1852                 };
1853
1854                 pll {
1855                         polling-delay = <0>;
1856                         polling-delay-passive = <1000>;
1857
1858                         thermal-sensors =
1859                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1860
1861                         trips {
1862                                 critical {
1863                                         temperature = <101000>;
1864                                         hysteresis = <0>;
1865                                         type = "critical";
1866                                 };
1867                         };
1868
1869                         cooling-maps {
1870                         };
1871                 };
1872
1873                 always_on {
1874                         polling-delay = <0>;
1875                         polling-delay-passive = <1000>;
1876
1877                         thermal-sensors =
1878                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1879
1880                         trips {
1881                                 critical {
1882                                         temperature = <101000>;
1883                                         hysteresis = <0>;
1884                                         type = "critical";
1885                                 };
1886                         };
1887
1888                         cooling-maps {
1889                         };
1890                 };
1891         };
1892
1893         timer {
1894                 compatible = "arm,armv8-timer";
1895                 interrupts = <GIC_PPI 13
1896                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1897                              <GIC_PPI 14
1898                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1899                              <GIC_PPI 11
1900                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1901                              <GIC_PPI 10
1902                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1903                 interrupt-parent = <&gic>;
1904                 always-on;
1905         };
1906 };