arch/arm64/boot/dts/microchip/sparx5.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/microchip,sparx5.h>
   9
  10 / {
  11         compatible = "microchip,sparx5";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <1>;
  15
  16         aliases {
  17                 spi0 = &spi0;
  18                 serial0 = &uart0;
  19                 serial1 = &uart1;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         cpus {
  27                 #address-cells = <2>;
  28                 #size-cells = <0>;
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                         };
  38                 };
  39                 cpu0: cpu@0 {
  40                         compatible = "arm,cortex-a53";
  41                         device_type = "cpu";
  42                         reg = <0x0 0x0>;
  43                         enable-method = "psci";
  44                         next-level-cache = <&L2_0>;
  45                 };
  46                 cpu1: cpu@1 {
  47                         compatible = "arm,cortex-a53";
  48                         device_type = "cpu";
  49                         reg = <0x0 0x1>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&L2_0>;
  52                 };
  53                 L2_0: l2-cache0 {
  54                         compatible = "cache";
  55                 };
  56         };
  57
  58         arm-pmu {
  59                 compatible = "arm,cortex-a53-pmu";
  60                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  61                 interrupt-affinity = <&cpu0>, <&cpu1>;
  62         };
  63
  64         psci {
  65                 compatible = "arm,psci-0.2";
  66                 method = "smc";
  67         };
  68
  69         timer {
  70                 compatible = "arm,armv8-timer";
  71                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  72                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  73                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  74                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  75         };
  76
  77         lcpll_clk: lcpll-clk {
  78                 compatible = "fixed-clock";
  79                 #clock-cells = <0>;
  80                 clock-frequency = <2500000000>;
  81         };
  82
  83         clks: clock-controller@61110000c {
  84                 compatible = "microchip,sparx5-dpll";
  85                 #clock-cells = <1>;
  86                 clocks = <&lcpll_clk>;
  87                 reg = <0x6 0x1110000c 0x24>;
  88         };
  89
  90         ahb_clk: ahb-clk {
  91                 compatible = "fixed-clock";
  92                 #clock-cells = <0>;
  93                 clock-frequency = <250000000>;
  94         };
  95
  96         sys_clk: sys-clk {
  97                 compatible = "fixed-clock";
  98                 #clock-cells = <0>;
  99                 clock-frequency = <625000000>;
 100         };
 101
 102         axi: axi@600000000 {
 103                 compatible = "simple-bus";
 104                 #address-cells = <2>;
 105                 #size-cells = <1>;
 106                 ranges;
 107
 108                 gic: interrupt-controller@600300000 {
 109                         compatible = "arm,gic-v3";
 110                         #interrupt-cells = <3>;
 111                         #address-cells = <2>;
 112                         #size-cells = <2>;
 113                         interrupt-controller;
 114                         reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
 115                               <0x6 0x00340000 0xc0000>, /* GICR */
 116                               <0x6 0x00200000 0x2000>,  /* GICC */
 117                               <0x6 0x00210000 0x2000>,  /* GICV */
 118                               <0x6 0x00220000 0x2000>;  /* GICH */
 119                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 120                 };
 121
 122                 cpu_ctrl: syscon@600000000 {
 123                         compatible = "microchip,sparx5-cpu-syscon", "syscon",
 124                                      "simple-mfd";
 125                         reg = <0x6 0x00000000 0xd0>;
 126                         mux: mux-controller {
 127                                 compatible = "mmio-mux";
 128                                 #mux-control-cells = <0>;
 129                                 /*
 130                                  * SI_OWNER and SI2_OWNER in GENERAL_CTRL
 131                                  * SPI:  value 9 - (SIMC,SIBM) = 0b1001
 132                                  * SPI2: value 6 - (SIBM,SIMC) = 0b0110
 133                                  */
 134                                 mux-reg-masks = <0x88 0xf0>;
 135                         };
 136                 };
 137
 138                 reset: reset-controller@611010008 {
 139                         compatible = "microchip,sparx5-switch-reset";
 140                         reg = <0x6 0x11010008 0x4>;
 141                         reg-names = "gcb";
 142                         #reset-cells = <1>;
 143                         cpu-syscon = <&cpu_ctrl>;
 144                 };
 145
 146                 uart0: serial@600100000 {
 147                         pinctrl-0 = <&uart_pins>;
 148                         pinctrl-names = "default";
 149                         compatible = "ns16550a";
 150                         reg = <0x6 0x00100000 0x20>;
 151                         clocks = <&ahb_clk>;
 152                         reg-io-width = <4>;
 153                         reg-shift = <2>;
 154                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 155
 156                         status = "disabled";
 157                 };
 158
 159                 uart1: serial@600102000 {
 160                         pinctrl-0 = <&uart2_pins>;
 161                         pinctrl-names = "default";
 162                         compatible = "ns16550a";
 163                         reg = <0x6 0x00102000 0x20>;
 164                         clocks = <&ahb_clk>;
 165                         reg-io-width = <4>;
 166                         reg-shift = <2>;
 167                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 168
 169                         status = "disabled";
 170                 };
 171
 172                 spi0: spi@600104000 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         compatible = "microchip,sparx5-spi";
 176                         reg = <0x6 0x00104000 0x40>;
 177                         num-cs = <16>;
 178                         reg-io-width = <4>;
 179                         reg-shift = <2>;
 180                         clocks = <&ahb_clk>;
 181                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 182                         status = "disabled";
 183                 };
 184
 185                 timer1: timer@600105000 {
 186                         compatible = "snps,dw-apb-timer";
 187                         reg = <0x6 0x00105000 0x1000>;
 188                         clocks = <&ahb_clk>;
 189                         clock-names = "timer";
 190                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 191                 };
 192
 193                 sdhci0: mmc@600800000 {
 194                         compatible = "microchip,dw-sparx5-sdhci";
 195                         status = "disabled";
 196                         reg = <0x6 0x00800000 0x1000>;
 197                         pinctrl-0 = <&emmc_pins>;
 198                         pinctrl-names = "default";
 199                         clocks = <&clks CLK_ID_AUX1>;
 200                         clock-names = "core";
 201                         assigned-clocks = <&clks CLK_ID_AUX1>;
 202                         assigned-clock-rates = <800000000>;
 203                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 204                         bus-width = <8>;
 205                 };
 206
 207                 gpio: pinctrl@6110101e0 {
 208                         compatible = "microchip,sparx5-pinctrl";
 209                         reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
 210                         gpio-controller;
 211                         #gpio-cells = <2>;
 212                         gpio-ranges = <&gpio 0 0 64>;
 213                         interrupt-controller;
 214                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 215                         #interrupt-cells = <2>;
 216
 217                         cs1_pins: cs1-pins {
 218                                 pins = "GPIO_16";
 219                                 function = "si";
 220                         };
 221
 222                         cs2_pins: cs2-pins {
 223                                 pins = "GPIO_17";
 224                                 function = "si";
 225                         };
 226
 227                         cs3_pins: cs3-pins {
 228                                 pins = "GPIO_18";
 229                                 function = "si";
 230                         };
 231
 232                         si2_pins: si2-pins {
 233                                 pins = "GPIO_39", "GPIO_40", "GPIO_41";
 234                                 function = "si2";
 235                         };
 236
 237                         sgpio0_pins: sgpio-pins {
 238                                 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
 239                                 function = "sg0";
 240                         };
 241
 242                         sgpio1_pins: sgpio1-pins {
 243                                 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
 244                                 function = "sg1";
 245                         };
 246
 247                         sgpio2_pins: sgpio2-pins {
 248                                 pins = "GPIO_30", "GPIO_31", "GPIO_32",
 249                                        "GPIO_33";
 250                                 function = "sg2";
 251                         };
 252
 253                         uart_pins: uart-pins {
 254                                 pins = "GPIO_10", "GPIO_11";
 255                                 function = "uart";
 256                         };
 257
 258                         uart2_pins: uart2-pins {
 259                                 pins = "GPIO_26", "GPIO_27";
 260                                 function = "uart2";
 261                         };
 262
 263                         i2c_pins: i2c-pins {
 264                                 pins = "GPIO_14", "GPIO_15";
 265                                 function = "twi";
 266                         };
 267
 268                         i2c2_pins: i2c2-pins {
 269                                 pins = "GPIO_28", "GPIO_29";
 270                                 function = "twi2";
 271                         };
 272
 273                         emmc_pins: emmc-pins {
 274                                 pins = "GPIO_34", "GPIO_35", "GPIO_36",
 275                                         "GPIO_37", "GPIO_38", "GPIO_39",
 276                                         "GPIO_40", "GPIO_41", "GPIO_42",
 277                                         "GPIO_43", "GPIO_44", "GPIO_45",
 278                                         "GPIO_46", "GPIO_47";
 279                                 function = "emmc";
 280                         };
 281
 282                         miim1_pins: miim1-pins {
 283                                 pins = "GPIO_56", "GPIO_57";
 284                                 function = "miim";
 285                         };
 286
 287                         miim2_pins: miim2-pins {
 288                                 pins = "GPIO_58", "GPIO_59";
 289                                 function = "miim";
 290                         };
 291
 292                         miim3_pins: miim3-pins {
 293                                 pins = "GPIO_52", "GPIO_53";
 294                                 function = "miim";
 295                         };
 296                 };
 297
 298                 sgpio0: gpio@61101036c {
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         compatible = "microchip,sparx5-sgpio";
 302                         status = "disabled";
 303                         clocks = <&sys_clk>;
 304                         pinctrl-0 = <&sgpio0_pins>;
 305                         pinctrl-names = "default";
 306                         resets = <&reset 0>;
 307                         reset-names = "switch";
 308                         reg = <0x6 0x1101036c 0x100>;
 309                         sgpio_in0: gpio@0 {
 310                                 compatible = "microchip,sparx5-sgpio-bank";
 311                                 reg = <0>;
 312                                 gpio-controller;
 313                                 #gpio-cells = <3>;
 314                                 ngpios = <96>;
 315                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 316                                 interrupt-controller;
 317                                 #interrupt-cells = <3>;
 318                         };
 319                         sgpio_out0: gpio@1 {
 320                                 compatible = "microchip,sparx5-sgpio-bank";
 321                                 reg = <1>;
 322                                 gpio-controller;
 323                                 #gpio-cells = <3>;
 324                                 ngpios = <96>;
 325                         };
 326                 };
 327
 328                 sgpio1: gpio@611010484 {
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         compatible = "microchip,sparx5-sgpio";
 332                         status = "disabled";
 333                         clocks = <&sys_clk>;
 334                         pinctrl-0 = <&sgpio1_pins>;
 335                         pinctrl-names = "default";
 336                         resets = <&reset 0>;
 337                         reset-names = "switch";
 338                         reg = <0x6 0x11010484 0x100>;
 339                         sgpio_in1: gpio@0 {
 340                                 compatible = "microchip,sparx5-sgpio-bank";
 341                                 reg = <0>;
 342                                 gpio-controller;
 343                                 #gpio-cells = <3>;
 344                                 ngpios = <96>;
 345                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 346                                 interrupt-controller;
 347                                 #interrupt-cells = <3>;
 348                         };
 349                         sgpio_out1: gpio@1 {
 350                                 compatible = "microchip,sparx5-sgpio-bank";
 351                                 reg = <1>;
 352                                 gpio-controller;
 353                                 #gpio-cells = <3>;
 354                                 ngpios = <96>;
 355                         };
 356                 };
 357
 358                 sgpio2: gpio@61101059c {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         compatible = "microchip,sparx5-sgpio";
 362                         status = "disabled";
 363                         clocks = <&sys_clk>;
 364                         pinctrl-0 = <&sgpio2_pins>;
 365                         pinctrl-names = "default";
 366                         resets = <&reset 0>;
 367                         reset-names = "switch";
 368                         reg = <0x6 0x1101059c 0x100>;
 369                         sgpio_in2: gpio@0 {
 370                                 reg = <0>;
 371                                 compatible = "microchip,sparx5-sgpio-bank";
 372                                 gpio-controller;
 373                                 #gpio-cells = <3>;
 374                                 ngpios = <96>;
 375                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <3>;
 378                         };
 379                         sgpio_out2: gpio@1 {
 380                                 compatible = "microchip,sparx5-sgpio-bank";
 381                                 reg = <1>;
 382                                 gpio-controller;
 383                                 #gpio-cells = <3>;
 384                                 ngpios = <96>;
 385                         };
 386                 };
 387
 388                 i2c0: i2c@600101000 {
 389                         compatible = "snps,designware-i2c";
 390                         status = "disabled";
 391                         pinctrl-0 = <&i2c_pins>;
 392                         pinctrl-names = "default";
 393                         reg = <0x6 0x00101000 0x100>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 397                         i2c-sda-hold-time-ns = <300>;
 398                         clock-frequency = <100000>;
 399                         clocks = <&ahb_clk>;
 400                 };
 401
 402                 i2c1: i2c@600103000 {
 403                         compatible = "snps,designware-i2c";
 404                         status = "disabled";
 405                         pinctrl-0 = <&i2c2_pins>;
 406                         pinctrl-names = "default";
 407                         reg = <0x6 0x00103000 0x100>;
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 411                         i2c-sda-hold-time-ns = <300>;
 412                         clock-frequency = <100000>;
 413                         clocks = <&ahb_clk>;
 414                 };
 415
 416                 tmon0: tmon@610508110 {
 417                         compatible = "microchip,sparx5-temp";
 418                         reg = <0x6 0x10508110 0xc>;
 419                         #thermal-sensor-cells = <0>;
 420                         clocks = <&ahb_clk>;
 421                 };
 422
 423                 mdio0: mdio@6110102b0 {
 424                         compatible = "mscc,ocelot-miim";
 425                         status = "disabled";
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         reg = <0x6 0x110102b0 0x24>;
 429                 };
 430
 431                 mdio1: mdio@6110102d4 {
 432                         compatible = "mscc,ocelot-miim";
 433                         status = "disabled";
 434                         pinctrl-0 = <&miim1_pins>;
 435                         pinctrl-names = "default";
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         reg = <0x6 0x110102d4 0x24>;
 439                 };
 440
 441                 mdio2: mdio@6110102f8 {
 442                         compatible = "mscc,ocelot-miim";
 443                         status = "disabled";
 444                         pinctrl-0 = <&miim2_pins>;
 445                         pinctrl-names = "default";
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         reg = <0x6 0x110102d4 0x24>;
 449                 };
 450
 451                 mdio3: mdio@61101031c {
 452                         compatible = "mscc,ocelot-miim";
 453                         status = "disabled";
 454                         pinctrl-0 = <&miim3_pins>;
 455                         pinctrl-names = "default";
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         reg = <0x6 0x1101031c 0x24>;
 459                 };
 460
 461                 serdes: serdes@10808000 {
 462                         compatible = "microchip,sparx5-serdes";
 463                         #phy-cells = <1>;
 464                         clocks = <&sys_clk>;
 465                         reg = <0x6 0x10808000 0x5d0000>;
 466                 };
 467
 468                 switch: switch@0x600000000 {
 469                         compatible = "microchip,sparx5-switch";
 470                         reg =   <0x6 0 0x401000>,
 471                                 <0x6 0x10004000 0x7fc000>,
 472                                 <0x6 0x11010000 0xaf0000>;
 473                         reg-names = "cpu", "dev", "gcb";
 474                         interrupt-names = "xtr", "fdma";
 475                         interrupts =    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 476                                         <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 477                         resets = <&reset 0>;
 478                         reset-names = "switch";
 479                 };
 480         };
 481 };