arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include <dt-bindings/gce/mt8173-gce.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23 #include "mt8173-pinfunc.h"
  24
  25 / {
  26         compatible = "mediatek,mt8173";
  27         interrupt-parent = <&sysirq>;
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         aliases {
  32                 ovl0 = &ovl0;
  33                 ovl1 = &ovl1;
  34                 rdma0 = &rdma0;
  35                 rdma1 = &rdma1;
  36                 rdma2 = &rdma2;
  37                 wdma0 = &wdma0;
  38                 wdma1 = &wdma1;
  39                 color0 = &color0;
  40                 color1 = &color1;
  41                 split0 = &split0;
  42                 split1 = &split1;
  43                 dpi0 = &dpi0;
  44                 dsi0 = &dsi0;
  45                 dsi1 = &dsi1;
  46                 mdp-rdma0 = &mdp_rdma0;
  47                 mdp-rdma1 = &mdp_rdma1;
  48                 mdp-rsz0 = &mdp_rsz0;
  49                 mdp-rsz1 = &mdp_rsz1;
  50                 mdp-rsz2 = &mdp_rsz2;
  51                 mdp-wdma0 = &mdp_wdma0;
  52                 mdp-wrot0 = &mdp_wrot0;
  53                 mdp-wrot1 = &mdp_wrot1;
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57                 serial3 = &uart3;
  58         };
  59
  60         cluster0_opp: opp_table0 {
  61                 compatible = "operating-points-v2";
  62                 opp-shared;
  63                 opp-507000000 {
  64                         opp-hz = /bits/ 64 <507000000>;
  65                         opp-microvolt = <859000>;
  66                 };
  67                 opp-702000000 {
  68                         opp-hz = /bits/ 64 <702000000>;
  69                         opp-microvolt = <908000>;
  70                 };
  71                 opp-1001000000 {
  72                         opp-hz = /bits/ 64 <1001000000>;
  73                         opp-microvolt = <983000>;
  74                 };
  75                 opp-1105000000 {
  76                         opp-hz = /bits/ 64 <1105000000>;
  77                         opp-microvolt = <1009000>;
  78                 };
  79                 opp-1209000000 {
  80                         opp-hz = /bits/ 64 <1209000000>;
  81                         opp-microvolt = <1034000>;
  82                 };
  83                 opp-1300000000 {
  84                         opp-hz = /bits/ 64 <1300000000>;
  85                         opp-microvolt = <1057000>;
  86                 };
  87                 opp-1508000000 {
  88                         opp-hz = /bits/ 64 <1508000000>;
  89                         opp-microvolt = <1109000>;
  90                 };
  91                 opp-1703000000 {
  92                         opp-hz = /bits/ 64 <1703000000>;
  93                         opp-microvolt = <1125000>;
  94                 };
  95         };
  96
  97         cluster1_opp: opp_table1 {
  98                 compatible = "operating-points-v2";
  99                 opp-shared;
 100                 opp-507000000 {
 101                         opp-hz = /bits/ 64 <507000000>;
 102                         opp-microvolt = <828000>;
 103                 };
 104                 opp-702000000 {
 105                         opp-hz = /bits/ 64 <702000000>;
 106                         opp-microvolt = <867000>;
 107                 };
 108                 opp-1001000000 {
 109                         opp-hz = /bits/ 64 <1001000000>;
 110                         opp-microvolt = <927000>;
 111                 };
 112                 opp-1209000000 {
 113                         opp-hz = /bits/ 64 <1209000000>;
 114                         opp-microvolt = <968000>;
 115                 };
 116                 opp-1404000000 {
 117                         opp-hz = /bits/ 64 <1404000000>;
 118                         opp-microvolt = <1007000>;
 119                 };
 120                 opp-1612000000 {
 121                         opp-hz = /bits/ 64 <1612000000>;
 122                         opp-microvolt = <1049000>;
 123                 };
 124                 opp-1807000000 {
 125                         opp-hz = /bits/ 64 <1807000000>;
 126                         opp-microvolt = <1089000>;
 127                 };
 128                 opp-2106000000 {
 129                         opp-hz = /bits/ 64 <2106000000>;
 130                         opp-microvolt = <1125000>;
 131                 };
 132         };
 133
 134         cpus {
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137
 138                 cpu-map {
 139                         cluster0 {
 140                                 core0 {
 141                                         cpu = <&cpu0>;
 142                                 };
 143                                 core1 {
 144                                         cpu = <&cpu1>;
 145                                 };
 146                         };
 147
 148                         cluster1 {
 149                                 core0 {
 150                                         cpu = <&cpu2>;
 151                                 };
 152                                 core1 {
 153                                         cpu = <&cpu3>;
 154                                 };
 155                         };
 156                 };
 157
 158                 cpu0: cpu@0 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a53";
 161                         reg = <0x000>;
 162                         enable-method = "psci";
 163                         cpu-idle-states = <&CPU_SLEEP_0>;
 164                         #cooling-cells = <2>;
 165                         dynamic-power-coefficient = <263>;
 166                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 167                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 168                         clock-names = "cpu", "intermediate";
 169                         operating-points-v2 = <&cluster0_opp>;
 170                         capacity-dmips-mhz = <740>;
 171                 };
 172
 173                 cpu1: cpu@1 {
 174                         device_type = "cpu";
 175                         compatible = "arm,cortex-a53";
 176                         reg = <0x001>;
 177                         enable-method = "psci";
 178                         cpu-idle-states = <&CPU_SLEEP_0>;
 179                         #cooling-cells = <2>;
 180                         dynamic-power-coefficient = <263>;
 181                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 182                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 183                         clock-names = "cpu", "intermediate";
 184                         operating-points-v2 = <&cluster0_opp>;
 185                         capacity-dmips-mhz = <740>;
 186                 };
 187
 188                 cpu2: cpu@100 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a72";
 191                         reg = <0x100>;
 192                         enable-method = "psci";
 193                         cpu-idle-states = <&CPU_SLEEP_0>;
 194                         #cooling-cells = <2>;
 195                         dynamic-power-coefficient = <530>;
 196                         clocks = <&infracfg CLK_INFRA_CA72SEL>,
 197                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 198                         clock-names = "cpu", "intermediate";
 199                         operating-points-v2 = <&cluster1_opp>;
 200                         capacity-dmips-mhz = <1024>;
 201                 };
 202
 203                 cpu3: cpu@101 {
 204                         device_type = "cpu";
 205                         compatible = "arm,cortex-a72";
 206                         reg = <0x101>;
 207                         enable-method = "psci";
 208                         cpu-idle-states = <&CPU_SLEEP_0>;
 209                         #cooling-cells = <2>;
 210                         dynamic-power-coefficient = <530>;
 211                         clocks = <&infracfg CLK_INFRA_CA72SEL>,
 212                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 213                         clock-names = "cpu", "intermediate";
 214                         operating-points-v2 = <&cluster1_opp>;
 215                         capacity-dmips-mhz = <1024>;
 216                 };
 217
 218                 idle-states {
 219                         entry-method = "psci";
 220
 221                         CPU_SLEEP_0: cpu-sleep-0 {
 222                                 compatible = "arm,idle-state";
 223                                 local-timer-stop;
 224                                 entry-latency-us = <639>;
 225                                 exit-latency-us = <680>;
 226                                 min-residency-us = <1088>;
 227                                 arm,psci-suspend-param = <0x0010000>;
 228                         };
 229                 };
 230         };
 231
 232         pmu_a53 {
 233                 compatible = "arm,cortex-a53-pmu";
 234                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 235                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu0>, <&cpu1>;
 237         };
 238
 239         pmu_a72 {
 240                 compatible = "arm,cortex-a72-pmu";
 241                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
 242                              <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
 243                 interrupt-affinity = <&cpu2>, <&cpu3>;
 244         };
 245
 246         psci {
 247                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 248                 method = "smc";
 249                 cpu_suspend   = <0x84000001>;
 250                 cpu_off       = <0x84000002>;
 251                 cpu_on        = <0x84000003>;
 252         };
 253
 254         clk26m: oscillator0 {
 255                 compatible = "fixed-clock";
 256                 #clock-cells = <0>;
 257                 clock-frequency = <26000000>;
 258                 clock-output-names = "clk26m";
 259         };
 260
 261         clk32k: oscillator1 {
 262                 compatible = "fixed-clock";
 263                 #clock-cells = <0>;
 264                 clock-frequency = <32000>;
 265                 clock-output-names = "clk32k";
 266         };
 267
 268         cpum_ck: oscillator2 {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <0>;
 272                 clock-output-names = "cpum_ck";
 273         };
 274
 275         thermal-zones {
 276                 cpu_thermal: cpu_thermal {
 277                         polling-delay-passive = <1000>; /* milliseconds */
 278                         polling-delay = <1000>; /* milliseconds */
 279
 280                         thermal-sensors = <&thermal>;
 281                         sustainable-power = <1500>; /* milliwatts */
 282
 283                         trips {
 284                                 threshold: trip-point0 {
 285                                         temperature = <68000>;
 286                                         hysteresis = <2000>;
 287                                         type = "passive";
 288                                 };
 289
 290                                 target: trip-point1 {
 291                                         temperature = <85000>;
 292                                         hysteresis = <2000>;
 293                                         type = "passive";
 294                                 };
 295
 296                                 cpu_crit: cpu_crit0 {
 297                                         temperature = <115000>;
 298                                         hysteresis = <2000>;
 299                                         type = "critical";
 300                                 };
 301                         };
 302
 303                         cooling-maps {
 304                                 map0 {
 305                                         trip = <&target>;
 306                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT
 307                                                           THERMAL_NO_LIMIT>,
 308                                                          <&cpu1 THERMAL_NO_LIMIT
 309                                                           THERMAL_NO_LIMIT>;
 310                                         contribution = <3072>;
 311                                 };
 312                                 map1 {
 313                                         trip = <&target>;
 314                                         cooling-device = <&cpu2 THERMAL_NO_LIMIT
 315                                                           THERMAL_NO_LIMIT>,
 316                                                          <&cpu3 THERMAL_NO_LIMIT
 317                                                           THERMAL_NO_LIMIT>;
 318                                         contribution = <1024>;
 319                                 };
 320                         };
 321                 };
 322         };
 323
 324         reserved-memory {
 325                 #address-cells = <2>;
 326                 #size-cells = <2>;
 327                 ranges;
 328                 vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
 329                         compatible = "shared-dma-pool";
 330                         reg = <0 0xb7000000 0 0x500000>;
 331                         alignment = <0x1000>;
 332                         no-map;
 333                 };
 334         };
 335
 336         timer {
 337                 compatible = "arm,armv8-timer";
 338                 interrupt-parent = <&gic>;
 339                 interrupts = <GIC_PPI 13
 340                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 341                              <GIC_PPI 14
 342                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 343                              <GIC_PPI 11
 344                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 345                              <GIC_PPI 10
 346                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 347                 arm,no-tick-in-suspend;
 348         };
 349
 350         soc {
 351                 #address-cells = <2>;
 352                 #size-cells = <2>;
 353                 compatible = "simple-bus";
 354                 ranges;
 355
 356                 topckgen: clock-controller@10000000 {
 357                         compatible = "mediatek,mt8173-topckgen";
 358                         reg = <0 0x10000000 0 0x1000>;
 359                         #clock-cells = <1>;
 360                 };
 361
 362                 infracfg: power-controller@10001000 {
 363                         compatible = "mediatek,mt8173-infracfg", "syscon";
 364                         reg = <0 0x10001000 0 0x1000>;
 365                         #clock-cells = <1>;
 366                         #reset-cells = <1>;
 367                 };
 368
 369                 pericfg: power-controller@10003000 {
 370                         compatible = "mediatek,mt8173-pericfg", "syscon";
 371                         reg = <0 0x10003000 0 0x1000>;
 372                         #clock-cells = <1>;
 373                         #reset-cells = <1>;
 374                 };
 375
 376                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 377                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 378                         reg = <0 0x10005000 0 0x1000>;
 379                 };
 380
 381                 pio: pinctrl@1000b000 {
 382                         compatible = "mediatek,mt8173-pinctrl";
 383                         reg = <0 0x1000b000 0 0x1000>;
 384                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 385                         pins-are-numbered;
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <2>;
 390                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 391                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 392                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 393
 394                         hdmi_pin: xxx {
 395
 396                                 /*hdmi htplg pin*/
 397                                 pins1 {
 398                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 399                                         input-enable;
 400                                         bias-pull-down;
 401                                 };
 402                         };
 403
 404                         i2c0_pins_a: i2c0 {
 405                                 pins1 {
 406                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 407                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 408                                         bias-disable;
 409                                 };
 410                         };
 411
 412                         i2c1_pins_a: i2c1 {
 413                                 pins1 {
 414                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 415                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 416                                         bias-disable;
 417                                 };
 418                         };
 419
 420                         i2c2_pins_a: i2c2 {
 421                                 pins1 {
 422                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 423                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 424                                         bias-disable;
 425                                 };
 426                         };
 427
 428                         i2c3_pins_a: i2c3 {
 429                                 pins1 {
 430                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 431                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 432                                         bias-disable;
 433                                 };
 434                         };
 435
 436                         i2c4_pins_a: i2c4 {
 437                                 pins1 {
 438                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 439                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 440                                         bias-disable;
 441                                 };
 442                         };
 443
 444                         i2c6_pins_a: i2c6 {
 445                                 pins1 {
 446                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 447                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 448                                         bias-disable;
 449                                 };
 450                         };
 451                 };
 452
 453                 scpsys: syscon@10006000 {
 454                         compatible = "syscon", "simple-mfd";
 455                         reg = <0 0x10006000 0 0x1000>;
 456                         #power-domain-cells = <1>;
 457
 458                         /* System Power Manager */
 459                         spm: power-controller {
 460                                 compatible = "mediatek,mt8173-power-controller";
 461                                 #address-cells = <1>;
 462                                 #size-cells = <0>;
 463                                 #power-domain-cells = <1>;
 464
 465                                 /* power domains of the SoC */
 466                                 power-domain@MT8173_POWER_DOMAIN_VDEC {
 467                                         reg = <MT8173_POWER_DOMAIN_VDEC>;
 468                                         clocks = <&topckgen CLK_TOP_MM_SEL>;
 469                                         clock-names = "mm";
 470                                         #power-domain-cells = <0>;
 471                                 };
 472                                 power-domain@MT8173_POWER_DOMAIN_VENC {
 473                                         reg = <MT8173_POWER_DOMAIN_VENC>;
 474                                         clocks = <&topckgen CLK_TOP_MM_SEL>,
 475                                                  <&topckgen CLK_TOP_VENC_SEL>;
 476                                         clock-names = "mm", "venc";
 477                                         #power-domain-cells = <0>;
 478                                 };
 479                                 power-domain@MT8173_POWER_DOMAIN_ISP {
 480                                         reg = <MT8173_POWER_DOMAIN_ISP>;
 481                                         clocks = <&topckgen CLK_TOP_MM_SEL>;
 482                                         clock-names = "mm";
 483                                         #power-domain-cells = <0>;
 484                                 };
 485                                 power-domain@MT8173_POWER_DOMAIN_MM {
 486                                         reg = <MT8173_POWER_DOMAIN_MM>;
 487                                         clocks = <&topckgen CLK_TOP_MM_SEL>;
 488                                         clock-names = "mm";
 489                                         #power-domain-cells = <0>;
 490                                         mediatek,infracfg = <&infracfg>;
 491                                 };
 492                                 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
 493                                         reg = <MT8173_POWER_DOMAIN_VENC_LT>;
 494                                         clocks = <&topckgen CLK_TOP_MM_SEL>,
 495                                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 496                                         clock-names = "mm", "venclt";
 497                                         #power-domain-cells = <0>;
 498                                 };
 499                                 power-domain@MT8173_POWER_DOMAIN_AUDIO {
 500                                         reg = <MT8173_POWER_DOMAIN_AUDIO>;
 501                                         #power-domain-cells = <0>;
 502                                 };
 503                                 power-domain@MT8173_POWER_DOMAIN_USB {
 504                                         reg = <MT8173_POWER_DOMAIN_USB>;
 505                                         #power-domain-cells = <0>;
 506                                 };
 507                                 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
 508                                         reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
 509                                         clocks = <&clk26m>;
 510                                         clock-names = "mfg";
 511                                         #address-cells = <1>;
 512                                         #size-cells = <0>;
 513                                         #power-domain-cells = <1>;
 514
 515                                         power-domain@MT8173_POWER_DOMAIN_MFG_2D {
 516                                                 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
 517                                                 #address-cells = <1>;
 518                                                 #size-cells = <0>;
 519                                                 #power-domain-cells = <1>;
 520
 521                                                 power-domain@MT8173_POWER_DOMAIN_MFG {
 522                                                         reg = <MT8173_POWER_DOMAIN_MFG>;
 523                                                         #power-domain-cells = <0>;
 524                                                         mediatek,infracfg = <&infracfg>;
 525                                                 };
 526                                         };
 527                                 };
 528                         };
 529                 };
 530
 531                 watchdog: watchdog@10007000 {
 532                         compatible = "mediatek,mt8173-wdt",
 533                                      "mediatek,mt6589-wdt";
 534                         reg = <0 0x10007000 0 0x100>;
 535                 };
 536
 537                 timer: timer@10008000 {
 538                         compatible = "mediatek,mt8173-timer",
 539                                      "mediatek,mt6577-timer";
 540                         reg = <0 0x10008000 0 0x1000>;
 541                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 542                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 543                                  <&topckgen CLK_TOP_RTC_SEL>;
 544                 };
 545
 546                 pwrap: pwrap@1000d000 {
 547                         compatible = "mediatek,mt8173-pwrap";
 548                         reg = <0 0x1000d000 0 0x1000>;
 549                         reg-names = "pwrap";
 550                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 551                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 552                         reset-names = "pwrap";
 553                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 554                         clock-names = "spi", "wrap";
 555                 };
 556
 557                 cec: cec@10013000 {
 558                         compatible = "mediatek,mt8173-cec";
 559                         reg = <0 0x10013000 0 0xbc>;
 560                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 561                         clocks = <&infracfg CLK_INFRA_CEC>;
 562                         status = "disabled";
 563                 };
 564
 565                 vpu: vpu@10020000 {
 566                         compatible = "mediatek,mt8173-vpu";
 567                         reg = <0 0x10020000 0 0x30000>,
 568                               <0 0x10050000 0 0x100>;
 569                         reg-names = "tcm", "cfg_reg";
 570                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 572                         clock-names = "main";
 573                         memory-region = <&vpu_dma_reserved>;
 574                 };
 575
 576                 sysirq: intpol-controller@10200620 {
 577                         compatible = "mediatek,mt8173-sysirq",
 578                                      "mediatek,mt6577-sysirq";
 579                         interrupt-controller;
 580                         #interrupt-cells = <3>;
 581                         interrupt-parent = <&gic>;
 582                         reg = <0 0x10200620 0 0x20>;
 583                 };
 584
 585                 iommu: iommu@10205000 {
 586                         compatible = "mediatek,mt8173-m4u";
 587                         reg = <0 0x10205000 0 0x1000>;
 588                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 589                         clocks = <&infracfg CLK_INFRA_M4U>;
 590                         clock-names = "bclk";
 591                         mediatek,larbs = <&larb0 &larb1 &larb2
 592                                           &larb3 &larb4 &larb5>;
 593                         #iommu-cells = <1>;
 594                 };
 595
 596                 efuse: efuse@10206000 {
 597                         compatible = "mediatek,mt8173-efuse";
 598                         reg = <0 0x10206000 0 0x1000>;
 599                         #address-cells = <1>;
 600                         #size-cells = <1>;
 601                         thermal_calibration: calib@528 {
 602                                 reg = <0x528 0xc>;
 603                         };
 604                 };
 605
 606                 apmixedsys: clock-controller@10209000 {
 607                         compatible = "mediatek,mt8173-apmixedsys";
 608                         reg = <0 0x10209000 0 0x1000>;
 609                         #clock-cells = <1>;
 610                 };
 611
 612                 hdmi_phy: hdmi-phy@10209100 {
 613                         compatible = "mediatek,mt8173-hdmi-phy";
 614                         reg = <0 0x10209100 0 0x24>;
 615                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 616                         clock-names = "pll_ref";
 617                         clock-output-names = "hdmitx_dig_cts";
 618                         mediatek,ibias = <0xa>;
 619                         mediatek,ibias_up = <0x1c>;
 620                         #clock-cells = <0>;
 621                         #phy-cells = <0>;
 622                         status = "disabled";
 623                 };
 624
 625                 gce: mailbox@10212000 {
 626                         compatible = "mediatek,mt8173-gce";
 627                         reg = <0 0x10212000 0 0x1000>;
 628                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 629                         clocks = <&infracfg CLK_INFRA_GCE>;
 630                         clock-names = "gce";
 631                         #mbox-cells = <2>;
 632                 };
 633
 634                 mipi_tx0: dsi-phy@10215000 {
 635                         compatible = "mediatek,mt8173-mipi-tx";
 636                         reg = <0 0x10215000 0 0x1000>;
 637                         clocks = <&clk26m>;
 638                         clock-output-names = "mipi_tx0_pll";
 639                         #clock-cells = <0>;
 640                         #phy-cells = <0>;
 641                         status = "disabled";
 642                 };
 643
 644                 mipi_tx1: dsi-phy@10216000 {
 645                         compatible = "mediatek,mt8173-mipi-tx";
 646                         reg = <0 0x10216000 0 0x1000>;
 647                         clocks = <&clk26m>;
 648                         clock-output-names = "mipi_tx1_pll";
 649                         #clock-cells = <0>;
 650                         #phy-cells = <0>;
 651                         status = "disabled";
 652                 };
 653
 654                 gic: interrupt-controller@10221000 {
 655                         compatible = "arm,gic-400";
 656                         #interrupt-cells = <3>;
 657                         interrupt-parent = <&gic>;
 658                         interrupt-controller;
 659                         reg = <0 0x10221000 0 0x1000>,
 660                               <0 0x10222000 0 0x2000>,
 661                               <0 0x10224000 0 0x2000>,
 662                               <0 0x10226000 0 0x2000>;
 663                         interrupts = <GIC_PPI 9
 664                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 665                 };
 666
 667                 auxadc: auxadc@11001000 {
 668                         compatible = "mediatek,mt8173-auxadc";
 669                         reg = <0 0x11001000 0 0x1000>;
 670                         clocks = <&pericfg CLK_PERI_AUXADC>;
 671                         clock-names = "main";
 672                         #io-channel-cells = <1>;
 673                 };
 674
 675                 uart0: serial@11002000 {
 676                         compatible = "mediatek,mt8173-uart",
 677                                      "mediatek,mt6577-uart";
 678                         reg = <0 0x11002000 0 0x400>;
 679                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 680                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 681                         clock-names = "baud", "bus";
 682                         status = "disabled";
 683                 };
 684
 685                 uart1: serial@11003000 {
 686                         compatible = "mediatek,mt8173-uart",
 687                                      "mediatek,mt6577-uart";
 688                         reg = <0 0x11003000 0 0x400>;
 689                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 690                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 691                         clock-names = "baud", "bus";
 692                         status = "disabled";
 693                 };
 694
 695                 uart2: serial@11004000 {
 696                         compatible = "mediatek,mt8173-uart",
 697                                      "mediatek,mt6577-uart";
 698                         reg = <0 0x11004000 0 0x400>;
 699                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 700                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 701                         clock-names = "baud", "bus";
 702                         status = "disabled";
 703                 };
 704
 705                 uart3: serial@11005000 {
 706                         compatible = "mediatek,mt8173-uart",
 707                                      "mediatek,mt6577-uart";
 708                         reg = <0 0x11005000 0 0x400>;
 709                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 710                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 711                         clock-names = "baud", "bus";
 712                         status = "disabled";
 713                 };
 714
 715                 i2c0: i2c@11007000 {
 716                         compatible = "mediatek,mt8173-i2c";
 717                         reg = <0 0x11007000 0 0x70>,
 718                               <0 0x11000100 0 0x80>;
 719                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 720                         clock-div = <16>;
 721                         clocks = <&pericfg CLK_PERI_I2C0>,
 722                                  <&pericfg CLK_PERI_AP_DMA>;
 723                         clock-names = "main", "dma";
 724                         pinctrl-names = "default";
 725                         pinctrl-0 = <&i2c0_pins_a>;
 726                         #address-cells = <1>;
 727                         #size-cells = <0>;
 728                         status = "disabled";
 729                 };
 730
 731                 i2c1: i2c@11008000 {
 732                         compatible = "mediatek,mt8173-i2c";
 733                         reg = <0 0x11008000 0 0x70>,
 734                               <0 0x11000180 0 0x80>;
 735                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 736                         clock-div = <16>;
 737                         clocks = <&pericfg CLK_PERI_I2C1>,
 738                                  <&pericfg CLK_PERI_AP_DMA>;
 739                         clock-names = "main", "dma";
 740                         pinctrl-names = "default";
 741                         pinctrl-0 = <&i2c1_pins_a>;
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744                         status = "disabled";
 745                 };
 746
 747                 i2c2: i2c@11009000 {
 748                         compatible = "mediatek,mt8173-i2c";
 749                         reg = <0 0x11009000 0 0x70>,
 750                               <0 0x11000200 0 0x80>;
 751                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 752                         clock-div = <16>;
 753                         clocks = <&pericfg CLK_PERI_I2C2>,
 754                                  <&pericfg CLK_PERI_AP_DMA>;
 755                         clock-names = "main", "dma";
 756                         pinctrl-names = "default";
 757                         pinctrl-0 = <&i2c2_pins_a>;
 758                         #address-cells = <1>;
 759                         #size-cells = <0>;
 760                         status = "disabled";
 761                 };
 762
 763                 spi: spi@1100a000 {
 764                         compatible = "mediatek,mt8173-spi";
 765                         #address-cells = <1>;
 766                         #size-cells = <0>;
 767                         reg = <0 0x1100a000 0 0x1000>;
 768                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 769                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 770                                  <&topckgen CLK_TOP_SPI_SEL>,
 771                                  <&pericfg CLK_PERI_SPI0>;
 772                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 773                         status = "disabled";
 774                 };
 775
 776                 thermal: thermal@1100b000 {
 777                         #thermal-sensor-cells = <0>;
 778                         compatible = "mediatek,mt8173-thermal";
 779                         reg = <0 0x1100b000 0 0x1000>;
 780                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 781                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 782                         clock-names = "therm", "auxadc";
 783                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 784                         mediatek,auxadc = <&auxadc>;
 785                         mediatek,apmixedsys = <&apmixedsys>;
 786                         nvmem-cells = <&thermal_calibration>;
 787                         nvmem-cell-names = "calibration-data";
 788                 };
 789
 790                 nor_flash: spi@1100d000 {
 791                         compatible = "mediatek,mt8173-nor";
 792                         reg = <0 0x1100d000 0 0xe0>;
 793                         clocks = <&pericfg CLK_PERI_SPI>,
 794                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 795                         clock-names = "spi", "sf";
 796                         #address-cells = <1>;
 797                         #size-cells = <0>;
 798                         status = "disabled";
 799                 };
 800
 801                 i2c3: i2c@11010000 {
 802                         compatible = "mediatek,mt8173-i2c";
 803                         reg = <0 0x11010000 0 0x70>,
 804                               <0 0x11000280 0 0x80>;
 805                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 806                         clock-div = <16>;
 807                         clocks = <&pericfg CLK_PERI_I2C3>,
 808                                  <&pericfg CLK_PERI_AP_DMA>;
 809                         clock-names = "main", "dma";
 810                         pinctrl-names = "default";
 811                         pinctrl-0 = <&i2c3_pins_a>;
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                         status = "disabled";
 815                 };
 816
 817                 i2c4: i2c@11011000 {
 818                         compatible = "mediatek,mt8173-i2c";
 819                         reg = <0 0x11011000 0 0x70>,
 820                               <0 0x11000300 0 0x80>;
 821                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 822                         clock-div = <16>;
 823                         clocks = <&pericfg CLK_PERI_I2C4>,
 824                                  <&pericfg CLK_PERI_AP_DMA>;
 825                         clock-names = "main", "dma";
 826                         pinctrl-names = "default";
 827                         pinctrl-0 = <&i2c4_pins_a>;
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830                         status = "disabled";
 831                 };
 832
 833                 hdmiddc0: i2c@11012000 {
 834                         compatible = "mediatek,mt8173-hdmi-ddc";
 835                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 836                         reg = <0 0x11012000 0 0x1C>;
 837                         clocks = <&pericfg CLK_PERI_I2C5>;
 838                         clock-names = "ddc-i2c";
 839                 };
 840
 841                 i2c6: i2c@11013000 {
 842                         compatible = "mediatek,mt8173-i2c";
 843                         reg = <0 0x11013000 0 0x70>,
 844                               <0 0x11000080 0 0x80>;
 845                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 846                         clock-div = <16>;
 847                         clocks = <&pericfg CLK_PERI_I2C6>,
 848                                  <&pericfg CLK_PERI_AP_DMA>;
 849                         clock-names = "main", "dma";
 850                         pinctrl-names = "default";
 851                         pinctrl-0 = <&i2c6_pins_a>;
 852                         #address-cells = <1>;
 853                         #size-cells = <0>;
 854                         status = "disabled";
 855                 };
 856
 857                 afe: audio-controller@11220000  {
 858                         compatible = "mediatek,mt8173-afe-pcm";
 859                         reg = <0 0x11220000 0 0x1000>;
 860                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 861                         power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
 862                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 863                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 864                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 865                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 866                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 867                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 868                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 869                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 870                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 871                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 872                         clock-names = "infra_sys_audio_clk",
 873                                       "top_pdn_audio",
 874                                       "top_pdn_aud_intbus",
 875                                       "bck0",
 876                                       "bck1",
 877                                       "i2s0_m",
 878                                       "i2s1_m",
 879                                       "i2s2_m",
 880                                       "i2s3_m",
 881                                       "i2s3_b";
 882                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 883                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 884                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 885                                                  <&topckgen CLK_TOP_APLL2>;
 886                 };
 887
 888                 mmc0: mmc@11230000 {
 889                         compatible = "mediatek,mt8173-mmc";
 890                         reg = <0 0x11230000 0 0x1000>;
 891                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 892                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 893                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 894                         clock-names = "source", "hclk";
 895                         status = "disabled";
 896                 };
 897
 898                 mmc1: mmc@11240000 {
 899                         compatible = "mediatek,mt8173-mmc";
 900                         reg = <0 0x11240000 0 0x1000>;
 901                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 902                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 903                                  <&topckgen CLK_TOP_AXI_SEL>;
 904                         clock-names = "source", "hclk";
 905                         status = "disabled";
 906                 };
 907
 908                 mmc2: mmc@11250000 {
 909                         compatible = "mediatek,mt8173-mmc";
 910                         reg = <0 0x11250000 0 0x1000>;
 911                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 912                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 913                                  <&topckgen CLK_TOP_AXI_SEL>;
 914                         clock-names = "source", "hclk";
 915                         status = "disabled";
 916                 };
 917
 918                 mmc3: mmc@11260000 {
 919                         compatible = "mediatek,mt8173-mmc";
 920                         reg = <0 0x11260000 0 0x1000>;
 921                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 922                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 923                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 924                         clock-names = "source", "hclk";
 925                         status = "disabled";
 926                 };
 927
 928                 ssusb: usb@11271000 {
 929                         compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
 930                         reg = <0 0x11271000 0 0x3000>,
 931                               <0 0x11280700 0 0x0100>;
 932                         reg-names = "mac", "ippc";
 933                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 934                         phys = <&u2port0 PHY_TYPE_USB2>,
 935                                <&u3port0 PHY_TYPE_USB3>,
 936                                <&u2port1 PHY_TYPE_USB2>;
 937                         power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
 938                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 939                         clock-names = "sys_ck", "ref_ck";
 940                         mediatek,syscon-wakeup = <&pericfg 0x400 1>;
 941                         #address-cells = <2>;
 942                         #size-cells = <2>;
 943                         ranges;
 944                         status = "disabled";
 945
 946                         usb_host: usb@11270000 {
 947                                 compatible = "mediatek,mt8173-xhci",
 948                                              "mediatek,mtk-xhci";
 949                                 reg = <0 0x11270000 0 0x1000>;
 950                                 reg-names = "mac";
 951                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 952                                 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
 953                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 954                                 clock-names = "sys_ck", "ref_ck";
 955                                 status = "disabled";
 956                         };
 957                 };
 958
 959                 u3phy: t-phy@11290000 {
 960                         compatible = "mediatek,mt8173-u3phy";
 961                         reg = <0 0x11290000 0 0x800>;
 962                         #address-cells = <2>;
 963                         #size-cells = <2>;
 964                         ranges;
 965                         status = "okay";
 966
 967                         u2port0: usb-phy@11290800 {
 968                                 reg = <0 0x11290800 0 0x100>;
 969                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 970                                 clock-names = "ref";
 971                                 #phy-cells = <1>;
 972                                 status = "okay";
 973                         };
 974
 975                         u3port0: usb-phy@11290900 {
 976                                 reg = <0 0x11290900 0 0x700>;
 977                                 clocks = <&clk26m>;
 978                                 clock-names = "ref";
 979                                 #phy-cells = <1>;
 980                                 status = "okay";
 981                         };
 982
 983                         u2port1: usb-phy@11291000 {
 984                                 reg = <0 0x11291000 0 0x100>;
 985                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 986                                 clock-names = "ref";
 987                                 #phy-cells = <1>;
 988                                 status = "okay";
 989                         };
 990                 };
 991
 992                 mmsys: syscon@14000000 {
 993                         compatible = "mediatek,mt8173-mmsys", "syscon";
 994                         reg = <0 0x14000000 0 0x1000>;
 995                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
 996                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
 997                         assigned-clock-rates = <400000000>;
 998                         #clock-cells = <1>;
 999                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1000                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1001                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1002                 };
1003
1004                 mdp_rdma0: rdma@14001000 {
1005                         compatible = "mediatek,mt8173-mdp-rdma",
1006                                      "mediatek,mt8173-mdp";
1007                         reg = <0 0x14001000 0 0x1000>;
1008                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1009                                  <&mmsys CLK_MM_MUTEX_32K>;
1010                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1011                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1012                         mediatek,larb = <&larb0>;
1013                         mediatek,vpu = <&vpu>;
1014                 };
1015
1016                 mdp_rdma1: rdma@14002000 {
1017                         compatible = "mediatek,mt8173-mdp-rdma";
1018                         reg = <0 0x14002000 0 0x1000>;
1019                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1020                                  <&mmsys CLK_MM_MUTEX_32K>;
1021                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1022                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1023                         mediatek,larb = <&larb4>;
1024                 };
1025
1026                 mdp_rsz0: rsz@14003000 {
1027                         compatible = "mediatek,mt8173-mdp-rsz";
1028                         reg = <0 0x14003000 0 0x1000>;
1029                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1030                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1031                 };
1032
1033                 mdp_rsz1: rsz@14004000 {
1034                         compatible = "mediatek,mt8173-mdp-rsz";
1035                         reg = <0 0x14004000 0 0x1000>;
1036                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1037                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1038                 };
1039
1040                 mdp_rsz2: rsz@14005000 {
1041                         compatible = "mediatek,mt8173-mdp-rsz";
1042                         reg = <0 0x14005000 0 0x1000>;
1043                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1044                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1045                 };
1046
1047                 mdp_wdma0: wdma@14006000 {
1048                         compatible = "mediatek,mt8173-mdp-wdma";
1049                         reg = <0 0x14006000 0 0x1000>;
1050                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
1051                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1052                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
1053                         mediatek,larb = <&larb0>;
1054                 };
1055
1056                 mdp_wrot0: wrot@14007000 {
1057                         compatible = "mediatek,mt8173-mdp-wrot";
1058                         reg = <0 0x14007000 0 0x1000>;
1059                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
1060                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1061                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
1062                         mediatek,larb = <&larb0>;
1063                 };
1064
1065                 mdp_wrot1: wrot@14008000 {
1066                         compatible = "mediatek,mt8173-mdp-wrot";
1067                         reg = <0 0x14008000 0 0x1000>;
1068                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
1069                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1070                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
1071                         mediatek,larb = <&larb4>;
1072                 };
1073
1074                 ovl0: ovl@1400c000 {
1075                         compatible = "mediatek,mt8173-disp-ovl";
1076                         reg = <0 0x1400c000 0 0x1000>;
1077                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1078                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1079                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1080                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
1081                         mediatek,larb = <&larb0>;
1082                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1083                 };
1084
1085                 ovl1: ovl@1400d000 {
1086                         compatible = "mediatek,mt8173-disp-ovl";
1087                         reg = <0 0x1400d000 0 0x1000>;
1088                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1089                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1090                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
1091                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
1092                         mediatek,larb = <&larb4>;
1093                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1094                 };
1095
1096                 rdma0: rdma@1400e000 {
1097                         compatible = "mediatek,mt8173-disp-rdma";
1098                         reg = <0 0x1400e000 0 0x1000>;
1099                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1100                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1101                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1102                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1103                         mediatek,larb = <&larb0>;
1104                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1105                 };
1106
1107                 rdma1: rdma@1400f000 {
1108                         compatible = "mediatek,mt8173-disp-rdma";
1109                         reg = <0 0x1400f000 0 0x1000>;
1110                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1111                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1112                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1113                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1114                         mediatek,larb = <&larb4>;
1115                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1116                 };
1117
1118                 rdma2: rdma@14010000 {
1119                         compatible = "mediatek,mt8173-disp-rdma";
1120                         reg = <0 0x14010000 0 0x1000>;
1121                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1122                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1123                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1124                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1125                         mediatek,larb = <&larb4>;
1126                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1127                 };
1128
1129                 wdma0: wdma@14011000 {
1130                         compatible = "mediatek,mt8173-disp-wdma";
1131                         reg = <0 0x14011000 0 0x1000>;
1132                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1133                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1134                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1135                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1136                         mediatek,larb = <&larb0>;
1137                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1138                 };
1139
1140                 wdma1: wdma@14012000 {
1141                         compatible = "mediatek,mt8173-disp-wdma";
1142                         reg = <0 0x14012000 0 0x1000>;
1143                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1144                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1145                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1146                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1147                         mediatek,larb = <&larb4>;
1148                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1149                 };
1150
1151                 color0: color@14013000 {
1152                         compatible = "mediatek,mt8173-disp-color";
1153                         reg = <0 0x14013000 0 0x1000>;
1154                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1155                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1156                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1157                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1158                 };
1159
1160                 color1: color@14014000 {
1161                         compatible = "mediatek,mt8173-disp-color";
1162                         reg = <0 0x14014000 0 0x1000>;
1163                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1164                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1165                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1166                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1167                 };
1168
1169                 aal@14015000 {
1170                         compatible = "mediatek,mt8173-disp-aal";
1171                         reg = <0 0x14015000 0 0x1000>;
1172                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1173                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1174                         clocks = <&mmsys CLK_MM_DISP_AAL>;
1175                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1176                 };
1177
1178                 gamma@14016000 {
1179                         compatible = "mediatek,mt8173-disp-gamma";
1180                         reg = <0 0x14016000 0 0x1000>;
1181                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1182                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1183                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1184                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1185                 };
1186
1187                 merge@14017000 {
1188                         compatible = "mediatek,mt8173-disp-merge";
1189                         reg = <0 0x14017000 0 0x1000>;
1190                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1191                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
1192                 };
1193
1194                 split0: split@14018000 {
1195                         compatible = "mediatek,mt8173-disp-split";
1196                         reg = <0 0x14018000 0 0x1000>;
1197                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1198                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1199                 };
1200
1201                 split1: split@14019000 {
1202                         compatible = "mediatek,mt8173-disp-split";
1203                         reg = <0 0x14019000 0 0x1000>;
1204                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1205                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1206                 };
1207
1208                 ufoe@1401a000 {
1209                         compatible = "mediatek,mt8173-disp-ufoe";
1210                         reg = <0 0x1401a000 0 0x1000>;
1211                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1212                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1213                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1214                 };
1215
1216                 dsi0: dsi@1401b000 {
1217                         compatible = "mediatek,mt8173-dsi";
1218                         reg = <0 0x1401b000 0 0x1000>;
1219                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1220                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1221                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1222                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1223                                  <&mipi_tx0>;
1224                         clock-names = "engine", "digital", "hs";
1225                         phys = <&mipi_tx0>;
1226                         phy-names = "dphy";
1227                         status = "disabled";
1228                 };
1229
1230                 dsi1: dsi@1401c000 {
1231                         compatible = "mediatek,mt8173-dsi";
1232                         reg = <0 0x1401c000 0 0x1000>;
1233                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1234                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1235                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1236                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1237                                  <&mipi_tx1>;
1238                         clock-names = "engine", "digital", "hs";
1239                         phys = <&mipi_tx1>;
1240                         phy-names = "dphy";
1241                         status = "disabled";
1242                 };
1243
1244                 dpi0: dpi@1401d000 {
1245                         compatible = "mediatek,mt8173-dpi";
1246                         reg = <0 0x1401d000 0 0x1000>;
1247                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1248                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1249                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1250                                  <&mmsys CLK_MM_DPI_ENGINE>,
1251                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1252                         clock-names = "pixel", "engine", "pll";
1253                         status = "disabled";
1254
1255                         port {
1256                                 dpi0_out: endpoint {
1257                                         remote-endpoint = <&hdmi0_in>;
1258                                 };
1259                         };
1260                 };
1261
1262                 pwm0: pwm@1401e000 {
1263                         compatible = "mediatek,mt8173-disp-pwm",
1264                                      "mediatek,mt6595-disp-pwm";
1265                         reg = <0 0x1401e000 0 0x1000>;
1266                         #pwm-cells = <2>;
1267                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1268                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1269                         clock-names = "main", "mm";
1270                         status = "disabled";
1271                 };
1272
1273                 pwm1: pwm@1401f000 {
1274                         compatible = "mediatek,mt8173-disp-pwm",
1275                                      "mediatek,mt6595-disp-pwm";
1276                         reg = <0 0x1401f000 0 0x1000>;
1277                         #pwm-cells = <2>;
1278                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1279                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1280                         clock-names = "main", "mm";
1281                         status = "disabled";
1282                 };
1283
1284                 mutex: mutex@14020000 {
1285                         compatible = "mediatek,mt8173-disp-mutex";
1286                         reg = <0 0x14020000 0 0x1000>;
1287                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1288                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1289                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1290                         mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1291                                               <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
1292                 };
1293
1294                 larb0: larb@14021000 {
1295                         compatible = "mediatek,mt8173-smi-larb";
1296                         reg = <0 0x14021000 0 0x1000>;
1297                         mediatek,smi = <&smi_common>;
1298                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1299                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1300                                  <&mmsys CLK_MM_SMI_LARB0>;
1301                         clock-names = "apb", "smi";
1302                 };
1303
1304                 smi_common: smi@14022000 {
1305                         compatible = "mediatek,mt8173-smi-common";
1306                         reg = <0 0x14022000 0 0x1000>;
1307                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1308                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1309                                  <&mmsys CLK_MM_SMI_COMMON>;
1310                         clock-names = "apb", "smi";
1311                 };
1312
1313                 od@14023000 {
1314                         compatible = "mediatek,mt8173-disp-od";
1315                         reg = <0 0x14023000 0 0x1000>;
1316                         clocks = <&mmsys CLK_MM_DISP_OD>;
1317                 };
1318
1319                 hdmi0: hdmi@14025000 {
1320                         compatible = "mediatek,mt8173-hdmi";
1321                         reg = <0 0x14025000 0 0x400>;
1322                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1323                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1324                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1325                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1326                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1327                         clock-names = "pixel", "pll", "bclk", "spdif";
1328                         pinctrl-names = "default";
1329                         pinctrl-0 = <&hdmi_pin>;
1330                         phys = <&hdmi_phy>;
1331                         phy-names = "hdmi";
1332                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1333                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1334                         assigned-clock-parents = <&hdmi_phy>;
1335                         status = "disabled";
1336
1337                         ports {
1338                                 #address-cells = <1>;
1339                                 #size-cells = <0>;
1340
1341                                 port@0 {
1342                                         reg = <0>;
1343
1344                                         hdmi0_in: endpoint {
1345                                                 remote-endpoint = <&dpi0_out>;
1346                                         };
1347                                 };
1348                         };
1349                 };
1350
1351                 larb4: larb@14027000 {
1352                         compatible = "mediatek,mt8173-smi-larb";
1353                         reg = <0 0x14027000 0 0x1000>;
1354                         mediatek,smi = <&smi_common>;
1355                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1356                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1357                                  <&mmsys CLK_MM_SMI_LARB4>;
1358                         clock-names = "apb", "smi";
1359                 };
1360
1361                 imgsys: clock-controller@15000000 {
1362                         compatible = "mediatek,mt8173-imgsys", "syscon";
1363                         reg = <0 0x15000000 0 0x1000>;
1364                         #clock-cells = <1>;
1365                 };
1366
1367                 larb2: larb@15001000 {
1368                         compatible = "mediatek,mt8173-smi-larb";
1369                         reg = <0 0x15001000 0 0x1000>;
1370                         mediatek,smi = <&smi_common>;
1371                         power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1372                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1373                                  <&imgsys CLK_IMG_LARB2_SMI>;
1374                         clock-names = "apb", "smi";
1375                 };
1376
1377                 vdecsys: clock-controller@16000000 {
1378                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1379                         reg = <0 0x16000000 0 0x1000>;
1380                         #clock-cells = <1>;
1381                 };
1382
1383                 vcodec_dec: vcodec@16000000 {
1384                         compatible = "mediatek,mt8173-vcodec-dec";
1385                         reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
1386                               <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1387                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1388                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1389                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1390                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1391                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1392                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1393                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1394                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1395                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1396                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1397                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1398                         mediatek,larb = <&larb1>;
1399                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1400                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1401                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1402                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1403                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1404                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1405                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1406                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1407                         mediatek,vpu = <&vpu>;
1408                         power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1409                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1410                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1411                                  <&topckgen CLK_TOP_CCI400_SEL>,
1412                                  <&topckgen CLK_TOP_VDEC_SEL>,
1413                                  <&topckgen CLK_TOP_VCODECPLL>,
1414                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1415                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1416                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1417                         clock-names = "vcodecpll",
1418                                       "univpll_d2",
1419                                       "clk_cci400_sel",
1420                                       "vdec_sel",
1421                                       "vdecpll",
1422                                       "vencpll",
1423                                       "venc_lt_sel",
1424                                       "vdec_bus_clk_src";
1425                         assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1426                                           <&topckgen CLK_TOP_CCI400_SEL>,
1427                                           <&topckgen CLK_TOP_VDEC_SEL>,
1428                                           <&apmixedsys CLK_APMIXED_VCODECPLL>,
1429                                           <&apmixedsys CLK_APMIXED_VENCPLL>;
1430                         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1431                                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1432                                                  <&topckgen CLK_TOP_VCODECPLL>;
1433                         assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1434                 };
1435
1436                 larb1: larb@16010000 {
1437                         compatible = "mediatek,mt8173-smi-larb";
1438                         reg = <0 0x16010000 0 0x1000>;
1439                         mediatek,smi = <&smi_common>;
1440                         power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1441                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1442                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1443                         clock-names = "apb", "smi";
1444                 };
1445
1446                 vencsys: clock-controller@18000000 {
1447                         compatible = "mediatek,mt8173-vencsys", "syscon";
1448                         reg = <0 0x18000000 0 0x1000>;
1449                         #clock-cells = <1>;
1450                 };
1451
1452                 larb3: larb@18001000 {
1453                         compatible = "mediatek,mt8173-smi-larb";
1454                         reg = <0 0x18001000 0 0x1000>;
1455                         mediatek,smi = <&smi_common>;
1456                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1457                         clocks = <&vencsys CLK_VENC_CKE1>,
1458                                  <&vencsys CLK_VENC_CKE0>;
1459                         clock-names = "apb", "smi";
1460                 };
1461
1462                 vcodec_enc_avc: vcodec@18002000 {
1463                         compatible = "mediatek,mt8173-vcodec-enc";
1464                         reg = <0 0x18002000 0 0x1000>;  /* VENC_SYS */
1465                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1466                         mediatek,larb = <&larb3>;
1467                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1468                                  <&iommu M4U_PORT_VENC_REC>,
1469                                  <&iommu M4U_PORT_VENC_BSDMA>,
1470                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1471                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1472                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1473                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1474                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1475                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1476                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1477                                  <&iommu M4U_PORT_VENC_NBM_WDMA>;
1478                         mediatek,vpu = <&vpu>;
1479                         clocks = <&topckgen CLK_TOP_VENC_SEL>;
1480                         clock-names = "venc_sel";
1481                         assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1482                         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1483                 };
1484
1485                 jpegdec: jpegdec@18004000 {
1486                         compatible = "mediatek,mt8173-jpgdec";
1487                         reg = <0 0x18004000 0 0x1000>;
1488                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1489                         clocks = <&vencsys CLK_VENC_CKE0>,
1490                                  <&vencsys CLK_VENC_CKE3>;
1491                         clock-names = "jpgdec-smi",
1492                                       "jpgdec";
1493                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1494                         mediatek,larb = <&larb3>;
1495                         iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1496                                  <&iommu M4U_PORT_JPGDEC_BSDMA>;
1497                 };
1498
1499                 vencltsys: clock-controller@19000000 {
1500                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1501                         reg = <0 0x19000000 0 0x1000>;
1502                         #clock-cells = <1>;
1503                 };
1504
1505                 larb5: larb@19001000 {
1506                         compatible = "mediatek,mt8173-smi-larb";
1507                         reg = <0 0x19001000 0 0x1000>;
1508                         mediatek,smi = <&smi_common>;
1509                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1510                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1511                                  <&vencltsys CLK_VENCLT_CKE0>;
1512                         clock-names = "apb", "smi";
1513                 };
1514
1515                 vcodec_enc_vp8: vcodec@19002000 {
1516                         compatible = "mediatek,mt8173-vcodec-enc-vp8";
1517                         reg =  <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1518                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1519                         iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
1520                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1521                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1522                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1523                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1524                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1525                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1526                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1527                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1528                         mediatek,larb = <&larb5>;
1529                         mediatek,vpu = <&vpu>;
1530                         clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1531                         clock-names = "venc_lt_sel";
1532                         assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1533                         assigned-clock-parents =
1534                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1535                 };
1536         };
1537 };