arch/arm64/boot/dts/mediatek/mt8167.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Copyright (c) 2020 BayLibre, SAS.
   5  * Author: Fabien Parent <fparent@baylibre.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt8167-clk.h>
   9 #include <dt-bindings/memory/mt8167-larb-port.h>
  10 #include <dt-bindings/power/mt8167-power.h>
  11
  12 #include "mt8167-pinfunc.h"
  13
  14 #include "mt8516.dtsi"
  15
  16 / {
  17         compatible = "mediatek,mt8167";
  18
  19         soc {
  20                 topckgen: topckgen@10000000 {
  21                         compatible = "mediatek,mt8167-topckgen", "syscon";
  22                         reg = <0 0x10000000 0 0x1000>;
  23                         #clock-cells = <1>;
  24                 };
  25
  26                 infracfg: infracfg@10001000 {
  27                         compatible = "mediatek,mt8167-infracfg", "syscon";
  28                         reg = <0 0x10001000 0 0x1000>;
  29                         #clock-cells = <1>;
  30                 };
  31
  32                 apmixedsys: apmixedsys@10018000 {
  33                         compatible = "mediatek,mt8167-apmixedsys", "syscon";
  34                         reg = <0 0x10018000 0 0x710>;
  35                         #clock-cells = <1>;
  36                 };
  37
  38                 scpsys: syscon@10006000 {
  39                         compatible = "syscon", "simple-mfd";
  40                         reg = <0 0x10006000 0 0x1000>;
  41                         #power-domain-cells = <1>;
  42
  43                         spm: power-controller {
  44                                 compatible = "mediatek,mt8167-power-controller";
  45                                 #address-cells = <1>;
  46                                 #size-cells = <0>;
  47                                 #power-domain-cells = <1>;
  48
  49                                 /* power domains of the SoC */
  50                                 power-domain@MT8167_POWER_DOMAIN_MM {
  51                                         reg = <MT8167_POWER_DOMAIN_MM>;
  52                                         clocks = <&topckgen CLK_TOP_SMI_MM>;
  53                                         clock-names = "mm";
  54                                         #power-domain-cells = <0>;
  55                                         mediatek,infracfg = <&infracfg>;
  56                                 };
  57
  58                                 power-domain@MT8167_POWER_DOMAIN_VDEC {
  59                                         reg = <MT8167_POWER_DOMAIN_VDEC>;
  60                                         clocks = <&topckgen CLK_TOP_SMI_MM>,
  61                                                  <&topckgen CLK_TOP_RG_VDEC>;
  62                                         clock-names = "mm", "vdec";
  63                                         #power-domain-cells = <0>;
  64                                 };
  65
  66                                 power-domain@MT8167_POWER_DOMAIN_ISP {
  67                                         reg = <MT8167_POWER_DOMAIN_ISP>;
  68                                         clocks = <&topckgen CLK_TOP_SMI_MM>;
  69                                         clock-names = "mm";
  70                                         #power-domain-cells = <0>;
  71                                 };
  72
  73                                 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
  74                                         reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
  75                                         clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
  76                                                  <&topckgen CLK_TOP_RG_SLOW_MFG>;
  77                                         clock-names = "axi_mfg", "mfg";
  78                                         #address-cells = <1>;
  79                                         #size-cells = <0>;
  80                                         #power-domain-cells = <1>;
  81                                         mediatek,infracfg = <&infracfg>;
  82
  83                                         power-domain@MT8167_POWER_DOMAIN_MFG_2D {
  84                                                 reg = <MT8167_POWER_DOMAIN_MFG_2D>;
  85                                                 #address-cells = <1>;
  86                                                 #size-cells = <0>;
  87                                                 #power-domain-cells = <1>;
  88
  89                                                 power-domain@MT8167_POWER_DOMAIN_MFG {
  90                                                         reg = <MT8167_POWER_DOMAIN_MFG>;
  91                                                         #power-domain-cells = <0>;
  92                                                         mediatek,infracfg = <&infracfg>;
  93                                                 };
  94                                         };
  95                                 };
  96
  97                                 power-domain@MT8167_POWER_DOMAIN_CONN {
  98                                         reg = <MT8167_POWER_DOMAIN_CONN>;
  99                                         #power-domain-cells = <0>;
 100                                         mediatek,infracfg = <&infracfg>;
 101                                 };
 102                         };
 103                 };
 104
 105                 imgsys: syscon@15000000 {
 106                         compatible = "mediatek,mt8167-imgsys", "syscon";
 107                         reg = <0 0x15000000 0 0x1000>;
 108                         #clock-cells = <1>;
 109                 };
 110
 111                 vdecsys: syscon@16000000 {
 112                         compatible = "mediatek,mt8167-vdecsys", "syscon";
 113                         reg = <0 0x16000000 0 0x1000>;
 114                         #clock-cells = <1>;
 115                 };
 116
 117                 pio: pinctrl@1000b000 {
 118                         compatible = "mediatek,mt8167-pinctrl";
 119                         reg = <0 0x1000b000 0 0x1000>;
 120                         mediatek,pctl-regmap = <&syscfg_pctl>;
 121                         pins-are-numbered;
 122                         gpio-controller;
 123                         #gpio-cells = <2>;
 124                         interrupt-controller;
 125                         #interrupt-cells = <2>;
 126                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 127                 };
 128
 129                 mmsys: mmsys@14000000 {
 130                         compatible = "mediatek,mt8167-mmsys", "syscon";
 131                         reg = <0 0x14000000 0 0x1000>;
 132                         #clock-cells = <1>;
 133                 };
 134
 135                 smi_common: smi@14017000 {
 136                         compatible = "mediatek,mt8167-smi-common";
 137                         reg = <0 0x14017000 0 0x1000>;
 138                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
 139                                  <&mmsys CLK_MM_SMI_COMMON>;
 140                         clock-names = "apb", "smi";
 141                         power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
 142                 };
 143
 144                 larb0: larb@14016000 {
 145                         compatible = "mediatek,mt8167-smi-larb";
 146                         reg = <0 0x14016000 0 0x1000>;
 147                         mediatek,smi = <&smi_common>;
 148                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
 149                                  <&mmsys CLK_MM_SMI_LARB0>;
 150                         clock-names = "apb", "smi";
 151                         power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
 152                 };
 153
 154                 larb1: larb@15001000 {
 155                         compatible = "mediatek,mt8167-smi-larb";
 156                         reg = <0 0x15001000 0 0x1000>;
 157                         mediatek,smi = <&smi_common>;
 158                         clocks = <&imgsys CLK_IMG_LARB1_SMI>,
 159                                  <&imgsys CLK_IMG_LARB1_SMI>;
 160                         clock-names = "apb", "smi";
 161                         power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
 162                 };
 163
 164                 larb2: larb@16010000 {
 165                         compatible = "mediatek,mt8167-smi-larb";
 166                         reg = <0 0x16010000 0 0x1000>;
 167                         mediatek,smi = <&smi_common>;
 168                         clocks = <&vdecsys CLK_VDEC_CKEN>,
 169                                  <&vdecsys CLK_VDEC_LARB1_CKEN>;
 170                         clock-names = "apb", "smi";
 171                         power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
 172                 };
 173
 174                 iommu: m4u@10203000 {
 175                         compatible = "mediatek,mt8167-m4u";
 176                         reg = <0 0x10203000 0 0x1000>;
 177                         mediatek,larbs = <&larb0 &larb1 &larb2>;
 178                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
 179                         #iommu-cells = <1>;
 180                 };
 181         };
 182 };