arch/arm64/boot/dts/marvell/armada-8040-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada 8040 Development board platform
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "armada-8040.dtsi"
  10
  11 / {
  12         model = "Marvell Armada 8040 DB board";
  13         compatible = "marvell,armada8040-db", "marvell,armada8040",
  14                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x0 0x0 0x80000000>;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth2;
  28                 ethernet2 = &cp1_eth0;
  29                 ethernet3 = &cp1_eth1;
  30                 i2c1 = &cp0_i2c0;
  31                 i2c2 = &cp1_i2c0;
  32         };
  33
  34         cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "cp0-usb3h0-vbus";
  37                 regulator-min-microvolt = <5000000>;
  38                 regulator-max-microvolt = <5000000>;
  39                 enable-active-high;
  40                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  41         };
  42
  43         cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "cp0-usb3h1-vbus";
  46                 regulator-min-microvolt = <5000000>;
  47                 regulator-max-microvolt = <5000000>;
  48                 enable-active-high;
  49                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         cp0_usb3_0_phy: cp0-usb3-0-phy {
  53                 compatible = "usb-nop-xceiv";
  54                 vcc-supply = <&cp0_reg_usb3_0_vbus>;
  55         };
  56
  57         cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "cp1-usb3h0-vbus";
  60                 regulator-min-microvolt = <5000000>;
  61                 regulator-max-microvolt = <5000000>;
  62                 enable-active-high;
  63                 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
  64         };
  65
  66         cp1_usb3_0_phy: cp1-usb3-0-phy {
  67                 compatible = "usb-nop-xceiv";
  68                 vcc-supply = <&cp1_reg_usb3_0_vbus>;
  69         };
  70 };
  71
  72 &spi0 {
  73         status = "okay";
  74
  75         spi-flash@0 {
  76                 compatible = "jedec,spi-nor";
  77                 reg = <0>;
  78                 spi-max-frequency = <10000000>;
  79
  80                 partitions {
  81                         compatible = "fixed-partitions";
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84
  85                         partition@0 {
  86                                 label = "U-Boot";
  87                                 reg = <0 0x200000>;
  88                         };
  89                         partition@400000 {
  90                                 label = "Filesystem";
  91                                 reg = <0x200000 0xce0000>;
  92                         };
  93                 };
  94         };
  95 };
  96
  97 /* Accessible over the mini-USB CON9 connector on the main board */
  98 &uart0 {
  99         status = "okay";
 100         pinctrl-0 = <&uart0_pins>;
 101         pinctrl-names = "default";
 102 };
 103
 104 /* CON6 on CP0 expansion */
 105 &cp0_pcie0 {
 106         phys = <&cp0_comphy0 0>;
 107         phy-names = "cp0-pcie0-x1-phy";
 108         status = "okay";
 109 };
 110
 111 /* CON5 on CP0 expansion */
 112 &cp0_pcie2 {
 113         phys = <&cp0_comphy5 2>;
 114         phy-names = "cp0-pcie2-x1-phy";
 115         status = "okay";
 116 };
 117
 118 &cp0_i2c0 {
 119         status = "okay";
 120         clock-frequency = <100000>;
 121
 122         /* U31 */
 123         expander0: pca9555@21 {
 124                 compatible = "nxp,pca9555";
 125                 pinctrl-names = "default";
 126                 gpio-controller;
 127                 #gpio-cells = <2>;
 128                 reg = <0x21>;
 129         };
 130
 131         /* U25 */
 132         expander1: pca9555@25 {
 133                 compatible = "nxp,pca9555";
 134                 pinctrl-names = "default";
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137                 reg = <0x25>;
 138         };
 139
 140 };
 141
 142 /* CON4 on CP0 expansion */
 143 &cp0_sata0 {
 144         status = "okay";
 145
 146         sata-port@0 {
 147                 phys = <&cp0_comphy1 0>;
 148                 phy-names = "cp0-sata0-0-phy";
 149         };
 150         sata-port@1 {
 151                 phys = <&cp0_comphy3 1>;
 152                 phy-names = "cp0-sata0-1-phy";
 153         };
 154 };
 155
 156 /* CON9 on CP0 expansion */
 157 &cp0_utmi {
 158         status = "okay";
 159 };
 160
 161 &cp0_usb3_0 {
 162         usb-phy = <&cp0_usb3_0_phy>;
 163         phys = <&cp0_utmi0>;
 164         phy-names = "utmi";
 165         dr_mode = "host";
 166         status = "okay";
 167 };
 168
 169 &cp0_comphy4 {
 170         cp0_usbh1_con: connector {
 171                 compatible = "usb-a-connector";
 172                 phy-supply = <&cp0_reg_usb3_1_vbus>;
 173         };
 174 };
 175
 176 /* CON10 on CP0 expansion */
 177 &cp0_usb3_1 {
 178         phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
 179         phy-names = "usb", "utmi";
 180         dr_mode = "host";
 181         status = "okay";
 182 };
 183
 184 &cp0_mdio {
 185         status = "okay";
 186
 187         phy1: ethernet-phy@1 {
 188                 reg = <1>;
 189         };
 190 };
 191
 192 &cp0_ethernet {
 193         status = "okay";
 194 };
 195
 196 &cp0_eth0 {
 197         status = "okay";
 198         phy-mode = "10gbase-r";
 199
 200         fixed-link {
 201                 speed = <10000>;
 202                 full-duplex;
 203         };
 204 };
 205
 206 &cp0_eth2 {
 207         status = "okay";
 208         phy = <&phy1>;
 209         phy-mode = "rgmii-id";
 210 };
 211
 212 /* CON6 on CP1 expansion */
 213 &cp1_pcie0 {
 214         phys = <&cp1_comphy0 0>;
 215         phy-names = "cp1-pcie0-x1-phy";
 216         status = "okay";
 217 };
 218
 219 /* CON7 on CP1 expansion */
 220 &cp1_pcie1 {
 221         phys = <&cp1_comphy4 1>;
 222         phy-names = "cp1-pcie1-x1-phy";
 223         status = "okay";
 224 };
 225
 226 /* CON5 on CP1 expansion */
 227 &cp1_pcie2 {
 228         phys = <&cp1_comphy5 2>;
 229         phy-names = "cp1-pcie2-x1-phy";
 230         status = "okay";
 231 };
 232
 233 &cp1_i2c0 {
 234         status = "okay";
 235         clock-frequency = <100000>;
 236 };
 237
 238 &cp1_spi1 {
 239         status = "okay";
 240
 241         spi-flash@0 {
 242                 compatible = "jedec,spi-nor";
 243                 reg = <0x0>;
 244                 spi-max-frequency = <20000000>;
 245
 246                 partitions {
 247                         compatible = "fixed-partitions";
 248                         #address-cells = <1>;
 249                         #size-cells = <1>;
 250
 251                         partition@0 {
 252                                 label = "Boot";
 253                                 reg = <0x0 0x200000>;
 254                         };
 255                         partition@200000 {
 256                                 label = "Filesystem";
 257                                 reg = <0x200000 0xd00000>;
 258                         };
 259                         partition@f00000 {
 260                                 label = "Boot_2nd";
 261                                 reg = <0xf00000 0x100000>;
 262                         };
 263                 };
 264         };
 265 };
 266
 267 /*
 268  * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
 269  * MDIO signal of CP1.
 270  */
 271 &cp1_nand_controller {
 272         pinctrl-0 = <&nand_pins>, <&nand_rb>;
 273         pinctrl-names = "default";
 274
 275         nand@0 {
 276                 reg = <0>;
 277                 nand-rb = <0>;
 278                 nand-on-flash-bbt;
 279                 nand-ecc-strength = <4>;
 280                 nand-ecc-step-size = <512>;
 281
 282                 partitions {
 283                         compatible = "fixed-partitions";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286
 287                         partition@0 {
 288                                 label = "U-Boot";
 289                                 reg = <0 0x200000>;
 290                         };
 291                         partition@200000 {
 292                                 label = "Linux";
 293                                 reg = <0x200000 0xe00000>;
 294                         };
 295                         partition@1000000 {
 296                                 label = "Filesystem";
 297                                 reg = <0x1000000 0x3f000000>;
 298                         };
 299                 };
 300         };
 301 };
 302
 303 /* CON4 on CP1 expansion */
 304 &cp1_sata0 {
 305         status = "okay";
 306
 307         sata-port@0 {
 308                 phys = <&cp1_comphy1 0>;
 309                 phy-names = "cp1-sata0-0-phy";
 310         };
 311         sata-port@1 {
 312                 phys = <&cp1_comphy3 1>;
 313                 phy-names = "cp1-sata0-1-phy";
 314         };
 315 };
 316
 317 &cp1_utmi {
 318         status = "okay";
 319 };
 320
 321 /* CON9 on CP1 expansion */
 322 &cp1_usb3_0 {
 323         usb-phy = <&cp1_usb3_0_phy>;
 324         phys = <&cp1_utmi0>;
 325         phy-names = "utmi";
 326         dr_mode = "host";
 327         status = "okay";
 328 };
 329
 330 /* CON10 on CP1 expansion */
 331 &cp1_usb3_1 {
 332         phys = <&cp1_utmi1>;
 333         phy-names = "utmi";
 334         status = "okay";
 335 };
 336
 337 &cp1_mdio {
 338         status = "okay";
 339
 340         phy0: ethernet-phy@0 {
 341                 reg = <0>;
 342         };
 343 };
 344
 345 &cp1_ethernet {
 346         status = "okay";
 347 };
 348
 349 &cp1_eth0 {
 350         status = "okay";
 351         phy-mode = "10gbase-r";
 352
 353         fixed-link {
 354                 speed = <10000>;
 355                 full-duplex;
 356         };
 357 };
 358
 359 &cp1_eth1 {
 360         status = "okay";
 361         phy = <&phy0>;
 362         phy-mode = "rgmii-id";
 363 };
 364
 365 &ap_sdhci0 {
 366         status = "okay";
 367         bus-width = <4>;
 368         non-removable;
 369 };
 370
 371 &cp0_sdhci0 {
 372         status = "okay";
 373         bus-width = <8>;
 374         non-removable;
 375 };